diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-25 13:14:42 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-25 13:14:42 -0400 |
| commit | 8fe556338db4cc50a3f1ba20306bc5e464941f2b (patch) | |
| tree | d95b1933c18d142f9c533f32ac7b84bd1f2d0da5 /tests/quick/fs/10.linux-boot/ref/arm/linux | |
| parent | 66e331c7bb7d503c35808325e1bfaa9f18f4bdb9 (diff) | |
| download | gem5-8fe556338db4cc50a3f1ba20306bc5e464941f2b.tar.xz | |
stats: Update stats to reflect use of SimpleDRAM
This patch bumps the stats to match the use of SimpleDRAM instead of
SimpleMemory in all inorder and O3 regressions, and also all
full-system regressions. A number of performance-related stats change,
and a whole bunch of stats are added for the memory controller.
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux')
4 files changed, 2158 insertions, 1526 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index b7f76478e..3841577ac 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.912097 # Nu sim_ticks 912096763500 # Number of ticks simulated final_tick 912096763500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1783031 # Simulator instruction rate (inst/s) -host_op_rate 2295648 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 26389770183 # Simulator tick rate (ticks/s) -host_mem_usage 380112 # Number of bytes of host memory used -host_seconds 34.56 # Real time elapsed on the host +host_inst_rate 1752000 # Simulator instruction rate (inst/s) +host_op_rate 2255696 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 25930494646 # Simulator tick rate (ticks/s) +host_mem_usage 382232 # Number of bytes of host memory used +host_seconds 35.17 # Real time elapsed on the host sim_insts 61625970 # Number of instructions simulated sim_ops 79343340 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory @@ -66,6 +66,164 @@ system.physmem.bw_total::cpu1.dtb.walker 211 # To system.physmem.bw_total::cpu1.inst 235234 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.data 6988969 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 62341162 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 0 # Total number of read requests seen +system.physmem.writeReqs 0 # Total number of write requests seen +system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 0 # Total number of bytes read from memory +system.physmem.bytesWritten 0 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 0 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 0 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 0 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 0 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 0 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 0 # Sum of mem lat for all requests +system.physmem.totBusLat 0 # Total cycles spent in databus access +system.physmem.totBankLat 0 # Total cycles spent in bank access +system.physmem.avgQLat nan # Average queueing delay per request +system.physmem.avgBankLat nan # Average bank access latency per request +system.physmem.avgBusLat nan # Average bus latency per request +system.physmem.avgMemAccLat nan # Average memory access latency +system.physmem.avgRdBW 0.00 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.00 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.00 # Average read queue length over time +system.physmem.avgWrQLen 0.00 # Average write queue length over time +system.physmem.readRowHits 0 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate nan # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap nan # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index 206441d13..ccb9a5402 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.332810 # Nu sim_ticks 2332810264000 # Number of ticks simulated final_tick 2332810264000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1681370 # Simulator instruction rate (inst/s) -host_op_rate 2162138 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 64929680145 # Simulator tick rate (ticks/s) -host_mem_usage 380112 # Number of bytes of host memory used -host_seconds 35.93 # Real time elapsed on the host +host_inst_rate 1184768 # Simulator instruction rate (inst/s) +host_op_rate 1523538 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45752340761 # Simulator tick rate (ticks/s) +host_mem_usage 382236 # Number of bytes of host memory used +host_seconds 50.99 # Real time elapsed on the host sim_insts 60408639 # Number of instructions simulated sim_ops 77681819 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory @@ -49,6 +49,164 @@ system.physmem.bw_total::cpu.itb.walker 82 # To system.physmem.bw_total::cpu.inst 302262 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 5181496 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 54942169 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 0 # Total number of read requests seen +system.physmem.writeReqs 0 # Total number of write requests seen +system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 0 # Total number of bytes read from memory +system.physmem.bytesWritten 0 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 0 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 0 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 0 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 0 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 0 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 0 # Sum of mem lat for all requests +system.physmem.totBusLat 0 # Total cycles spent in databus access +system.physmem.totBankLat 0 # Total cycles spent in bank access +system.physmem.avgQLat nan # Average queueing delay per request +system.physmem.avgBankLat nan # Average bank access latency per request +system.physmem.avgBusLat nan # Average bus latency per request +system.physmem.avgMemAccLat nan # Average memory access latency +system.physmem.avgRdBW 0.00 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.00 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.00 # Average read queue length over time +system.physmem.avgWrQLen 0.00 # Average write queue length over time +system.physmem.readRowHits 0 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate nan # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap nan # Average gap between requests system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -61,114 +219,6 @@ system.realview.nvmem.bw_inst_read::cpu.inst 9 system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 9 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s) -system.cpu.l2cache.replacements 62243 # number of replacements -system.cpu.l2cache.tagsinuse 50007.272909 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1669922 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 127628 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 13.084292 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 2316901489000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 36899.582990 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.dtb.walker 2.960148 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.993931 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 7014.720482 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 6089.015357 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.563043 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.107036 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.092911 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.763050 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7507 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3129 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 838871 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 366771 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1216278 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 592643 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 592643 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 113739 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 113739 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 7507 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 3129 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 838871 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 480510 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1330017 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 7507 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 3129 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 838871 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 480510 # number of overall hits -system.cpu.l2cache.overall_hits::total 1330017 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 10604 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 9871 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 20483 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 2919 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2919 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 133468 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133468 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 10604 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 143339 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 153951 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 5 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 10604 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 143339 # number of overall misses -system.cpu.l2cache.overall_misses::total 153951 # number of overall misses -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7512 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3132 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 849475 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 376642 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1236761 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 592643 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 592643 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2945 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2945 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 247207 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 247207 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7512 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 3132 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 849475 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 623849 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1483968 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7512 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 3132 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 849475 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 623849 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1483968 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000666 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000958 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012483 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026208 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.016562 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991171 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991171 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.539904 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.539904 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000666 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000958 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012483 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.229766 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.103743 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000666 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000958 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012483 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.229766 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.103743 # miss rate for overall accesses -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 57863 # number of writebacks -system.cpu.l2cache.writebacks::total 57863 # number of writebacks -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). @@ -347,6 +397,114 @@ system.cpu.dcache.cache_copies 0 # nu system.cpu.dcache.writebacks::writebacks 592643 # number of writebacks system.cpu.dcache.writebacks::total 592643 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 62243 # number of replacements +system.cpu.l2cache.tagsinuse 50007.272909 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1669922 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 127628 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 13.084292 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 2316901489000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 36899.582990 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.dtb.walker 2.960148 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.993931 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 7014.720482 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 6089.015357 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.563043 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.107036 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.092911 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.763050 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7507 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3129 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 838871 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 366771 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1216278 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 592643 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 592643 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 113739 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 113739 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 7507 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 3129 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 838871 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 480510 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1330017 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 7507 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 3129 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 838871 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 480510 # number of overall hits +system.cpu.l2cache.overall_hits::total 1330017 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 10604 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 9871 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 20483 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 2919 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 2919 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 133468 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 133468 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 10604 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 143339 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 153951 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 5 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 10604 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 143339 # number of overall misses +system.cpu.l2cache.overall_misses::total 153951 # number of overall misses +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7512 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3132 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 849475 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 376642 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1236761 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 592643 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 592643 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2945 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2945 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 247207 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 247207 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7512 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 3132 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 849475 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 623849 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1483968 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7512 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 3132 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 849475 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 623849 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1483968 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000666 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000958 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012483 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026208 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.016562 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991171 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991171 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.539904 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.539904 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000666 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000958 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012483 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.229766 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.103743 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000666 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000958 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012483 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.229766 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.103743 # miss rate for overall accesses +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.writebacks::writebacks 57863 # number of writebacks +system.cpu.l2cache.writebacks::total 57863 # number of writebacks +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index db4dfffca..70af125f4 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,71 +1,229 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.203606 # Number of seconds simulated -sim_ticks 1203606499000 # Number of ticks simulated -final_tick 1203606499000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.182883 # Number of seconds simulated +sim_ticks 1182883077500 # Number of ticks simulated +final_tick 1182883077500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 418240 # Simulator instruction rate (inst/s) -host_op_rate 532998 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8191230777 # Simulator tick rate (ticks/s) -host_mem_usage 386340 # Number of bytes of host memory used -host_seconds 146.94 # Real time elapsed on the host -sim_insts 61455549 # Number of instructions simulated -sim_ops 78317886 # Number of ops (including micro ops) simulated +host_inst_rate 330156 # Simulator instruction rate (inst/s) +host_op_rate 420694 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6355289452 # Simulator tick rate (ticks/s) +host_mem_usage 400808 # Number of bytes of host memory used +host_seconds 186.13 # Real time elapsed on the host +sim_insts 61450599 # Number of instructions simulated +sim_ops 78301940 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 354084 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4259252 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 364956 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5307824 # Number of bytes read from this memory -system.physmem.bytes_read::total 62191076 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 354084 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 364956 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 719040 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4163904 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 393380 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4712308 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 323164 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4776304 # Number of bytes read from this memory +system.physmem.bytes_read::total 62110116 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 393380 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 323164 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 716544 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4085952 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7191248 # Number of bytes written to this memory +system.physmem.bytes_written::total 7113296 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 11751 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 66623 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 5784 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 82961 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6655190 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 65061 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 12365 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 73702 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 5131 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 74656 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6653925 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 63843 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 821897 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43124154 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 53 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 160 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 294186 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3538741 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 160 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 303219 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4409933 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51670605 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 294186 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 303219 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 597405 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3459523 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 14124 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2501103 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 5974750 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3459523 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43124154 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 53 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 160 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 294186 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3552865 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 303219 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 6911036 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 57645355 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_writes::total 820679 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43879664 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 54 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 108 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 332560 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3983748 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 216 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 273200 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4037850 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52507401 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 332560 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 273200 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 605761 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3454232 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 14372 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2544921 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6013524 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3454232 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43879664 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 54 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 108 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 332560 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3998120 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 216 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 273200 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 6582771 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 58520925 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 6653925 # Total number of read requests seen +system.physmem.writeReqs 820679 # Total number of write requests seen +system.physmem.cpureqs 271820 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 425851200 # Total number of bytes read from memory +system.physmem.bytesWritten 52523456 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 62110116 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7113296 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 132 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 11750 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 415519 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 415704 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 415458 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 415465 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 415493 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 415211 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 415304 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 415265 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 422311 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 415383 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 415455 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 415586 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 415355 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 415574 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 415386 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 415324 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50680 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 50792 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50611 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 50651 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51629 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 51413 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 51506 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51453 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51654 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51491 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 51429 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51462 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51424 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 51618 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51455 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51411 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 1182878628500 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 6825 # Categorize read packet sizes +system.physmem.readPktSize::3 6488064 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 159036 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 756836 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 63843 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 11750 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 6597380 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 40502 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 11414 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1777 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 643 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 481 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 367 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 271 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 201 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 155 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 139 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 117 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 109 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 105 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 69 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 44 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 19 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 35674 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 35680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 35681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 35681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 35681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 35682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 35682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 35682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 35682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 3516126974 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 123045854974 # Sum of mem lat for all requests +system.physmem.totBusLat 26615172000 # Total cycles spent in databus access +system.physmem.totBankLat 92914556000 # Total cycles spent in bank access +system.physmem.avgQLat 528.44 # Average queueing delay per request +system.physmem.avgBankLat 13964.15 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 18492.59 # Average memory access latency +system.physmem.avgRdBW 360.01 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 44.40 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 52.51 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 6.01 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 2.53 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.10 # Average read queue length over time +system.physmem.avgWrQLen 15.12 # Average write queue length over time +system.physmem.readRowHits 6625021 # Number of row buffer hits during reads +system.physmem.writeRowHits 788582 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.57 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 96.09 # Row buffer hit rate for writes +system.physmem.avgGap 158253.02 # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -76,245 +234,245 @@ system.realview.nvmem.num_reads::cpu0.inst 5 # system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 40 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 56 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 41 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 57 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 40 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 56 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 41 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 57 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 56 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 70188 # number of replacements -system.l2c.tagsinuse 53228.072476 # Cycle average of tags in use -system.l2c.total_refs 1643838 # Total number of references to valid blocks. -system.l2c.sampled_refs 135351 # Sample count of references to valid blocks. -system.l2c.avg_refs 12.145001 # Average number of references to valid blocks. +system.realview.nvmem.bw_total::cpu1.inst 41 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 68923 # number of replacements +system.l2c.tagsinuse 53039.119781 # Cycle average of tags in use +system.l2c.total_refs 1673706 # Total number of references to valid blocks. +system.l2c.sampled_refs 134114 # Sample count of references to valid blocks. +system.l2c.avg_refs 12.479726 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 40453.574010 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 0.000402 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.003089 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 3394.604865 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 2735.402876 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 2.669960 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 3118.943835 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 3522.873439 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.617273 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 40183.428696 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 0.000405 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 0.001414 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 3728.892697 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 4238.506487 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 2.742166 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 2823.934351 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 2061.613566 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.613150 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.051798 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.041739 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000041 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.047591 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.053755 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.812196 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 2523 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 1490 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 278308 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 124645 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 5210 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1502 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 576222 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 223363 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1213263 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 571562 # number of Writeback hits -system.l2c.Writeback_hits::total 571562 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 992 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 878 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1870 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 189 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 96 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 285 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 39231 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 70244 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 109475 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 2523 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 1490 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 278308 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 163876 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 5210 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 1502 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 576222 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 293607 # number of demand (read+write) hits -system.l2c.demand_hits::total 1322738 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 2523 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 1490 # number of overall hits -system.l2c.overall_hits::cpu0.inst 278308 # number of overall hits -system.l2c.overall_hits::cpu0.data 163876 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 5210 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 1502 # number of overall hits -system.l2c.overall_hits::cpu1.inst 576222 # number of overall hits -system.l2c.overall_hits::cpu1.data 293607 # number of overall hits -system.l2c.overall_hits::total 1322738 # number of overall hits +system.l2c.occ_percent::cpu0.inst 0.056898 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.064674 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.043090 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.031458 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.809313 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 4148 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 1813 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 419656 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 206316 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 5506 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 1906 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 464180 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 143508 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1247033 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 571732 # number of Writeback hits +system.l2c.Writeback_hits::total 571732 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 1159 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 640 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1799 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 215 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 97 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 312 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 56965 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 52844 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 109809 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 4148 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 1813 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 419656 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 263281 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 5506 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 1906 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 464180 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 196352 # number of demand (read+write) hits +system.l2c.demand_hits::total 1356842 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 4148 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 1813 # number of overall hits +system.l2c.overall_hits::cpu0.inst 419656 # number of overall hits +system.l2c.overall_hits::cpu0.data 263281 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 5506 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 1906 # number of overall hits +system.l2c.overall_hits::cpu1.inst 464180 # number of overall hits +system.l2c.overall_hits::cpu1.data 196352 # number of overall hits +system.l2c.overall_hits::total 1356842 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 5119 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6000 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 3 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 5697 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 5608 # number of ReadReq misses -system.l2c.ReadReq_misses::total 22431 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 4011 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 4908 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 8919 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 652 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 388 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1040 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 61450 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 78839 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 140289 # number of ReadExReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 5733 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 7859 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 4 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 5044 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 3621 # number of ReadReq misses +system.l2c.ReadReq_misses::total 22264 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 4676 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 3594 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 8270 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 564 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 474 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1038 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 67114 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 72101 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 139215 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 5119 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 67450 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 3 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 5697 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 84447 # number of demand (read+write) misses -system.l2c.demand_misses::total 162720 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 5733 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 74973 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 4 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 5044 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 75722 # number of demand (read+write) misses +system.l2c.demand_misses::total 161479 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses -system.l2c.overall_misses::cpu0.inst 5119 # number of overall misses -system.l2c.overall_misses::cpu0.data 67450 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 3 # number of overall misses -system.l2c.overall_misses::cpu1.inst 5697 # number of overall misses -system.l2c.overall_misses::cpu1.data 84447 # number of overall misses -system.l2c.overall_misses::total 162720 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 52000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 156500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 267825000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 313081000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 156000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 298083000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 292866500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1172220000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 15780999 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 31202500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 46983499 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1357500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 6172500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 7530000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 3221673990 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 4120152496 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7341826486 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 52000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 156500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 267825000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 3534754990 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 156000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 298083000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 4413018996 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 8514046486 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 52000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 156500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 267825000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 3534754990 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 156000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 298083000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 4413018996 # number of overall miss cycles -system.l2c.overall_miss_latency::total 8514046486 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 2524 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 1493 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 283427 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 130645 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 5213 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 1502 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 581919 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 228971 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1235694 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 571562 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 571562 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 5003 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 5786 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 10789 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 841 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 484 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1325 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 100681 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 149083 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 249764 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 2524 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 1493 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 283427 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 231326 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 5213 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 1502 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 581919 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 378054 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1485458 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 2524 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 1493 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 283427 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 231326 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 5213 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 1502 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 581919 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 378054 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1485458 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000396 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.002009 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.018061 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.045926 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000575 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.009790 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.024492 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.018153 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.801719 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.848254 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.826675 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.775268 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.801653 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.784906 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.610344 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.528826 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.561686 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000396 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.002009 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.018061 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.291580 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000575 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.009790 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.223373 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.109542 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000396 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.002009 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.018061 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.291580 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000575 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.009790 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.223373 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.109542 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 52166.666667 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52319.789021 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 52180.166667 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52322.801474 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 52222.985021 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52258.927377 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3934.430067 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6357.477588 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 5267.798968 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2082.055215 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 15908.505155 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 7240.384615 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52427.566965 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52260.334302 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52333.586283 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 52166.666667 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 52319.789021 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 52405.559526 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 52322.801474 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 52257.853991 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52323.294530 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 52166.666667 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 52319.789021 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 52405.559526 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 52322.801474 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 52257.853991 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52323.294530 # average overall miss latency +system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses +system.l2c.overall_misses::cpu0.inst 5733 # number of overall misses +system.l2c.overall_misses::cpu0.data 74973 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 4 # number of overall misses +system.l2c.overall_misses::cpu1.inst 5044 # number of overall misses +system.l2c.overall_misses::cpu1.data 75722 # number of overall misses +system.l2c.overall_misses::total 161479 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 69000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 67500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 285133000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 404030000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 247500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 261135000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 212169500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1162851500 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 12638997 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 11749999 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 24388996 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1751500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2408500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 4160000 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 3003544975 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 3416776995 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 6420321970 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 69000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 67500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 285133000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 3407574975 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 247500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 261135000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 3628946495 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 7583173470 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 69000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 67500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 285133000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 3407574975 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 247500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 261135000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 3628946495 # number of overall miss cycles +system.l2c.overall_miss_latency::total 7583173470 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 4149 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 1815 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 425389 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 214175 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 5510 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 1906 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 469224 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 147129 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1269297 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 571732 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 571732 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 5835 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 4234 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 10069 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 779 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 571 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1350 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 124079 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 124945 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 249024 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 4149 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 1815 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 425389 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 338254 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 5510 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 1906 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 469224 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 272074 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1518321 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 4149 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 1815 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 425389 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 338254 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 5510 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 1906 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 469224 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 272074 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1518321 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000241 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001102 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.013477 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.036694 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000726 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.010750 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.024611 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.017540 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.801371 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.848843 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.821333 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.724005 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.830123 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.768889 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.540897 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.577062 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.559043 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000241 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.001102 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.013477 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.221647 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000726 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.010750 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.278314 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.106354 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000241 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.001102 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.013477 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.221647 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000726 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.010750 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.278314 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.106354 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 69000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 33750 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 49735.391593 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 51409.848581 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 61875 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51771.411578 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 58594.172880 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52230.124865 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2702.950599 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3269.337507 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 2949.092624 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3105.496454 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5081.223629 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 4007.707129 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 44752.882782 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 47388.760142 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 46118.033042 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 69000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 33750 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 49735.391593 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 45450.695250 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 61875 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 51771.411578 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 47924.599126 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 46960.740839 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 69000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 33750 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 49735.391593 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 45450.695250 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 61875 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 51771.411578 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 47924.599126 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 46960.740839 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -323,8 +481,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 65061 # number of writebacks -system.l2c.writebacks::total 65061 # number of writebacks +system.l2c.writebacks::writebacks 63843 # number of writebacks +system.l2c.writebacks::total 63843 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits @@ -332,150 +490,150 @@ system.l2c.demand_mshr_hits::total 1 # nu system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 3 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 5118 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 6000 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 3 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 5697 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 5608 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 22430 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 4011 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 4908 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 8919 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 652 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 388 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1040 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 61450 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 78839 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 140289 # number of ReadExReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 5732 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 7859 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 4 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 5044 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 3621 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 22263 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 4676 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 3594 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 8270 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 564 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 474 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1038 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 67114 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 72101 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 139215 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu0.dtb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 3 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 5118 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 67450 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 3 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 5697 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 84447 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 162719 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 5732 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 74973 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 4 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 5044 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 75722 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 161478 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0.dtb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 3 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 5118 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 67450 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 3 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 5697 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 84447 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 162719 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 40000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 120000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 204790500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 240017000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 120000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 227965500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 224340500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 897393500 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 160489997 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 196385999 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 356875996 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 26081499 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 15523499 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 41604998 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2458644990 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3153935496 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5612580486 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 40000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 120000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 204790500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 2698661990 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 120000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 227965500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 3378275996 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 6509973986 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 40000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 120000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 204790500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 2698661990 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 120000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 227965500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 3378275996 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 6509973986 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 265520000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 11136863000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3961500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 155607031000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 167013375500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1070738498 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 30849143000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 31919881498 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 265520000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 12207601498 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3961500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 186456174000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 198933256998 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000396 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.002009 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.018058 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.045926 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000575 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009790 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.024492 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.018152 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.801719 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.848254 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.826675 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.775268 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.801653 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.784906 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.610344 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.528826 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.561686 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000396 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.002009 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018058 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.291580 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000575 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009790 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.223373 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.109541 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000396 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.002009 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018058 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.291580 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000575 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009790 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.223373 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.109541 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40013.774912 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40002.833333 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40015.007899 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40003.655492 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40008.626839 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40012.464971 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40013.447229 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40013.005494 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40002.299080 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40009.018041 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40004.805769 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40010.496176 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40004.762820 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40007.274170 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40013.774912 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40009.814529 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40015.007899 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40004.689284 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40007.460628 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40013.774912 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40009.814529 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40015.007899 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40004.689284 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40007.460628 # average overall mshr miss latency +system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 5732 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 74973 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 4 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 5044 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 75722 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 161478 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 56002 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 42004 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 212317379 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 303283129 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 196008 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 197074983 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 165938649 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 878908154 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 46908094 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 36050560 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 82958654 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 5654558 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4769959 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 10424517 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2158776151 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2496303754 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 4655079905 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 56002 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 42004 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 212317379 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 2462059280 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 196008 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 197074983 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 2662242403 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 5533988059 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 56002 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 42004 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 212317379 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 2462059280 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 196008 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 197074983 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 2662242403 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 5533988059 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 197971583 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12448379609 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3031674 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154289730543 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 166939113409 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1000300750 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8208718440 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 9209019190 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 197971583 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13448680359 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3031674 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 162498448983 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 176148132599 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000241 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001102 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013475 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036694 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000726 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010750 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.024611 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.017540 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.801371 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.848843 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.821333 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.724005 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.830123 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.768889 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.540897 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.577062 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.559043 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000241 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001102 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013475 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.221647 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000726 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010750 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.278314 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.106353 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000241 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001102 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013475 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.221647 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000726 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010750 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.278314 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.106353 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 56002 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 21002 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 37040.715108 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 38590.549561 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 49002 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 39071.170301 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 45826.746479 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 39478.424022 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10031.671086 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10030.762382 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10031.276179 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10025.812057 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10063.204641 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10042.887283 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 32165.809682 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 34622.318054 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 33438.062745 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 56002 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 21002 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 37040.715108 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 32839.279207 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 49002 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 39071.170301 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 35158.109968 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 34270.848407 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 56002 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 21002 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 37040.715108 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 32839.279207 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 49002 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 39071.170301 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 35158.109968 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 34270.848407 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -498,27 +656,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 4800569 # DTB read hits -system.cpu0.dtb.read_misses 2116 # DTB read misses -system.cpu0.dtb.write_hits 4101188 # DTB write hits -system.cpu0.dtb.write_misses 405 # DTB write misses +system.cpu0.dtb.read_hits 7072899 # DTB read hits +system.cpu0.dtb.read_misses 3762 # DTB read misses +system.cpu0.dtb.write_hits 5658444 # DTB write hits +system.cpu0.dtb.write_misses 809 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1539 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 1807 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 91 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 139 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 203 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 4802685 # DTB read accesses -system.cpu0.dtb.write_accesses 4101593 # DTB write accesses +system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 7076661 # DTB read accesses +system.cpu0.dtb.write_accesses 5659253 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 8901757 # DTB hits -system.cpu0.dtb.misses 2521 # DTB misses -system.cpu0.dtb.accesses 8904278 # DTB accesses -system.cpu0.itb.inst_hits 19425317 # ITB inst hits -system.cpu0.itb.inst_misses 1350 # ITB inst misses +system.cpu0.dtb.hits 12731343 # DTB hits +system.cpu0.dtb.misses 4571 # DTB misses +system.cpu0.dtb.accesses 12735914 # DTB accesses +system.cpu0.itb.inst_hits 29570664 # ITB inst hits +system.cpu0.itb.inst_misses 2205 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -527,86 +685,86 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1347 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1332 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 19426667 # ITB inst accesses -system.cpu0.itb.hits 19425317 # DTB hits -system.cpu0.itb.misses 1350 # DTB misses -system.cpu0.itb.accesses 19426667 # DTB accesses -system.cpu0.numCycles 2405785466 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 29572869 # ITB inst accesses +system.cpu0.itb.hits 29570664 # DTB hits +system.cpu0.itb.misses 2205 # DTB misses +system.cpu0.itb.accesses 29572869 # DTB accesses +system.cpu0.numCycles 2365766155 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 19048205 # Number of instructions committed -system.cpu0.committedOps 25051835 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 22684157 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 4364 # Number of float alu accesses -system.cpu0.num_func_calls 868672 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 2620308 # number of instructions that are conditional controls -system.cpu0.num_int_insts 22684157 # number of integer instructions -system.cpu0.num_fp_insts 4364 # number of float instructions -system.cpu0.num_int_register_reads 128951400 # number of times the integer registers were read -system.cpu0.num_int_register_writes 23731440 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3980 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 384 # number of times the floating registers were written -system.cpu0.num_mem_refs 9388218 # number of memory refs -system.cpu0.num_load_insts 5047895 # Number of load instructions -system.cpu0.num_store_insts 4340323 # Number of store instructions -system.cpu0.num_idle_cycles 2301327262.807119 # Number of idle cycles -system.cpu0.num_busy_cycles 104458203.192881 # Number of busy cycles -system.cpu0.not_idle_fraction 0.043420 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.956580 # Percentage of idle cycles +system.cpu0.committedInsts 28872728 # Number of instructions committed +system.cpu0.committedOps 37219681 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 33106320 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses +system.cpu0.num_func_calls 1241688 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4373344 # number of instructions that are conditional controls +system.cpu0.num_int_insts 33106320 # number of integer instructions +system.cpu0.num_fp_insts 3860 # number of float instructions +system.cpu0.num_int_register_reads 190095843 # number of times the integer registers were read +system.cpu0.num_int_register_writes 36231130 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written +system.cpu0.num_mem_refs 13399483 # number of memory refs +system.cpu0.num_load_insts 7410404 # Number of load instructions +system.cpu0.num_store_insts 5989079 # Number of store instructions +system.cpu0.num_idle_cycles 2224921697.356119 # Number of idle cycles +system.cpu0.num_busy_cycles 140844457.643881 # Number of busy cycles +system.cpu0.not_idle_fraction 0.059534 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.940466 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 34019 # number of quiesce instructions executed -system.cpu0.icache.replacements 283204 # number of replacements -system.cpu0.icache.tagsinuse 509.502445 # Cycle average of tags in use -system.cpu0.icache.total_refs 19141584 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 283716 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 67.467411 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 75588601000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 509.502445 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.995122 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.995122 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 19141584 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 19141584 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 19141584 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 19141584 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 19141584 # number of overall hits -system.cpu0.icache.overall_hits::total 19141584 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 283716 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 283716 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 283716 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 283716 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 283716 # number of overall misses -system.cpu0.icache.overall_misses::total 283716 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 3929859500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 3929859500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 3929859500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 3929859500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 3929859500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 3929859500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 19425300 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 19425300 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 19425300 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 19425300 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 19425300 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 19425300 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014605 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014605 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014605 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014605 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014605 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014605 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13851.384836 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13851.384836 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13851.384836 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13851.384836 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13851.384836 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13851.384836 # average overall miss latency +system.cpu0.kern.inst.quiesce 46697 # number of quiesce instructions executed +system.cpu0.icache.replacements 425421 # number of replacements +system.cpu0.icache.tagsinuse 509.627794 # Cycle average of tags in use +system.cpu0.icache.total_refs 29144714 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 425933 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 68.425583 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 74931906000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 509.627794 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.995367 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.995367 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 29144714 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 29144714 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 29144714 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 29144714 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 29144714 # number of overall hits +system.cpu0.icache.overall_hits::total 29144714 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 425933 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 425933 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 425933 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 425933 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 425933 # number of overall misses +system.cpu0.icache.overall_misses::total 425933 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5794506500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5794506500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5794506500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5794506500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5794506500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5794506500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 29570647 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 29570647 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 29570647 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 29570647 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 29570647 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 29570647 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014404 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014404 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014404 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014404 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014404 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014404 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13604.267573 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13604.267573 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13604.267573 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13604.267573 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13604.267573 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13604.267573 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -615,120 +773,120 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 283716 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 283716 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 283716 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 283716 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 283716 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 283716 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 3362427500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 3362427500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 3362427500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 3362427500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 3362427500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 3362427500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 353907000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 353907000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 353907000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 353907000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014605 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014605 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014605 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014605 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014605 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014605 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11851.384836 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11851.384836 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11851.384836 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11851.384836 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11851.384836 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11851.384836 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 425933 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 425933 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 425933 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 425933 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 425933 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 425933 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4942640500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4942640500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4942640500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4942640500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4942640500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4942640500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 288882000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 288882000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 288882000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 288882000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014404 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014404 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014404 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014404 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014404 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014404 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11604.267573 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11604.267573 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11604.267573 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11604.267573 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11604.267573 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11604.267573 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 220249 # number of replacements -system.cpu0.dcache.tagsinuse 456.517669 # Cycle average of tags in use -system.cpu0.dcache.total_refs 8560161 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 220619 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 38.800652 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 656029000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 456.517669 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.891636 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.891636 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 4452439 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 4452439 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3852551 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3852551 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 117730 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 117730 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 117854 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 117854 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 8304990 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 8304990 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 8304990 # number of overall hits -system.cpu0.dcache.overall_hits::total 8304990 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 146457 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 146457 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 116961 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 116961 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 7881 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 7881 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7692 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7692 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 263418 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 263418 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 263418 # number of overall misses -system.cpu0.dcache.overall_misses::total 263418 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 1991139500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 1991139500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4199443500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 4199443500 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 70259000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 70259000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 66131000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 66131000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 6190583000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 6190583000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 6190583000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 6190583000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 4598896 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 4598896 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 3969512 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 3969512 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 125611 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 125611 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 125546 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 125546 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 8568408 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 8568408 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 8568408 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 8568408 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.031846 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.031846 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.029465 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.029465 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.062741 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.062741 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.061268 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.061268 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.030743 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.030743 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.030743 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.030743 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13595.386359 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13595.386359 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35904.647703 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 35904.647703 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 8914.985408 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 8914.985408 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8597.373895 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 8597.373895 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 23500.987024 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 23500.987024 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23500.987024 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 23500.987024 # average overall miss latency +system.cpu0.dcache.replacements 330958 # number of replacements +system.cpu0.dcache.tagsinuse 453.838533 # Cycle average of tags in use +system.cpu0.dcache.total_refs 12275558 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 331470 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 37.033692 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 462692000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 453.838533 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.886403 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.886403 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6602415 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6602415 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5353315 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5353315 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147939 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 147939 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149687 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 149687 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 11955730 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 11955730 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11955730 # number of overall hits +system.cpu0.dcache.overall_hits::total 11955730 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 228156 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 228156 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 141693 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 141693 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9329 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 9329 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7496 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7496 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 369849 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 369849 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 369849 # number of overall misses +system.cpu0.dcache.overall_misses::total 369849 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3134416000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 3134416000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4131327000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 4131327000 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88312000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 88312000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44497000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 44497000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 7265743000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 7265743000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 7265743000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 7265743000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6830571 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6830571 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5495008 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5495008 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157268 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 157268 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157183 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 157183 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12325579 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12325579 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12325579 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12325579 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033402 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.033402 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025786 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.025786 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059319 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059319 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047690 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047690 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.030007 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.030007 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.030007 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.030007 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13738.038886 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13738.038886 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 29156.888484 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 29156.888484 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9466.395112 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9466.395112 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5936.099253 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5936.099253 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19645.160593 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 19645.160593 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 19645.160593 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 19645.160593 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -737,66 +895,66 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 205058 # number of writebacks -system.cpu0.dcache.writebacks::total 205058 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 146457 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 146457 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 116961 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 116961 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 7881 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7881 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7690 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7690 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 263418 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 263418 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 263418 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 263418 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 1698225500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 1698225500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3965521500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3965521500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 54497000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 54497000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 50753000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 50753000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.writebacks::writebacks 306622 # number of writebacks +system.cpu0.dcache.writebacks::total 306622 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 228156 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 228156 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141693 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 141693 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9329 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9329 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7493 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7493 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 369849 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 369849 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 369849 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 369849 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2678104000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2678104000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3847941000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3847941000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69654000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 69654000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 29513000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29513000 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 5663747000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 5663747000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 5663747000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 5663747000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 12130745000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 12130745000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1193494500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1193494500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 13324239500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 13324239500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.031846 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.031846 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.029465 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.029465 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.062741 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.062741 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.061252 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.061252 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030743 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.030743 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030743 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.030743 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11595.386359 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11595.386359 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33904.647703 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33904.647703 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 6914.985408 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6914.985408 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6599.869961 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6599.869961 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6526045000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 6526045000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6526045000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 6526045000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13559793500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13559793500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1128518500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1128518500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14688312000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14688312000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033402 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033402 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025786 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025786 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059319 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059319 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047671 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047671 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030007 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.030007 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030007 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.030007 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11738.038886 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11738.038886 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27156.888484 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27156.888484 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7466.395112 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7466.395112 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3938.742827 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3938.742827 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21500.987024 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21500.987024 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21500.987024 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21500.987024 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17645.160593 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17645.160593 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17645.160593 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17645.160593 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -806,27 +964,27 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 10589201 # DTB read hits -system.cpu1.dtb.read_misses 5231 # DTB read misses -system.cpu1.dtb.write_hits 7383574 # DTB write hits -system.cpu1.dtb.write_misses 1834 # DTB write misses +system.cpu1.dtb.read_hits 8308478 # DTB read hits +system.cpu1.dtb.read_misses 3644 # DTB read misses +system.cpu1.dtb.write_hits 5825596 # DTB write hits +system.cpu1.dtb.write_misses 1434 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2257 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1965 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 193 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 140 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 249 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 10594432 # DTB read accesses -system.cpu1.dtb.write_accesses 7385408 # DTB write accesses +system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 8312122 # DTB read accesses +system.cpu1.dtb.write_accesses 5827030 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 17972775 # DTB hits -system.cpu1.dtb.misses 7065 # DTB misses -system.cpu1.dtb.accesses 17979840 # DTB accesses -system.cpu1.itb.inst_hits 43338256 # ITB inst hits -system.cpu1.itb.inst_misses 3017 # ITB inst misses +system.cpu1.dtb.hits 14134074 # DTB hits +system.cpu1.dtb.misses 5078 # DTB misses +system.cpu1.dtb.accesses 14139152 # DTB accesses +system.cpu1.itb.inst_hits 33188345 # ITB inst hits +system.cpu1.itb.inst_misses 2171 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -835,86 +993,86 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1458 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1495 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 43341273 # ITB inst accesses -system.cpu1.itb.hits 43338256 # DTB hits -system.cpu1.itb.misses 3017 # DTB misses -system.cpu1.itb.accesses 43341273 # DTB accesses -system.cpu1.numCycles 2407212998 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 33190516 # ITB inst accesses +system.cpu1.itb.hits 33188345 # DTB hits +system.cpu1.itb.misses 2171 # DTB misses +system.cpu1.itb.accesses 33190516 # DTB accesses +system.cpu1.numCycles 2364324255 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 42407344 # Number of instructions committed -system.cpu1.committedOps 53266051 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 47734651 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 5457 # Number of float alu accesses -system.cpu1.num_func_calls 1334953 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 5482869 # number of instructions that are conditional controls -system.cpu1.num_int_insts 47734651 # number of integer instructions -system.cpu1.num_fp_insts 5457 # number of float instructions -system.cpu1.num_int_register_reads 274813771 # number of times the integer registers were read -system.cpu1.num_int_register_writes 51971016 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 3577 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1884 # number of times the floating registers were written -system.cpu1.num_mem_refs 18681443 # number of memory refs -system.cpu1.num_load_insts 10999206 # Number of load instructions -system.cpu1.num_store_insts 7682237 # Number of store instructions -system.cpu1.num_idle_cycles 1827286039.250482 # Number of idle cycles -system.cpu1.num_busy_cycles 579926958.749518 # Number of busy cycles -system.cpu1.not_idle_fraction 0.240912 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.759088 # Percentage of idle cycles +system.cpu1.committedInsts 32577871 # Number of instructions committed +system.cpu1.committedOps 41082259 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 37307050 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses +system.cpu1.num_func_calls 961975 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3732476 # number of instructions that are conditional controls +system.cpu1.num_int_insts 37307050 # number of integer instructions +system.cpu1.num_fp_insts 6793 # number of float instructions +system.cpu1.num_int_register_reads 213626787 # number of times the integer registers were read +system.cpu1.num_int_register_writes 39450306 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written +system.cpu1.num_mem_refs 14671800 # number of memory refs +system.cpu1.num_load_insts 8630367 # Number of load instructions +system.cpu1.num_store_insts 6041433 # Number of store instructions +system.cpu1.num_idle_cycles 1868325738.966939 # Number of idle cycles +system.cpu1.num_busy_cycles 495998516.033061 # Number of busy cycles +system.cpu1.not_idle_fraction 0.209784 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.790216 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 56704 # number of quiesce instructions executed -system.cpu1.icache.replacements 582576 # number of replacements -system.cpu1.icache.tagsinuse 479.066528 # Cycle average of tags in use -system.cpu1.icache.total_refs 42755164 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 583088 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 73.325405 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 92849627500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 479.066528 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.935677 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.935677 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 42755164 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 42755164 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 42755164 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 42755164 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 42755164 # number of overall hits -system.cpu1.icache.overall_hits::total 42755164 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 583088 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 583088 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 583088 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 583088 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 583088 # number of overall misses -system.cpu1.icache.overall_misses::total 583088 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7852005500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 7852005500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 7852005500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 7852005500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 7852005500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 7852005500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 43338252 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 43338252 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 43338252 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 43338252 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 43338252 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 43338252 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013454 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.013454 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013454 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.013454 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013454 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.013454 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13466.244375 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13466.244375 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13466.244375 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13466.244375 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13466.244375 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13466.244375 # average overall miss latency +system.cpu1.kern.inst.quiesce 43884 # number of quiesce instructions executed +system.cpu1.icache.replacements 469230 # number of replacements +system.cpu1.icache.tagsinuse 478.783120 # Cycle average of tags in use +system.cpu1.icache.total_refs 32718599 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 469742 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 69.652275 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 92024110500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 478.783120 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.935123 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.935123 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 32718599 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 32718599 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 32718599 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 32718599 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 32718599 # number of overall hits +system.cpu1.icache.overall_hits::total 32718599 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 469742 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 469742 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 469742 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 469742 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 469742 # number of overall misses +system.cpu1.icache.overall_misses::total 469742 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6348514000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 6348514000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 6348514000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 6348514000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 6348514000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 6348514000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 33188341 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 33188341 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 33188341 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 33188341 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 33188341 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 33188341 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014154 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.014154 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014154 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.014154 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014154 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.014154 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13514.895411 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13514.895411 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13514.895411 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13514.895411 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13514.895411 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13514.895411 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -923,120 +1081,120 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 583088 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 583088 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 583088 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 583088 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 583088 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 583088 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6685829500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 6685829500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6685829500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 6685829500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6685829500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 6685829500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5251000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5251000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5251000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 5251000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013454 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013454 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013454 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.013454 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013454 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.013454 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11466.244375 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11466.244375 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11466.244375 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11466.244375 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11466.244375 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11466.244375 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 469742 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 469742 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 469742 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 469742 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 469742 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 469742 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5409030000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5409030000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5409030000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5409030000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5409030000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5409030000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 4406000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 4406000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 4406000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 4406000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014154 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014154 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014154 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.014154 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014154 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.014154 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11514.895411 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11514.895411 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11514.895411 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11514.895411 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11514.895411 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11514.895411 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 401285 # number of replacements -system.cpu1.dcache.tagsinuse 473.299929 # Cycle average of tags in use -system.cpu1.dcache.total_refs 15679399 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 401797 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 39.023186 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 84382221000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 473.299929 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.924414 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.924414 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 9100620 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 9100620 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 6322619 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 6322619 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 111839 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 111839 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 114463 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 114463 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 15423239 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 15423239 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 15423239 # number of overall hits -system.cpu1.dcache.overall_hits::total 15423239 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 253127 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 253127 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 178055 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 178055 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13099 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 13099 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10399 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10399 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 431182 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 431182 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 431182 # number of overall misses -system.cpu1.dcache.overall_misses::total 431182 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3277248500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 3277248500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5648876500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 5648876500 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 115793500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 115793500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 63008000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 63008000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 8926125000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 8926125000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 8926125000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 8926125000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 9353747 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 9353747 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 6500674 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 6500674 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 124938 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 124938 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 124862 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 124862 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 15854421 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 15854421 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 15854421 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 15854421 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.027062 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.027062 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027390 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.027390 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.104844 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.104844 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.083284 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.083284 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027196 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.027196 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.027196 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.027196 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12947.052270 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12947.052270 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 31725.458426 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 31725.458426 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8839.873273 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8839.873273 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 6059.044139 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 6059.044139 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20701.525110 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 20701.525110 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20701.525110 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 20701.525110 # average overall miss latency +system.cpu1.dcache.replacements 291659 # number of replacements +system.cpu1.dcache.tagsinuse 472.058793 # Cycle average of tags in use +system.cpu1.dcache.total_refs 11957529 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 292006 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 40.949600 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 83625331000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 472.058793 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.921990 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.921990 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 6944275 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 6944275 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4825543 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4825543 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 81753 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 81753 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 82700 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 82700 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 11769818 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 11769818 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 11769818 # number of overall hits +system.cpu1.dcache.overall_hits::total 11769818 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 170271 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 170271 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 149767 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 149767 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11060 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 11060 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10038 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10038 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 320038 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 320038 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 320038 # number of overall misses +system.cpu1.dcache.overall_misses::total 320038 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2152137500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2152137500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4507881000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 4507881000 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 91883000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 91883000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 51759500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 51759500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 6660018500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 6660018500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 6660018500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 6660018500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 7114546 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 7114546 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 4975310 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 4975310 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 92813 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 92813 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92738 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 92738 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 12089856 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 12089856 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 12089856 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 12089856 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023933 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.023933 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030102 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.030102 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119164 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119164 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108240 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108240 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026472 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.026472 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026472 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.026472 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12639.483529 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12639.483529 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 30099.294237 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 30099.294237 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8307.685353 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8307.685353 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5156.355848 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5156.355848 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20810.086615 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 20810.086615 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20810.086615 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 20810.086615 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1045,66 +1203,66 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 366504 # number of writebacks -system.cpu1.dcache.writebacks::total 366504 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 253127 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 253127 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 178055 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 178055 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 13099 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 13099 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10394 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10394 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 431182 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 431182 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 431182 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 431182 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2770994500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2770994500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5292766500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5292766500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89595500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89595500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 42224000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 42224000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8063761000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 8063761000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8063761000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 8063761000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 170066366500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 170066366500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 40314514000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 40314514000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 210380880500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 210380880500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027062 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.027062 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027390 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027390 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.104844 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.104844 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.083244 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.083244 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027196 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.027196 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027196 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.027196 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10947.052270 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10947.052270 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29725.458426 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 29725.458426 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6839.873273 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6839.873273 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4062.343660 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4062.343660 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 265110 # number of writebacks +system.cpu1.dcache.writebacks::total 265110 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170271 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 170271 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 149767 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 149767 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11060 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11060 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10034 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10034 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 320038 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 320038 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 320038 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 320038 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1811595500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1811595500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4208347000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4208347000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 69763000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 69763000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31693500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31693500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6019942500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 6019942500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6019942500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 6019942500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168625975500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168625975500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 17666930000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 17666930000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 186292905500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 186292905500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023933 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023933 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030102 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030102 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119164 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119164 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108197 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108197 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026472 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026472 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026472 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026472 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10639.483529 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10639.483529 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28099.294237 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28099.294237 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6307.685353 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6307.685353 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3158.610724 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3158.610724 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18701.525110 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18701.525110 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18701.525110 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18701.525110 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18810.086615 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18810.086615 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18810.086615 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18810.086615 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1126,10 +1284,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 522347967555 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 522347967555 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 522347967555 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 522347967555 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 446709885400 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 446709885400 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 446709885400 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 446709885400 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index d1abeb8c8..e97027568 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,54 +1,212 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.624627 # Number of seconds simulated -sim_ticks 2624627401000 # Number of ticks simulated -final_tick 2624627401000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.603636 # Number of seconds simulated +sim_ticks 2603636076000 # Number of ticks simulated +final_tick 2603636076000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 463403 # Simulator instruction rate (inst/s) -host_op_rate 589674 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 20203281292 # Simulator tick rate (ticks/s) -host_mem_usage 381220 # Number of bytes of host memory used -host_seconds 129.91 # Real time elapsed on the host -sim_insts 60201162 # Number of instructions simulated -sim_ops 76605148 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::realview.clcd 123834568 # Number of bytes read from this memory +host_inst_rate 485506 # Simulator instruction rate (inst/s) +host_op_rate 617798 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 20998999798 # Simulator tick rate (ticks/s) +host_mem_usage 395692 # Number of bytes of host memory used +host_seconds 123.99 # Real time elapsed on the host +sim_insts 60197128 # Number of instructions simulated +sim_ops 76599899 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 705824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9049808 # Number of bytes read from this memory -system.physmem.bytes_read::total 133590712 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 705824 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 705824 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3677120 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 704800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9050128 # Number of bytes read from this memory +system.physmem.bytes_read::total 132438832 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 704800 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 704800 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3677504 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6693192 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 15479321 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 6693576 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 17231 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141437 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15637997 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57455 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 17215 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141442 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15494089 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57461 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811473 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47181771 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 122 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 73 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 268924 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3448035 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50898925 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 268924 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 268924 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1401006 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1149143 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2550149 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1401006 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47181771 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 122 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 73 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 268924 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4597178 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53449074 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_writes::total 811479 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47120023 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 123 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 74 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 270698 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3475957 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50866875 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 270698 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 270698 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1412449 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1158408 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2570857 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1412449 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47120023 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 123 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 74 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 270698 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4634365 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53437732 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15494089 # Total number of read requests seen +system.physmem.writeReqs 811479 # Total number of write requests seen +system.physmem.cpureqs 213984 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 991621696 # Total number of bytes read from memory +system.physmem.bytesWritten 51934656 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 132438832 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6693576 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 336 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4510 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 968203 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 968434 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 967969 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 967930 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 967593 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 967540 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 967550 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 967729 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 974541 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 967896 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 968053 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 968056 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 968172 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 968177 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 968121 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 967789 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50184 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 50353 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 49939 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 49917 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50620 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50586 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50545 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50763 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 50925 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 50957 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50984 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51005 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51208 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 51196 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51260 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51037 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 2603631716000 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 6652 # Categorize read packet sizes +system.physmem.readPktSize::3 15335424 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 152013 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 754018 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 57461 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 4510 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 15419651 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 56393 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 11796 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2238 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1067 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 810 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 578 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 393 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 217 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 134 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 116 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 105 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 89 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 74 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 49 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 35279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 35281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 35281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 35282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 35282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 35282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 35282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 35282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 35282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 3755940486 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 281915228486 # Sum of mem lat for all requests +system.physmem.totBusLat 61975012000 # Total cycles spent in databus access +system.physmem.totBankLat 216184276000 # Total cycles spent in bank access +system.physmem.avgQLat 242.42 # Average queueing delay per request +system.physmem.avgBankLat 13953.00 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 18195.41 # Average memory access latency +system.physmem.avgRdBW 380.86 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 19.95 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 50.87 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 2.57 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 2.51 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.11 # Average read queue length over time +system.physmem.avgWrQLen 12.38 # Average write queue length over time +system.physmem.readRowHits 15449465 # Number of row buffer hits during reads +system.physmem.writeRowHits 784611 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.71 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 96.69 # Row buffer hit rate for writes +system.physmem.avgGap 159677.46 # Average gap between requests system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -69,26 +227,26 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 14996727 # DTB read hits -system.cpu.dtb.read_misses 7361 # DTB read misses -system.cpu.dtb.write_hits 11231610 # DTB write hits -system.cpu.dtb.write_misses 2211 # DTB write misses +system.cpu.dtb.read_hits 14995523 # DTB read hits +system.cpu.dtb.read_misses 7332 # DTB read misses +system.cpu.dtb.write_hits 11230789 # DTB write hits +system.cpu.dtb.write_misses 2203 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_entries 3487 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 186 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 184 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 15004088 # DTB read accesses -system.cpu.dtb.write_accesses 11233821 # DTB write accesses +system.cpu.dtb.read_accesses 15002855 # DTB read accesses +system.cpu.dtb.write_accesses 11232992 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 26228337 # DTB hits -system.cpu.dtb.misses 9572 # DTB misses -system.cpu.dtb.accesses 26237909 # DTB accesses -system.cpu.itb.inst_hits 61495131 # ITB inst hits +system.cpu.dtb.hits 26226312 # DTB hits +system.cpu.dtb.misses 9535 # DTB misses +system.cpu.dtb.accesses 26235847 # DTB accesses +system.cpu.itb.inst_hits 61491068 # ITB inst hits system.cpu.itb.inst_misses 4471 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -105,79 +263,79 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 61499602 # ITB inst accesses -system.cpu.itb.hits 61495131 # DTB hits +system.cpu.itb.inst_accesses 61495539 # ITB inst accesses +system.cpu.itb.hits 61491068 # DTB hits system.cpu.itb.misses 4471 # DTB misses -system.cpu.itb.accesses 61499602 # DTB accesses -system.cpu.numCycles 5249254802 # number of cpu cycles simulated +system.cpu.itb.accesses 61495539 # DTB accesses +system.cpu.numCycles 5207272152 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60201162 # Number of instructions committed -system.cpu.committedOps 76605148 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 68872531 # Number of integer alu accesses +system.cpu.committedInsts 60197128 # Number of instructions committed +system.cpu.committedOps 76599899 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 68867725 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses -system.cpu.num_func_calls 2139915 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7948068 # number of instructions that are conditional controls -system.cpu.num_int_insts 68872531 # number of integer instructions +system.cpu.num_func_calls 2139710 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7947746 # number of instructions that are conditional controls +system.cpu.num_int_insts 68867725 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions -system.cpu.num_int_register_reads 394780405 # number of times the integer registers were read -system.cpu.num_int_register_writes 74180740 # number of times the integer registers were written +system.cpu.num_int_register_reads 394752708 # number of times the integer registers were read +system.cpu.num_int_register_writes 74175592 # number of times the integer registers were written system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written -system.cpu.num_mem_refs 27395680 # number of memory refs -system.cpu.num_load_insts 15660706 # Number of load instructions -system.cpu.num_store_insts 11734974 # Number of store instructions -system.cpu.num_idle_cycles 4573851223.612257 # Number of idle cycles -system.cpu.num_busy_cycles 675403578.387743 # Number of busy cycles -system.cpu.not_idle_fraction 0.128667 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.871333 # Percentage of idle cycles +system.cpu.num_mem_refs 27393681 # number of memory refs +system.cpu.num_load_insts 15659530 # Number of load instructions +system.cpu.num_store_insts 11734151 # Number of store instructions +system.cpu.num_idle_cycles 4579082960.576241 # Number of idle cycles +system.cpu.num_busy_cycles 628189191.423759 # Number of busy cycles +system.cpu.not_idle_fraction 0.120637 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.879363 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83018 # number of quiesce instructions executed -system.cpu.icache.replacements 855895 # number of replacements -system.cpu.icache.tagsinuse 510.920698 # Cycle average of tags in use -system.cpu.icache.total_refs 60638724 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 856407 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 70.805965 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 19300651000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.920698 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.997892 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.997892 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 60638724 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 60638724 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 60638724 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 60638724 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 60638724 # number of overall hits -system.cpu.icache.overall_hits::total 60638724 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 856407 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 856407 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 856407 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 856407 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 856407 # number of overall misses -system.cpu.icache.overall_misses::total 856407 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11564476500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11564476500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11564476500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11564476500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11564476500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11564476500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 61495131 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 61495131 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 61495131 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 61495131 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 61495131 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 61495131 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013926 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.013926 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.013926 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.013926 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.013926 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.013926 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13503.481989 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13503.481989 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13503.481989 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13503.481989 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13503.481989 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13503.481989 # average overall miss latency +system.cpu.kern.inst.quiesce 83000 # number of quiesce instructions executed +system.cpu.icache.replacements 855498 # number of replacements +system.cpu.icache.tagsinuse 510.984783 # Cycle average of tags in use +system.cpu.icache.total_refs 60635058 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 856010 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 70.834521 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 18657050000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.984783 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.998017 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.998017 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 60635058 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 60635058 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 60635058 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 60635058 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 60635058 # number of overall hits +system.cpu.icache.overall_hits::total 60635058 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 856010 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 856010 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 856010 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 856010 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 856010 # number of overall misses +system.cpu.icache.overall_misses::total 856010 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11542526000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11542526000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11542526000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11542526000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11542526000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11542526000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 61491068 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 61491068 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 61491068 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 61491068 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 61491068 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 61491068 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013921 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.013921 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.013921 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.013921 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.013921 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.013921 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13484.101821 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13484.101821 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13484.101821 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13484.101821 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13484.101821 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13484.101821 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -186,112 +344,112 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856407 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 856407 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 856407 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 856407 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 856407 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 856407 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9851662500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9851662500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9851662500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9851662500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9851662500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9851662500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 353004500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 353004500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 353004500 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 353004500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013926 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013926 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013926 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.013926 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013926 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.013926 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11503.481989 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11503.481989 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11503.481989 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11503.481989 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11503.481989 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11503.481989 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856010 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 856010 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 856010 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 856010 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 856010 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 856010 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9830506000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9830506000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9830506000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9830506000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9830506000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9830506000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 288141500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 288141500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 288141500 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 288141500 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013921 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013921 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013921 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.013921 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013921 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.013921 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11484.101821 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11484.101821 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11484.101821 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11484.101821 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11484.101821 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11484.101821 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 627232 # number of replacements -system.cpu.dcache.tagsinuse 511.878513 # Cycle average of tags in use -system.cpu.dcache.total_refs 23656893 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 627744 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 37.685574 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 653137000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.878513 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999763 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999763 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13196266 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13196266 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 9973744 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 9973744 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 236294 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 236294 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247690 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247690 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 23170010 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 23170010 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 23170010 # number of overall hits -system.cpu.dcache.overall_hits::total 23170010 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 368699 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 368699 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 250547 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 250547 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 11397 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 11397 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 619246 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 619246 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 619246 # number of overall misses -system.cpu.dcache.overall_misses::total 619246 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5200667500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5200667500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8968842000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8968842000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 154755000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 154755000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 14169509500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 14169509500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 14169509500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 14169509500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13564965 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13564965 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10224291 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10224291 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247691 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 247691 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 247690 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 247690 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 23789256 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 23789256 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 23789256 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 23789256 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027180 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.027180 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024505 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.024505 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046013 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046013 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.026030 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.026030 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.026030 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.026030 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14105.455941 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14105.455941 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35797.044068 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35797.044068 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13578.573309 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13578.573309 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22881.874893 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22881.874893 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22881.874893 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22881.874893 # average overall miss latency +system.cpu.dcache.replacements 627255 # number of replacements +system.cpu.dcache.tagsinuse 511.914823 # Cycle average of tags in use +system.cpu.dcache.total_refs 23654861 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 627767 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 37.680956 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 460735000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.914823 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999834 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999834 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 13195024 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13195024 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 9972994 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 9972994 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 236273 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 236273 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247672 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247672 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 23168018 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 23168018 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 23168018 # number of overall hits +system.cpu.dcache.overall_hits::total 23168018 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 368763 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 368763 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 250502 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 250502 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 11400 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 11400 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 619265 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 619265 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 619265 # number of overall misses +system.cpu.dcache.overall_misses::total 619265 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5206335000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5206335000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8061427000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8061427000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 154571000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 154571000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 13267762000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 13267762000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 13267762000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 13267762000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13563787 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13563787 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10223496 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10223496 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247673 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 247673 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247672 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247672 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 23787283 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 23787283 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 23787283 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 23787283 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027187 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.027187 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024503 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.024503 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046028 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046028 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.026033 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.026033 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.026033 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.026033 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14118.376844 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14118.376844 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 32181.088375 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 32181.088375 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13558.859649 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13558.859649 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 21425.015139 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 21425.015139 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 21425.015139 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 21425.015139 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -300,54 +458,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 595999 # number of writebacks -system.cpu.dcache.writebacks::total 595999 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368699 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 368699 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250547 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 250547 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11397 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 11397 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 619246 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 619246 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 619246 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 619246 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4463269500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4463269500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8467748000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8467748000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 131961000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 131961000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12931017500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12931017500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12931017500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12931017500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182084322500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182084322500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41323476000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41323476000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 223407798500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 223407798500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027180 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027180 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024505 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024505 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046013 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046013 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026030 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.026030 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026030 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.026030 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12105.455941 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12105.455941 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33797.044068 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33797.044068 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11578.573309 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11578.573309 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20881.874893 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20881.874893 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20881.874893 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20881.874893 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 596013 # number of writebacks +system.cpu.dcache.writebacks::total 596013 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368763 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 368763 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250502 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 250502 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11400 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 11400 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 619265 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 619265 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 619265 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 619265 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4468809000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4468809000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7560423000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7560423000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 131771000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 131771000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12029232000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12029232000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12029232000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12029232000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182087740500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182087740500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 18708092000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 18708092000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 200795832500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 200795832500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027187 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027187 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024503 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024503 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046028 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046028 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026033 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.026033 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026033 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.026033 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12118.376844 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12118.376844 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30181.088375 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30181.088375 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11558.859649 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11558.859649 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19425.015139 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19425.015139 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19425.015139 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19425.015139 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -355,141 +513,141 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 61916 # number of replacements -system.cpu.l2cache.tagsinuse 50867.720143 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1683066 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 127296 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 13.221672 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 2574019400000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 37864.952088 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.dtb.walker 3.885583 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.001416 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 6985.681192 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 6013.199864 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.577773 # Average percentage of cache occupancy +system.cpu.l2cache.replacements 61906 # number of replacements +system.cpu.l2cache.tagsinuse 50893.840844 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1682731 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 127288 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 13.219871 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 2553095647000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 37868.665500 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.dtb.walker 3.885586 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.001398 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 6995.476724 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 6025.811636 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.577830 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.106593 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.091754 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.776180 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8772 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3549 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 844153 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 370237 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1226711 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 595999 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 595999 # number of Writeback hits +system.cpu.l2cache.occ_percent::cpu.inst 0.106743 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.091947 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.776578 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8702 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3548 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 843786 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 370305 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1226341 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 596013 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 596013 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 114469 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 114469 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 8772 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 3549 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 844153 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 484706 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1341180 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 8772 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 3549 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 844153 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 484706 # number of overall hits -system.cpu.l2cache.overall_hits::total 1341180 # number of overall hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 114418 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 114418 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 8702 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 3548 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 843786 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 484723 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1340759 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 8702 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 3548 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 843786 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 484723 # number of overall hits +system.cpu.l2cache.overall_hits::total 1340759 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 10615 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 9859 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 20482 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 2873 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2873 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 133179 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133179 # number of ReadExReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 10599 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 9858 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 20465 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 2872 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 2872 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 133186 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 133186 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 10615 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 143038 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 153661 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 10599 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 143044 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 153651 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 5 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 10615 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 143038 # number of overall misses -system.cpu.l2cache.overall_misses::total 153661 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 261500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 156000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 552086500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 512764500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1065268500 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1041000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 1041000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6925666500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6925666500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 261500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 156000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 552086500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7438431000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 7990935000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 261500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 156000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 552086500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7438431000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 7990935000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8777 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3552 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 854768 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 380096 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1247193 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 595999 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 595999 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2899 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2899 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 247648 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 247648 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 8777 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 3552 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 854768 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 627744 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1494841 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 8777 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 3552 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 854768 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 627744 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1494841 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000570 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_misses::cpu.inst 10599 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 143044 # number of overall misses +system.cpu.l2cache.overall_misses::total 153651 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 287500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 137000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 535011000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 517367000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1052802500 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 460000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 460000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6102272500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6102272500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 287500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 137000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 535011000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6619639500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 7155075000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 287500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 137000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 535011000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6619639500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 7155075000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8707 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3551 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 854385 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 380163 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1246806 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 596013 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 596013 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2898 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2898 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 247604 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 247604 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 8707 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 3551 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 854385 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 627767 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1494410 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 8707 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 3551 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 854385 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 627767 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1494410 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000574 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000845 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012419 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025938 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.016422 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991031 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991031 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.537775 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.537775 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000570 # miss rate for demand accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012405 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025931 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.016414 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991028 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991028 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.537899 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.537899 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000574 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000845 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012419 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.227860 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.102794 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000570 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012405 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.227862 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.102817 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000574 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000845 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012419 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.227860 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.102794 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 52300 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52010.032972 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52009.788011 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52009.984377 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 362.339018 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 362.339018 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52002.691866 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52002.691866 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 52300 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52010.032972 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52003.180973 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52003.663910 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 52300 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52010.032972 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52003.180973 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52003.663910 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012405 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.227862 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.102817 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 57500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 45666.666667 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50477.497877 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52481.943599 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 51444.050818 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 160.167131 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 160.167131 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 45817.672278 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 45817.672278 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 57500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 45666.666667 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50477.497877 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46276.946254 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 46567.057813 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 57500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 45666.666667 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50477.497877 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46276.946254 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 46567.057813 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -498,92 +656,92 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 57455 # number of writebacks -system.cpu.l2cache.writebacks::total 57455 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 57461 # number of writebacks +system.cpu.l2cache.writebacks::total 57461 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 5 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10615 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 9859 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 20482 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2873 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 2873 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133179 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 133179 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10599 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 9858 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 20465 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2872 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 2872 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133186 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 133186 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 5 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 10615 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 143038 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 153661 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 10599 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 143044 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 153651 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 5 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 10615 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 143038 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 153661 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 200000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 120000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 424634000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 394375000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 819329000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 114934000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 114934000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5327448000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5327448000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 200000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 120000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 424634000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5721823000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6146777000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 200000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 120000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 424634000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5721823000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6146777000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 264840000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166685236000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166950076000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 31792706500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 31792706500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 264840000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 198477942500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 198742782500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000570 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 10599 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 143044 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 153651 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 224010 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 98006 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 397346579 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 389320096 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 786988691 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 28812314 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 28812314 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4371883715 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4371883715 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 224010 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 98006 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 397346579 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4761203811 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 5158872406 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 224010 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 98006 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 397346579 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4761203811 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 5158872406 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 197466551 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166688827565 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166886294116 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 9174375606 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 9174375606 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 197466551 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 175863203171 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 176060669722 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012419 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025938 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016422 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991031 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991031 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.537775 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.537775 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000570 # mshr miss rate for demand accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012405 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025931 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016414 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991028 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991028 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.537899 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.537899 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012419 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.227860 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.102794 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000570 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012405 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.227862 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.102817 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012419 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.227860 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.102794 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40003.203015 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40001.521452 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40002.392344 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40004.872955 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40004.872955 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40002.162503 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40002.162503 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40003.203015 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40002.118318 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40002.193139 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40003.203015 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40002.118318 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40002.193139 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012405 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.227862 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.102817 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 44802 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 32668.666667 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37489.063025 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39492.807466 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38455.347716 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10032.142758 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10032.142758 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 32825.399929 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 32825.399929 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 44802 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 32668.666667 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37489.063025 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33284.890041 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33575.260857 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 44802 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 32668.666667 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37489.063025 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33284.890041 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33575.260857 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -607,10 +765,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1246144703911 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1246144703911 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1246144703911 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1246144703911 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1052670853165 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1052670853165 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1052670853165 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1052670853165 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency |