diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-15 08:12:21 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-15 08:12:21 -0400 |
| commit | d52adc4eb68c2733f9af4ac68834583c0a555f9d (patch) | |
| tree | 2ee5c3d271af63a3ef527c54950f57f406a05d90 /tests/quick/fs/10.linux-boot/ref/arm/linux | |
| parent | 88554790c34f6fef4ba6285927fb9742b90ab258 (diff) | |
| download | gem5-d52adc4eb68c2733f9af4ac68834583c0a555f9d.tar.xz | |
Stats: Update stats for cache timings in cycles
This patch updates the stats to reflect the change in how cache
latencies are expressed. In addition, the latencies are now rounded to
multiples of the clock period, thus also affecting other stats.
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm/linux')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt | 1880 | ||||
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt | 370 |
2 files changed, 1112 insertions, 1138 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 0ffcacbe4..0a013f420 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,75 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.207291 # Number of seconds simulated -sim_ticks 1207290627000 # Number of ticks simulated -final_tick 1207290627000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.203695 # Number of seconds simulated +sim_ticks 1203694548000 # Number of ticks simulated +final_tick 1203694548000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 648322 # Simulator instruction rate (inst/s) -host_op_rate 826248 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 12731770448 # Simulator tick rate (ticks/s) -host_mem_usage 380152 # Number of bytes of host memory used -host_seconds 94.83 # Real time elapsed on the host -sim_insts 61477134 # Number of instructions simulated -sim_ops 78349023 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::realview.clcd 52642784 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 394084 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4718772 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 323100 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4791152 # Number of bytes read from this memory -system.physmem.bytes_read::total 62870404 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 394084 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 323100 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 717184 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4105920 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7133264 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 6580348 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 12376 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 73803 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 5130 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 74888 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6746553 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 64155 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 820991 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43604069 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 53 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 106 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 326420 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3908563 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 212 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 53 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 267624 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 3968516 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52075617 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 326420 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 267624 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 594044 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3400938 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 14081 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2493471 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 5908490 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3400938 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43604069 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 53 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 106 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 326420 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3922645 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 212 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 53 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 267624 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 6461987 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 57984106 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 610810 # Simulator instruction rate (inst/s) +host_op_rate 778429 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 11963163223 # Simulator tick rate (ticks/s) +host_mem_usage 383784 # Number of bytes of host memory used +host_seconds 100.62 # Real time elapsed on the host +sim_insts 61457649 # Number of instructions simulated +sim_ops 78322983 # Number of ops (including micro ops) simulated system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -88,251 +29,292 @@ system.realview.nvmem.bw_inst_read::total 56 # I system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 56 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 69267 # number of replacements -system.l2c.tagsinuse 52917.687101 # Cycle average of tags in use -system.l2c.total_refs 1645693 # Total number of references to valid blocks. -system.l2c.sampled_refs 134464 # Sample count of references to valid blocks. -system.l2c.avg_refs 12.238912 # Average number of references to valid blocks. +system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 354404 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4259252 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 364636 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5307760 # Number of bytes read from this memory +system.physmem.bytes_read::total 62191012 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 354404 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 364636 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 719040 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4163840 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory +system.physmem.bytes_written::total 7191184 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 11756 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 66623 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 5779 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 82960 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6655189 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 65060 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory +system.physmem.num_writes::total 821896 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43120999 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 53 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 160 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 294430 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3538482 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 160 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 302931 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4409557 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51666772 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 294430 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 302931 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 597361 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3459216 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 14123 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2500920 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 5974260 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3459216 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43120999 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 53 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 160 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 294430 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3552606 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 302931 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 6910477 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 57641032 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 70187 # number of replacements +system.l2c.tagsinuse 53228.642974 # Cycle average of tags in use +system.l2c.total_refs 1643789 # Total number of references to valid blocks. +system.l2c.sampled_refs 135350 # Sample count of references to valid blocks. +system.l2c.avg_refs 12.144728 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 40124.661917 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 0.000403 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.001466 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 3720.854167 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 4213.259554 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 2.746626 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.itb.walker 0.001732 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 2800.295591 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 2055.865645 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.612254 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 40454.040636 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 0.000402 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 0.003088 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 3394.914064 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 2735.381228 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 2.669984 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 3118.851455 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 3522.782116 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.617280 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.056776 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.064289 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.042729 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.031370 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.807460 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 4114 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 1841 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 402307 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 205875 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 5723 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1959 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 449970 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 144091 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1215880 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 572580 # number of Writeback hits -system.l2c.Writeback_hits::total 572580 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1130 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 572 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1702 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 212 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 104 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 316 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 56723 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 53017 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 109740 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 4114 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 1841 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 402307 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 262598 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 5723 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 1959 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 449970 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 197108 # number of demand (read+write) hits -system.l2c.demand_hits::total 1325620 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 4114 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 1841 # number of overall hits -system.l2c.overall_hits::cpu0.inst 402307 # number of overall hits -system.l2c.overall_hits::cpu0.data 262598 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 5723 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 1959 # number of overall hits -system.l2c.overall_hits::cpu1.inst 449970 # number of overall hits -system.l2c.overall_hits::cpu1.data 197108 # number of overall hits -system.l2c.overall_hits::total 1325620 # number of overall hits +system.l2c.occ_percent::cpu0.inst 0.051802 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.041739 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.dtb.walker 0.000041 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.047590 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.053753 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.812205 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 2523 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 1490 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 278283 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 124654 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 5208 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 1502 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 576279 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 223386 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1213325 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 571443 # number of Writeback hits +system.l2c.Writeback_hits::total 571443 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 992 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 888 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1880 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 191 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 95 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 286 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 39230 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 70245 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 109475 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 2523 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 1490 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 278283 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 163884 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 5208 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 1502 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 576279 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 293631 # number of demand (read+write) hits +system.l2c.demand_hits::total 1322800 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 2523 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 1490 # number of overall hits +system.l2c.overall_hits::cpu0.inst 278283 # number of overall hits +system.l2c.overall_hits::cpu0.data 163884 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 5208 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 1502 # number of overall hits +system.l2c.overall_hits::cpu1.inst 576279 # number of overall hits +system.l2c.overall_hits::cpu1.data 293631 # number of overall hits +system.l2c.overall_hits::total 1322800 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 5744 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 7874 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 4 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 5043 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 3639 # number of ReadReq misses -system.l2c.ReadReq_misses::total 22308 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 4704 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 3584 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 8288 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 569 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 485 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1054 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 67193 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 72340 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 139533 # number of ReadExReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 5124 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6001 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 3 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 5692 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 5607 # number of ReadReq misses +system.l2c.ReadReq_misses::total 22431 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 4012 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 4909 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 8921 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 655 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 388 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1043 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 61449 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 78839 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 140288 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 5744 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 75067 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 4 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 5043 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 75979 # number of demand (read+write) misses -system.l2c.demand_misses::total 161841 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 5124 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 67450 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 3 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 5692 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 84446 # number of demand (read+write) misses +system.l2c.demand_misses::total 162719 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 5744 # number of overall misses -system.l2c.overall_misses::cpu0.data 75067 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 4 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 5043 # number of overall misses -system.l2c.overall_misses::cpu1.data 75979 # number of overall misses -system.l2c.overall_misses::total 161841 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses +system.l2c.overall_misses::cpu0.inst 5124 # number of overall misses +system.l2c.overall_misses::cpu0.data 67450 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 3 # number of overall misses +system.l2c.overall_misses::cpu1.inst 5692 # number of overall misses +system.l2c.overall_misses::cpu1.data 84446 # number of overall misses +system.l2c.overall_misses::total 162719 # number of overall misses system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 52000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 104000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 298939500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 409670500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 208500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 52500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 263172000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 189494500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1161693500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 30053000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 27343000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 57396000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 3692000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 6036000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 9728000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 3494513965 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 3764719994 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7259233959 # number of ReadExReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 156500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 268094000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 313174000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 160000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 298650000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 293295000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1173581500 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 15964999 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 31408500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 47373499 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1462500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 6173000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 7635500 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 3221682991 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 4131389996 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7353072987 # number of ReadExReq miss cycles system.l2c.demand_miss_latency::cpu0.dtb.walker 52000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 104000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 298939500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 3904184465 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 208500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 52500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 263172000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 3954214494 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 8420927459 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 156500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 268094000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 3534856991 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 160000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 298650000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 4424684996 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 8526654487 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu0.dtb.walker 52000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 104000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 298939500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 3904184465 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 208500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 52500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 263172000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 3954214494 # number of overall miss cycles -system.l2c.overall_miss_latency::total 8420927459 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 4115 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 1843 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 408051 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 213749 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 5727 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 1960 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 455013 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 147730 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1238188 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 572580 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 572580 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 5834 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 4156 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 9990 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 781 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 589 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1370 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 123916 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 125357 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 249273 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 4115 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 1843 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 408051 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 337665 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 5727 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 1960 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 455013 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 273087 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1487461 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 4115 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 1843 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 408051 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 337665 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 5727 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 1960 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 455013 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 273087 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1487461 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000243 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001085 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.014077 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.036838 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000698 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000510 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.011083 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.024633 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.018017 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.806308 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.862368 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.829630 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.728553 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.823430 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.769343 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.542246 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.577072 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.559760 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000243 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.001085 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.014077 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.222312 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000698 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.000510 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.011083 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.278223 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.108804 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000243 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.001085 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.014077 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.222312 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000698 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.000510 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.011083 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.278223 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.108804 # miss rate for overall accesses +system.l2c.overall_miss_latency::cpu0.itb.walker 156500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 268094000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 3534856991 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 160000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 298650000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 4424684996 # number of overall miss cycles +system.l2c.overall_miss_latency::total 8526654487 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 2524 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 1493 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 283407 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 130655 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 5211 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 1502 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 581971 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 228993 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1235756 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 571443 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 571443 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 5004 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 5797 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 10801 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 846 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 483 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1329 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 100679 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 149084 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 249763 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 2524 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 1493 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 283407 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 231334 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 5211 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 1502 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 581971 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 378077 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1485519 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 2524 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 1493 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 283407 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 231334 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 5211 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 1502 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 581971 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 378077 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1485519 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000396 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.002009 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.018080 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.045930 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000576 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.009781 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.024485 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.018152 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.801759 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.846817 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.825942 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.774232 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.803313 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.784801 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.610346 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.528823 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.561684 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000396 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.002009 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.018080 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.291570 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000576 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.009781 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.223357 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.109537 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000396 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.002009 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.018080 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.291570 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000576 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.009781 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.223357 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.109537 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 52000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52043.784819 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 52028.257557 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52125 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 52500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52185.603807 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 52073.234405 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52075.197239 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6388.818027 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 7629.185268 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 6925.193050 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6488.576450 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 12445.360825 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 9229.601518 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52007.113315 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52042.023694 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52025.212380 # average ReadExReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 52166.666667 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52321.233411 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 52186.968839 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 53333.333333 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52468.376669 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 52308.721241 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52319.624627 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3979.311815 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6398.146262 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 5310.335052 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2232.824427 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 15909.793814 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 7320.709492 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52428.566632 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52402.871624 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52414.126561 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 52000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 52043.784819 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 52009.331197 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52125 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 52500 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 52185.603807 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 52043.518525 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52032.102242 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 52166.666667 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 52321.233411 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 52407.071772 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 53333.333333 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 52468.376669 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 52396.620278 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52401.099361 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 52000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 52043.784819 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 52009.331197 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52125 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 52500 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 52185.603807 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 52043.518525 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52032.102242 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 52166.666667 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 52321.233411 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 52407.071772 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 53333.333333 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 52468.376669 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 52396.620278 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52401.099361 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -341,8 +323,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 64155 # number of writebacks -system.l2c.writebacks::total 64155 # number of writebacks +system.l2c.writebacks::writebacks 65060 # number of writebacks +system.l2c.writebacks::total 65060 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits @@ -350,162 +332,150 @@ system.l2c.demand_mshr_hits::total 1 # nu system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 5743 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 7874 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 4 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 5043 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 3639 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 22307 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 4704 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 3584 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 8288 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 569 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 485 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1054 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 67193 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 72340 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 139533 # number of ReadExReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 3 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 5123 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 6001 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 3 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 5692 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 5607 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 22430 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 4012 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 4909 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 8921 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 655 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 388 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1043 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 61449 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 78839 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 140288 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu0.dtb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 5743 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 75067 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 4 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 5043 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 75979 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 161840 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 3 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 5123 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 67450 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 3 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 5692 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 84446 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 162718 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0.dtb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 5743 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 75067 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 4 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 5043 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 75979 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 161840 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 3 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 5123 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 67450 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 3 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 5692 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 84446 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 162718 # number of overall MSHR misses system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 40000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 80000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 229995000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 315180000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 160000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 40000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 202652000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 145824000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 893971000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 188550000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 143713000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 332263000 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 22778000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 19436000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 42214000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2688153000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2896625000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5584778000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 120000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 204994000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 240097000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 124000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 228616000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 224783500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 898774500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 160670998 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 196506499 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 357177497 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 26201999 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 15527999 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 41729998 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2458624491 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3165174496 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5623798987 # number of ReadExReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 40000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 80000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 229995000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 3003333000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 160000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 40000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 202652000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 3042449000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 6478749000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 120000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 204994000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 2698721491 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 124000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 228616000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 3389957996 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 6522573487 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 40000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 80000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 229995000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 3003333000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 160000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 40000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 202652000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 3042449000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 6478749000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 120000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 204994000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 2698721491 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 124000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 228616000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 3389957996 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 6522573487 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 265520000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12448669498 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3961000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154365762499 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 167083912997 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1128303000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 30843801500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 31972104500 # number of WriteReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 11136775500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3961500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 155704815500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 167111072500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1070730500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 30910255000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 31980985500 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 265520000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13576972498 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3961000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 185209563999 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 199056017497 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000243 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001085 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014074 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036838 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000698 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000510 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.011083 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.024633 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.018016 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.806308 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.862368 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.829630 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.728553 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.823430 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.769343 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.542246 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.577072 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.559760 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000243 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001085 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014074 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.222312 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000698 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000510 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011083 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.278223 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.108803 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000243 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001085 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014074 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.222312 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000698 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000510 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011083 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.278223 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.108803 # mshr miss rate for overall accesses +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 12207506000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3961500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 186615070500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 199092058000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000396 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.002009 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.018076 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.045930 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000576 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009781 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.024485 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.018151 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.801759 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.846817 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.825942 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.774232 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.803313 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.784801 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.610346 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.528823 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.561684 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000396 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.002009 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018076 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.291570 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000576 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009781 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.223357 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.109536 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000396 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.002009 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018076 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.291570 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000576 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009781 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.223357 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.109536 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40047.884381 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40027.940056 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40184.810629 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40072.547403 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40075.805801 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40082.908163 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40098.493304 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40089.647683 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40031.634446 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40074.226804 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40051.233397 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40006.444124 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40041.816422 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40024.782668 # average ReadExReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40014.444661 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40009.498417 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 41333.333333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40164.441321 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40089.798466 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40070.196166 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40047.606680 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40029.842942 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40037.831745 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40003.051908 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40020.615979 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40009.585810 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40010.813699 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40147.319169 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40087.526994 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40047.884381 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40008.698896 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40184.810629 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40043.288277 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40031.815373 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40014.444661 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40010.696679 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 41333.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40164.441321 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40143.499941 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40085.138012 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40047.884381 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40008.698896 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40184.810629 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40043.288277 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40031.815373 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40014.444661 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40010.696679 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 41333.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40164.441321 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40143.499941 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40085.138012 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -528,27 +498,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7076084 # DTB read hits -system.cpu0.dtb.read_misses 3743 # DTB read misses -system.cpu0.dtb.write_hits 5660386 # DTB write hits -system.cpu0.dtb.write_misses 804 # DTB write misses +system.cpu0.dtb.read_hits 4800541 # DTB read hits +system.cpu0.dtb.read_misses 2116 # DTB read misses +system.cpu0.dtb.write_hits 4101169 # DTB write hits +system.cpu0.dtb.write_misses 405 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1791 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 1539 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 141 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 91 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7079827 # DTB read accesses -system.cpu0.dtb.write_accesses 5661190 # DTB write accesses +system.cpu0.dtb.perms_faults 203 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 4802657 # DTB read accesses +system.cpu0.dtb.write_accesses 4101574 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12736470 # DTB hits -system.cpu0.dtb.misses 4547 # DTB misses -system.cpu0.dtb.accesses 12741017 # DTB accesses -system.cpu0.itb.inst_hits 29574655 # ITB inst hits -system.cpu0.itb.inst_misses 2205 # ITB inst misses +system.cpu0.dtb.hits 8901710 # DTB hits +system.cpu0.dtb.misses 2521 # DTB misses +system.cpu0.dtb.accesses 8904231 # DTB accesses +system.cpu0.itb.inst_hits 19425295 # ITB inst hits +system.cpu0.itb.inst_misses 1350 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -557,86 +527,86 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1332 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1347 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 29576860 # ITB inst accesses -system.cpu0.itb.hits 29574655 # DTB hits -system.cpu0.itb.misses 2205 # DTB misses -system.cpu0.itb.accesses 29576860 # DTB accesses -system.cpu0.numCycles 2414581254 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 19426645 # ITB inst accesses +system.cpu0.itb.hits 19425295 # DTB hits +system.cpu0.itb.misses 1350 # DTB misses +system.cpu0.itb.accesses 19426645 # DTB accesses +system.cpu0.numCycles 2405961611 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 28876799 # Number of instructions committed -system.cpu0.committedOps 37228975 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 33114839 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses -system.cpu0.num_func_calls 1241592 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4373527 # number of instructions that are conditional controls -system.cpu0.num_int_insts 33114839 # number of integer instructions -system.cpu0.num_fp_insts 3860 # number of float instructions -system.cpu0.num_int_register_reads 190147140 # number of times the integer registers were read -system.cpu0.num_int_register_writes 36238708 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written -system.cpu0.num_mem_refs 13404188 # number of memory refs -system.cpu0.num_load_insts 7413537 # Number of load instructions -system.cpu0.num_store_insts 5990651 # Number of store instructions -system.cpu0.num_idle_cycles 2267023582.330122 # Number of idle cycles -system.cpu0.num_busy_cycles 147557671.669878 # Number of busy cycles -system.cpu0.not_idle_fraction 0.061111 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.938889 # Percentage of idle cycles +system.cpu0.committedInsts 19048182 # Number of instructions committed +system.cpu0.committedOps 25051772 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 22684080 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 4364 # Number of float alu accesses +system.cpu0.num_func_calls 868675 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 2620305 # number of instructions that are conditional controls +system.cpu0.num_int_insts 22684080 # number of integer instructions +system.cpu0.num_fp_insts 4364 # number of float instructions +system.cpu0.num_int_register_reads 128950966 # number of times the integer registers were read +system.cpu0.num_int_register_writes 23731370 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3980 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 384 # number of times the floating registers were written +system.cpu0.num_mem_refs 9388163 # number of memory refs +system.cpu0.num_load_insts 5047859 # Number of load instructions +system.cpu0.num_store_insts 4340304 # Number of store instructions +system.cpu0.num_idle_cycles 2301502404.823749 # Number of idle cycles +system.cpu0.num_busy_cycles 104459206.176251 # Number of busy cycles +system.cpu0.not_idle_fraction 0.043417 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.956583 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 46683 # number of quiesce instructions executed -system.cpu0.icache.replacements 408135 # number of replacements -system.cpu0.icache.tagsinuse 509.469782 # Cycle average of tags in use -system.cpu0.icache.total_refs 29165991 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 408647 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 71.372091 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 75845657000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 509.469782 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.995058 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.995058 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 29165991 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 29165991 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 29165991 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 29165991 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 29165991 # number of overall hits -system.cpu0.icache.overall_hits::total 29165991 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 408647 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 408647 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 408647 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 408647 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 408647 # number of overall misses -system.cpu0.icache.overall_misses::total 408647 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6096279000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6096279000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 6096279000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6096279000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 6096279000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6096279000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 29574638 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 29574638 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 29574638 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 29574638 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 29574638 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 29574638 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013817 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.013817 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013817 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.013817 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013817 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.013817 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14918.203241 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14918.203241 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14918.203241 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14918.203241 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14918.203241 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14918.203241 # average overall miss latency +system.cpu0.kern.inst.quiesce 34020 # number of quiesce instructions executed +system.cpu0.icache.replacements 283184 # number of replacements +system.cpu0.icache.tagsinuse 509.502628 # Cycle average of tags in use +system.cpu0.icache.total_refs 19141582 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 283696 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 67.472160 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 75588601000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 509.502628 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.995122 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.995122 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 19141582 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 19141582 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 19141582 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 19141582 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 19141582 # number of overall hits +system.cpu0.icache.overall_hits::total 19141582 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 283696 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 283696 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 283696 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 283696 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 283696 # number of overall misses +system.cpu0.icache.overall_misses::total 283696 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 3929923500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 3929923500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 3929923500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 3929923500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 3929923500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 3929923500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 19425278 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 19425278 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 19425278 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 19425278 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 19425278 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 19425278 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014604 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014604 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014604 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014604 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014604 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014604 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13852.586924 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13852.586924 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13852.586924 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13852.586924 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13852.586924 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13852.586924 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -645,120 +615,120 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 408647 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 408647 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 408647 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 408647 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 408647 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 408647 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4869493500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4869493500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4869493500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4869493500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4869493500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4869493500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 351814000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 351814000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 351814000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 351814000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013817 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013817 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013817 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.013817 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013817 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.013817 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11916.136666 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11916.136666 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11916.136666 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11916.136666 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11916.136666 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11916.136666 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 283696 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 283696 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 283696 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 283696 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 283696 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 283696 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 3362531500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 3362531500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 3362531500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 3362531500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 3362531500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 3362531500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 353907000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 353907000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 353907000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 353907000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014604 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014604 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014604 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014604 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014604 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014604 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11852.586924 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11852.586924 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11852.586924 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11852.586924 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11852.586924 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11852.586924 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 330734 # number of replacements -system.cpu0.dcache.tagsinuse 459.649702 # Cycle average of tags in use -system.cpu0.dcache.total_refs 12280871 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 331246 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 37.074775 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 664264000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 459.649702 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.897753 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.897753 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6605687 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6605687 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5355220 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5355220 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147939 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 147939 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149683 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 149683 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 11960907 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 11960907 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11960907 # number of overall hits -system.cpu0.dcache.overall_hits::total 11960907 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 228053 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 228053 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 141722 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 141722 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9325 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 9325 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7497 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7497 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 369775 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 369775 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 369775 # number of overall misses -system.cpu0.dcache.overall_misses::total 369775 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3443058000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 3443058000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4918727500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 4918727500 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 100897000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 100897000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 74611000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 74611000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 8361785500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 8361785500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 8361785500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 8361785500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6833740 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6833740 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5496942 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5496942 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157264 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 157264 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157180 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 157180 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12330682 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12330682 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12330682 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12330682 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033372 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.033372 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025782 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.025782 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059295 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059295 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047697 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047697 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029988 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.029988 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029988 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.029988 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15097.622044 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15097.622044 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34706.873315 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 34706.873315 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10820.053619 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10820.053619 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9952.114179 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9952.114179 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 22613.171523 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 22613.171523 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 22613.171523 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 22613.171523 # average overall miss latency +system.cpu0.dcache.replacements 220187 # number of replacements +system.cpu0.dcache.tagsinuse 456.524851 # Cycle average of tags in use +system.cpu0.dcache.total_refs 8560144 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 220557 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 38.811482 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 656029000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 456.524851 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.891650 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.891650 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 4452407 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 4452407 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3852535 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3852535 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 117731 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 117731 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 117849 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 117849 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 8304942 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 8304942 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 8304942 # number of overall hits +system.cpu0.dcache.overall_hits::total 8304942 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 146461 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 146461 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 116958 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 116958 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 7880 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 7880 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7697 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7697 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 263419 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 263419 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 263419 # number of overall misses +system.cpu0.dcache.overall_misses::total 263419 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 1991314500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 1991314500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4199641500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 4199641500 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 70263500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 70263500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 66334500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 66334500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 6190956000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 6190956000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 6190956000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 6190956000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 4598868 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 4598868 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 3969493 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 3969493 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 125611 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 125611 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 125546 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 125546 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 8568361 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 8568361 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 8568361 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 8568361 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.031847 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.031847 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.029464 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.029464 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.062733 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.062733 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.061308 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.061308 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.030743 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.030743 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.030743 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.030743 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13596.209913 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13596.209913 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35907.261581 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 35907.261581 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 8916.687817 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 8916.687817 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8618.227881 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 8618.227881 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 23502.313804 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 23502.313804 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23502.313804 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 23502.313804 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -767,66 +737,66 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 306480 # number of writebacks -system.cpu0.dcache.writebacks::total 306480 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 228053 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 228053 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141722 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 141722 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9325 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9325 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7489 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7489 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 369775 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 369775 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 369775 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 369775 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2758303642 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2758303642 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4493366071 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4493366071 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 72896006 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 72896006 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 52131016 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 52131016 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1001 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1001 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7251669713 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 7251669713 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7251669713 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 7251669713 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13559876000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13559876000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1253192500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1253192500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14813068500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14813068500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033372 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033372 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025782 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025782 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059295 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059295 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047646 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047646 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029988 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029988 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029988 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.029988 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12095.011432 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12095.011432 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31705.494355 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31705.494355 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7817.266059 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7817.266059 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6961.011617 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6961.011617 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 204960 # number of writebacks +system.cpu0.dcache.writebacks::total 204960 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 146461 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 146461 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 116958 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 116958 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 7880 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7880 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7695 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7695 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 263419 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 263419 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 263419 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 263419 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 1698392500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 1698392500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3965725500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3965725500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 54503500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 54503500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 50946500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 50946500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 5664118000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 5664118000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 5664118000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 5664118000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 12130688000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 12130688000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1193496500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1193496500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 13324184500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 13324184500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.031847 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.031847 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.029464 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.029464 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.062733 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.062733 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.061292 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.061292 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030743 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.030743 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030743 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.030743 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11596.209913 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11596.209913 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33907.261581 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33907.261581 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 6916.687817 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6916.687817 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6620.727745 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6620.727745 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19611.032961 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19611.032961 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19611.032961 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19611.032961 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21502.313804 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21502.313804 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21502.313804 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21502.313804 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -836,27 +806,27 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 8318170 # DTB read hits -system.cpu1.dtb.read_misses 3663 # DTB read misses -system.cpu1.dtb.write_hits 5832653 # DTB write hits -system.cpu1.dtb.write_misses 1435 # DTB write misses +system.cpu1.dtb.read_hits 10590618 # DTB read hits +system.cpu1.dtb.read_misses 5230 # DTB read misses +system.cpu1.dtb.write_hits 7384755 # DTB write hits +system.cpu1.dtb.write_misses 1835 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1968 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 2257 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 142 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 194 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 8321833 # DTB read accesses -system.cpu1.dtb.write_accesses 5834088 # DTB write accesses +system.cpu1.dtb.perms_faults 249 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 10595848 # DTB read accesses +system.cpu1.dtb.write_accesses 7386590 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 14150823 # DTB hits -system.cpu1.dtb.misses 5098 # DTB misses -system.cpu1.dtb.accesses 14155921 # DTB accesses -system.cpu1.itb.inst_hits 33211066 # ITB inst hits -system.cpu1.itb.inst_misses 2171 # ITB inst misses +system.cpu1.dtb.hits 17975373 # DTB hits +system.cpu1.dtb.misses 7065 # DTB misses +system.cpu1.dtb.accesses 17982438 # DTB accesses +system.cpu1.itb.inst_hits 43340388 # ITB inst hits +system.cpu1.itb.inst_misses 3017 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -865,86 +835,86 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1495 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1458 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 33213237 # ITB inst accesses -system.cpu1.itb.hits 33211066 # DTB hits -system.cpu1.itb.misses 2171 # DTB misses -system.cpu1.itb.accesses 33213237 # DTB accesses -system.cpu1.numCycles 2413083038 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 43343405 # ITB inst accesses +system.cpu1.itb.hits 43340388 # DTB hits +system.cpu1.itb.misses 3017 # DTB misses +system.cpu1.itb.accesses 43343405 # DTB accesses +system.cpu1.numCycles 2407389096 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 32600335 # Number of instructions committed -system.cpu1.committedOps 41120048 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 37342001 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses -system.cpu1.num_func_calls 963082 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3735102 # number of instructions that are conditional controls -system.cpu1.num_int_insts 37342001 # number of integer instructions -system.cpu1.num_fp_insts 6793 # number of float instructions -system.cpu1.num_int_register_reads 213831809 # number of times the integer registers were read -system.cpu1.num_int_register_writes 39482622 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written -system.cpu1.num_mem_refs 14689113 # number of memory refs -system.cpu1.num_load_insts 8640454 # Number of load instructions -system.cpu1.num_store_insts 6048659 # Number of store instructions -system.cpu1.num_idle_cycles 1863361359.722463 # Number of idle cycles -system.cpu1.num_busy_cycles 549721678.277537 # Number of busy cycles -system.cpu1.not_idle_fraction 0.227809 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.772191 # Percentage of idle cycles +system.cpu1.committedInsts 42409467 # Number of instructions committed +system.cpu1.committedOps 53271211 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 47739499 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 5457 # Number of float alu accesses +system.cpu1.num_func_calls 1335008 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 5483103 # number of instructions that are conditional controls +system.cpu1.num_int_insts 47739499 # number of integer instructions +system.cpu1.num_fp_insts 5457 # number of float instructions +system.cpu1.num_int_register_reads 274842107 # number of times the integer registers were read +system.cpu1.num_int_register_writes 51975033 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 3577 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1884 # number of times the floating registers were written +system.cpu1.num_mem_refs 18684058 # number of memory refs +system.cpu1.num_load_insts 11000639 # Number of load instructions +system.cpu1.num_store_insts 7683419 # Number of store instructions +system.cpu1.num_idle_cycles 1827105047.254482 # Number of idle cycles +system.cpu1.num_busy_cycles 580284048.745518 # Number of busy cycles +system.cpu1.not_idle_fraction 0.241043 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.758957 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 43948 # number of quiesce instructions executed -system.cpu1.icache.replacements 455071 # number of replacements -system.cpu1.icache.tagsinuse 479.019014 # Cycle average of tags in use -system.cpu1.icache.total_refs 32755479 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 455583 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 71.897940 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 94151388000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 479.019014 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.935584 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.935584 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 32755479 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 32755479 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 32755479 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 32755479 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 32755479 # number of overall hits -system.cpu1.icache.overall_hits::total 32755479 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 455583 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 455583 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 455583 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 455583 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 455583 # number of overall misses -system.cpu1.icache.overall_misses::total 455583 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6728250000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 6728250000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 6728250000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 6728250000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 6728250000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 6728250000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 33211062 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 33211062 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 33211062 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 33211062 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 33211062 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 33211062 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013718 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.013718 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013718 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.013718 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013718 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.013718 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14768.439560 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 14768.439560 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14768.439560 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 14768.439560 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14768.439560 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 14768.439560 # average overall miss latency +system.cpu1.kern.inst.quiesce 56706 # number of quiesce instructions executed +system.cpu1.icache.replacements 582628 # number of replacements +system.cpu1.icache.tagsinuse 479.068937 # Cycle average of tags in use +system.cpu1.icache.total_refs 42757244 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 583140 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 73.322434 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 92849627500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 479.068937 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.935682 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.935682 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 42757244 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 42757244 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 42757244 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 42757244 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 42757244 # number of overall hits +system.cpu1.icache.overall_hits::total 42757244 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 583140 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 583140 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 583140 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 583140 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 583140 # number of overall misses +system.cpu1.icache.overall_misses::total 583140 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7853505000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 7853505000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 7853505000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 7853505000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 7853505000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 7853505000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 43340384 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 43340384 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 43340384 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 43340384 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 43340384 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 43340384 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013455 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.013455 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013455 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.013455 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013455 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.013455 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13467.614981 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13467.614981 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13467.614981 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13467.614981 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13467.614981 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13467.614981 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -953,120 +923,120 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 455583 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 455583 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 455583 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 455583 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 455583 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 455583 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5360597500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5360597500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5360597500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5360597500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5360597500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5360597500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5250000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5250000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5250000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 5250000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013718 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013718 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013718 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.013718 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013718 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.013718 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11766.456387 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11766.456387 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11766.456387 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11766.456387 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11766.456387 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11766.456387 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 583140 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 583140 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 583140 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 583140 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 583140 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 583140 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6687225000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 6687225000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6687225000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 6687225000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6687225000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 6687225000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5251000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5251000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5251000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 5251000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013455 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013455 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013455 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.013455 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013455 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.013455 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11467.614981 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11467.614981 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11467.614981 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11467.614981 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11467.614981 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11467.614981 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 292605 # number of replacements -system.cpu1.dcache.tagsinuse 473.034237 # Cycle average of tags in use -system.cpu1.dcache.total_refs 11973075 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 292945 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 40.871409 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 85130110000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 473.034237 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.923895 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.923895 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 6952995 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 6952995 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4831955 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4831955 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 81928 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 81928 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 82891 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 82891 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 11784950 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 11784950 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 11784950 # number of overall hits -system.cpu1.dcache.overall_hits::total 11784950 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 170988 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 170988 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 150171 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 150171 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11121 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 11121 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10078 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10078 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 321159 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 321159 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 321159 # number of overall misses -system.cpu1.dcache.overall_misses::total 321159 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2374362000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2374362000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5137708000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 5137708000 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 106370500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 106370500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 87843000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 87843000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 7512070000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 7512070000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 7512070000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 7512070000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 7123983 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 7123983 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 4982126 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 4982126 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 93049 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 93049 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92969 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 92969 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 12106109 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 12106109 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 12106109 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 12106109 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.024002 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.024002 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030142 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.030142 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119518 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119518 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108402 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108402 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026529 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.026529 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026529 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.026529 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13886.132360 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 13886.132360 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34212.384548 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 34212.384548 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9564.832299 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9564.832299 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8716.312760 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8716.312760 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23390.501278 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 23390.501278 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23390.501278 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 23390.501278 # average overall miss latency +system.cpu1.dcache.replacements 401361 # number of replacements +system.cpu1.dcache.tagsinuse 473.304740 # Cycle average of tags in use +system.cpu1.dcache.total_refs 15681919 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 401873 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 39.022077 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 84382221000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 473.304740 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.924423 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.924423 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 9101949 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 9101949 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 6323711 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 6323711 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 111853 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 111853 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 114473 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 114473 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 15425660 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 15425660 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 15425660 # number of overall hits +system.cpu1.dcache.overall_hits::total 15425660 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 253200 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 253200 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 178129 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 178129 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13100 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 13100 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10404 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10404 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 431329 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 431329 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 431329 # number of overall misses +system.cpu1.dcache.overall_misses::total 431329 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3278248500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 3278248500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5660664500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 5660664500 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 115759000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 115759000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 63020500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 63020500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 8938913000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 8938913000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 8938913000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 8938913000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 9355149 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 9355149 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 6501840 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 6501840 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 124953 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 124953 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 124877 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 124877 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 15856989 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 15856989 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 15856989 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 15856989 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.027065 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.027065 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027397 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.027397 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.104839 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.104839 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.083314 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.083314 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027201 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.027201 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.027201 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.027201 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12947.268957 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12947.268957 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 31778.455501 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 31778.455501 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8836.564885 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8836.564885 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 6057.333718 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 6057.333718 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20724.117785 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 20724.117785 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20724.117785 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 20724.117785 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1075,62 +1045,66 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 266100 # number of writebacks -system.cpu1.dcache.writebacks::total 266100 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170988 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 170988 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 150171 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 150171 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11121 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11121 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10070 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10070 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 321159 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 321159 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 321159 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 321159 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1860790612 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1860790612 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4686951190 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4686951190 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 72983005 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 72983005 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 57622011 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 57622011 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6547741802 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 6547741802 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6547741802 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 6547741802 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168686201000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168686201000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 39932204000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 39932204000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 208618405000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 208618405000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024002 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.024002 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030142 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030142 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119518 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119518 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108316 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108316 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026529 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026529 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026529 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026529 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10882.580134 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10882.580134 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31210.760999 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31210.760999 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6562.629710 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6562.629710 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5722.146077 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5722.146077 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20387.850884 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20387.850884 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20387.850884 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20387.850884 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 366483 # number of writebacks +system.cpu1.dcache.writebacks::total 366483 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 253200 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 253200 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 178129 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 178129 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 13100 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 13100 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10399 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10399 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 431329 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 431329 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 431329 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 431329 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2771848500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2771848500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5304406500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5304406500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89559000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89559000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 42226500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 42226500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8076255000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 8076255000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8076255000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 8076255000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 170163530000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 170163530000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 40377042500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 40377042500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 210540572500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 210540572500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027065 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.027065 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027397 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027397 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.104839 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.104839 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.083274 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.083274 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027201 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.027201 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027201 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.027201 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10947.268957 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10947.268957 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29778.455501 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 29778.455501 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6836.564885 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6836.564885 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4060.630830 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4060.630830 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18724.117785 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18724.117785 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18724.117785 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18724.117785 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1152,10 +1126,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 574279130811 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 574279130811 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 574279130811 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 574279130811 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 567076826640 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 567076826640 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 567076826640 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 567076826640 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 07e356a30..e07e69ea6 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,28 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 2.624688 # Number of seconds simulated -sim_ticks 2624688029000 # Number of ticks simulated -final_tick 2624688029000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 2624688000000 # Number of ticks simulated +final_tick 2624688000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 388710 # Simulator instruction rate (inst/s) -host_op_rate 494628 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 16947208284 # Simulator tick rate (ticks/s) -host_mem_usage 385844 # Number of bytes of host memory used -host_seconds 154.87 # Real time elapsed on the host +host_inst_rate 509092 # Simulator instruction rate (inst/s) +host_op_rate 647812 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 22195691402 # Simulator tick rate (ticks/s) +host_mem_usage 379628 # Number of bytes of host memory used +host_seconds 118.25 # Real time elapsed on the host sim_insts 60201138 # Number of instructions simulated sim_ops 76605123 # Number of ops (including micro ops) simulated -system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory @@ -60,7 +48,19 @@ system.physmem.bw_total::cpu.dtb.walker 122 # To system.physmem.bw_total::cpu.itb.walker 73 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 268917 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 4596999 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53608355 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53608356 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). @@ -109,7 +109,7 @@ system.cpu.itb.inst_accesses 61499578 # IT system.cpu.itb.hits 61495107 # DTB hits system.cpu.itb.misses 4471 # DTB misses system.cpu.itb.accesses 61499578 # DTB accesses -system.cpu.numCycles 5249376058 # number of cpu cycles simulated +system.cpu.numCycles 5249376000 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 60201138 # Number of instructions committed @@ -121,14 +121,14 @@ system.cpu.num_conditional_control_insts 7948064 # nu system.cpu.num_int_insts 68872510 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions system.cpu.num_int_register_reads 394780312 # number of times the integer registers were read -system.cpu.num_int_register_writes 74180713 # number of times the integer registers were written +system.cpu.num_int_register_writes 74180711 # number of times the integer registers were written system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written system.cpu.num_mem_refs 27395681 # number of memory refs system.cpu.num_load_insts 15660705 # Number of load instructions system.cpu.num_store_insts 11734976 # Number of store instructions -system.cpu.num_idle_cycles 4573668194.612258 # Number of idle cycles -system.cpu.num_busy_cycles 675707863.387743 # Number of busy cycles +system.cpu.num_idle_cycles 4573668198.612257 # Number of idle cycles +system.cpu.num_busy_cycles 675707801.387743 # Number of busy cycles system.cpu.not_idle_fraction 0.128722 # Percentage of non-idle cycles system.cpu.idle_fraction 0.871278 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed @@ -154,12 +154,12 @@ system.cpu.icache.demand_misses::cpu.inst 856390 # n system.cpu.icache.demand_misses::total 856390 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 856390 # number of overall misses system.cpu.icache.overall_misses::total 856390 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11565472500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11565472500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11565472500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11565472500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11565472500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11565472500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11565531500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11565531500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11565531500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11565531500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11565531500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11565531500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 61495107 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 61495107 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 61495107 # number of demand (read+write) accesses @@ -172,12 +172,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.013926 system.cpu.icache.demand_miss_rate::total 0.013926 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.013926 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.013926 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13504.913065 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13504.913065 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13504.913065 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13504.913065 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13504.913065 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13504.913065 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13504.981959 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13504.981959 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13504.981959 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13504.981959 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13504.981959 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13504.981959 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -192,12 +192,12 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 856390 system.cpu.icache.demand_mshr_misses::total 856390 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 856390 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 856390 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9852692500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9852692500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9852692500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9852692500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9852692500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9852692500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9852751500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9852751500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9852751500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9852751500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9852751500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9852751500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 353004500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 353004500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 353004500 # number of overall MSHR uncacheable cycles @@ -208,58 +208,58 @@ system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013926 system.cpu.icache.demand_mshr_miss_rate::total 0.013926 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013926 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.013926 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11504.913065 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11504.913065 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11504.913065 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11504.913065 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11504.913065 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11504.913065 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11504.981959 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11504.981959 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11504.981959 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11504.981959 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11504.981959 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11504.981959 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 627202 # number of replacements +system.cpu.dcache.replacements 627203 # number of replacements system.cpu.dcache.tagsinuse 511.878516 # Cycle average of tags in use -system.cpu.dcache.total_refs 23656924 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 627714 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 37.687425 # Average number of references to valid blocks. +system.cpu.dcache.total_refs 23656923 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 627715 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 37.687363 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 653137000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 511.878516 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999763 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999763 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13196261 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13196261 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 13196260 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13196260 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 9973783 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 9973783 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 236291 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 236291 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 247690 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 247690 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 23170044 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 23170044 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 23170044 # number of overall hits -system.cpu.dcache.overall_hits::total 23170044 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 368703 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 368703 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 23170043 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 23170043 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 23170043 # number of overall hits +system.cpu.dcache.overall_hits::total 23170043 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 368704 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 368704 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 250510 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 250510 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 11400 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 11400 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 619213 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 619213 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 619213 # number of overall misses -system.cpu.dcache.overall_misses::total 619213 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5201080500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5201080500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8976707500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8976707500 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 619214 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 619214 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 619214 # number of overall misses +system.cpu.dcache.overall_misses::total 619214 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5201105500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5201105500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8977284500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8977284500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 154794000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 154794000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 14177788000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 14177788000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 14177788000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 14177788000 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 14178390000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 14178390000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 14178390000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14178390000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 13564964 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 13564964 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 10224293 # number of WriteReq accesses(hits+misses) @@ -282,16 +282,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.026029 system.cpu.dcache.demand_miss_rate::total 0.026029 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.026029 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.026029 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14106.423056 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14106.423056 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35833.729192 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35833.729192 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14106.452602 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14106.452602 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35836.032494 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35836.032494 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13578.421053 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13578.421053 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22896.463737 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22896.463737 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22896.463737 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22896.463737 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22897.398961 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22897.398961 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22897.398961 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22897.398961 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -302,32 +302,32 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 595968 # number of writebacks system.cpu.dcache.writebacks::total 595968 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368703 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 368703 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368704 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 368704 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250510 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 250510 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11400 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 11400 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 619213 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 619213 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 619213 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 619213 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4463674500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4463674500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8475687500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8475687500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 619214 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 619214 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 619214 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 619214 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4463697500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4463697500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8476264500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8476264500 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 131994000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 131994000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12939362000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12939362000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12939362000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12939362000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182162796000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182162796000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41387867000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41387867000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 223550663000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 223550663000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12939962000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12939962000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12939962000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12939962000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182162296000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182162296000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41387676000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41387676000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 223549972000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 223549972000 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027181 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027181 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024501 # mshr miss rate for WriteReq accesses @@ -338,16 +338,16 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026029 system.cpu.dcache.demand_mshr_miss_rate::total 0.026029 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026029 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.026029 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12106.423056 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12106.423056 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33833.729192 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33833.729192 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12106.452602 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12106.452602 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33836.032494 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33836.032494 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11578.421053 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11578.421053 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20896.463737 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20896.463737 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20896.463737 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20896.463737 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20897.398961 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20897.398961 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20897.398961 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20897.398961 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -356,16 +356,16 @@ system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 61913 # number of replacements -system.cpu.l2cache.tagsinuse 50867.983375 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1683054 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 50867.983864 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1683055 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 127295 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 13.221682 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 2574063802000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 37864.330216 # Average occupied blocks per requestor +system.cpu.l2cache.avg_refs 13.221690 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 2574063892000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 37864.330390 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.dtb.walker 3.885586 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.001416 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 6985.667758 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 6014.098399 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 6985.667850 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 6014.098622 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.577764 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy @@ -375,8 +375,8 @@ system.cpu.l2cache.occ_percent::total 0.776184 # Av system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8765 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3551 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.inst 844136 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 370245 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1226697 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 370246 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1226698 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 595968 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 595968 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits @@ -386,13 +386,13 @@ system.cpu.l2cache.ReadExReq_hits::total 114435 # nu system.cpu.l2cache.demand_hits::cpu.dtb.walker 8765 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.itb.walker 3551 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.inst 844136 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 484680 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1341132 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 484681 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1341133 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.dtb.walker 8765 # number of overall hits system.cpu.l2cache.overall_hits::cpu.itb.walker 3551 # number of overall hits system.cpu.l2cache.overall_hits::cpu.inst 844136 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 484680 # number of overall hits -system.cpu.l2cache.overall_hits::total 1341132 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 484681 # number of overall hits +system.cpu.l2cache.overall_hits::total 1341133 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.inst 10615 # number of ReadReq misses @@ -414,28 +414,28 @@ system.cpu.l2cache.overall_misses::cpu.data 143034 # system.cpu.l2cache.overall_misses::total 153657 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 261500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 156000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 553303500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 513115500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1066836500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 553362500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 513127500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1066907500 # number of ReadReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1040000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 1040000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6933900000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6933900000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6934471000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6934471000 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 261500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 156000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 553303500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7447015500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 8000736500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 553362500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7447598500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 8001378500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 261500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 156000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 553303500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7447015500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 8000736500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 553362500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7447598500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 8001378500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8770 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3554 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.inst 854751 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 380103 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1247178 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 380104 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1247179 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 595968 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 595968 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2899 # number of UpgradeReq accesses(hits+misses) @@ -445,13 +445,13 @@ system.cpu.l2cache.ReadExReq_accesses::total 247611 system.cpu.l2cache.demand_accesses::cpu.dtb.walker 8770 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.itb.walker 3554 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.inst 854751 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 627714 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1494789 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 627715 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1494790 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.dtb.walker 8770 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.itb.walker 3554 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 854751 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 627714 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1494789 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 627715 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1494790 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000570 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000844 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012419 # miss rate for ReadReq accesses @@ -473,23 +473,23 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 0.227865 system.cpu.l2cache.overall_miss_rate::total 0.102795 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 52300 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52124.682054 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52050.669507 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52089.082564 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52130.240226 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52051.886792 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52092.549192 # average ReadReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 361.990950 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 361.990950 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52065.687511 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52065.687511 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52069.975071 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52069.975071 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 52300 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52124.682054 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52064.652460 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52068.805847 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52130.240226 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52068.728414 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52072.983984 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 52300 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52124.682054 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52064.652460 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52068.805847 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52130.240226 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52068.728414 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52072.983984 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -521,31 +521,31 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 143034 system.cpu.l2cache.overall_mshr_misses::total 153657 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 200000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 120000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 425853000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 394738000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 820911000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 115017000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 115017000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5335717000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5335717000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 425912000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 394750500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 820982500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 115023000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 115023000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5336288000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5336288000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 200000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 120000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 425853000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5730455000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6156628000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 425912000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5731038500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6157270500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 200000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 120000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 425853000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5730455000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6156628000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 425912000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5731038500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6157270500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 264840000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166763732500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167028572500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 31856780000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 31856780000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166763232500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167028072500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 31856015000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 31856015000 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 264840000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 198620512500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 198885352500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 198619247500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 198884087500 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000570 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000844 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012419 # mshr miss rate for ReadReq accesses @@ -567,23 +567,23 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.227865 system.cpu.l2cache.overall_mshr_miss_rate::total 0.102795 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40118.040509 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40042.402110 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40081.587813 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40033.762617 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40033.762617 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40065.154382 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40065.154382 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40123.598681 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40043.670116 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40085.078854 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40035.851027 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40035.851027 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40069.441941 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40069.441941 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40118.040509 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40063.586280 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40067.344800 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40123.598681 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40067.665730 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40071.526191 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40118.040509 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40063.586280 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40067.344800 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40123.598681 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40067.665730 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40071.526191 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -607,10 +607,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1358750753218 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1358750753218 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1358750753218 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1358750753218 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1359273920420 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1359273920420 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1359273920420 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1359273920420 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency |