diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-11-26 17:05:25 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-11-26 17:05:25 -0600 |
| commit | 2823982a3cbd60a1b21db1a73b78440468df158a (patch) | |
| tree | b955647023da451506138be5a325dfaa2bfd8ee5 /tests/quick/fs/10.linux-boot/ref/arm | |
| parent | 9fb93e5cd226ca928ef9cd45bcefcbd94649f4ea (diff) | |
| download | gem5-2823982a3cbd60a1b21db1a73b78440468df158a.tar.xz | |
stats: updates due to changes to ticksToCycles()
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm')
10 files changed, 2741 insertions, 2296 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini index b499d5442..db7088ff9 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=true +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -10,17 +12,18 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=256 -boot_loader=/dist/m5/system/binaries/boot.arm +boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=False +dtb_filename= early_kernel_symbols=false enable_context_switch_stats_dump=false +eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=atomic @@ -45,6 +48,7 @@ system_port=system.membus.slave[0] type=Bridge clk_domain=system.clk_domain delay=50000 +eventq_index=0 ranges=268435456:520093695 1073741824:1610612735 req_size=16 resp_size=16 @@ -56,24 +60,28 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.cf0.image [system.cf0.image] type=CowDiskImage children=child child=system.cf0.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-arm-ael.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img read_only=true [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu0] @@ -86,6 +94,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu0.dtb +eventq_index=0 fastmem=false function_trace=false function_trace_start=0 @@ -119,6 +128,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -141,18 +151,21 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu0.dtb.walker [system.cpu0.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[3] @@ -163,6 +176,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -185,14 +199,17 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu0.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -211,18 +228,21 @@ midr=890224640 [system.cpu0.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu0.itb.walker [system.cpu0.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[2] [system.cpu0.tracer] type=ExeTracer +eventq_index=0 [system.cpu1] type=AtomicSimpleCPU @@ -234,6 +254,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu1.dtb +eventq_index=0 fastmem=false function_trace=false function_trace_start=0 @@ -267,6 +288,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -289,18 +311,21 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu1.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu1.dtb.walker [system.cpu1.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[7] @@ -311,6 +336,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -333,14 +359,17 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu1.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu1.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -359,31 +388,37 @@ midr=890224640 [system.cpu1.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu1.itb.walker [system.cpu1.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[6] [system.cpu1.tracer] type=ExeTracer +eventq_index=0 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.intrctrl] type=IntrControl +eventq_index=0 sys=system [system.iobus] type=NoncoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 use_default_range=false width=8 @@ -396,6 +431,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +eventq_index=0 forward_snoops=false hit_latency=50 is_top_level=true @@ -418,6 +454,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +eventq_index=0 hit_latency=50 size=1024 @@ -427,6 +464,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -449,6 +487,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=4194304 @@ -456,6 +495,7 @@ size=4194304 type=CoherentBus children=badaddr_responder clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -467,6 +507,7 @@ slave=system.system_port system.l2c.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=0 pio_latency=100000 @@ -482,41 +523,22 @@ warn_access=warn pio=system.membus.default [system.physmem] -type=SimpleDRAM -activation_limit=4 -addr_mapping=RaBaChCo -banks_per_rank=8 -burst_length=8 -channels=1 +type=SimpleMemory +bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true -device_bus_width=8 -device_rowbuffer_size=1024 -devices_per_rank=8 +eventq_index=0 in_addr_map=true -mem_sched_policy=frfcfs +latency=30000 +latency_var=0 null=false -page_policy=open range=0:134217727 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCL=13750 -tRCD=13750 -tREFI=7800000 -tRFC=300000 -tRP=13750 -tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_thresh_perc=70 port=system.membus.master[6] [system.realview] type=RealView children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +eventq_index=0 intrctrl=system.intrctrl max_mem_size=268435456 mem_start_addr=0 @@ -526,6 +548,7 @@ system=system [system.realview.a9scu] type=A9SCU clk_domain=system.clk_domain +eventq_index=0 pio_addr=520093696 pio_latency=100000 system=system @@ -535,6 +558,7 @@ pio=system.membus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268451840 pio_latency=100000 @@ -563,6 +587,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=1 Command=1 @@ -572,8 +597,40 @@ HeaderType=0 InterruptLine=31 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=0 MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=133 Revision=0 Status=640 @@ -585,6 +642,7 @@ clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 disks=system.cf0 +eventq_index=0 io_shift=1 pci_bus=2 pci_dev=7 @@ -600,6 +658,8 @@ pio=system.iobus.master[7] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 gic=system.realview.gic int_num=55 pio_addr=268566528 @@ -614,6 +674,7 @@ pio=system.iobus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268632064 pio_latency=100000 @@ -623,6 +684,7 @@ pio=system.iobus.master[9] [system.realview.flash_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=true pio_addr=1073741824 pio_latency=100000 @@ -644,8 +706,10 @@ cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 dist_pio_delay=10000 +eventq_index=0 int_latency=10000 it_lines=128 +msix_addr=0 platform=system.realview system=system pio=system.membus.master[2] @@ -654,6 +718,7 @@ pio=system.membus.master[2] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268513280 pio_latency=100000 @@ -664,6 +729,7 @@ pio=system.iobus.master[16] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268517376 pio_latency=100000 @@ -674,6 +740,7 @@ pio=system.iobus.master[17] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268521472 pio_latency=100000 @@ -684,6 +751,7 @@ pio=system.iobus.master[18] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=52 @@ -698,6 +766,7 @@ pio=system.iobus.master[5] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=53 @@ -711,6 +780,7 @@ pio=system.iobus.master[6] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=520101888 pio_latency=100000 @@ -728,6 +798,7 @@ pio=system.membus.master[3] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 @@ -740,6 +811,7 @@ pio=system.membus.master[5] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268455936 pio_latency=100000 @@ -751,6 +823,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -761,6 +834,7 @@ port=system.membus.master[1] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +eventq_index=0 idreg=0 pio_addr=268435456 pio_latency=100000 @@ -773,6 +847,7 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=42 @@ -786,6 +861,7 @@ pio=system.iobus.master[23] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268492800 pio_latency=100000 @@ -796,6 +872,7 @@ pio=system.iobus.master[20] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=269357056 pio_latency=100000 @@ -806,6 +883,7 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=true pio_addr=268439552 pio_latency=100000 @@ -816,6 +894,7 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268488704 pio_latency=100000 @@ -828,6 +907,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=36 int_num1=36 @@ -842,6 +922,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=37 int_num1=37 @@ -854,6 +935,7 @@ pio=system.iobus.master[3] type=Pl011 clk_domain=system.clk_domain end_on_eot=false +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=44 @@ -868,6 +950,7 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268476416 pio_latency=100000 @@ -878,6 +961,7 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268480512 pio_latency=100000 @@ -888,6 +972,7 @@ pio=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268484608 pio_latency=100000 @@ -898,6 +983,7 @@ pio=system.iobus.master[12] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268500992 pio_latency=100000 @@ -906,6 +992,7 @@ pio=system.iobus.master[15] [system.terminal] type=Terminal +eventq_index=0 intr_control=system.intrctrl number=0 output=true @@ -914,6 +1001,7 @@ port=3456 [system.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -923,11 +1011,13 @@ slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.wa [system.vncserver] type=VncServer +eventq_index=0 frame_capture=false number=0 port=5900 [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index fb725ba91..622f0dad2 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.912097 # Nu sim_ticks 912096763500 # Number of ticks simulated final_tick 912096763500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1640213 # Simulator instruction rate (inst/s) -host_op_rate 2111770 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 24275992963 # Simulator tick rate (ticks/s) -host_mem_usage 394600 # Number of bytes of host memory used -host_seconds 37.57 # Real time elapsed on the host +host_inst_rate 1031681 # Simulator instruction rate (inst/s) +host_op_rate 1328287 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15269405009 # Simulator tick rate (ticks/s) +host_mem_usage 443324 # Number of bytes of host memory used +host_seconds 59.73 # Real time elapsed on the host sim_insts 61625970 # Number of instructions simulated sim_ops 79343340 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory @@ -316,7 +316,7 @@ system.cpu0.itb.inst_accesses 30240979 # IT system.cpu0.itb.hits 30238804 # DTB hits system.cpu0.itb.misses 2175 # DTB misses system.cpu0.itb.accesses 30240979 # DTB accesses -system.cpu0.numCycles 1823633059 # number of cpu cycles simulated +system.cpu0.numCycles 1823671407 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.committedInsts 29750005 # Number of instructions committed @@ -334,8 +334,8 @@ system.cpu0.num_fp_register_writes 916 # nu system.cpu0.num_mem_refs 14626951 # number of memory refs system.cpu0.num_load_insts 8357226 # Number of load instructions system.cpu0.num_store_insts 6269725 # Number of store instructions -system.cpu0.num_idle_cycles 1783968822.941743 # Number of idle cycles -system.cpu0.num_busy_cycles 39664236.058257 # Number of busy cycles +system.cpu0.num_idle_cycles 1784006336.868180 # Number of idle cycles +system.cpu0.num_busy_cycles 39665070.131821 # Number of busy cycles system.cpu0.not_idle_fraction 0.021750 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.978250 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed @@ -492,7 +492,7 @@ system.cpu1.itb.inst_accesses 32414506 # IT system.cpu1.itb.hits 32412306 # DTB hits system.cpu1.itb.misses 2200 # DTB misses system.cpu1.itb.accesses 32414506 # DTB accesses -system.cpu1.numCycles 1824154149 # number of cpu cycles simulated +system.cpu1.numCycles 1824193528 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.committedInsts 31875965 # Number of instructions committed @@ -510,8 +510,8 @@ system.cpu1.num_fp_register_writes 1416 # nu system.cpu1.num_mem_refs 13370713 # number of memory refs system.cpu1.num_load_insts 7642673 # Number of load instructions system.cpu1.num_store_insts 5728040 # Number of store instructions -system.cpu1.num_idle_cycles 1783362859.317266 # Number of idle cycles -system.cpu1.num_busy_cycles 40791289.682734 # Number of busy cycles +system.cpu1.num_idle_cycles 1783401357.733683 # Number of idle cycles +system.cpu1.num_busy_cycles 40792170.266317 # Number of busy cycles system.cpu1.not_idle_fraction 0.022362 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.977638 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini index 4246eb19f..196c32809 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=true +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -10,17 +12,18 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu cpu_clk_domain intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain atags_addr=256 -boot_loader=/dist/m5/system/binaries/boot.arm +boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=False +dtb_filename= early_kernel_symbols=false enable_context_switch_stats_dump=false +eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=atomic @@ -45,6 +48,7 @@ system_port=system.membus.slave[0] type=Bridge clk_domain=system.clk_domain delay=50000 +eventq_index=0 ranges=268435456:520093695 1073741824:1610612735 req_size=16 resp_size=16 @@ -56,24 +60,28 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.cf0.image [system.cf0.image] type=CowDiskImage children=child child=system.cf0.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-arm-ael.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img read_only=true [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -86,6 +94,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 fastmem=false function_trace=false function_trace_start=0 @@ -119,6 +128,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -141,18 +151,21 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -163,6 +176,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -185,14 +199,17 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -211,12 +228,14 @@ midr=890224640 [system.cpu.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -227,6 +246,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -249,12 +269,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=4194304 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -264,19 +286,23 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.intrctrl] type=IntrControl +eventq_index=0 sys=system [system.iobus] type=NoncoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 use_default_range=false width=8 @@ -289,6 +315,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +eventq_index=0 forward_snoops=false hit_latency=50 is_top_level=true @@ -311,6 +338,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +eventq_index=0 hit_latency=50 size=1024 @@ -318,6 +346,7 @@ size=1024 type=CoherentBus children=badaddr_responder clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -329,6 +358,7 @@ slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=0 pio_latency=100000 @@ -344,41 +374,22 @@ warn_access=warn pio=system.membus.default [system.physmem] -type=SimpleDRAM -activation_limit=4 -addr_mapping=RaBaChCo -banks_per_rank=8 -burst_length=8 -channels=1 +type=SimpleMemory +bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true -device_bus_width=8 -device_rowbuffer_size=1024 -devices_per_rank=8 +eventq_index=0 in_addr_map=true -mem_sched_policy=frfcfs +latency=30000 +latency_var=0 null=false -page_policy=open range=0:134217727 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCL=13750 -tRCD=13750 -tREFI=7800000 -tRFC=300000 -tRP=13750 -tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_thresh_perc=70 port=system.membus.master[6] [system.realview] type=RealView children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +eventq_index=0 intrctrl=system.intrctrl max_mem_size=268435456 mem_start_addr=0 @@ -388,6 +399,7 @@ system=system [system.realview.a9scu] type=A9SCU clk_domain=system.clk_domain +eventq_index=0 pio_addr=520093696 pio_latency=100000 system=system @@ -397,6 +409,7 @@ pio=system.membus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268451840 pio_latency=100000 @@ -425,6 +438,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=1 Command=1 @@ -434,8 +448,40 @@ HeaderType=0 InterruptLine=31 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=0 MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=133 Revision=0 Status=640 @@ -447,6 +493,7 @@ clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 disks=system.cf0 +eventq_index=0 io_shift=1 pci_bus=2 pci_dev=7 @@ -462,6 +509,8 @@ pio=system.iobus.master[7] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 gic=system.realview.gic int_num=55 pio_addr=268566528 @@ -476,6 +525,7 @@ pio=system.iobus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268632064 pio_latency=100000 @@ -485,6 +535,7 @@ pio=system.iobus.master[9] [system.realview.flash_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=true pio_addr=1073741824 pio_latency=100000 @@ -506,8 +557,10 @@ cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 dist_pio_delay=10000 +eventq_index=0 int_latency=10000 it_lines=128 +msix_addr=0 platform=system.realview system=system pio=system.membus.master[2] @@ -516,6 +569,7 @@ pio=system.membus.master[2] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268513280 pio_latency=100000 @@ -526,6 +580,7 @@ pio=system.iobus.master[16] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268517376 pio_latency=100000 @@ -536,6 +591,7 @@ pio=system.iobus.master[17] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268521472 pio_latency=100000 @@ -546,6 +602,7 @@ pio=system.iobus.master[18] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=52 @@ -560,6 +617,7 @@ pio=system.iobus.master[5] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=53 @@ -573,6 +631,7 @@ pio=system.iobus.master[6] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=520101888 pio_latency=100000 @@ -590,6 +649,7 @@ pio=system.membus.master[3] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 @@ -602,6 +662,7 @@ pio=system.membus.master[5] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268455936 pio_latency=100000 @@ -613,6 +674,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -623,6 +685,7 @@ port=system.membus.master[1] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +eventq_index=0 idreg=0 pio_addr=268435456 pio_latency=100000 @@ -635,6 +698,7 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=42 @@ -648,6 +712,7 @@ pio=system.iobus.master[23] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268492800 pio_latency=100000 @@ -658,6 +723,7 @@ pio=system.iobus.master[20] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=269357056 pio_latency=100000 @@ -668,6 +734,7 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=true pio_addr=268439552 pio_latency=100000 @@ -678,6 +745,7 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268488704 pio_latency=100000 @@ -690,6 +758,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=36 int_num1=36 @@ -704,6 +773,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=37 int_num1=37 @@ -716,6 +786,7 @@ pio=system.iobus.master[3] type=Pl011 clk_domain=system.clk_domain end_on_eot=false +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=44 @@ -730,6 +801,7 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268476416 pio_latency=100000 @@ -740,6 +812,7 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268480512 pio_latency=100000 @@ -750,6 +823,7 @@ pio=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268484608 pio_latency=100000 @@ -760,6 +834,7 @@ pio=system.iobus.master[12] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268500992 pio_latency=100000 @@ -768,6 +843,7 @@ pio=system.iobus.master[15] [system.terminal] type=Terminal +eventq_index=0 intr_control=system.intrctrl number=0 output=true @@ -775,11 +851,13 @@ port=3456 [system.vncserver] type=VncServer +eventq_index=0 frame_capture=false number=0 port=5900 [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index 503d37a74..cb6c51df2 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.332810 # Nu sim_ticks 2332810264000 # Number of ticks simulated final_tick 2332810264000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1754227 # Simulator instruction rate (inst/s) -host_op_rate 2255827 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 67743178392 # Simulator tick rate (ticks/s) -host_mem_usage 394608 # Number of bytes of host memory used -host_seconds 34.44 # Real time elapsed on the host +host_inst_rate 993135 # Simulator instruction rate (inst/s) +host_op_rate 1277110 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38352024586 # Simulator tick rate (ticks/s) +host_mem_usage 443324 # Number of bytes of host memory used +host_seconds 60.83 # Real time elapsed on the host sim_insts 60408639 # Number of instructions simulated sim_ops 77681819 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory @@ -114,7 +114,7 @@ system.cpu.itb.inst_accesses 61436311 # IT system.cpu.itb.hits 61431840 # DTB hits system.cpu.itb.misses 4471 # DTB misses system.cpu.itb.accesses 61436311 # DTB accesses -system.cpu.numCycles 4665543516 # number of cpu cycles simulated +system.cpu.numCycles 4665620529 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 60408639 # Number of instructions committed @@ -132,8 +132,8 @@ system.cpu.num_fp_register_writes 2780 # nu system.cpu.num_mem_refs 27361637 # number of memory refs system.cpu.num_load_insts 15639527 # Number of load instructions system.cpu.num_store_insts 11722110 # Number of store instructions -system.cpu.num_idle_cycles 4586746360.692756 # Number of idle cycles -system.cpu.num_busy_cycles 78797155.307244 # Number of busy cycles +system.cpu.num_idle_cycles 4586822073.007144 # Number of idle cycles +system.cpu.num_busy_cycles 78798455.992855 # Number of busy cycles system.cpu.not_idle_fraction 0.016889 # Percentage of non-idle cycles system.cpu.idle_fraction 0.983111 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini index 6e5d183fa..051cf58a2 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=true +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -10,17 +12,18 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=256 -boot_loader=/dist/m5/system/binaries/boot.arm +boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=False +dtb_filename= early_kernel_symbols=false enable_context_switch_stats_dump=false +eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -45,6 +48,7 @@ system_port=system.membus.slave[0] type=Bridge clk_domain=system.clk_domain delay=50000 +eventq_index=0 ranges=268435456:520093695 1073741824:1610612735 req_size=16 resp_size=16 @@ -56,24 +60,28 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.cf0.image [system.cf0.image] type=CowDiskImage children=child child=system.cf0.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-arm-ael.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img read_only=true [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu0] @@ -86,6 +94,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu0.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu0.interrupts @@ -112,6 +121,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -134,18 +144,21 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu0.dtb.walker [system.cpu0.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[3] @@ -156,6 +169,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -178,14 +192,17 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu0.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -204,18 +221,21 @@ midr=890224640 [system.cpu0.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu0.itb.walker [system.cpu0.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[2] [system.cpu0.tracer] type=ExeTracer +eventq_index=0 [system.cpu1] type=TimingSimpleCPU @@ -227,6 +247,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu1.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu1.interrupts @@ -253,6 +274,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -275,18 +297,21 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu1.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu1.dtb.walker [system.cpu1.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[7] @@ -297,6 +322,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -319,14 +345,17 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu1.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu1.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -345,31 +374,37 @@ midr=890224640 [system.cpu1.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu1.itb.walker [system.cpu1.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[6] [system.cpu1.tracer] type=ExeTracer +eventq_index=0 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.intrctrl] type=IntrControl +eventq_index=0 sys=system [system.iobus] type=NoncoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 use_default_range=false width=8 @@ -382,6 +417,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +eventq_index=0 forward_snoops=false hit_latency=50 is_top_level=true @@ -404,6 +440,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +eventq_index=0 hit_latency=50 size=1024 @@ -413,6 +450,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -435,6 +473,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=4194304 @@ -442,6 +481,7 @@ size=4194304 type=CoherentBus children=badaddr_responder clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -453,6 +493,7 @@ slave=system.system_port system.l2c.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=0 pio_latency=100000 @@ -479,6 +520,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -490,19 +532,23 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[6] [system.realview] type=RealView children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +eventq_index=0 intrctrl=system.intrctrl max_mem_size=268435456 mem_start_addr=0 @@ -512,6 +558,7 @@ system=system [system.realview.a9scu] type=A9SCU clk_domain=system.clk_domain +eventq_index=0 pio_addr=520093696 pio_latency=100000 system=system @@ -521,6 +568,7 @@ pio=system.membus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268451840 pio_latency=100000 @@ -549,6 +597,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=1 Command=1 @@ -558,8 +607,40 @@ HeaderType=0 InterruptLine=31 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=0 MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=133 Revision=0 Status=640 @@ -571,6 +652,7 @@ clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 disks=system.cf0 +eventq_index=0 io_shift=1 pci_bus=2 pci_dev=7 @@ -586,6 +668,8 @@ pio=system.iobus.master[7] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 gic=system.realview.gic int_num=55 pio_addr=268566528 @@ -600,6 +684,7 @@ pio=system.iobus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268632064 pio_latency=100000 @@ -609,6 +694,7 @@ pio=system.iobus.master[9] [system.realview.flash_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=true pio_addr=1073741824 pio_latency=100000 @@ -630,8 +716,10 @@ cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 dist_pio_delay=10000 +eventq_index=0 int_latency=10000 it_lines=128 +msix_addr=0 platform=system.realview system=system pio=system.membus.master[2] @@ -640,6 +728,7 @@ pio=system.membus.master[2] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268513280 pio_latency=100000 @@ -650,6 +739,7 @@ pio=system.iobus.master[16] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268517376 pio_latency=100000 @@ -660,6 +750,7 @@ pio=system.iobus.master[17] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268521472 pio_latency=100000 @@ -670,6 +761,7 @@ pio=system.iobus.master[18] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=52 @@ -684,6 +776,7 @@ pio=system.iobus.master[5] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=53 @@ -697,6 +790,7 @@ pio=system.iobus.master[6] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=520101888 pio_latency=100000 @@ -714,6 +808,7 @@ pio=system.membus.master[3] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 @@ -726,6 +821,7 @@ pio=system.membus.master[5] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268455936 pio_latency=100000 @@ -737,6 +833,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -747,6 +844,7 @@ port=system.membus.master[1] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +eventq_index=0 idreg=0 pio_addr=268435456 pio_latency=100000 @@ -759,6 +857,7 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=42 @@ -772,6 +871,7 @@ pio=system.iobus.master[23] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268492800 pio_latency=100000 @@ -782,6 +882,7 @@ pio=system.iobus.master[20] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=269357056 pio_latency=100000 @@ -792,6 +893,7 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=true pio_addr=268439552 pio_latency=100000 @@ -802,6 +904,7 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268488704 pio_latency=100000 @@ -814,6 +917,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=36 int_num1=36 @@ -828,6 +932,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=37 int_num1=37 @@ -840,6 +945,7 @@ pio=system.iobus.master[3] type=Pl011 clk_domain=system.clk_domain end_on_eot=false +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=44 @@ -854,6 +960,7 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268476416 pio_latency=100000 @@ -864,6 +971,7 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268480512 pio_latency=100000 @@ -874,6 +982,7 @@ pio=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268484608 pio_latency=100000 @@ -884,6 +993,7 @@ pio=system.iobus.master[12] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268500992 pio_latency=100000 @@ -892,6 +1002,7 @@ pio=system.iobus.master[15] [system.terminal] type=Terminal +eventq_index=0 intr_control=system.intrctrl number=0 output=true @@ -900,6 +1011,7 @@ port=3456 [system.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -909,11 +1021,13 @@ slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.wa [system.vncserver] type=VncServer +eventq_index=0 frame_capture=false number=0 port=5900 [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 951921c42..168e14479 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,150 +1,150 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.195756 # Number of seconds simulated -sim_ticks 1195756323500 # Number of ticks simulated -final_tick 1195756323500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.195792 # Number of seconds simulated +sim_ticks 1195791950500 # Number of ticks simulated +final_tick 1195791950500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 469394 # Simulator instruction rate (inst/s) -host_op_rate 598174 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9145402965 # Simulator tick rate (ticks/s) -host_mem_usage 398732 # Number of bytes of host memory used -host_seconds 130.75 # Real time elapsed on the host -sim_insts 61373013 # Number of instructions simulated -sim_ops 78210923 # Number of ops (including micro ops) simulated +host_inst_rate 418462 # Simulator instruction rate (inst/s) +host_op_rate 533251 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8153682245 # Simulator tick rate (ticks/s) +host_mem_usage 447424 # Number of bytes of host memory used +host_seconds 146.66 # Real time elapsed on the host +sim_insts 61370228 # Number of instructions simulated +sim_ops 78204808 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 463908 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 6634996 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 463716 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 6626164 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 256412 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2903984 # Number of bytes read from this memory -system.physmem.bytes_read::total 62164260 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 463908 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu1.data 2903920 # Number of bytes read from this memory +system.physmem.bytes_read::total 62155172 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 463716 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 256412 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 720320 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4143232 # Number of bytes written to this memory +system.physmem.bytes_inst_read::total 720128 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4136128 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 3027304 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 7170576 # Number of bytes written to this memory +system.physmem.bytes_written::total 7163472 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 13467 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 103744 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 13464 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 103606 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 4088 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 45401 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6654771 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 64738 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.data 45400 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6654629 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 64627 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 756826 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 821574 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43407265 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 821463 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43405972 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 214 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 107 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 387962 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 5548786 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 387790 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 5541235 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 54 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 214435 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2428575 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51987398 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 387962 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 214435 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 602397 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3464947 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 2531706 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 214429 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 2428449 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51978249 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 387790 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 214429 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 602218 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3458903 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 2531631 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 33 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 5996687 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3464947 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43407265 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 5990567 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3458903 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43405972 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 214 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 107 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 387962 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 8080492 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 387790 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 8072866 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 54 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 214435 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2428609 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 57984085 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6654771 # Number of read requests accepted -system.physmem.writeReqs 821574 # Number of write requests accepted -system.physmem.readBursts 6654771 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 821574 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 425880832 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 24512 # Total number of bytes read from write queue -system.physmem.bytesWritten 7300224 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 62164260 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7170576 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 383 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 707506 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 10656 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 415729 # Per bank write bursts +system.physmem.bw_total::cpu1.inst 214429 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2428483 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 57968816 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 6654629 # Number of read requests accepted +system.physmem.writeReqs 821463 # Number of write requests accepted +system.physmem.readBursts 6654629 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 821463 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 425873472 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 22784 # Total number of bytes read from write queue +system.physmem.bytesWritten 7293184 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 62155172 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7163472 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 356 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 707504 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 10661 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 415730 # Per bank write bursts system.physmem.perBankRdBursts::1 415559 # Per bank write bursts -system.physmem.perBankRdBursts::2 414962 # Per bank write bursts -system.physmem.perBankRdBursts::3 415336 # Per bank write bursts -system.physmem.perBankRdBursts::4 422370 # Per bank write bursts +system.physmem.perBankRdBursts::2 414961 # Per bank write bursts +system.physmem.perBankRdBursts::3 415335 # Per bank write bursts +system.physmem.perBankRdBursts::4 422368 # Per bank write bursts system.physmem.perBankRdBursts::5 415375 # Per bank write bursts -system.physmem.perBankRdBursts::6 415451 # Per bank write bursts +system.physmem.perBankRdBursts::6 415446 # Per bank write bursts system.physmem.perBankRdBursts::7 415289 # Per bank write bursts system.physmem.perBankRdBursts::8 415350 # Per bank write bursts system.physmem.perBankRdBursts::9 415631 # Per bank write bursts system.physmem.perBankRdBursts::10 415265 # Per bank write bursts system.physmem.perBankRdBursts::11 414898 # Per bank write bursts -system.physmem.perBankRdBursts::12 415464 # Per bank write bursts +system.physmem.perBankRdBursts::12 415491 # Per bank write bursts system.physmem.perBankRdBursts::13 416088 # Per bank write bursts -system.physmem.perBankRdBursts::14 415829 # Per bank write bursts -system.physmem.perBankRdBursts::15 415792 # Per bank write bursts -system.physmem.perBankWrBursts::0 7314 # Per bank write bursts -system.physmem.perBankWrBursts::1 7200 # Per bank write bursts -system.physmem.perBankWrBursts::2 6696 # Per bank write bursts -system.physmem.perBankWrBursts::3 6864 # Per bank write bursts -system.physmem.perBankWrBursts::4 7395 # Per bank write bursts -system.physmem.perBankWrBursts::5 6961 # Per bank write bursts -system.physmem.perBankWrBursts::6 7170 # Per bank write bursts -system.physmem.perBankWrBursts::7 6990 # Per bank write bursts -system.physmem.perBankWrBursts::8 6985 # Per bank write bursts -system.physmem.perBankWrBursts::9 7249 # Per bank write bursts +system.physmem.perBankRdBursts::14 415759 # Per bank write bursts +system.physmem.perBankRdBursts::15 415728 # Per bank write bursts +system.physmem.perBankWrBursts::0 7313 # Per bank write bursts +system.physmem.perBankWrBursts::1 7201 # Per bank write bursts +system.physmem.perBankWrBursts::2 6692 # Per bank write bursts +system.physmem.perBankWrBursts::3 6866 # Per bank write bursts +system.physmem.perBankWrBursts::4 7393 # Per bank write bursts +system.physmem.perBankWrBursts::5 6958 # Per bank write bursts +system.physmem.perBankWrBursts::6 7169 # Per bank write bursts +system.physmem.perBankWrBursts::7 6986 # Per bank write bursts +system.physmem.perBankWrBursts::8 6988 # Per bank write bursts +system.physmem.perBankWrBursts::9 7250 # Per bank write bursts system.physmem.perBankWrBursts::10 6972 # Per bank write bursts system.physmem.perBankWrBursts::11 6687 # Per bank write bursts -system.physmem.perBankWrBursts::12 7224 # Per bank write bursts -system.physmem.perBankWrBursts::13 7527 # Per bank write bursts -system.physmem.perBankWrBursts::14 7429 # Per bank write bursts -system.physmem.perBankWrBursts::15 7403 # Per bank write bursts +system.physmem.perBankWrBursts::12 7223 # Per bank write bursts +system.physmem.perBankWrBursts::13 7529 # Per bank write bursts +system.physmem.perBankWrBursts::14 7375 # Per bank write bursts +system.physmem.perBankWrBursts::15 7354 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1195751937000 # Total gap between requests +system.physmem.totGap 1195787534500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 6825 # Read request sizes (log2) system.physmem.readPktSize::3 6488064 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 159882 # Read request sizes (log2) +system.physmem.readPktSize::6 159740 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 756836 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 64738 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 632405 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 479192 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 479926 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1578313 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1129029 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1122994 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1119651 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 25389 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 24020 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 9298 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 9280 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 9200 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 8958 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 8876 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 8828 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 8796 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 217 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 16 # What read queue length does an incoming req see +system.physmem.writePktSize::6 64627 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 636769 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 483388 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 484627 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1579502 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1123930 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1118197 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1114450 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 25137 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 24391 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 9450 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 9387 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 9266 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 8971 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 8900 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 8855 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 8823 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 219 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 11 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -159,31 +159,31 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 5183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 5183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5186 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 5178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 5182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see @@ -191,423 +191,408 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 75043 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 5772.432765 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 392.553072 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 13030.260865 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 26180 34.89% 34.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 15268 20.35% 55.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 3440 4.58% 59.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 2311 3.08% 62.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 1510 2.01% 64.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 1328 1.77% 66.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 1040 1.39% 68.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 1132 1.51% 69.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 816 1.09% 70.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 593 0.79% 71.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 586 0.78% 72.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 709 0.94% 73.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 314 0.42% 73.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 269 0.36% 73.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 220 0.29% 74.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 291 0.39% 74.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 182 0.24% 74.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 143 0.19% 75.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 140 0.19% 75.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 157 0.21% 75.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 122 0.16% 75.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 2241 2.99% 78.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 115 0.15% 78.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 232 0.31% 79.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 71 0.09% 79.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 55 0.07% 79.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 54 0.07% 79.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 56 0.07% 79.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 28 0.04% 79.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 28 0.04% 79.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 21 0.03% 79.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 107 0.14% 79.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 143 0.19% 79.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 11 0.01% 79.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 15 0.02% 79.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 43 0.06% 79.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 9 0.01% 79.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 16 0.02% 79.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 18 0.02% 79.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 98 0.13% 80.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 8 0.01% 80.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 10 0.01% 80.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 12 0.02% 80.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 36 0.05% 80.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 9 0.01% 80.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 5 0.01% 80.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3015 10 0.01% 80.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 168 0.22% 80.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 11 0.01% 80.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 9 0.01% 80.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 4 0.01% 80.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 161 0.21% 80.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 6 0.01% 80.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 6 0.01% 80.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 6 0.01% 80.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 16 0.02% 80.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 2 0.00% 80.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 6 0.01% 80.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 30 0.04% 80.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 86 0.11% 80.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 3 0.00% 80.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 4 0.01% 80.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4039 9 0.01% 80.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4103 188 0.25% 81.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 2 0.00% 81.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4295 2 0.00% 81.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4359 22 0.03% 81.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 2 0.00% 81.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 1 0.00% 81.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4551 3 0.00% 81.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 27 0.04% 81.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4679 2 0.00% 81.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4743 2 0.00% 81.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4807 4 0.01% 81.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 207 0.28% 81.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 4 0.01% 81.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4999 1 0.00% 81.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5063 13 0.02% 81.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 90 0.12% 81.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 6 0.01% 81.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5319 1 0.00% 81.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5383 76 0.10% 81.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5447 12 0.02% 81.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 206 0.27% 82.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 11 0.01% 82.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5703 1 0.00% 82.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5895 30 0.04% 82.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5959 1 0.00% 82.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6023 2 0.00% 82.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6087 2 0.00% 82.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6151 144 0.19% 82.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6215 2 0.00% 82.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6343 1 0.00% 82.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6407 86 0.11% 82.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6535 2 0.00% 82.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6599 1 0.00% 82.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6663 18 0.02% 82.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6727 1 0.00% 82.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6919 5 0.01% 82.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7111 1 0.00% 82.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7175 166 0.22% 82.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7431 24 0.03% 82.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7687 69 0.09% 82.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7815 1 0.00% 82.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7943 30 0.04% 82.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8007 1 0.00% 82.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8071 1 0.00% 82.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8199 161 0.21% 83.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8320-8327 2 0.00% 83.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8384-8391 1 0.00% 83.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8455 26 0.03% 83.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8711 70 0.09% 83.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8967 24 0.03% 83.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9088-9095 2 0.00% 83.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9223 167 0.22% 83.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9479 10 0.01% 83.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9735 21 0.03% 83.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9856-9863 1 0.00% 83.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9920-9927 1 0.00% 83.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9991 83 0.11% 83.64% # Bytes accessed per row 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+system.physmem.bytesPerActivate::32768-32775 269 0.36% 91.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33031 14 0.02% 91.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33216-33223 1 0.00% 91.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33287 25 0.03% 91.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33344-33351 2 0.00% 91.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33543 22 0.03% 91.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33600-33607 1 0.00% 91.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33664-33671 1 0.00% 91.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33728-33735 1 0.00% 91.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33799 216 0.29% 92.19% # Bytes accessed per row activation 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+system.physmem.bytesPerActivate::38400-38407 79 0.11% 93.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38656-38663 11 0.01% 93.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38919 85 0.11% 93.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38976-38983 1 0.00% 93.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39104-39111 1 0.00% 93.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39168-39175 73 0.10% 93.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39232-39239 2 0.00% 93.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39431 96 0.13% 94.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39680-39687 14 0.02% 94.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39936-39943 27 0.04% 94.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40192-40199 131 0.17% 94.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40320-40327 1 0.00% 94.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40448-40455 24 0.03% 94.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40512-40519 1 0.00% 94.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40704-40711 75 0.10% 94.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40768-40775 1 0.00% 94.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40967 23 0.03% 94.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41152-41159 1 0.00% 94.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41223 72 0.10% 94.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41344-41351 1 0.00% 94.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41479 24 0.03% 94.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41735 130 0.17% 94.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 25 0.03% 94.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42247 15 0.02% 94.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42503 101 0.13% 94.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42759 70 0.09% 95.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42944-42951 1 0.00% 95.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 85 0.11% 95.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 8 0.01% 95.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 78 0.10% 95.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43648-43655 1 0.00% 95.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 24 0.03% 95.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 140 0.19% 95.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 12 0.02% 95.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44352-44359 1 0.00% 95.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44416-44423 1 0.00% 95.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 23 0.03% 95.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 80 0.11% 95.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44928-44935 2 0.00% 95.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 165 0.22% 95.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45184-45191 1 0.00% 95.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45248-45255 1 0.00% 95.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 38 0.05% 95.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 12 0.02% 95.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 71 0.09% 96.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45952-45959 1 0.00% 96.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 165 0.22% 96.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46144-46151 1 0.00% 96.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 15 0.02% 96.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 12 0.02% 96.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46720-46727 1 0.00% 96.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 31 0.04% 96.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 151 0.20% 96.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47168-47175 1 0.00% 96.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 87 0.12% 96.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47488-47495 1 0.00% 96.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 21 0.03% 96.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47744-47751 1 0.00% 96.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 24 0.03% 96.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47936-47943 2 0.00% 96.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48000-48007 1 0.00% 96.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 239 0.32% 97.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48192-48199 1 0.00% 97.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48256-48263 1 0.00% 97.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 36 0.05% 97.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 14 0.02% 97.13% # Bytes accessed per row activation system.physmem.bytesPerActivate::48768-48775 14 0.02% 97.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48903 17 0.02% 97.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48960-48967 9 0.01% 97.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49024-49031 6 0.01% 97.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49088-49095 6 0.01% 97.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49159 2103 2.80% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49792-49799 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 75043 # Bytes accessed per row activation -system.physmem.totQLat 159590177750 # Total ticks spent queuing -system.physmem.totMemAccLat 202588661500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 33271940000 # Total ticks spent in databus transfers -system.physmem.totBankLat 9726543750 # Total ticks spent accessing banks -system.physmem.avgQLat 23982.70 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1461.67 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::48896-48903 4 0.01% 97.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48960-48967 5 0.01% 97.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49024-49031 3 0.00% 97.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 2 0.00% 97.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 2125 2.83% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 74963 # Bytes accessed per row activation +system.physmem.totQLat 159518930750 # Total ticks spent queuing +system.physmem.totMemAccLat 202571234500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 33271365000 # Total ticks spent in databus transfers +system.physmem.totBankLat 9780938750 # Total ticks spent accessing banks +system.physmem.avgQLat 23972.41 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1469.87 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30444.37 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 356.16 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 6.11 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 51.99 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 6.00 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30442.28 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 356.14 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 6.10 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 51.98 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 5.99 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.83 # Data bus utilization in percentage system.physmem.busUtilRead 2.78 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.17 # Average read queue length when enqueuing -system.physmem.avgWrQLen 12.10 # Average write queue length when enqueuing -system.physmem.readRowHits 6598517 # Number of row buffer hits during reads -system.physmem.writeRowHits 94894 # Number of row buffer hits during writes +system.physmem.avgWrQLen 12.12 # Average write queue length when enqueuing +system.physmem.readRowHits 6598430 # Number of row buffer hits during reads +system.physmem.writeRowHits 94836 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.16 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 83.19 # Row buffer hit rate for writes -system.physmem.avgGap 159938.04 # Average gap between requests +system.physmem.writeRowHitRate 83.22 # Row buffer hit rate for writes +system.physmem.avgGap 159948.21 # Average gap between requests system.physmem.pageHitRate 98.89 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 4.89 # Percentage of time for which DRAM has all the banks in precharge state +system.physmem.prechargeAllPercent 4.87 # Percentage of time for which DRAM has all the banks in precharge state system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -626,286 +611,286 @@ system.realview.nvmem.bw_inst_read::total 57 # I system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 59999152 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 7703168 # Transaction distribution -system.membus.trans_dist::ReadResp 7703168 # Transaction distribution +system.membus.throughput 59983824 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 7703157 # Transaction distribution +system.membus.trans_dist::ReadResp 7703157 # Transaction distribution system.membus.trans_dist::WriteReq 767205 # Transaction distribution system.membus.trans_dist::WriteResp 767205 # Transaction distribution -system.membus.trans_dist::Writeback 64738 # Transaction distribution -system.membus.trans_dist::UpgradeReq 27605 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 16481 # Transaction distribution -system.membus.trans_dist::UpgradeResp 10656 # Transaction distribution -system.membus.trans_dist::ReadExReq 137900 # Transaction distribution -system.membus.trans_dist::ReadExResp 137428 # Transaction distribution +system.membus.trans_dist::Writeback 64627 # Transaction distribution +system.membus.trans_dist::UpgradeReq 27746 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 16446 # Transaction distribution +system.membus.trans_dist::UpgradeResp 10661 # Transaction distribution +system.membus.trans_dist::ReadExReq 137744 # Transaction distribution +system.membus.trans_dist::ReadExResp 137297 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382570 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 8870 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 910 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1967038 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4359426 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1966729 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4359117 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12976128 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 12976128 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 17335554 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 17335245 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389894 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 17740 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1820 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17430324 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 19839854 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17414132 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 19823662 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 51904512 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 51904512 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 71744366 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 71744366 # Total data (bytes) +system.membus.tot_pkt_size::total 71728174 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 71728174 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1219669500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1224786000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 18000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 7974500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 7986500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 781000 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 782000 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 9159249500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 9213145499 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 5040906450 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 5079077969 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.respLayer2.occupancy 14657427498 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 14657796999 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.2 # Layer utilization (%) -system.l2c.tags.replacements 69764 # number of replacements -system.l2c.tags.tagsinuse 53155.979727 # Cycle average of tags in use -system.l2c.tags.total_refs 1654767 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 134953 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 12.261802 # Average number of references to valid blocks. +system.l2c.tags.replacements 69622 # number of replacements +system.l2c.tags.tagsinuse 53154.714662 # Cycle average of tags in use +system.l2c.tags.total_refs 1651251 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 134786 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 12.250909 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 40044.748185 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.667732 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 40043.388352 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.667642 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001544 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4637.745622 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 5787.407955 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4637.694613 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 5787.547519 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.itb.walker 0.001664 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1927.694562 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 755.712463 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.611034 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu1.inst 1927.667021 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 755.746308 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.611014 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000041 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.inst 0.070766 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.088309 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.088311 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.inst 0.029414 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.011531 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.811096 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 4686 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 1510 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 483170 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 242041 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 3562 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1809 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 372569 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 110996 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1220343 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 576824 # number of Writeback hits -system.l2c.Writeback_hits::total 576824 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1289 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 452 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1741 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 268 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 98 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 366 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 65622 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 45295 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 110917 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 4686 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 1510 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 483170 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 307663 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 3562 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 1809 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 372569 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 156291 # number of demand (read+write) hits -system.l2c.demand_hits::total 1331260 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 4686 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 1510 # number of overall hits -system.l2c.overall_hits::cpu0.inst 483170 # number of overall hits -system.l2c.overall_hits::cpu0.data 307663 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 3562 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 1809 # number of overall hits -system.l2c.overall_hits::cpu1.inst 372569 # number of overall hits -system.l2c.overall_hits::cpu1.data 156291 # number of overall hits -system.l2c.overall_hits::total 1331260 # number of overall hits +system.l2c.tags.occ_percent::cpu1.data 0.011532 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.811077 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 4526 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 1443 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 483144 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 241974 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 3792 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 1866 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 372505 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 110561 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1219811 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 576138 # number of Writeback hits +system.l2c.Writeback_hits::total 576138 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 1247 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 445 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1692 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 260 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 101 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 361 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 65526 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 45407 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 110933 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 4526 # number of demand (read+write) hits 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accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.825862 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.706026 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.592150 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.495483 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.557442 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000883 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001384 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013941 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.254274 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000536 # mshr miss rate for demand accesses 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rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 63625 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59373.792801 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 63169.701337 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59980.237154 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 62750.797509 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58422.456886 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 67697.542283 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 61549.990959 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10012.407974 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10039.718297 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10024.942342 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10016.501292 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10015.611691 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10016.009238 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56187.238680 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 64785.004126 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 58929.114754 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 63500 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59486.440890 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 66057.804233 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 61604.186027 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10009.547900 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10032.172281 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10019.948784 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10003.574742 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10021.874739 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10013.685121 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56045.714220 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 64546.202494 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 58758.594590 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 63625 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59373.792801 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 56833.806114 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59980.237154 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 56666.917644 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58422.456886 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 64903.535470 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 59291.707432 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 63500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59486.440890 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 64607.662938 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 59152.393857 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 63625 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59373.792801 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 56833.806114 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59980.237154 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 56666.917644 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58422.456886 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 64903.535470 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 59291.707432 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59486.440890 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 64607.662938 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 59152.393857 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -1087,56 +1072,56 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 118413539 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2505894 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2505894 # Transaction distribution +system.toL2Bus.throughput 118330469 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2505274 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2505274 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 767205 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 767205 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 576824 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 26927 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 16847 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 43774 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 262598 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 262598 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 994053 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2951842 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 5908 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 15091 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 754073 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 2881163 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 6136 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 11790 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7620056 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 31386872 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 53739672 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 6048 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 18760 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 24100876 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 28000722 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 7240 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 14248 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 137274438 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 137274438 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 4319300 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4769236119 # Layer occupancy (ticks) +system.toL2Bus.trans_dist::Writeback 576138 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 27005 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 16807 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 43812 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 262415 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 262415 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 993978 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2951141 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 5841 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 14926 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 753985 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 2879812 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 6193 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 12022 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7617898 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 31385016 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 53721240 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 5780 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 18120 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 24096780 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 27936146 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 7468 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 15168 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 137185718 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 137185718 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 4312904 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4765712727 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2218068983 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2217854478 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 2472016836 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 2469983321 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) system.toL2Bus.respLayer2.occupancy 4396000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 10401000 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 10396000 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 1698781961 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.occupancy 1698669462 # Layer occupancy (ticks) system.toL2Bus.respLayer4.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 2209782432 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.occupancy 2208533441 # Layer occupancy (ticks) system.toL2Bus.respLayer5.utilization 0.2 # Layer utilization (%) system.toL2Bus.respLayer6.occupancy 4326000 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 8228499 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 8230499 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 45405912 # Throughput (bytes/s) +system.iobus.throughput 45404559 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 7671403 # Transaction distribution system.iobus.trans_dist::ReadResp 7671403 # Transaction distribution system.iobus.trans_dist::WriteReq 7946 # Transaction distribution @@ -1246,13 +1231,13 @@ system.iobus.reqLayer25.occupancy 6488064000 # La system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%) system.iobus.respLayer0.occupancy 2374624000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.2 # Layer utilization (%) -system.iobus.respLayer1.occupancy 17778330502 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 17777853001 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 9652613 # DTB read hits -system.cpu0.dtb.read_misses 3746 # DTB read misses -system.cpu0.dtb.write_hits 7596890 # DTB write hits +system.cpu0.dtb.read_hits 9652640 # DTB read hits +system.cpu0.dtb.read_misses 3742 # DTB read misses +system.cpu0.dtb.write_hits 7596858 # DTB write hits system.cpu0.dtb.write_misses 1582 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -1260,16 +1245,16 @@ system.cpu0.dtb.flush_tlb_mva_asid 1439 # Nu system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu0.dtb.flush_entries 1811 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 144 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 138 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 9656359 # DTB read accesses -system.cpu0.dtb.write_accesses 7598472 # DTB write accesses +system.cpu0.dtb.read_accesses 9656382 # DTB read accesses +system.cpu0.dtb.write_accesses 7598440 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 17249503 # DTB hits -system.cpu0.dtb.misses 5328 # DTB misses -system.cpu0.dtb.accesses 17254831 # DTB accesses -system.cpu0.itb.inst_hits 43298526 # ITB inst hits +system.cpu0.dtb.hits 17249498 # DTB hits +system.cpu0.dtb.misses 5324 # DTB misses +system.cpu0.dtb.accesses 17254822 # DTB accesses +system.cpu0.itb.inst_hits 43298691 # ITB inst hits system.cpu0.itb.inst_misses 2205 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -1286,79 +1271,79 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 43300731 # ITB inst accesses -system.cpu0.itb.hits 43298526 # DTB hits +system.cpu0.itb.inst_accesses 43300896 # ITB inst accesses +system.cpu0.itb.hits 43298691 # DTB hits system.cpu0.itb.misses 2205 # DTB misses -system.cpu0.itb.accesses 43300731 # DTB accesses -system.cpu0.numCycles 2391512647 # number of cpu cycles simulated +system.cpu0.itb.accesses 43300896 # DTB accesses +system.cpu0.numCycles 2391583901 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 42571581 # Number of instructions committed -system.cpu0.committedOps 53301862 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 48058821 # Number of integer alu accesses +system.cpu0.committedInsts 42571767 # Number of instructions committed +system.cpu0.committedOps 53302041 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 48059042 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses -system.cpu0.num_func_calls 1403638 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 5582830 # number of instructions that are conditional controls -system.cpu0.num_int_insts 48058821 # number of integer instructions +system.cpu0.num_func_calls 1403630 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 5582817 # number of instructions that are conditional controls +system.cpu0.num_int_insts 48059042 # number of integer instructions system.cpu0.num_fp_insts 3860 # number of float instructions -system.cpu0.num_int_register_reads 272440712 # number of times the integer registers were read -system.cpu0.num_int_register_writes 52270303 # number of times the integer registers were written +system.cpu0.num_int_register_reads 272441604 # number of times the integer registers were read +system.cpu0.num_int_register_writes 52270515 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written system.cpu0.num_mem_refs 18019009 # number of memory refs -system.cpu0.num_load_insts 10036459 # Number of load instructions -system.cpu0.num_store_insts 7982550 # Number of store instructions -system.cpu0.num_idle_cycles 2151176097.904201 # Number of idle cycles -system.cpu0.num_busy_cycles 240336549.095799 # Number of busy cycles -system.cpu0.not_idle_fraction 0.100496 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.899504 # Percentage of idle cycles +system.cpu0.num_load_insts 10036503 # Number of load instructions +system.cpu0.num_store_insts 7982506 # Number of store instructions +system.cpu0.num_idle_cycles 2151142905.888201 # Number of idle cycles +system.cpu0.num_busy_cycles 240440995.111799 # Number of busy cycles +system.cpu0.not_idle_fraction 0.100536 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.899464 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 51331 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 490259 # number of replacements -system.cpu0.icache.tags.tagsinuse 509.365280 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 42807737 # Total number of references to valid blocks. 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436393250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 436393250 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 436393250 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011335 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011335 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011335 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.011335 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011335 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.011335 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11892.155149 # average ReadReq mshr miss latency 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11902.398226 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11902.398226 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11902.398226 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11902.398226 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11902.398226 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were 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LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 166349 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 166349 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 16071438 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 16071438 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 16071438 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 16071438 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028088 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.028088 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.026487 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.026487 # miss rate for WriteReq accesses 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-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44670.147868 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 44670.147868 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9955.188917 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9955.188917 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5497.898371 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5497.898371 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26815.399057 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 26815.399057 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26815.399057 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 26815.399057 # average overall miss latency +system.cpu0.dcache.tags.occ_blocks::cpu0.data 471.656866 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.921205 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.921205 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 9136610 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 9136610 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 6494353 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 6494353 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 156522 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 156522 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 158977 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 158977 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 15630963 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 15630963 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 15630963 # number of overall hits +system.cpu0.dcache.overall_hits::total 15630963 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 263803 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 263803 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 176623 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 176623 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9911 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 9911 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7399 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7399 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 440426 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 440426 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 440426 # number of overall misses +system.cpu0.dcache.overall_misses::total 440426 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3917573248 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 3917573248 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7906184046 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 7906184046 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 99581999 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 99581999 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 40689888 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 40689888 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 11823757294 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 11823757294 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 11823757294 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 11823757294 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 9400413 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 9400413 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 6670976 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 6670976 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 166433 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 166433 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 166376 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 166376 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 16071389 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 16071389 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 16071389 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 16071389 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028063 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.028063 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.026476 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.026476 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059549 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059549 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.044472 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.044472 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027404 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.027404 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.027404 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.027404 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14850.374135 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14850.374135 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44763.049240 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 44763.049240 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10047.623751 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10047.623751 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5499.376673 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5499.376673 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26846.183681 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 26846.183681 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26846.183681 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 26846.183681 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1489,66 +1474,66 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 376552 # number of writebacks -system.cpu0.dcache.writebacks::total 376552 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 264039 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 264039 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 176698 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 176698 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9925 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9925 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7424 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7424 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 440737 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 440737 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 440737 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 440737 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3395057254 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3395057254 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7495344212 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7495344212 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 78904750 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 78904750 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 25999113 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 25999113 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10890401466 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10890401466 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10890401466 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10890401466 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13765517500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13765517500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 25807250835 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 25807250835 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 39572768335 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 39572768335 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028088 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.028088 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.026487 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.026487 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059640 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059640 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.044629 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.044629 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027424 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.027424 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027424 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.027424 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12858.165854 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12858.165854 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42418.953310 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42418.953310 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7950.100756 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7950.100756 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3502.035695 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3502.035695 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 376546 # number of writebacks +system.cpu0.dcache.writebacks::total 376546 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 263803 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 263803 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 176623 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 176623 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9911 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9911 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7395 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7395 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 440426 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 440426 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 440426 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 440426 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3387671752 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3387671752 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7508595954 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7508595954 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 79710001 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 79710001 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 25901112 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 25901112 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10896267706 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10896267706 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10896267706 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10896267706 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13765830000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13765830000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 25807312360 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 25807312360 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 39573142360 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 39573142360 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028063 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.028063 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.026476 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.026476 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059549 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059549 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.044448 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.044448 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027404 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.027404 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027404 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.027404 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12841.672581 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12841.672581 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42511.994214 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42511.994214 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8042.579054 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8042.579054 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3502.516836 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3502.516836 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24709.523970 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24709.523970 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24709.523970 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24709.523970 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24740.291686 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24740.291686 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24740.291686 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24740.291686 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1558,26 +1543,26 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 5708064 # DTB read hits -system.cpu1.dtb.read_misses 3582 # DTB read misses -system.cpu1.dtb.write_hits 3874465 # DTB write hits -system.cpu1.dtb.write_misses 647 # DTB write misses +system.cpu1.dtb.read_hits 5706417 # DTB read hits +system.cpu1.dtb.read_misses 3586 # DTB read misses +system.cpu1.dtb.write_hits 3873093 # DTB write hits +system.cpu1.dtb.write_misses 644 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu1.dtb.flush_entries 1989 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 142 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 148 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 5711646 # DTB read accesses -system.cpu1.dtb.write_accesses 3875112 # DTB write accesses +system.cpu1.dtb.read_accesses 5710003 # DTB read accesses +system.cpu1.dtb.write_accesses 3873737 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 9582529 # DTB hits -system.cpu1.dtb.misses 4229 # DTB misses -system.cpu1.dtb.accesses 9586758 # DTB accesses -system.cpu1.itb.inst_hits 19382020 # ITB inst hits +system.cpu1.dtb.hits 9579510 # DTB hits +system.cpu1.dtb.misses 4230 # DTB misses +system.cpu1.dtb.accesses 9583740 # DTB accesses +system.cpu1.itb.inst_hits 19379017 # ITB inst hits system.cpu1.itb.inst_misses 2171 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -1594,79 +1579,79 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 19384191 # ITB inst accesses -system.cpu1.itb.hits 19382020 # DTB hits +system.cpu1.itb.inst_accesses 19381188 # ITB inst accesses +system.cpu1.itb.hits 19379017 # DTB hits system.cpu1.itb.misses 2171 # DTB misses -system.cpu1.itb.accesses 19384191 # DTB accesses -system.cpu1.numCycles 2390063941 # number of cpu cycles simulated +system.cpu1.itb.accesses 19381188 # DTB accesses +system.cpu1.numCycles 2390136116 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 18801432 # Number of instructions committed -system.cpu1.committedOps 24909061 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 22272671 # Number of integer alu accesses +system.cpu1.committedInsts 18798461 # Number of instructions committed +system.cpu1.committedOps 24902767 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 22266699 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses -system.cpu1.num_func_calls 796781 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 2514806 # number of instructions that are conditional controls -system.cpu1.num_int_insts 22272671 # number of integer instructions +system.cpu1.num_func_calls 796691 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 2514546 # number of instructions that are conditional controls +system.cpu1.num_int_insts 22266699 # number of integer instructions system.cpu1.num_fp_insts 6793 # number of float instructions -system.cpu1.num_int_register_reads 130802029 # number of times the integer registers were read -system.cpu1.num_int_register_writes 23323968 # number of times the integer registers were written +system.cpu1.num_int_register_reads 130767489 # number of times the integer registers were read +system.cpu1.num_int_register_writes 23318960 # number of times the integer registers were written system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written -system.cpu1.num_mem_refs 10017952 # number of memory refs -system.cpu1.num_load_insts 5984754 # Number of load instructions -system.cpu1.num_store_insts 4033198 # Number of store instructions -system.cpu1.num_idle_cycles 1969143633.381917 # Number of idle cycles -system.cpu1.num_busy_cycles 420920307.618083 # Number of busy cycles -system.cpu1.not_idle_fraction 0.176113 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.823887 # Percentage of idle cycles +system.cpu1.num_mem_refs 10014870 # number of memory refs +system.cpu1.num_load_insts 5983067 # Number of load instructions +system.cpu1.num_store_insts 4031803 # Number of store instructions +system.cpu1.num_idle_cycles 1969216562.004314 # Number of idle cycles +system.cpu1.num_busy_cycles 420919553.995686 # Number of busy cycles +system.cpu1.not_idle_fraction 0.176107 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.823893 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 39084 # number of quiesce instructions executed -system.cpu1.icache.tags.replacements 376793 # number of replacements -system.cpu1.icache.tags.tagsinuse 474.907040 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 19004711 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 377305 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 50.369624 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 327169943500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 474.907040 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.927553 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.927553 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 19004711 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 19004711 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 19004711 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 19004711 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 19004711 # number of overall hits -system.cpu1.icache.overall_hits::total 19004711 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 377305 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 377305 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 377305 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 377305 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 377305 # number of overall misses -system.cpu1.icache.overall_misses::total 377305 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5159789711 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 5159789711 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 5159789711 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 5159789711 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 5159789711 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 5159789711 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 19382016 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 19382016 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 19382016 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 19382016 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 19382016 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 19382016 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.019467 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.019467 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.019467 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.019467 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.019467 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.019467 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13675.381219 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13675.381219 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13675.381219 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13675.381219 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13675.381219 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13675.381219 # average overall miss latency +system.cpu1.kern.inst.quiesce 39069 # number of quiesce instructions executed +system.cpu1.icache.tags.replacements 376769 # number of replacements +system.cpu1.icache.tags.tagsinuse 474.890792 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 19001732 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 377281 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 50.364932 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 327211938000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 474.890792 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.927521 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.927521 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 19001732 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 19001732 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 19001732 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 19001732 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 19001732 # number of overall hits +system.cpu1.icache.overall_hits::total 19001732 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 377281 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 377281 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 377281 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 377281 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 377281 # number of overall misses +system.cpu1.icache.overall_misses::total 377281 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5163865212 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 5163865212 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 5163865212 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 5163865212 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 5163865212 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 5163865212 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 19379013 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 19379013 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 19379013 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 19379013 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 19379013 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 19379013 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.019469 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.019469 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.019469 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.019469 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.019469 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.019469 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13687.053448 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13687.053448 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13687.053448 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13687.053448 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13687.053448 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13687.053448 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1675,120 +1660,120 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 377305 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 377305 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 377305 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 377305 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 377305 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 377305 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4403600289 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 4403600289 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4403600289 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 4403600289 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4403600289 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 4403600289 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6432750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6432750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6432750 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 6432750 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.019467 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.019467 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.019467 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.019467 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.019467 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.019467 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11671.195158 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11671.195158 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11671.195158 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11671.195158 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11671.195158 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11671.195158 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 377281 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 377281 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 377281 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 377281 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 377281 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 377281 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4407732788 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 4407732788 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4407732788 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 4407732788 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4407732788 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 4407732788 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6483750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6483750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6483750 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 6483750 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.019469 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.019469 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.019469 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.019469 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.019469 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.019469 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11682.890970 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11682.890970 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11682.890970 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11682.890970 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11682.890970 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11682.890970 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 220883 # number of replacements -system.cpu1.dcache.tags.tagsinuse 471.477381 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 8233318 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 221230 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 37.216101 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 106377423000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 471.477381 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.920854 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.920854 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 4390672 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 4390672 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 3674527 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 3674527 # number of WriteReq hits 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-system.cpu1.dcache.overall_accesses::total 8312116 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.029635 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.029635 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.029790 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.029790 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.117265 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.117265 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.113382 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.113382 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029706 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.029706 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.029706 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.029706 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12357.198367 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12357.198367 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 38584.731279 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 38584.731279 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 7943.505327 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 7943.505327 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5233.850673 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5233.850673 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24341.686498 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 24341.686498 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24341.686498 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 24341.686498 # average overall miss latency +system.cpu1.dcache.tags.replacements 220436 # number of replacements +system.cpu1.dcache.tags.tagsinuse 471.379597 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 8230755 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 220801 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 37.276801 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 106418022500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 471.379597 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.920663 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.920663 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 4389351 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 4389351 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 3673214 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 3673214 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 73456 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 73456 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 73714 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 73714 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 8062565 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 8062565 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 8062565 # number of overall hits +system.cpu1.dcache.overall_hits::total 8062565 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 133803 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 133803 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 112797 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 112797 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9752 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 9752 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 9418 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 9418 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 246600 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 246600 # 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overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1797,66 +1782,66 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 200272 # number of writebacks -system.cpu1.dcache.writebacks::total 200272 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 134090 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 134090 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 112827 # number of WriteReq MSHR misses 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-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1388441271 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4117774524 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4117774524 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 58015501 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 58015501 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 30499022 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30499022 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles 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-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 5942.993342 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3235.627201 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3235.627201 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 199592 # number of writebacks +system.cpu1.dcache.writebacks::total 199592 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 133803 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 133803 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 112797 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 112797 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9752 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9752 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9415 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 9415 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 246600 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 246600 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 246600 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 246600 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1380025261 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1380025261 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4109897774 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4109897774 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 57992002 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 57992002 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 30524522 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30524522 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5489923035 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 5489923035 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5489923035 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 5489923035 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168387761500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168387761500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 531061000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 531061000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 168918822500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 168918822500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.029582 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.029582 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.029793 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.029793 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.117200 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.117200 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.113254 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.113254 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029678 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.029678 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.029678 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.029678 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10313.858890 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10313.858890 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36436.233003 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 36436.233003 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 5946.677810 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 5946.677810 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3242.115985 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3242.115985 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22299.865117 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22299.865117 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22299.865117 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22299.865117 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22262.461618 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22262.461618 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22262.461618 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22262.461618 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1878,10 +1863,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 651875253502 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 651875253502 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 651875253502 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 651875253502 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 651879453001 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 651879453001 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 651879453001 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 651879453001 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini index 01d95ba19..925b86307 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=true +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -10,17 +12,18 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu cpu_clk_domain intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain atags_addr=256 -boot_loader=/dist/m5/system/binaries/boot.arm +boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=False +dtb_filename= early_kernel_symbols=false enable_context_switch_stats_dump=false +eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -45,6 +48,7 @@ system_port=system.membus.slave[0] type=Bridge clk_domain=system.clk_domain delay=50000 +eventq_index=0 ranges=268435456:520093695 1073741824:1610612735 req_size=16 resp_size=16 @@ -56,24 +60,28 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.cf0.image [system.cf0.image] type=CowDiskImage children=child child=system.cf0.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-arm-ael.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img read_only=true [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -86,6 +94,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -112,6 +121,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -134,18 +144,21 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -156,6 +169,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -178,14 +192,17 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -204,12 +221,14 @@ midr=890224640 [system.cpu.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -220,6 +239,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -242,12 +262,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=4194304 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -257,19 +279,23 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.intrctrl] type=IntrControl +eventq_index=0 sys=system [system.iobus] type=NoncoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 use_default_range=false width=8 @@ -282,6 +308,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +eventq_index=0 forward_snoops=false hit_latency=50 is_top_level=true @@ -304,6 +331,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +eventq_index=0 hit_latency=50 size=1024 @@ -311,6 +339,7 @@ size=1024 type=CoherentBus children=badaddr_responder clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -322,6 +351,7 @@ slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=0 pio_latency=100000 @@ -348,6 +378,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -359,19 +390,23 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[6] [system.realview] type=RealView children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +eventq_index=0 intrctrl=system.intrctrl max_mem_size=268435456 mem_start_addr=0 @@ -381,6 +416,7 @@ system=system [system.realview.a9scu] type=A9SCU clk_domain=system.clk_domain +eventq_index=0 pio_addr=520093696 pio_latency=100000 system=system @@ -390,6 +426,7 @@ pio=system.membus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268451840 pio_latency=100000 @@ -418,6 +455,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=1 Command=1 @@ -427,8 +465,40 @@ HeaderType=0 InterruptLine=31 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=0 MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=133 Revision=0 Status=640 @@ -440,6 +510,7 @@ clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 disks=system.cf0 +eventq_index=0 io_shift=1 pci_bus=2 pci_dev=7 @@ -455,6 +526,8 @@ pio=system.iobus.master[7] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 gic=system.realview.gic int_num=55 pio_addr=268566528 @@ -469,6 +542,7 @@ pio=system.iobus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268632064 pio_latency=100000 @@ -478,6 +552,7 @@ pio=system.iobus.master[9] [system.realview.flash_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=true pio_addr=1073741824 pio_latency=100000 @@ -499,8 +574,10 @@ cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 dist_pio_delay=10000 +eventq_index=0 int_latency=10000 it_lines=128 +msix_addr=0 platform=system.realview system=system pio=system.membus.master[2] @@ -509,6 +586,7 @@ pio=system.membus.master[2] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268513280 pio_latency=100000 @@ -519,6 +597,7 @@ pio=system.iobus.master[16] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268517376 pio_latency=100000 @@ -529,6 +608,7 @@ pio=system.iobus.master[17] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268521472 pio_latency=100000 @@ -539,6 +619,7 @@ pio=system.iobus.master[18] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=52 @@ -553,6 +634,7 @@ pio=system.iobus.master[5] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=53 @@ -566,6 +648,7 @@ pio=system.iobus.master[6] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=520101888 pio_latency=100000 @@ -583,6 +666,7 @@ pio=system.membus.master[3] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 @@ -595,6 +679,7 @@ pio=system.membus.master[5] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268455936 pio_latency=100000 @@ -606,6 +691,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -616,6 +702,7 @@ port=system.membus.master[1] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +eventq_index=0 idreg=0 pio_addr=268435456 pio_latency=100000 @@ -628,6 +715,7 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=42 @@ -641,6 +729,7 @@ pio=system.iobus.master[23] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268492800 pio_latency=100000 @@ -651,6 +740,7 @@ pio=system.iobus.master[20] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=269357056 pio_latency=100000 @@ -661,6 +751,7 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=true pio_addr=268439552 pio_latency=100000 @@ -671,6 +762,7 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268488704 pio_latency=100000 @@ -683,6 +775,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=36 int_num1=36 @@ -697,6 +790,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=37 int_num1=37 @@ -709,6 +803,7 @@ pio=system.iobus.master[3] type=Pl011 clk_domain=system.clk_domain end_on_eot=false +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=44 @@ -723,6 +818,7 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268476416 pio_latency=100000 @@ -733,6 +829,7 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268480512 pio_latency=100000 @@ -743,6 +840,7 @@ pio=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268484608 pio_latency=100000 @@ -753,6 +851,7 @@ pio=system.iobus.master[12] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268500992 pio_latency=100000 @@ -761,6 +860,7 @@ pio=system.iobus.master[15] [system.terminal] type=Terminal +eventq_index=0 intr_control=system.intrctrl number=0 output=true @@ -768,11 +868,13 @@ port=3456 [system.vncserver] type=VncServer +eventq_index=0 frame_capture=false number=0 port=5900 [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 50a428e90..df8a2beae 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.616536 # Nu sim_ticks 2616536483000 # Number of ticks simulated final_tick 2616536483000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 552343 # Simulator instruction rate (inst/s) -host_op_rate 702879 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 24008008080 # Simulator tick rate (ticks/s) -host_mem_usage 395660 # Number of bytes of host memory used -host_seconds 108.99 # Real time elapsed on the host +host_inst_rate 343075 # Simulator instruction rate (inst/s) +host_op_rate 436578 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 14912044248 # Simulator tick rate (ticks/s) +host_mem_usage 444348 # Number of bytes of host memory used +host_seconds 175.46 # Real time elapsed on the host sim_insts 60197580 # Number of instructions simulated sim_ops 76603973 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory @@ -110,23 +110,23 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 57909 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1265330 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1118297 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1122310 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3740106 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2667387 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2661184 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2667924 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 52364 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 54482 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 20799 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 20747 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 20660 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 20420 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 20349 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 20284 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 20256 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 152 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1246989 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1099674 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1103822 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3738072 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2684241 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2677986 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2686359 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 54486 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 57692 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 20800 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 20766 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 20672 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 20426 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 20356 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 20289 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 20260 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 161 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -174,461 +174,452 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 89727 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 11127.069087 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 1028.273701 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 16706.873806 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 23194 25.85% 25.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 14559 16.23% 42.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 2860 3.19% 45.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 2118 2.36% 47.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 1356 1.51% 49.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 1216 1.36% 50.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 947 1.06% 51.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 1180 1.32% 52.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 650 0.72% 53.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 587 0.65% 54.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 521 0.58% 54.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 703 0.78% 55.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 336 0.37% 55.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 268 0.30% 56.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 216 0.24% 56.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 509 0.57% 57.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 151 0.17% 57.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 159 0.18% 57.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 138 0.15% 57.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 229 0.26% 57.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 105 0.12% 57.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 2288 2.55% 60.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 101 0.11% 60.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 246 0.27% 60.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 69 0.08% 60.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 53 0.06% 61.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 41 0.05% 61.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 188 0.21% 61.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 32 0.04% 61.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 26 0.03% 61.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 28 0.03% 61.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 180 0.20% 61.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 16 0.02% 61.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 28 0.03% 61.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 12 0.01% 61.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 150 0.17% 61.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 18 0.02% 61.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 17 0.02% 61.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 27 0.03% 61.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 112 0.12% 62.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 10 0.01% 62.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 11 0.01% 62.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 11 0.01% 62.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 157 0.17% 62.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 13 0.01% 62.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 16 0.02% 62.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3015 13 0.01% 62.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 359 0.40% 62.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 14 0.02% 62.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 18 0.02% 62.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 14 0.02% 62.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 100 0.11% 62.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 13 0.01% 62.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 18 0.02% 62.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 9 0.01% 62.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 89 0.10% 62.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 10 0.01% 62.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 18 0.02% 63.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 39 0.04% 63.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 147 0.16% 63.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 89677 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 11133.273058 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 1028.792401 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 16712.114180 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 23203 25.87% 25.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 14561 16.24% 42.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 2861 3.19% 45.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 2042 2.28% 47.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 1356 1.51% 49.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 1217 1.36% 50.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 956 1.07% 51.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 1130 1.26% 52.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 649 0.72% 53.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 589 0.66% 54.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 514 0.57% 54.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 694 0.77% 55.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 336 0.37% 55.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 266 0.30% 56.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 214 0.24% 56.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 726 0.81% 57.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 152 0.17% 57.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 154 0.17% 57.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1223 137 0.15% 57.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1287 157 0.18% 57.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1351 104 0.12% 58.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 2288 2.55% 60.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 101 0.11% 60.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 181 0.20% 60.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 64 0.07% 60.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 57 0.06% 61.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 41 0.05% 61.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1799 133 0.15% 61.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1863 31 0.03% 61.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1927 28 0.03% 61.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1991 28 0.03% 61.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2055 301 0.34% 61.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2119 17 0.02% 61.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2183 32 0.04% 61.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2247 11 0.01% 61.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2311 93 0.10% 61.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2375 18 0.02% 61.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2439 15 0.02% 61.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2503 26 0.03% 61.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2567 91 0.10% 61.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2631 10 0.01% 61.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2695 14 0.02% 62.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2759 13 0.01% 62.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2823 158 0.18% 62.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2887 12 0.01% 62.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2951 12 0.01% 62.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3015 13 0.01% 62.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3079 372 0.41% 62.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3143 14 0.02% 62.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3207 19 0.02% 62.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3271 14 0.02% 62.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3335 153 0.17% 62.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3399 13 0.01% 62.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3463 19 0.02% 62.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3527 8 0.01% 62.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3591 102 0.11% 63.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3655 10 0.01% 63.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3719 17 0.02% 63.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3783 39 0.04% 63.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3847 95 0.11% 63.21% # Bytes accessed per row activation system.physmem.bytesPerActivate::3904-3911 12 0.01% 63.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 13 0.01% 63.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3975 14 0.02% 63.23% # Bytes accessed per row activation system.physmem.bytesPerActivate::4032-4039 10 0.01% 63.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4103 177 0.20% 63.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4167 8 0.01% 63.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 12 0.01% 63.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4295 6 0.01% 63.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4359 149 0.17% 63.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 6 0.01% 63.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 10 0.01% 63.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4551 9 0.01% 63.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 161 0.18% 63.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4679 7 0.01% 63.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4743 6 0.01% 63.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4807 11 0.01% 63.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 82 0.09% 63.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 7 0.01% 63.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4999 13 0.01% 63.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5063 7 0.01% 63.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 497 0.55% 64.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 11 0.01% 64.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5255 8 0.01% 64.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5319 7 0.01% 64.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5383 18 0.02% 64.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5447 18 0.02% 64.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 64 0.07% 64.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5575 10 0.01% 64.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 138 0.15% 64.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5703 1 0.00% 64.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5831 1 0.00% 64.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5895 89 0.10% 64.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5959 1 0.00% 64.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6023 2 0.00% 64.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6151 276 0.31% 65.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6215 1 0.00% 65.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6407 33 0.04% 65.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6535 3 0.00% 65.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6599 1 0.00% 65.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6663 146 0.16% 65.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6727 1 0.00% 65.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6919 83 0.09% 65.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7047 5 0.01% 65.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7175 526 0.59% 66.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7239 1 0.00% 66.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7431 79 0.09% 66.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7559 1 0.00% 66.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7623 1 0.00% 66.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7687 37 0.04% 66.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7879 1 0.00% 66.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7943 10 0.01% 66.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8071 2 0.00% 66.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8199 407 0.45% 66.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8320-8327 1 0.00% 66.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8455 12 0.01% 66.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8711 33 0.04% 66.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8967 77 0.09% 66.89% # Bytes accessed per row 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-system.physmem.bytesPerActivate::46976-46983 3 0.00% 92.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47104-47111 149 0.17% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47232-47239 3 0.00% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47367 156 0.17% 93.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47623 157 0.17% 93.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47744-47751 3 0.00% 93.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47872-47879 88 0.10% 93.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47936-47943 1 0.00% 93.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48000-48007 1 0.00% 93.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48135 298 0.33% 93.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48192-48199 4 0.00% 93.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48256-48263 1 0.00% 93.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48320-48327 3 0.00% 93.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48391 110 0.12% 93.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48512-48519 1 0.00% 93.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48640-48647 200 0.22% 94.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48768-48775 70 0.08% 94.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48903 136 0.15% 94.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48960-48967 5 0.01% 94.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49024-49031 9 0.01% 94.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49088-49095 6 0.01% 94.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49159 5002 5.57% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 89727 # Bytes accessed per row activation -system.physmem.totQLat 373414318500 # Total ticks spent queuing -system.physmem.totMemAccLat 469593144750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::46208-46215 1 0.00% 92.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 145 0.16% 92.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 72 0.08% 92.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46720-46727 3 0.00% 92.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 83 0.09% 92.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46976-46983 3 0.00% 92.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 266 0.30% 93.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 97 0.11% 93.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 87 0.10% 93.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47744-47751 5 0.01% 93.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 17 0.02% 93.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47936-47943 1 0.00% 93.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 515 0.57% 93.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48192-48199 4 0.00% 93.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48256-48263 2 0.00% 93.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48320-48327 3 0.00% 93.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 100 0.11% 94.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 142 0.16% 94.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48768-48775 73 0.08% 94.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 73 0.08% 94.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48960-48967 3 0.00% 94.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49024-49031 8 0.01% 94.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 7 0.01% 94.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 5062 5.64% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 89677 # Bytes accessed per row activation +system.physmem.totQLat 373683436750 # Total ticks spent queuing +system.physmem.totMemAccLat 469596379250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 77465255000 # Total ticks spent in databus transfers -system.physmem.totBankLat 18713571250 # Total ticks spent accessing banks -system.physmem.avgQLat 24102.05 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1207.87 # Average bank access latency per DRAM burst +system.physmem.totBankLat 18447687500 # Total ticks spent accessing banks +system.physmem.avgQLat 24119.42 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1190.71 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30309.92 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 30310.13 # Average memory access latency per DRAM burst system.physmem.avgRdBW 378.96 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.62 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 50.63 # Average system read bandwidth in MiByte/s @@ -639,12 +630,12 @@ system.physmem.busUtilRead 2.96 # Da system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing system.physmem.avgWrQLen 14.75 # Average write queue length when enqueuing -system.physmem.readRowHits 15419103 # Number of row buffer hits during reads -system.physmem.writeRowHits 91153 # Number of row buffer hits during writes +system.physmem.readRowHits 15419160 # Number of row buffer hits during reads +system.physmem.writeRowHits 91146 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 85.23 # Row buffer hit rate for writes +system.physmem.writeRowHitRate 85.22 # Row buffer hit rate for writes system.physmem.avgGap 160458.28 # Average gap between requests -system.physmem.pageHitRate 99.42 # Row buffer hit rate, read and write combined +system.physmem.pageHitRate 99.43 # Row buffer hit rate, read and write combined system.physmem.prechargeAllPercent 2.19 # Percentage of time for which DRAM has all the banks in precharge state system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory @@ -696,11 +687,11 @@ system.membus.reqLayer2.occupancy 3614000 # La system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17910601500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17910610000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4950348835 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4950347835 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 34633819250 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 34635983250 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -818,7 +809,7 @@ system.iobus.reqLayer25.occupancy 15335424000 # La system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) system.iobus.respLayer0.occupancy 2374820000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42037561750 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42035380750 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses @@ -886,33 +877,33 @@ system.cpu.not_idle_fraction 0.124505 # Pe system.cpu.idle_fraction 0.875495 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 83016 # number of quiesce instructions executed -system.cpu.icache.tags.replacements 856254 # number of replacements +system.cpu.icache.tags.replacements 856260 # number of replacements system.cpu.icache.tags.tagsinuse 510.868538 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 60634647 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 856766 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 70.771537 # Average number of references to valid blocks. +system.cpu.icache.tags.total_refs 60634641 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 856772 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 70.771035 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 19982971250 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 510.868538 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.997790 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.997790 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 60634647 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 60634647 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 60634647 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 60634647 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 60634647 # number of overall hits -system.cpu.icache.overall_hits::total 60634647 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 856766 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 856766 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 856766 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 856766 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 856766 # number of overall misses -system.cpu.icache.overall_misses::total 856766 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11773893500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11773893500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11773893500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11773893500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11773893500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11773893500 # number of overall miss cycles +system.cpu.icache.ReadReq_hits::cpu.inst 60634641 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 60634641 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 60634641 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 60634641 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 60634641 # number of overall hits +system.cpu.icache.overall_hits::total 60634641 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 856772 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 856772 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 856772 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 856772 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 856772 # number of overall misses +system.cpu.icache.overall_misses::total 856772 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11773713250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11773713250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11773713250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11773713250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11773713250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11773713250 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 61491413 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 61491413 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 61491413 # number of demand (read+write) accesses @@ -925,12 +916,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.013933 system.cpu.icache.demand_miss_rate::total 0.013933 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.013933 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.013933 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13742.251093 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13742.251093 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13742.251093 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13742.251093 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13742.251093 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13742.251093 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13741.944473 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13741.944473 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13741.944473 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13741.944473 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13741.944473 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13741.944473 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -939,18 +930,18 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856766 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 856766 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 856766 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 856766 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 856766 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 856766 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10056315500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 10056315500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10056315500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 10056315500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10056315500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 10056315500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856772 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 856772 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 856772 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 856772 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 856772 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 856772 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10056122750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 10056122750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10056122750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 10056122750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10056122750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 10056122750 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 435321250 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 435321250 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 435321250 # number of overall MSHR uncacheable cycles @@ -961,28 +952,28 @@ system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013933 system.cpu.icache.demand_mshr_miss_rate::total 0.013933 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.013933 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11737.528683 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11737.528683 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11737.528683 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11737.528683 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11737.528683 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11737.528683 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11737.221513 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11737.221513 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11737.221513 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11737.221513 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11737.221513 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11737.221513 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 62509 # number of replacements -system.cpu.l2cache.tags.tagsinuse 50754.670173 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1682271 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 50754.670351 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1682272 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 127891 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 13.153944 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 13.153951 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 2565643785000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 37718.408308 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 37718.407530 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.884371 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000703 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 6993.399948 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 6038.976844 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 6993.400299 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 6038.977449 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.575537 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy @@ -991,122 +982,122 @@ system.cpu.l2cache.tags.occ_percent::cpu.data 0.092147 system.cpu.l2cache.tags.occ_percent::total 0.774455 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8705 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3532 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 844545 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 369635 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1226417 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 595234 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 595234 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 844551 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 369631 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1226419 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 595233 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 595233 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits 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system.cpu.l2cache.overall_hits::cpu.dtb.walker 8705 # number of overall hits system.cpu.l2cache.overall_hits::cpu.itb.walker 3532 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 844545 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 483020 # number of overall hits -system.cpu.l2cache.overall_hits::total 1339802 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 844551 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 483019 # number of overall hits +system.cpu.l2cache.overall_hits::total 1339807 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.inst 10585 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 9809 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 20401 # number of ReadReq misses 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-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229207 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.103228 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229206 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.103227 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58563.863958 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62731.216230 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60565.499240 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10003.407981 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10003.407981 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59368.017755 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59368.017755 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58539.230043 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62672.418187 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60524.447331 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.031637 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.031637 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59374.304918 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59374.304918 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58563.863958 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59597.697660 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59526.421514 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58539.230043 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59599.541585 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59526.447615 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58563.863958 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59597.697660 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59526.421514 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58539.230043 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59599.541585 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59526.447615 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1210,47 +1201,47 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 626141 # number of replacements +system.cpu.dcache.tags.replacements 626139 # number of replacements system.cpu.dcache.tags.tagsinuse 511.876746 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 23655438 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 626653 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37.748863 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 23655440 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 626651 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37.748986 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 664004250 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.876746 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999759 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999759 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13195736 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13195736 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 9972597 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 9972597 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 236394 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 236394 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 13195741 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13195741 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 9972594 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 9972594 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 236393 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 236393 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 247778 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 247778 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 23168333 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 23168333 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 23168333 # number of overall hits -system.cpu.dcache.overall_hits::total 23168333 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 368059 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 368059 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 250142 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 250142 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 11385 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 11385 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 618201 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 618201 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 618201 # number of overall misses -system.cpu.dcache.overall_misses::total 618201 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5416878250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5416878250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 11621403015 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 11621403015 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 158363750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 158363750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 17038281265 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17038281265 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 17038281265 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17038281265 # number of overall miss cycles +system.cpu.dcache.demand_hits::cpu.data 23168335 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 23168335 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 23168335 # number of overall hits +system.cpu.dcache.overall_hits::total 23168335 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 368054 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 368054 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 250145 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 250145 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 11386 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 11386 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 618199 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 618199 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 618199 # number of overall misses +system.cpu.dcache.overall_misses::total 618199 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5416240000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5416240000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 11622215515 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 11622215515 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 158376750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 158376750 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 17038455515 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17038455515 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 17038455515 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17038455515 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 13563795 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 13563795 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 10222739 # number of WriteReq accesses(hits+misses) @@ -1267,22 +1258,22 @@ system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027135 system.cpu.dcache.ReadReq_miss_rate::total 0.027135 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024469 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.024469 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045948 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045948 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025990 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025990 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.025990 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.025990 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14717.418267 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14717.418267 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46459.223221 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 46459.223221 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13909.859464 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13909.859464 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 27561.070372 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 27561.070372 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 27561.070372 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 27561.070372 # average overall miss latency +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045952 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045952 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.025989 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025989 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.025989 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.025989 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14715.884082 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14715.884082 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46461.914150 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 46461.914150 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13909.779554 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13909.779554 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 27561.441405 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 27561.441405 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 27561.441405 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 27561.441405 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1291,28 +1282,28 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 595234 # number of writebacks -system.cpu.dcache.writebacks::total 595234 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368059 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 368059 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250142 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 250142 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11385 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 11385 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 618201 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 618201 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 618201 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 618201 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4678465750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4678465750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11069177985 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11069177985 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 135539250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 135539250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15747643735 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 15747643735 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15747643735 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 15747643735 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 595233 # number of writebacks +system.cpu.dcache.writebacks::total 595233 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368054 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 368054 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250145 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 250145 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11386 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 11386 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 618199 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 618199 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 618199 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 618199 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4677837000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4677837000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11069989485 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11069989485 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 135550250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 135550250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15747826485 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15747826485 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15747826485 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15747826485 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182050613250 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182050613250 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26234152350 # number of WriteReq MSHR uncacheable cycles @@ -1323,22 +1314,22 @@ system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027135 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027135 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024469 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024469 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.045948 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.045948 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025990 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025990 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025990 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025990 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12711.184212 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12711.184212 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44251.577044 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44251.577044 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11905.072464 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11905.072464 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25473.339149 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25473.339149 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25473.339149 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 25473.339149 # average overall mshr miss latency +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.045952 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.045952 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025989 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025989 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025989 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025989 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12709.648584 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12709.648584 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44254.290452 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44254.290452 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11904.992974 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11904.992974 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25473.717177 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25473.717177 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25473.717177 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25473.717177 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1346,33 +1337,33 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 52965120 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2454582 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2454582 # Transaction distribution +system.cpu.toL2Bus.throughput 52965193 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2454584 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2454584 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 763368 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 763368 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 595234 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2933 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2933 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 247209 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 247209 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1725138 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5749352 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::Writeback 595233 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2934 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2934 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 247211 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 247211 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1725150 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5749349 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12460 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27430 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7514380 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54754804 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 83615077 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7514389 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54755188 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 83614885 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14136 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 34840 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 138418857 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 138418857 # Total data (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 138419049 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 138419049 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 166312 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3008581500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 3008582500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1295429750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1295439000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2534385915 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2534381165 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer2.occupancy 8926000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) @@ -1392,10 +1383,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1538389615750 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1538389615750 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1538389615750 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1538389615750 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1538393065750 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1538393065750 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1538393065750 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1538393065750 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini index d251aac9e..44d2483e8 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=true +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -10,22 +12,23 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=256 -boot_loader=/dist/m5/system/binaries/boot.arm +boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=False +dtb_filename= early_kernel_symbols=false enable_context_switch_stats_dump=false +eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=atomic mem_ranges=0:134217727 -memories=system.physmem system.realview.nvmem +memories=system.realview.nvmem system.physmem multi_proc=true num_work_ids=16 panic_on_oops=true @@ -45,6 +48,7 @@ system_port=system.membus.slave[0] type=Bridge clk_domain=system.clk_domain delay=50000 +eventq_index=0 ranges=268435456:520093695 1073741824:1610612735 req_size=16 resp_size=16 @@ -56,24 +60,28 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.cf0.image [system.cf0.image] type=CowDiskImage children=child child=system.cf0.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-arm-ael.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img read_only=true [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu0] @@ -86,6 +94,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu0.dtb +eventq_index=0 fastmem=false function_trace=false function_trace_start=0 @@ -119,6 +128,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -141,18 +151,21 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu0.dtb.walker [system.cpu0.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[3] @@ -163,6 +176,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -185,14 +199,17 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu0.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -211,18 +228,21 @@ midr=890224640 [system.cpu0.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu0.itb.walker [system.cpu0.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[2] [system.cpu0.tracer] type=ExeTracer +eventq_index=0 [system.cpu1] type=AtomicSimpleCPU @@ -234,6 +254,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu1.dtb +eventq_index=0 fastmem=false function_trace=false function_trace_start=0 @@ -262,17 +283,20 @@ workload= [system.cpu1.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu1.dtb.walker [system.cpu1.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system [system.cpu1.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -291,30 +315,36 @@ midr=890224640 [system.cpu1.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu1.itb.walker [system.cpu1.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system [system.cpu1.tracer] type=ExeTracer +eventq_index=0 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.intrctrl] type=IntrControl +eventq_index=0 sys=system [system.iobus] type=NoncoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 use_default_range=false width=8 @@ -327,6 +357,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +eventq_index=0 forward_snoops=false hit_latency=50 is_top_level=true @@ -349,6 +380,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +eventq_index=0 hit_latency=50 size=1024 @@ -358,6 +390,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -380,6 +413,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=4194304 @@ -387,6 +421,7 @@ size=4194304 type=CoherentBus children=badaddr_responder clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -398,6 +433,7 @@ slave=system.system_port system.l2c.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=0 pio_latency=100000 @@ -413,41 +449,22 @@ warn_access=warn pio=system.membus.default [system.physmem] -type=SimpleDRAM -activation_limit=4 -addr_mapping=RaBaChCo -banks_per_rank=8 -burst_length=8 -channels=1 +type=SimpleMemory +bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true -device_bus_width=8 -device_rowbuffer_size=1024 -devices_per_rank=8 +eventq_index=0 in_addr_map=true -mem_sched_policy=frfcfs +latency=30000 +latency_var=0 null=false -page_policy=open range=0:134217727 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCL=13750 -tRCD=13750 -tREFI=7800000 -tRFC=300000 -tRP=13750 -tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_thresh_perc=70 port=system.membus.master[6] [system.realview] type=RealView children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +eventq_index=0 intrctrl=system.intrctrl max_mem_size=268435456 mem_start_addr=0 @@ -457,6 +474,7 @@ system=system [system.realview.a9scu] type=A9SCU clk_domain=system.clk_domain +eventq_index=0 pio_addr=520093696 pio_latency=100000 system=system @@ -466,6 +484,7 @@ pio=system.membus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268451840 pio_latency=100000 @@ -494,6 +513,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=1 Command=1 @@ -503,8 +523,40 @@ HeaderType=0 InterruptLine=31 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=0 MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=133 Revision=0 Status=640 @@ -516,6 +568,7 @@ clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 disks=system.cf0 +eventq_index=0 io_shift=1 pci_bus=2 pci_dev=7 @@ -531,6 +584,8 @@ pio=system.iobus.master[7] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 gic=system.realview.gic int_num=55 pio_addr=268566528 @@ -545,6 +600,7 @@ pio=system.iobus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268632064 pio_latency=100000 @@ -554,6 +610,7 @@ pio=system.iobus.master[9] [system.realview.flash_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=true pio_addr=1073741824 pio_latency=100000 @@ -575,8 +632,10 @@ cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 dist_pio_delay=10000 +eventq_index=0 int_latency=10000 it_lines=128 +msix_addr=0 platform=system.realview system=system pio=system.membus.master[2] @@ -585,6 +644,7 @@ pio=system.membus.master[2] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268513280 pio_latency=100000 @@ -595,6 +655,7 @@ pio=system.iobus.master[16] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268517376 pio_latency=100000 @@ -605,6 +666,7 @@ pio=system.iobus.master[17] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268521472 pio_latency=100000 @@ -615,6 +677,7 @@ pio=system.iobus.master[18] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=52 @@ -629,6 +692,7 @@ pio=system.iobus.master[5] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=53 @@ -642,6 +706,7 @@ pio=system.iobus.master[6] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=520101888 pio_latency=100000 @@ -659,6 +724,7 @@ pio=system.membus.master[3] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 @@ -671,6 +737,7 @@ pio=system.membus.master[5] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268455936 pio_latency=100000 @@ -682,6 +749,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -692,6 +760,7 @@ port=system.membus.master[1] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +eventq_index=0 idreg=0 pio_addr=268435456 pio_latency=100000 @@ -704,6 +773,7 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=42 @@ -717,6 +787,7 @@ pio=system.iobus.master[23] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268492800 pio_latency=100000 @@ -727,6 +798,7 @@ pio=system.iobus.master[20] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=269357056 pio_latency=100000 @@ -737,6 +809,7 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=true pio_addr=268439552 pio_latency=100000 @@ -747,6 +820,7 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268488704 pio_latency=100000 @@ -759,6 +833,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=36 int_num1=36 @@ -773,6 +848,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=37 int_num1=37 @@ -785,6 +861,7 @@ pio=system.iobus.master[3] type=Pl011 clk_domain=system.clk_domain end_on_eot=false +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=44 @@ -799,6 +876,7 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268476416 pio_latency=100000 @@ -809,6 +887,7 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268480512 pio_latency=100000 @@ -819,6 +898,7 @@ pio=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268484608 pio_latency=100000 @@ -829,6 +909,7 @@ pio=system.iobus.master[12] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268500992 pio_latency=100000 @@ -837,6 +918,7 @@ pio=system.iobus.master[15] [system.terminal] type=Terminal +eventq_index=0 intr_control=system.intrctrl number=0 output=true @@ -845,6 +927,7 @@ port=3456 [system.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -854,11 +937,13 @@ slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.wa [system.vncserver] type=VncServer +eventq_index=0 frame_capture=false number=0 port=5900 [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt index fae0b4d4b..7eb912550 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt @@ -4,13 +4,25 @@ sim_seconds 2.332810 # Nu sim_ticks 2332810264000 # Number of ticks simulated final_tick 2332810264000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1464492 # Simulator instruction rate (inst/s) -host_op_rate 1883246 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56554479678 # Simulator tick rate (ticks/s) -host_mem_usage 398712 # Number of bytes of host memory used -host_seconds 41.25 # Real time elapsed on the host +host_inst_rate 840369 # Simulator instruction rate (inst/s) +host_op_rate 1080663 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 32452660609 # Simulator tick rate (ticks/s) +host_mem_usage 444352 # Number of bytes of host memory used +host_seconds 71.88 # Real time elapsed on the host sim_insts 60408639 # Number of instructions simulated sim_ops 77681819 # Number of ops (including micro ops) simulated +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 9 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 9 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 9 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory @@ -62,18 +74,6 @@ system.physmem.bw_total::cpu0.data 3386724 # To system.physmem.bw_total::cpu1.inst 91056 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.data 1794913 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 54942145 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 9 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 9 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 9 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s) system.membus.throughput 55969561 # Throughput (bytes/s) system.membus.data_through_bus 130566366 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) @@ -286,7 +286,7 @@ system.cpu0.itb.inst_accesses 32546956 # IT system.cpu0.itb.hits 32543253 # DTB hits system.cpu0.itb.misses 3703 # DTB misses system.cpu0.itb.accesses 32546956 # DTB accesses -system.cpu0.numCycles 4633589665 # number of cpu cycles simulated +system.cpu0.numCycles 4633633401 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.committedInsts 31998091 # Number of instructions committed @@ -304,8 +304,8 @@ system.cpu0.num_fp_register_writes 1428 # nu system.cpu0.num_mem_refs 15013057 # number of memory refs system.cpu0.num_load_insts 8304661 # Number of load instructions system.cpu0.num_store_insts 6708396 # Number of store instructions -system.cpu0.num_idle_cycles 4555625120.147407 # Number of idle cycles -system.cpu0.num_busy_cycles 77964544.852593 # Number of busy cycles +system.cpu0.num_idle_cycles 4555668120.247687 # Number of idle cycles +system.cpu0.num_busy_cycles 77965280.752313 # Number of busy cycles system.cpu0.not_idle_fraction 0.016826 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.983174 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed @@ -496,7 +496,7 @@ system.cpu1.itb.inst_accesses 28889355 # IT system.cpu1.itb.hits 28886892 # DTB hits system.cpu1.itb.misses 2463 # DTB misses system.cpu1.itb.accesses 28889355 # DTB accesses -system.cpu1.numCycles 4279954879 # number of cpu cycles simulated +system.cpu1.numCycles 4279988156 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.committedInsts 28410548 # Number of instructions committed @@ -514,8 +514,8 @@ system.cpu1.num_fp_register_writes 1352 # nu system.cpu1.num_mem_refs 12348580 # number of memory refs system.cpu1.num_load_insts 7334866 # Number of load instructions system.cpu1.num_store_insts 5013714 # Number of store instructions -system.cpu1.num_idle_cycles 4217653381.679553 # Number of idle cycles -system.cpu1.num_busy_cycles 62301497.320448 # Number of busy cycles +system.cpu1.num_idle_cycles 4217686174.280304 # Number of idle cycles +system.cpu1.num_busy_cycles 62301981.719696 # Number of busy cycles system.cpu1.not_idle_fraction 0.014557 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.985443 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed |