diff options
| author | Ali Saidi <saidi@eecs.umich.edu> | 2012-07-27 16:08:05 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2012-07-27 16:08:05 -0400 |
| commit | b1a58933e07d7af0eb5f43942f8ad9bc93f28039 (patch) | |
| tree | 21f36b849ba0aed06ec18ed45aef46feeacd7532 /tests/quick/fs/10.linux-boot/ref/arm | |
| parent | 630068be6f7b6dc5c612867c764c37e41fd90a4a (diff) | |
| download | gem5-b1a58933e07d7af0eb5f43942f8ad9bc93f28039.tar.xz | |
stats: update stats for icache change not allowing dirty data
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm')
12 files changed, 1971 insertions, 1995 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini index e2b1a3bea..cab94b1b5 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini @@ -20,7 +20,7 @@ kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=atomic -memories=system.realview.nvmem system.physmem +memories=system.physmem system.realview.nvmem midr_regval=890224640 multi_proc=true num_work_ids=16 @@ -306,7 +306,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma @@ -367,9 +367,9 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.realview.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio +master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio slave=system.system_port system.iocache.mem_side system.l2c.mem_side [system.membus.badaddr_responder] @@ -780,7 +780,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.l2c.cpu_side slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout index 50982556e..638b19e04 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:10:14 -gem5 started Jun 29 2012 00:36:18 +gem5 compiled Jul 26 2012 21:40:00 +gem5 started Jul 27 2012 00:55:21 gem5 executing on zizzer -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 911653589000 because m5_exit instruction encountered +Exiting @ tick 912096763500 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index c0313feaf..492e0d099 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -1,16 +1,71 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.911654 # Number of seconds simulated -sim_ticks 911653589000 # Number of ticks simulated -final_tick 911653589000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.912097 # Number of seconds simulated +sim_ticks 912096763500 # Number of ticks simulated +final_tick 912096763500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2171864 # Simulator instruction rate (inst/s) -host_op_rate 2807005 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32664627860 # Simulator tick rate (ticks/s) -host_mem_usage 382740 # Number of bytes of host memory used -host_seconds 27.91 # Real time elapsed on the host -sim_insts 60615585 # Number of instructions simulated -sim_ops 78342060 # Number of ops (including micro ops) simulated +host_inst_rate 1622636 # Simulator instruction rate (inst/s) +host_op_rate 2089140 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 24015838223 # Simulator tick rate (ticks/s) +host_mem_usage 388524 # Number of bytes of host memory used +host_seconds 37.98 # Real time elapsed on the host +sim_insts 61625970 # Number of instructions simulated +sim_ops 79343340 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 502180 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 6234996 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 214556 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 3364528 # Number of bytes read from this memory +system.physmem.bytes_read::total 49638308 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 502180 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 214556 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 716736 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4195776 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 3010088 # Number of bytes written to this memory +system.physmem.bytes_written::total 7222864 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 4915200 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 14065 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 97494 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 3434 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 52597 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5082797 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 65559 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 752522 # Number of write requests responded to by this memory +system.physmem.num_writes::total 822331 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43111215 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 70 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 211 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 550578 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 6835893 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 211 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 235234 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 3688784 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 54422195 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 550578 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 235234 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 785811 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4600144 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 18638 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 3300185 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 7918967 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4600144 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43111215 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 70 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 211 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 550578 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 6854532 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 211 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 235234 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 6988969 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 62341162 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -29,238 +84,171 @@ system.realview.nvmem.bw_inst_read::total 75 # I system.realview.nvmem.bw_total::cpu0.inst 22 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 53 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 75 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 506468 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 6290740 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 210652 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 3309616 # Number of bytes read from this memory -system.physmem.bytes_read::total 49639524 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 506468 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 210652 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 717120 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4196032 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 3010088 # Number of bytes written to this memory -system.physmem.bytes_written::total 7223120 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 4915200 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 14132 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 98365 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 3373 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 51739 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5082816 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 65563 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 752522 # Number of write requests responded to by this memory -system.physmem.num_writes::total 822335 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43132173 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 70 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 140 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 555549 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 6900362 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 211 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 70 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 231066 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 3630344 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 54449985 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 555549 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 231066 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 786615 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4602661 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 18647 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 3301789 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 7923097 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4602661 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43132173 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 70 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 140 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 555549 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 6919010 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 211 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 70 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 231066 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 6932133 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 62373082 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 70681 # number of replacements -system.l2c.tagsinuse 51554.827924 # Cycle average of tags in use -system.l2c.total_refs 1661073 # Total number of references to valid blocks. -system.l2c.sampled_refs 135855 # Sample count of references to valid blocks. -system.l2c.avg_refs 12.226808 # Average number of references to valid blocks. +system.l2c.replacements 70662 # number of replacements +system.l2c.tagsinuse 51560.217790 # Cycle average of tags in use +system.l2c.total_refs 1623342 # Total number of references to valid blocks. +system.l2c.sampled_refs 135814 # Sample count of references to valid blocks. +system.l2c.avg_refs 11.952685 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 39271.893324 # Average occupied blocks per requestor +system.l2c.occ_blocks::writebacks 39276.104351 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.dtb.walker 0.000049 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.000326 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4360.096185 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 2483.383308 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 2.678787 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.itb.walker 0.000776 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 2126.160779 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 3310.614391 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.599242 # Average percentage of cache occupancy +system.l2c.occ_blocks::cpu0.itb.walker 0.001108 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4360.752038 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 2483.307369 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 2.678940 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 2126.451282 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 3310.922653 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.599306 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.066530 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.037893 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.066540 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.037892 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.dtb.walker 0.000041 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.032443 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.050516 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.786664 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 5302 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 2202 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 487741 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 211552 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 4297 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1568 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 361833 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 130247 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1204742 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 613260 # number of Writeback hits -system.l2c.Writeback_hits::total 613260 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 827 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 750 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1577 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 123 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 53 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 176 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 71506 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 36206 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 107712 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 5302 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 2202 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 487741 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 283058 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 4297 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 1568 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 361833 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 166453 # number of demand (read+write) hits -system.l2c.demand_hits::total 1312454 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 5302 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 2202 # number of overall hits -system.l2c.overall_hits::cpu0.inst 487741 # number of overall hits -system.l2c.overall_hits::cpu0.data 283058 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 4297 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 1568 # number of overall hits -system.l2c.overall_hits::cpu1.inst 361833 # number of overall hits -system.l2c.overall_hits::cpu1.data 166453 # number of overall hits -system.l2c.overall_hits::total 1312454 # number of overall hits +system.l2c.occ_percent::cpu1.inst 0.032447 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.050521 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.786746 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 3874 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 1919 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 421038 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 175188 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 5331 # 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miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -269,8 +257,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 65563 # number of writebacks -system.l2c.writebacks::total 65563 # number of writebacks +system.l2c.writebacks::writebacks 65559 # number of writebacks +system.l2c.writebacks::total 65559 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -280,27 +268,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 9312139 # DTB read hits -system.cpu0.dtb.read_misses 5476 # DTB read misses -system.cpu0.dtb.write_hits 6895585 # DTB write hits -system.cpu0.dtb.write_misses 1137 # DTB write misses +system.cpu0.dtb.read_hits 7975768 # DTB read hits +system.cpu0.dtb.read_misses 3611 # DTB read misses +system.cpu0.dtb.write_hits 5966574 # DTB write hits +system.cpu0.dtb.write_misses 672 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2449 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 2004 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 187 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 135 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 267 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 9317615 # DTB read accesses -system.cpu0.dtb.write_accesses 6896722 # DTB write accesses +system.cpu0.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 7979379 # DTB read accesses +system.cpu0.dtb.write_accesses 5967246 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 16207724 # DTB hits -system.cpu0.dtb.misses 6613 # DTB misses -system.cpu0.dtb.accesses 16214337 # DTB accesses -system.cpu0.itb.inst_hits 34683994 # ITB inst hits -system.cpu0.itb.inst_misses 3170 # ITB inst misses +system.cpu0.dtb.hits 13942342 # DTB hits +system.cpu0.dtb.misses 4283 # DTB misses +system.cpu0.dtb.accesses 13946625 # DTB accesses +system.cpu0.itb.inst_hits 30238804 # ITB inst hits +system.cpu0.itb.inst_misses 2175 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -309,74 +297,74 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1558 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1499 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 34687164 # ITB inst accesses -system.cpu0.itb.hits 34683994 # DTB hits -system.cpu0.itb.misses 3170 # DTB misses -system.cpu0.itb.accesses 34687164 # DTB accesses -system.cpu0.numCycles 1823259919 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 30240979 # ITB inst accesses +system.cpu0.itb.hits 30238804 # DTB hits +system.cpu0.itb.misses 2175 # DTB misses +system.cpu0.itb.accesses 30240979 # DTB accesses +system.cpu0.numCycles 1823633059 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 33900598 # Number of instructions committed -system.cpu0.committedOps 44786074 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 39685287 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5074 # Number of float alu accesses -system.cpu0.num_func_calls 1436598 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4494112 # number of instructions that are conditional controls -system.cpu0.num_int_insts 39685287 # number of integer instructions -system.cpu0.num_fp_insts 5074 # number of float instructions -system.cpu0.num_int_register_reads 201262894 # number of times the integer registers were read -system.cpu0.num_int_register_writes 42034263 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3706 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1372 # number of times the floating registers were written -system.cpu0.num_mem_refs 16978573 # number of memory refs -system.cpu0.num_load_insts 9760184 # Number of load instructions -system.cpu0.num_store_insts 7218389 # Number of store instructions -system.cpu0.num_idle_cycles 1777623684.411826 # Number of idle cycles -system.cpu0.num_busy_cycles 45636234.588174 # Number of busy cycles -system.cpu0.not_idle_fraction 0.025030 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.974970 # Percentage of idle cycles +system.cpu0.committedInsts 29750005 # Number of instructions committed +system.cpu0.committedOps 39129633 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 34471201 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5449 # Number of float alu accesses +system.cpu0.num_func_calls 1241903 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4025450 # number of instructions that are conditional controls +system.cpu0.num_int_insts 34471201 # number of integer instructions +system.cpu0.num_fp_insts 5449 # number of float instructions +system.cpu0.num_int_register_reads 175121947 # number of times the integer registers were read +system.cpu0.num_int_register_writes 36551788 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 4535 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 916 # number of times the floating registers were written +system.cpu0.num_mem_refs 14626951 # number of memory refs +system.cpu0.num_load_insts 8357226 # Number of load instructions +system.cpu0.num_store_insts 6269725 # Number of store instructions +system.cpu0.num_idle_cycles 1783968822.941743 # Number of idle cycles +system.cpu0.num_busy_cycles 39664236.058257 # Number of busy cycles +system.cpu0.not_idle_fraction 0.021750 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.978250 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 58955 # number of quiesce instructions executed -system.cpu0.icache.replacements 497178 # number of replacements -system.cpu0.icache.tagsinuse 511.019581 # Cycle average of tags in use -system.cpu0.icache.total_refs 34187980 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 497690 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 68.693323 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 64536851000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.019581 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.998085 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.998085 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 34187980 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 34187980 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 34187980 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 34187980 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 34187980 # number of overall hits -system.cpu0.icache.overall_hits::total 34187980 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 497690 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 497690 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 497690 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 497690 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 497690 # number of overall misses -system.cpu0.icache.overall_misses::total 497690 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 34685670 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 34685670 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 34685670 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 34685670 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 34685670 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 34685670 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014349 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014349 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014349 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014349 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014349 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014349 # miss rate for overall accesses +system.cpu0.kern.inst.quiesce 49966 # number of quiesce instructions executed +system.cpu0.icache.replacements 428547 # number of replacements +system.cpu0.icache.tagsinuse 511.020000 # Cycle average of tags in use +system.cpu0.icache.total_refs 29811115 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 429059 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 69.480223 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 64537139000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 511.020000 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.998086 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.998086 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 29811115 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 29811115 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 29811115 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 29811115 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 29811115 # number of overall hits +system.cpu0.icache.overall_hits::total 29811115 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 429059 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 429059 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 429059 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 429059 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 429059 # number of overall misses +system.cpu0.icache.overall_misses::total 429059 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 30240174 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 30240174 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 30240174 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 30240174 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 30240174 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 30240174 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014188 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014188 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014188 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014188 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014188 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014188 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -385,66 +373,64 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 31457 # number of writebacks -system.cpu0.icache.writebacks::total 31457 # number of writebacks system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 380425 # number of replacements -system.cpu0.dcache.tagsinuse 495.308430 # Cycle average of tags in use -system.cpu0.dcache.total_refs 14671885 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 380937 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 38.515253 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 323609 # number of replacements +system.cpu0.dcache.tagsinuse 494.763091 # Cycle average of tags in use +system.cpu0.dcache.total_refs 12467604 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 323981 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 38.482516 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 22115000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 495.308430 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.967399 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.967399 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 7779192 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7779192 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 6519856 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 6519856 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 173153 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 173153 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 175464 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 175464 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 14299048 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 14299048 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 14299048 # number of overall hits -system.cpu0.dcache.overall_hits::total 14299048 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 237170 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 237170 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 185374 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 185374 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9761 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 9761 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7396 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7396 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 422544 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 422544 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 422544 # number of overall misses -system.cpu0.dcache.overall_misses::total 422544 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8016362 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8016362 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 6705230 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 6705230 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 182914 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 182914 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 182860 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 182860 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 14721592 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 14721592 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 14721592 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 14721592 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029586 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.029586 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027646 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.027646 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.053364 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.053364 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.040446 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.040446 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.028702 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.028702 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.028702 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.028702 # miss rate for overall accesses +system.cpu0.dcache.occ_blocks::cpu0.data 494.763091 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.966334 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.966334 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6512305 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6512305 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5630881 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5630881 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 151619 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 151619 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 153180 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 153180 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 12143186 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12143186 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 12143186 # number of overall hits +system.cpu0.dcache.overall_hits::total 12143186 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 197167 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 197167 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 167342 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 167342 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9062 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 9062 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7469 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7469 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 364509 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 364509 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 364509 # number of overall misses +system.cpu0.dcache.overall_misses::total 364509 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6709472 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6709472 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5798223 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5798223 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 160681 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 160681 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 160649 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 160649 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12507695 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12507695 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12507695 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12507695 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029386 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.029386 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.028861 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.028861 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056397 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056397 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.046493 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.046493 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029143 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.029143 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029143 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.029143 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -453,32 +439,32 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 353901 # number of writebacks -system.cpu0.dcache.writebacks::total 353901 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 300958 # number of writebacks +system.cpu0.dcache.writebacks::total 300958 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 6036043 # DTB read hits -system.cpu1.dtb.read_misses 1895 # DTB read misses -system.cpu1.dtb.write_hits 4565126 # DTB write hits -system.cpu1.dtb.write_misses 1147 # DTB write misses +system.cpu1.dtb.read_hits 7364781 # DTB read hits +system.cpu1.dtb.read_misses 3705 # DTB read misses +system.cpu1.dtb.write_hits 5489656 # DTB write hits +system.cpu1.dtb.write_misses 1595 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1364 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1788 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 95 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 145 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 185 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 6037938 # DTB read accesses -system.cpu1.dtb.write_accesses 4566273 # DTB write accesses +system.cpu1.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 7368486 # DTB read accesses +system.cpu1.dtb.write_accesses 5491251 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 10601169 # DTB hits -system.cpu1.dtb.misses 3042 # DTB misses -system.cpu1.dtb.accesses 10604211 # DTB accesses -system.cpu1.itb.inst_hits 26944447 # ITB inst hits -system.cpu1.itb.inst_misses 1203 # ITB inst misses +system.cpu1.dtb.hits 12854437 # DTB hits +system.cpu1.dtb.misses 5300 # DTB misses +system.cpu1.dtb.accesses 12859737 # DTB accesses +system.cpu1.itb.inst_hits 32412306 # ITB inst hits +system.cpu1.itb.inst_misses 2200 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -487,74 +473,74 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1228 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1327 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 26945650 # ITB inst accesses -system.cpu1.itb.hits 26944447 # DTB hits -system.cpu1.itb.misses 1203 # DTB misses -system.cpu1.itb.accesses 26945650 # DTB accesses -system.cpu1.numCycles 1822760078 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 32414506 # ITB inst accesses +system.cpu1.itb.hits 32412306 # DTB hits +system.cpu1.itb.misses 2200 # DTB misses +system.cpu1.itb.accesses 32414506 # DTB accesses +system.cpu1.numCycles 1824154149 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 26714987 # Number of instructions committed -system.cpu1.committedOps 33555986 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 30087808 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 5643 # Number of float alu accesses -system.cpu1.num_func_calls 761024 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3301562 # number of instructions that are conditional controls -system.cpu1.num_int_insts 30087808 # number of integer instructions -system.cpu1.num_fp_insts 5643 # number of float instructions -system.cpu1.num_int_register_reads 152234781 # number of times the integer registers were read -system.cpu1.num_int_register_writes 32495677 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 3915 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1728 # number of times the floating registers were written -system.cpu1.num_mem_refs 11031013 # number of memory refs -system.cpu1.num_load_insts 6247466 # Number of load instructions -system.cpu1.num_store_insts 4783547 # Number of store instructions -system.cpu1.num_idle_cycles 1788952556.347001 # Number of idle cycles -system.cpu1.num_busy_cycles 33807521.652999 # Number of busy cycles -system.cpu1.not_idle_fraction 0.018547 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.981453 # Percentage of idle cycles +system.cpu1.committedInsts 31875965 # Number of instructions committed +system.cpu1.committedOps 40213707 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 35797832 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 4436 # Number of float alu accesses +system.cpu1.num_func_calls 955227 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 4028429 # number of instructions that are conditional controls +system.cpu1.num_int_insts 35797832 # number of integer instructions +system.cpu1.num_fp_insts 4436 # number of float instructions +system.cpu1.num_int_register_reads 181634271 # number of times the integer registers were read +system.cpu1.num_int_register_writes 39007898 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 3022 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1416 # number of times the floating registers were written +system.cpu1.num_mem_refs 13370713 # number of memory refs +system.cpu1.num_load_insts 7642673 # Number of load instructions +system.cpu1.num_store_insts 5728040 # Number of store instructions +system.cpu1.num_idle_cycles 1783362859.317266 # Number of idle cycles +system.cpu1.num_busy_cycles 40791289.682734 # Number of busy cycles +system.cpu1.not_idle_fraction 0.022362 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.977638 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 31471 # number of quiesce instructions executed -system.cpu1.icache.replacements 365832 # number of replacements -system.cpu1.icache.tagsinuse 475.430525 # Cycle average of tags in use -system.cpu1.icache.total_refs 26579068 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 366344 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 72.552213 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 69967043000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 475.430525 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.928575 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.928575 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 26579068 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 26579068 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 26579068 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 26579068 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 26579068 # number of overall hits -system.cpu1.icache.overall_hits::total 26579068 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 366344 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 366344 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 366344 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 366344 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 366344 # number of overall misses -system.cpu1.icache.overall_misses::total 366344 # number of overall misses -system.cpu1.icache.ReadReq_accesses::cpu1.inst 26945412 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 26945412 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 26945412 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 26945412 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 26945412 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 26945412 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013596 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.013596 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013596 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.013596 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013596 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.013596 # miss rate for overall accesses +system.cpu1.kern.inst.quiesce 40379 # number of quiesce instructions executed +system.cpu1.icache.replacements 433942 # number of replacements +system.cpu1.icache.tagsinuse 475.447912 # Cycle average of tags in use +system.cpu1.icache.total_refs 31979125 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 434454 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 73.607620 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 69967763000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 475.447912 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.928609 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.928609 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 31979125 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 31979125 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 31979125 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 31979125 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 31979125 # number of overall hits +system.cpu1.icache.overall_hits::total 31979125 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 434454 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 434454 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 434454 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 434454 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 434454 # number of overall misses +system.cpu1.icache.overall_misses::total 434454 # number of overall misses +system.cpu1.icache.ReadReq_accesses::cpu1.inst 32413579 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 32413579 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 32413579 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 32413579 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 32413579 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 32413579 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013403 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.013403 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013403 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.013403 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013403 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.013403 # miss rate for overall accesses system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -563,66 +549,64 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 15197 # number of writebacks -system.cpu1.icache.writebacks::total 15197 # number of writebacks system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 236700 # number of replacements -system.cpu1.dcache.tagsinuse 447.071707 # Cycle average of tags in use -system.cpu1.dcache.total_refs 9515102 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 237061 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 40.137779 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 67292773000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 447.071707 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.873187 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.873187 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 5742078 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 5742078 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 3635346 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 3635346 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 56591 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 56591 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 56639 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 56639 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 9377424 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 9377424 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 9377424 # number of overall hits -system.cpu1.dcache.overall_hits::total 9377424 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 159026 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 159026 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 108254 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 108254 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 10539 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 10539 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10435 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10435 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 267280 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 267280 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 267280 # number of overall misses -system.cpu1.dcache.overall_misses::total 267280 # number of overall misses -system.cpu1.dcache.ReadReq_accesses::cpu1.data 5901104 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 5901104 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 3743600 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 3743600 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 67130 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 67130 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 67074 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 67074 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 9644704 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 9644704 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 9644704 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 9644704 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.026949 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.026949 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.028917 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.028917 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.156994 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.156994 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.155574 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.155574 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027713 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.027713 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.027713 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.027713 # miss rate for overall accesses +system.cpu1.dcache.replacements 294289 # number of replacements +system.cpu1.dcache.tagsinuse 447.573682 # Cycle average of tags in use +system.cpu1.dcache.total_refs 11707745 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 294801 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 39.714061 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 67293493000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 447.573682 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.874167 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.874167 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 7002209 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 7002209 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4520313 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4520313 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 77954 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 77954 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 79030 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 79030 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 11522522 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 11522522 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 11522522 # number of overall hits +system.cpu1.dcache.overall_hits::total 11522522 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 198275 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 198275 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 125920 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 125920 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11251 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 11251 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10139 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10139 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 324195 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 324195 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 324195 # number of overall misses +system.cpu1.dcache.overall_misses::total 324195 # number of overall misses +system.cpu1.dcache.ReadReq_accesses::cpu1.data 7200484 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 7200484 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 4646233 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 4646233 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 89205 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 89205 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 89169 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 89169 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 11846717 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 11846717 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 11846717 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 11846717 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.027536 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.027536 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027102 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.027102 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.126125 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.126125 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.113705 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.113705 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027366 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.027366 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.027366 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.027366 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -631,8 +615,8 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 212705 # number of writebacks -system.cpu1.dcache.writebacks::total 212705 # number of writebacks +system.cpu1.dcache.writebacks::writebacks 266849 # number of writebacks +system.cpu1.dcache.writebacks::total 266849 # number of writebacks system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini index f14835c6b..59476048e 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini @@ -191,7 +191,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma @@ -252,9 +252,9 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.realview.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio +master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio slave=system.system_port system.iocache.mem_side system.l2c.mem_side [system.membus.badaddr_responder] @@ -665,7 +665,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.l2c.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout index 4dbfc774f..5f92f06af 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:10:14 -gem5 started Jun 29 2012 00:35:36 +gem5 compiled Jul 26 2012 21:40:00 +gem5 started Jul 27 2012 00:54:29 gem5 executing on zizzer -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2332330037000 because m5_exit instruction encountered +Exiting @ tick 2332810264000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index 176436ee7..e8bc29aac 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -1,54 +1,54 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.332330 # Number of seconds simulated -sim_ticks 2332330037000 # Number of ticks simulated -final_tick 2332330037000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.332810 # Number of seconds simulated +sim_ticks 2332810264000 # Number of ticks simulated +final_tick 2332810264000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1988795 # Simulator instruction rate (inst/s) -host_op_rate 2567201 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 78099767101 # Simulator tick rate (ticks/s) -host_mem_usage 382744 # Number of bytes of host memory used -host_seconds 29.86 # Real time elapsed on the host -sim_insts 59392246 # Number of instructions simulated -sim_ops 76665494 # Number of ops (including micro ops) simulated +host_inst_rate 1498673 # Simulator instruction rate (inst/s) +host_op_rate 1927201 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 57874436068 # Simulator tick rate (ticks/s) +host_mem_usage 388524 # Number of bytes of host memory used +host_seconds 40.31 # Real time elapsed on the host +sim_insts 60408639 # Number of instructions simulated +sim_ops 77681819 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 704992 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9071568 # Number of bytes read from this memory -system.physmem.bytes_read::total 121450416 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 704992 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 704992 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3703040 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 705120 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9071632 # Number of bytes read from this memory +system.physmem.bytes_read::total 121450608 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 705120 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 705120 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3703232 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3015816 # Number of bytes written to this memory -system.physmem.bytes_written::total 6718856 # Number of bytes written to this memory +system.physmem.bytes_written::total 6719048 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 13959168 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 17218 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141777 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14118171 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57860 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 17220 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141778 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14118174 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57863 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 753954 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811814 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47880592 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 811817 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47870736 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 137 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 82 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 302269 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3889487 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52072569 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 302269 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 302269 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1587700 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1293049 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2880748 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1587700 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47880592 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 302262 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3888714 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52061931 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 302262 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 302262 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1587455 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1292782 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2880238 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1587455 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47870736 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 137 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 82 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 302269 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5182536 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54953317 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 302262 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5181496 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54942169 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -61,103 +61,103 @@ system.realview.nvmem.bw_inst_read::cpu.inst 9 system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 9 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 62240 # number of replacements -system.l2c.tagsinuse 50004.786190 # Cycle average of tags in use -system.l2c.total_refs 1717775 # Total number of references to valid blocks. -system.l2c.sampled_refs 127625 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.459549 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2316513323500 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 36897.037256 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 2.960071 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.itb.walker 0.993930 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 7014.608709 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 6089.186223 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.563004 # Average percentage of cache occupancy +system.l2c.replacements 62243 # number of replacements +system.l2c.tagsinuse 50007.272909 # Cycle average of tags in use +system.l2c.total_refs 1669922 # Total number of references to valid blocks. +system.l2c.sampled_refs 127628 # Sample count of references to valid blocks. +system.l2c.avg_refs 13.084292 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2316901489000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 36899.582990 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 2.960148 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.itb.walker 0.993931 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 7014.720482 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 6089.015357 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.563043 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.107034 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.092914 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.763012 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 7534 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 3151 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 838895 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 364444 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1214024 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 642748 # number of Writeback hits -system.l2c.Writeback_hits::total 642748 # number of Writeback hits +system.l2c.occ_percent::cpu.inst 0.107036 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.092911 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.763050 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 7507 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.itb.walker 3129 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.inst 838871 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 366771 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1216278 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 592643 # number of Writeback hits +system.l2c.Writeback_hits::total 592643 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 113737 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 113737 # number of ReadExReq hits -system.l2c.demand_hits::cpu.dtb.walker 7534 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.itb.walker 3151 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.inst 838895 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 478181 # 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number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000663 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000951 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.012480 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.026368 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.016590 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu.data 0.991168 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.991168 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.539910 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.539910 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.dtb.walker 0.000663 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.itb.walker 0.000951 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.inst 0.012480 # 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number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.itb.walker 3132 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.inst 849475 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.data 623849 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1483968 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000666 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000958 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.inst 0.012483 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.026208 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.016562 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu.data 0.991171 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.991171 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu.data 0.539904 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.539904 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu.dtb.walker 0.000666 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.itb.walker 0.000958 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.inst 0.012483 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.229766 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.103743 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.dtb.walker 0.000666 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.itb.walker 0.000958 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.inst 0.012483 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.229766 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.103743 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -166,8 +166,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 57860 # number of writebacks -system.l2c.writebacks::total 57860 # number of writebacks +system.l2c.writebacks::writebacks 57863 # number of writebacks +system.l2c.writebacks::total 57863 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -177,26 +177,26 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 14971229 # DTB read hits -system.cpu.dtb.read_misses 7293 # DTB read misses -system.cpu.dtb.write_hits 11217018 # DTB write hits +system.cpu.dtb.read_hits 14971214 # DTB read hits +system.cpu.dtb.read_misses 7294 # DTB read misses +system.cpu.dtb.write_hits 11217004 # DTB write hits system.cpu.dtb.write_misses 2181 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3492 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 3496 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.prefetch_faults 174 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 14978522 # DTB read accesses -system.cpu.dtb.write_accesses 11219199 # DTB write accesses +system.cpu.dtb.read_accesses 14978508 # DTB read accesses +system.cpu.dtb.write_accesses 11219185 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 26188247 # DTB hits -system.cpu.dtb.misses 9474 # DTB misses -system.cpu.dtb.accesses 26197721 # DTB accesses -system.cpu.itb.inst_hits 60403303 # ITB inst hits +system.cpu.dtb.hits 26188218 # DTB hits +system.cpu.dtb.misses 9475 # DTB misses +system.cpu.dtb.accesses 26197693 # DTB accesses +system.cpu.itb.inst_hits 61431840 # ITB inst hits system.cpu.itb.inst_misses 4471 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -213,67 +213,67 @@ system.cpu.itb.domain_faults 0 # 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Number of integer alu accesses +system.cpu.committedInsts 60408639 # Number of instructions committed +system.cpu.committedOps 77681819 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 68795605 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses -system.cpu.num_func_calls 2136013 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7647793 # number of instructions that are conditional controls -system.cpu.num_int_insts 68281415 # number of integer instructions +system.cpu.num_func_calls 2136008 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7904929 # number of instructions that are conditional controls +system.cpu.num_int_insts 68795605 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions -system.cpu.num_int_register_reads 345981857 # number of times the integer registers were read -system.cpu.num_int_register_writes 73062916 # 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number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 60406063 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014090 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.014090 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.014090 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.014090 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.014090 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.014090 # miss rate for overall accesses +system.cpu.icache.ReadReq_hits::cpu.inst 60583498 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 60583498 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 60583498 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 60583498 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 60583498 # number of overall hits +system.cpu.icache.overall_hits::total 60583498 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 851102 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 851102 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 851102 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 851102 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 851102 # number of overall misses +system.cpu.icache.overall_misses::total 851102 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 61434600 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 61434600 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 61434600 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 61434600 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 61434600 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 61434600 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013854 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.013854 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.013854 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.013854 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.013854 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.013854 # miss rate for overall accesses system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -282,58 +282,56 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 50093 # number of writebacks -system.cpu.icache.writebacks::total 50093 # number of writebacks system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 623347 # number of replacements -system.cpu.dcache.tagsinuse 511.997030 # Cycle average of tags in use -system.cpu.dcache.total_refs 23628362 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 623859 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 37.874523 # Average number of references to valid blocks. +system.cpu.dcache.replacements 623337 # number of replacements +system.cpu.dcache.tagsinuse 511.997031 # Cycle average of tags in use +system.cpu.dcache.total_refs 23628343 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 623849 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 37.875100 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 21763000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.997030 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 511.997031 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13180074 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13180074 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 9962087 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 9962087 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 236035 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 236035 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247222 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247222 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 23142161 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 23142161 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 23142161 # number of overall hits -system.cpu.dcache.overall_hits::total 23142161 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 365465 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 365465 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 250150 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 250150 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 11188 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 11188 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 615615 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 615615 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 615615 # number of overall misses -system.cpu.dcache.overall_misses::total 615615 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 13545539 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13545539 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10212237 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10212237 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247223 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 247223 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 247222 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 247222 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 23757776 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 23757776 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 23757776 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 23757776 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_hits::cpu.data 13180066 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13180066 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 9962072 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 9962072 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 236039 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 236039 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247221 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247221 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 23142138 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 23142138 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 23142138 # number of overall hits +system.cpu.dcache.overall_hits::total 23142138 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 365459 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 365459 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 250152 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 250152 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 11183 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 11183 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 615611 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 615611 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 615611 # number of overall misses +system.cpu.dcache.overall_misses::total 615611 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 13545525 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13545525 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10212224 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10212224 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247222 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 247222 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247221 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247221 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 23757749 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 23757749 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 23757749 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 23757749 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026980 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.026980 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024495 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.024495 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045255 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045255 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045235 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045235 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.025912 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.025912 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.025912 # miss rate for overall accesses @@ -346,8 +344,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 592655 # number of writebacks -system.cpu.dcache.writebacks::total 592655 # number of writebacks +system.cpu.dcache.writebacks::writebacks 592643 # number of writebacks +system.cpu.dcache.writebacks::total 592643 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini index 363bd4c66..f88222537 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini @@ -361,7 +361,7 @@ header_cycles=1 use_default_range=false width=8 default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.realview.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio +master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio slave=system.system_port system.iocache.mem_side system.l2c.mem_side [system.membus.badaddr_responder] diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout index 70032b595..3225b7372 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 09:08:16 -gem5 started Jul 2 2012 15:21:03 +gem5 compiled Jul 26 2012 21:40:00 +gem5 started Jul 27 2012 00:58:01 gem5 executing on zizzer -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1171612619000 because m5_exit instruction encountered +Exiting @ tick 1172544977000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index bf3a52c45..2693ffabe 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,71 +1,71 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.171613 # Number of seconds simulated -sim_ticks 1171612619000 # Number of ticks simulated -final_tick 1171612619000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.172545 # Number of seconds simulated +sim_ticks 1172544977000 # Number of ticks simulated +final_tick 1172544977000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 639669 # Simulator instruction rate (inst/s) -host_op_rate 818158 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 12399663305 # Simulator tick rate (ticks/s) -host_mem_usage 384708 # Number of bytes of host memory used -host_seconds 94.49 # Real time elapsed on the host -sim_insts 60440687 # Number of instructions simulated -sim_ops 77305655 # Number of ops (including micro ops) simulated +host_inst_rate 706392 # Simulator instruction rate (inst/s) +host_op_rate 900233 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 13469238975 # Simulator tick rate (ticks/s) +host_mem_usage 389548 # Number of bytes of host memory used +host_seconds 87.05 # Real time elapsed on the host +sim_insts 61493926 # Number of instructions simulated +sim_ops 78368454 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 50331648 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 395940 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4717108 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 394788 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4717236 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 321948 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4794672 # Number of bytes read from this memory -system.physmem.bytes_read::total 60561764 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 395940 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 321948 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 717888 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4107520 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 322588 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4794736 # Number of bytes read from this memory +system.physmem.bytes_read::total 60561444 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 394788 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 322588 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 717376 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4107264 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7134864 # Number of bytes written to this memory +system.physmem.bytes_written::total 7134608 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6291456 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 12405 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 73777 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 12387 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 73779 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 5112 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 74943 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6457700 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 64180 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.inst 5122 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 74944 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6457695 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 64176 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 821016 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 42959291 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 821012 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 42925132 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 55 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 109 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 337944 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 4026167 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 219 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 274790 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4092370 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51690945 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 337944 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 274790 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 612735 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3505869 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 14510 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2569402 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6089781 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3505869 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 42959291 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 336693 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 4023075 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 218 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 275118 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4089170 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51649570 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 336693 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 275118 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 611811 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3502863 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 14498 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2567359 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6084720 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3502863 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 42925132 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 55 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 109 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 337944 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 4040677 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 219 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 274790 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 6661772 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 57780726 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 336693 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 4037573 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 218 # 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average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40048.904347 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -498,9 +498,9 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7077919 # DTB read hits -system.cpu0.dtb.read_misses 3740 # DTB read misses -system.cpu0.dtb.write_hits 5661726 # DTB write hits +system.cpu0.dtb.read_hits 7082876 # DTB read hits +system.cpu0.dtb.read_misses 3736 # DTB read misses +system.cpu0.dtb.write_hits 5665319 # DTB write hits system.cpu0.dtb.write_misses 804 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -511,13 +511,13 @@ system.cpu0.dtb.align_faults 0 # Nu system.cpu0.dtb.prefetch_faults 141 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7081659 # DTB read accesses -system.cpu0.dtb.write_accesses 5662530 # DTB write accesses +system.cpu0.dtb.read_accesses 7086612 # DTB read accesses +system.cpu0.dtb.write_accesses 5666123 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12739645 # DTB hits -system.cpu0.dtb.misses 4544 # DTB misses -system.cpu0.dtb.accesses 12744189 # DTB accesses -system.cpu0.itb.inst_hits 29451654 # ITB inst hits +system.cpu0.dtb.hits 12748195 # DTB hits +system.cpu0.dtb.misses 4540 # DTB misses +system.cpu0.dtb.accesses 12752735 # DTB accesses +system.cpu0.itb.inst_hits 29606138 # ITB inst hits system.cpu0.itb.inst_misses 2205 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -534,79 +534,79 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 29453859 # ITB inst accesses -system.cpu0.itb.hits 29451654 # DTB hits +system.cpu0.itb.inst_accesses 29608343 # ITB inst accesses +system.cpu0.itb.hits 29606138 # DTB hits system.cpu0.itb.misses 2205 # DTB misses -system.cpu0.itb.accesses 29453859 # DTB accesses -system.cpu0.numCycles 2343225238 # number of cpu cycles simulated +system.cpu0.itb.accesses 29608343 # DTB accesses +system.cpu0.numCycles 2345089954 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 28759206 # Number of instructions committed -system.cpu0.committedOps 37112849 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 33058293 # Number of integer alu accesses +system.cpu0.committedInsts 28907917 # Number of instructions committed +system.cpu0.committedOps 37265600 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 33149705 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses -system.cpu0.num_func_calls 1242118 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4322812 # number of instructions that are conditional controls -system.cpu0.num_int_insts 33058293 # number of integer instructions +system.cpu0.num_func_calls 1243107 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4358822 # number of instructions that are conditional controls +system.cpu0.num_int_insts 33149705 # number of integer instructions system.cpu0.num_fp_insts 3860 # number of float instructions -system.cpu0.num_int_register_reads 189772382 # number of times the integer registers were read -system.cpu0.num_int_register_writes 36110779 # number of times the integer registers were written +system.cpu0.num_int_register_reads 190344582 # number of times the integer registers were read +system.cpu0.num_int_register_writes 36275228 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written -system.cpu0.num_mem_refs 13408219 # number of memory refs -system.cpu0.num_load_insts 7415624 # Number of load instructions -system.cpu0.num_store_insts 5992595 # Number of store instructions -system.cpu0.num_idle_cycles 2203054927.350120 # Number of idle cycles -system.cpu0.num_busy_cycles 140170310.649880 # Number of busy cycles -system.cpu0.not_idle_fraction 0.059819 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.940181 # Percentage of idle cycles +system.cpu0.num_mem_refs 13418689 # number of memory refs +system.cpu0.num_load_insts 7420825 # Number of load instructions +system.cpu0.num_store_insts 5997864 # Number of store instructions +system.cpu0.num_idle_cycles 2204555139.350120 # Number of idle cycles +system.cpu0.num_busy_cycles 140534814.649880 # Number of busy cycles +system.cpu0.not_idle_fraction 0.059927 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.940073 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 46686 # number of quiesce instructions executed -system.cpu0.icache.replacements 408292 # number of replacements -system.cpu0.icache.tagsinuse 509.494086 # Cycle average of tags in use -system.cpu0.icache.total_refs 29042833 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 408804 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 71.043417 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 75128321000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 509.494086 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.995106 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.995106 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 29042833 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 29042833 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 29042833 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 29042833 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 29042833 # number of overall hits -system.cpu0.icache.overall_hits::total 29042833 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 408804 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 408804 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 408804 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 408804 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 408804 # number of overall misses -system.cpu0.icache.overall_misses::total 408804 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6099412500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6099412500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 6099412500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6099412500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 6099412500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6099412500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 29451637 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 29451637 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 29451637 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 29451637 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 29451637 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 29451637 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013881 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.013881 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013881 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.013881 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013881 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.013881 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14920.138991 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14920.138991 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14920.138991 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14920.138991 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14920.138991 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14920.138991 # average overall miss latency +system.cpu0.kern.inst.quiesce 46687 # number of quiesce instructions executed +system.cpu0.icache.replacements 408797 # number of replacements +system.cpu0.icache.tagsinuse 509.495989 # Cycle average of tags in use +system.cpu0.icache.total_refs 29196812 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 409309 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 71.331957 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 75128897000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 509.495989 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.995109 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.995109 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 29196812 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 29196812 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 29196812 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 29196812 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 29196812 # number of overall hits +system.cpu0.icache.overall_hits::total 29196812 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 409309 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 409309 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 409309 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 409309 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 409309 # number of overall misses +system.cpu0.icache.overall_misses::total 409309 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6108172000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 6108172000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 6108172000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 6108172000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 6108172000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 6108172000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 29606121 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 29606121 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 29606121 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 29606121 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 29606121 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 29606121 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013825 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.013825 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013825 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.013825 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013825 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.013825 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14923.131424 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14923.131424 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14923.131424 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14923.131424 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14923.131424 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14923.131424 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -615,122 +615,120 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 20827 # number of writebacks -system.cpu0.icache.writebacks::total 20827 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 408804 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 408804 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 408804 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 408804 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 408804 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 408804 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4872150503 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4872150503 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4872150503 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4872150503 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4872150503 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4872150503 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 409309 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 409309 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 409309 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 409309 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 409309 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 409309 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4879387500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4879387500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4879387500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4879387500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4879387500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4879387500 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 351814000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 351814000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 351814000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 351814000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013881 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013881 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013881 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.013881 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013881 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.013881 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11918.059762 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11918.059762 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11918.059762 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11918.059762 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11918.059762 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11918.059762 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013825 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013825 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013825 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.013825 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013825 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.013825 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11921.036430 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11921.036430 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11921.036430 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11921.036430 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11921.036430 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11921.036430 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 330880 # number of replacements -system.cpu0.dcache.tagsinuse 457.764906 # Cycle average of tags in use -system.cpu0.dcache.total_refs 12284019 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 331392 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 37.067941 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 330813 # number of replacements +system.cpu0.dcache.tagsinuse 457.939353 # Cycle average of tags in use +system.cpu0.dcache.total_refs 12292528 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 331325 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 37.101118 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 664264000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 457.764906 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.894072 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.894072 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6607497 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6607497 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5356507 # 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number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5498234 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157283 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 157283 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157230 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 157230 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12333800 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12333800 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12333800 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12333800 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033365 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.033365 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025777 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.025777 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059059 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059059 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047688 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047688 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029982 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.029982 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029982 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.029982 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15067.400655 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15067.400655 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34695.548484 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 34695.548484 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10826.838196 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10826.838196 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9933.315551 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9933.315551 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 22590.030720 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 22590.030720 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 22590.030720 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 22590.030720 # average overall miss latency +system.cpu0.dcache.occ_blocks::cpu0.data 457.939353 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.894413 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.894413 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6612408 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6612408 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5360091 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5360091 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147992 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 147992 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149726 # 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miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059000 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047654 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047654 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029968 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.029968 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029968 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.029968 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15092.960000 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15092.960000 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34694.216538 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 34694.216538 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10813.611381 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10813.611381 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9961.025093 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9961.025093 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 22604.865441 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 22604.865441 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 22604.865441 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 22604.865441 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -739,62 +737,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 306522 # number of writebacks -system.cpu0.dcache.writebacks::total 306522 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 228069 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 228069 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141727 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 141727 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9289 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9289 # 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number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 819778500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 819778500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11243369000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11243369000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033365 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033365 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025777 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025777 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059059 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059059 # 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number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 228125 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 228125 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141749 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 141749 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9279 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9279 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7485 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7485 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 369874 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 369874 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 369874 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 369874 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2758091164 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2758091164 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4492431566 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4492431566 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 72483506 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 72483506 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 52154019 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 52154019 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7250522730 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 7250522730 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7250522730 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 7250522730 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 10425846000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 10425846000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 819721500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 819721500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11245567500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11245567500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033349 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033349 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025764 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025764 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059000 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059000 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047609 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047609 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029968 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029968 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029968 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.029968 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12090.262637 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12090.262637 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31692.862496 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31692.862496 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7811.564393 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7811.564393 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6967.804810 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6967.804810 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19602.682887 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19602.682887 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19602.682887 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19602.682887 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -804,9 +802,9 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 8311872 # DTB read hits -system.cpu1.dtb.read_misses 3663 # DTB read misses -system.cpu1.dtb.write_hits 5828412 # DTB write hits +system.cpu1.dtb.read_hits 8314117 # DTB read hits +system.cpu1.dtb.read_misses 3669 # DTB read misses +system.cpu1.dtb.write_hits 5830380 # DTB write hits system.cpu1.dtb.write_misses 1436 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -817,13 +815,13 @@ system.cpu1.dtb.align_faults 0 # Nu system.cpu1.dtb.prefetch_faults 140 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 8315535 # DTB read accesses -system.cpu1.dtb.write_accesses 5829848 # DTB write accesses +system.cpu1.dtb.read_accesses 8317786 # DTB read accesses +system.cpu1.dtb.write_accesses 5831816 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 14140284 # DTB hits -system.cpu1.dtb.misses 5099 # DTB misses -system.cpu1.dtb.accesses 14145383 # DTB accesses -system.cpu1.itb.inst_hits 32285286 # ITB inst hits +system.cpu1.dtb.hits 14144497 # DTB hits +system.cpu1.dtb.misses 5105 # DTB misses +system.cpu1.dtb.accesses 14149602 # DTB accesses +system.cpu1.itb.inst_hits 33196626 # ITB inst hits system.cpu1.itb.inst_misses 2171 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -840,79 +838,79 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 32287457 # ITB inst accesses -system.cpu1.itb.hits 32285286 # DTB hits +system.cpu1.itb.inst_accesses 33198797 # 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number of times the floating registers were written -system.cpu1.num_mem_refs 14678127 # number of memory refs -system.cpu1.num_load_insts 8633777 # Number of load instructions -system.cpu1.num_store_insts 6044350 # Number of store instructions -system.cpu1.num_idle_cycles 1858809543.114650 # Number of idle cycles -system.cpu1.num_busy_cycles 482929606.885350 # Number of busy cycles -system.cpu1.not_idle_fraction 0.206227 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.793773 # Percentage of idle cycles +system.cpu1.num_mem_refs 14682267 # number of memory refs +system.cpu1.num_load_insts 8636040 # Number of load instructions +system.cpu1.num_store_insts 6046227 # Number of store instructions +system.cpu1.num_idle_cycles 1858750530.714142 # Number of idle cycles +system.cpu1.num_busy_cycles 484842987.285858 # Number of busy cycles +system.cpu1.not_idle_fraction 0.206880 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.793120 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # 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number of quiesce instructions executed +system.cpu1.icache.replacements 454393 # number of replacements +system.cpu1.icache.tagsinuse 478.384673 # Cycle average of tags in use +system.cpu1.icache.total_refs 32741717 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 454905 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 71.974845 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 92994898000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 478.384673 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.934345 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.934345 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 32741717 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 32741717 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 32741717 # 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number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 6718353500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 6718353500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 6718353500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 33196622 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 33196622 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 33196622 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 33196622 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 33196622 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 33196622 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013703 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.013703 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013703 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.013703 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013703 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.013703 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14768.695662 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 14768.695662 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14768.695662 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 14768.695662 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14768.695662 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 14768.695662 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -921,122 +919,120 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 23436 # number of writebacks -system.cpu1.icache.writebacks::total 23436 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 454941 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 454941 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 454941 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 454941 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 454941 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 454941 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5350372502 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5350372502 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5350372502 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5350372502 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5350372502 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5350372502 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 454905 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 454905 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 454905 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 454905 # 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number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5250000 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 5250000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014091 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014091 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014091 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.014091 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014091 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.014091 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11760.585443 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11760.585443 # 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mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11766.707334 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11766.707334 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11766.707334 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11766.707334 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11766.707334 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11766.707334 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # 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average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23422.060587 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 23422.060587 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23422.060587 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 23422.060587 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1045,62 +1041,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 266082 # 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number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 6546421792 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6546421792 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 6546421792 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 136480079000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 136480079000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 39677118500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 39677118500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 176157197500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 176157197500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023970 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023970 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030151 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030151 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119446 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119446 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108127 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108127 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026513 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026513 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026513 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026513 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10877.453649 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10877.453649 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31251.691774 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31251.691774 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6573.887367 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6573.887367 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5698.148037 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5698.148037 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20412.723897 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20412.723897 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20412.723897 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20412.723897 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 266164 # number of writebacks +system.cpu1.dcache.writebacks::total 266164 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170766 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 170766 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 150259 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 150259 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11112 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11112 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10067 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10067 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 321025 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 321025 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 321025 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 321025 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1862452631 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1862452631 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4692688176 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4692688176 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 73165002 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 73165002 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 58182011 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 58182011 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6555140807 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 6555140807 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6555140807 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 6555140807 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 136477204500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 136477204500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 39709759000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 39709759000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 176186963500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 176186963500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023984 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023984 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030173 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030173 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119575 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119575 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108423 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108423 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026531 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026531 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026531 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026531 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10906.460484 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10906.460484 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31230.662895 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31230.662895 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6584.323434 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6584.323434 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5779.478593 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5779.478593 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20419.409102 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20419.409102 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20419.409102 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20419.409102 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1122,10 +1118,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 550047772786 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 550047772786 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 550047772786 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 550047772786 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 550791407487 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 550791407487 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 550791407487 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 550791407487 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini index b0e885f8a..adf32d590 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini @@ -20,7 +20,7 @@ kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing -memories=system.realview.nvmem system.physmem +memories=system.physmem system.realview.nvmem midr_regval=890224640 multi_proc=true num_work_ids=16 @@ -250,7 +250,7 @@ header_cycles=1 use_default_range=false width=8 default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.realview.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio +master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio slave=system.system_port system.iocache.mem_side system.l2c.mem_side [system.membus.badaddr_responder] diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout index a0fa03c1d..a561bb329 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 09:08:16 -gem5 started Jul 2 2012 15:20:44 +gem5 compiled Jul 26 2012 21:40:00 +gem5 started Jul 27 2012 00:56:10 gem5 executing on zizzer -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2593402521000 because m5_exit instruction encountered +Exiting @ tick 2594327510000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 5473fafb1..724af2042 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,201 +1,201 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.593403 # Number of seconds simulated -sim_ticks 2593402521000 # Number of ticks simulated -final_tick 2593402521000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.594328 # Number of seconds simulated +sim_ticks 2594327510000 # Number of ticks simulated +final_tick 2594327510000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 766927 # Simulator instruction rate (inst/s) -host_op_rate 979485 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 33608362861 # Simulator tick rate (ticks/s) -host_mem_usage 384708 # Number of bytes of host memory used -host_seconds 77.17 # Real time elapsed on the host -sim_insts 59180230 # Number of instructions simulated -sim_ops 75582343 # Number of ops (including micro ops) simulated -system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 600896 # Simulator instruction rate (inst/s) +host_op_rate 764626 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 25897323777 # Simulator tick rate (ticks/s) +host_mem_usage 390576 # Number of bytes of host memory used +host_seconds 100.18 # Real time elapsed on the host +sim_insts 60196191 # Number of instructions simulated +sim_ops 76598245 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 704224 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9067536 # Number of bytes read from this memory -system.physmem.bytes_read::total 132455600 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 704224 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 704224 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3695808 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 704288 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9067216 # Number of bytes read from this memory +system.physmem.bytes_read::total 132455344 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 704288 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 704288 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3695616 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6711880 # Number of bytes written to this memory +system.physmem.bytes_written::total 6711688 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 17206 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141714 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15494351 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57747 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 17207 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141709 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15494347 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57744 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811765 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47305958 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 811762 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47289092 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 123 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 271544 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3496386 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51074062 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 271544 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 271544 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1425081 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1162979 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2588059 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1425081 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47305958 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 271472 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3495016 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51055753 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 271472 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 271472 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1424499 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1162564 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2587063 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1424499 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47289092 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 123 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 271544 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4659365 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53662121 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 62163 # number of replacements -system.l2c.tagsinuse 51413.022429 # Cycle average of tags in use -system.l2c.total_refs 1730961 # Total number of references to valid blocks. -system.l2c.sampled_refs 127547 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.571162 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2544159444000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 38018.047073 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 3.884744 # Average occupied blocks per requestor +system.physmem.bw_total::cpu.inst 271472 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4657580 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53642816 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 8 # 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number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 31197392500 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu.inst 264840000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu.data 162603193000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 162868033000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.data 162632571500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 162897411500 # number of overall MSHR uncacheable cycles system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000571 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000564 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.012399 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.027105 # 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average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40144.381492 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40043.849611 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40050.765082 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40143.706921 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40038.812053 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40046.028693 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -307,26 +307,26 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 14995175 # DTB read hits -system.cpu.dtb.read_misses 7360 # DTB read misses -system.cpu.dtb.write_hits 11229808 # DTB write hits +system.cpu.dtb.read_hits 14995137 # DTB read hits +system.cpu.dtb.read_misses 7357 # DTB read misses +system.cpu.dtb.write_hits 11229787 # DTB write hits system.cpu.dtb.write_misses 2205 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3488 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 3485 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.prefetch_faults 182 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 15002535 # DTB read accesses -system.cpu.dtb.write_accesses 11232013 # DTB write accesses +system.cpu.dtb.read_accesses 15002494 # DTB read accesses +system.cpu.dtb.write_accesses 11231992 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 26224983 # DTB hits -system.cpu.dtb.misses 9565 # DTB misses -system.cpu.dtb.accesses 26234548 # DTB accesses -system.cpu.itb.inst_hits 60461981 # ITB inst hits +system.cpu.dtb.hits 26224924 # DTB hits +system.cpu.dtb.misses 9562 # DTB misses +system.cpu.dtb.accesses 26234486 # DTB accesses +system.cpu.itb.inst_hits 61490084 # ITB inst hits system.cpu.itb.inst_misses 4471 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -343,79 +343,79 @@ system.cpu.itb.domain_faults 0 # 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average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11687.332086 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11687.332086 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013917 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013917 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013917 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.013917 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013917 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.013917 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11670.805229 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11670.805229 # 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number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 23785932 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 23785932 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 23785932 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027191 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.027191 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024491 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.024491 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046693 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046693 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.026031 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.026031 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.026031 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.026031 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15560.172394 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15560.172394 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36865.463042 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 36865.463042 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14861.423383 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14861.423383 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 24174.858115 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 24174.858115 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 24174.858115 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 24174.858115 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -540,54 +538,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 596084 # number of writebacks -system.cpu.dcache.writebacks::total 596084 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368861 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 368861 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250370 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 250370 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11572 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 11572 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 619231 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 619231 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 619231 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 619231 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4614667500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4614667500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8480868000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8480868000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 137416000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 137416000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13095535500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13095535500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13095535500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13095535500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 146835601000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 146835601000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 40324843500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 40324843500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 187160444500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 187160444500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027195 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027195 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024492 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024492 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046725 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046725 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026033 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.026033 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026033 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.026033 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12510.586644 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12510.586644 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33873.339458 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33873.339458 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11874.870377 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11874.870377 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21148.061870 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 21148.061870 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21148.061870 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 21148.061870 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 596001 # number of writebacks +system.cpu.dcache.writebacks::total 596001 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368807 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 368807 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250355 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 250355 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11564 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 11564 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 619162 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 619162 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 619162 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 619162 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4631124500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4631124500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8478310000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8478310000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 137164000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 137164000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13109434500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13109434500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13109434500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13109434500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 146832035500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 146832035500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 40357680500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 40357680500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 187189716000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 187189716000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027191 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027191 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024491 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024491 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046693 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046693 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026031 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.026031 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026031 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.026031 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12557.040674 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12557.040674 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33865.151485 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33865.151485 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11861.293670 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11861.293670 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21172.866713 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 21172.866713 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21172.866713 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 21172.866713 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -609,10 +607,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1341484384445 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1341484384445 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1341484384445 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1341484384445 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1342178832750 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1342178832750 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1342178832750 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1342178832750 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency |