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authorAndreas Hansson <andreas.hansson@arm.com>2013-11-01 11:56:34 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2013-11-01 11:56:34 -0400
commitccfdc533b9d679f1596d43d647a093885d5e74ab (patch)
tree4c785a5e7a7e2d7244fbdbb0a316405898f99e75 /tests/quick/fs/10.linux-boot/ref/arm
parent460cc77d6db46eef34b14a458816084bf6097b32 (diff)
downloadgem5-ccfdc533b9d679f1596d43d647a093885d5e74ab.tar.xz
stats: Bump stats to match DRAM controller changes
This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm')
-rw-r--r--tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt2845
-rw-r--r--tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt1981
2 files changed, 2584 insertions, 2242 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
index 643b5e070..951921c42 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
@@ -1,148 +1,150 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 1.194884 # Number of seconds simulated
-sim_ticks 1194883580500 # Number of ticks simulated
-final_tick 1194883580500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.195756 # Number of seconds simulated
+sim_ticks 1195756323500 # Number of ticks simulated
+final_tick 1195756323500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 298011 # Simulator instruction rate (inst/s)
-host_op_rate 379758 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 5802481089 # Simulator tick rate (ticks/s)
-host_mem_usage 399660 # Number of bytes of host memory used
-host_seconds 205.93 # Real time elapsed on the host
-sim_insts 61368273 # Number of instructions simulated
-sim_ops 78202205 # Number of ops (including micro ops) simulated
+host_inst_rate 469394 # Simulator instruction rate (inst/s)
+host_op_rate 598174 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 9145402965 # Simulator tick rate (ticks/s)
+host_mem_usage 398732 # Number of bytes of host memory used
+host_seconds 130.75 # Real time elapsed on the host
+sim_insts 61373013 # Number of instructions simulated
+sim_ops 78210923 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 463716 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 6626292 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 463908 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 6634996 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 256092 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 2904240 # Number of bytes read from this memory
-system.physmem.bytes_read::total 62155300 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 463716 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 256092 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 719808 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 4136384 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu1.inst 256412 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 2903984 # Number of bytes read from this memory
+system.physmem.bytes_read::total 62164260 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 463908 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 256412 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 720320 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 4143232 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 3027304 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7163728 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7170576 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 13464 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 103608 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 13467 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 103744 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 4083 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 45405 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 6654631 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 64631 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 4088 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 45401 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 6654771 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 64738 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 756826 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 821467 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 43438970 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 821574 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 43407265 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker 214 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 107 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 388085 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 5545554 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 387962 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 5548786 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker 54 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 214324 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 2430563 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 52017871 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 388085 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 214324 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 602408 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 3461746 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 2533556 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 214435 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 2428575 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 51987398 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 387962 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 214435 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 602397 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 3464947 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 2531706 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 33 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 5995336 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 3461746 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 43438970 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total 5996687 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 3464947 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 43407265 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 214 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 107 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 388085 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 8079110 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 387962 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 8080492 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker 54 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 214324 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 2430597 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 58013207 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 6654631 # Total number of read requests accepted by DRAM controller
-system.physmem.writeReqs 821467 # Total number of write requests accepted by DRAM controller
-system.physmem.readBursts 6654631 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
-system.physmem.writeBursts 821467 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
-system.physmem.bytesRead 425896384 # Total number of bytes read from memory
-system.physmem.bytesWritten 52573888 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 62155300 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 7163728 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 531 # Number of DRAM read bursts serviced by write Q
-system.physmem.neitherReadNorWrite 10643 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 415730 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 415559 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 414958 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 415336 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 422327 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 415339 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 415446 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 415286 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 415350 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 415631 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 415270 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 414743 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 415547 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 416088 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 415759 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 415731 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 7326 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 7216 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 6699 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 6873 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 7393 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 6968 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 7176 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 6994 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 6995 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 7264 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 6985 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 6704 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 7238 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 7541 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 7391 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 7368 # Track writes on a per bank basis
-system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 1194879167500 # Total gap between requests
-system.physmem.readPktSize::0 0 # Categorize read packet sizes
-system.physmem.readPktSize::1 0 # Categorize read packet sizes
-system.physmem.readPktSize::2 6825 # Categorize read packet sizes
-system.physmem.readPktSize::3 6488064 # Categorize read packet sizes
-system.physmem.readPktSize::4 0 # Categorize read packet sizes
-system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 159742 # Categorize read packet sizes
-system.physmem.writePktSize::0 0 # Categorize write packet sizes
-system.physmem.writePktSize::1 0 # Categorize write packet sizes
-system.physmem.writePktSize::2 756836 # Categorize write packet sizes
-system.physmem.writePktSize::3 0 # Categorize write packet sizes
-system.physmem.writePktSize::4 0 # Categorize write packet sizes
-system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 64631 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 586175 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 426728 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 441027 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 1598520 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 1190036 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 1186243 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 1162812 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 9752 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 7190 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 12576 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 17869 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 12223 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 819 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 704 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 675 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 658 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 89 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 4 # What read queue length does an incoming req see
+system.physmem.bw_total::cpu1.inst 214435 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 2428609 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 57984085 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 6654771 # Number of read requests accepted
+system.physmem.writeReqs 821574 # Number of write requests accepted
+system.physmem.readBursts 6654771 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 821574 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 425880832 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 24512 # Total number of bytes read from write queue
+system.physmem.bytesWritten 7300224 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 62164260 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 7170576 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 383 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 707506 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 10656 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 415729 # Per bank write bursts
+system.physmem.perBankRdBursts::1 415559 # Per bank write bursts
+system.physmem.perBankRdBursts::2 414962 # Per bank write bursts
+system.physmem.perBankRdBursts::3 415336 # Per bank write bursts
+system.physmem.perBankRdBursts::4 422370 # Per bank write bursts
+system.physmem.perBankRdBursts::5 415375 # Per bank write bursts
+system.physmem.perBankRdBursts::6 415451 # Per bank write bursts
+system.physmem.perBankRdBursts::7 415289 # Per bank write bursts
+system.physmem.perBankRdBursts::8 415350 # Per bank write bursts
+system.physmem.perBankRdBursts::9 415631 # Per bank write bursts
+system.physmem.perBankRdBursts::10 415265 # Per bank write bursts
+system.physmem.perBankRdBursts::11 414898 # Per bank write bursts
+system.physmem.perBankRdBursts::12 415464 # Per bank write bursts
+system.physmem.perBankRdBursts::13 416088 # Per bank write bursts
+system.physmem.perBankRdBursts::14 415829 # Per bank write bursts
+system.physmem.perBankRdBursts::15 415792 # Per bank write bursts
+system.physmem.perBankWrBursts::0 7314 # Per bank write bursts
+system.physmem.perBankWrBursts::1 7200 # Per bank write bursts
+system.physmem.perBankWrBursts::2 6696 # Per bank write bursts
+system.physmem.perBankWrBursts::3 6864 # Per bank write bursts
+system.physmem.perBankWrBursts::4 7395 # Per bank write bursts
+system.physmem.perBankWrBursts::5 6961 # Per bank write bursts
+system.physmem.perBankWrBursts::6 7170 # Per bank write bursts
+system.physmem.perBankWrBursts::7 6990 # Per bank write bursts
+system.physmem.perBankWrBursts::8 6985 # Per bank write bursts
+system.physmem.perBankWrBursts::9 7249 # Per bank write bursts
+system.physmem.perBankWrBursts::10 6972 # Per bank write bursts
+system.physmem.perBankWrBursts::11 6687 # Per bank write bursts
+system.physmem.perBankWrBursts::12 7224 # Per bank write bursts
+system.physmem.perBankWrBursts::13 7527 # Per bank write bursts
+system.physmem.perBankWrBursts::14 7429 # Per bank write bursts
+system.physmem.perBankWrBursts::15 7403 # Per bank write bursts
+system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
+system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
+system.physmem.totGap 1195751937000 # Total gap between requests
+system.physmem.readPktSize::0 0 # Read request sizes (log2)
+system.physmem.readPktSize::1 0 # Read request sizes (log2)
+system.physmem.readPktSize::2 6825 # Read request sizes (log2)
+system.physmem.readPktSize::3 6488064 # Read request sizes (log2)
+system.physmem.readPktSize::4 0 # Read request sizes (log2)
+system.physmem.readPktSize::5 0 # Read request sizes (log2)
+system.physmem.readPktSize::6 159882 # Read request sizes (log2)
+system.physmem.writePktSize::0 0 # Write request sizes (log2)
+system.physmem.writePktSize::1 0 # Write request sizes (log2)
+system.physmem.writePktSize::2 756836 # Write request sizes (log2)
+system.physmem.writePktSize::3 0 # Write request sizes (log2)
+system.physmem.writePktSize::4 0 # Write request sizes (log2)
+system.physmem.writePktSize::5 0 # Write request sizes (log2)
+system.physmem.writePktSize::6 64738 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 632405 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 479192 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 479926 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 1578313 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 1129029 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 1122994 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 1119651 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 25389 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 24020 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 9298 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 9280 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 9200 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 8958 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 8876 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 8828 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 8796 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 217 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 16 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
@@ -157,31 +159,31 @@ system.physmem.rdQLenPdf::28 0 # Wh
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 4962 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 4963 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 4963 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 4963 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 4963 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 4962 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 4962 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 4962 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 4962 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 4962 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 4962 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 4962 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 4962 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 4962 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 4962 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 4962 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::22 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
@@ -189,282 +191,423 @@ system.physmem.wrQLenPdf::28 0 # Wh
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 34155 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 12682.337813 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 707.328285 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 25224.390929 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64-127 7803 22.85% 22.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-191 4015 11.76% 34.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192-255 2702 7.91% 42.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-319 1928 5.64% 48.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320-383 1397 4.09% 52.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-447 1203 3.52% 55.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448-511 946 2.77% 58.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-575 826 2.42% 60.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576-639 667 1.95% 62.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-703 557 1.63% 64.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704-767 438 1.28% 65.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-831 432 1.26% 67.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832-895 317 0.93% 68.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-959 252 0.74% 68.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960-1023 181 0.53% 69.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1087 297 0.87% 70.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088-1151 146 0.43% 70.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152-1215 131 0.38% 70.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216-1279 122 0.36% 71.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280-1343 99 0.29% 71.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1344-1407 97 0.28% 71.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1408-1471 161 0.47% 72.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1472-1535 728 2.13% 74.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1536-1599 239 0.70% 75.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600-1663 168 0.49% 75.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664-1727 146 0.43% 76.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1728-1791 103 0.30% 76.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1792-1855 87 0.25% 76.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856-1919 68 0.20% 76.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1920-1983 55 0.16% 77.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1984-2047 40 0.12% 77.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2048-2111 46 0.13% 77.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2112-2175 38 0.11% 77.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2176-2239 21 0.06% 77.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2240-2303 23 0.07% 77.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2304-2367 20 0.06% 77.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2368-2431 20 0.06% 77.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2432-2495 20 0.06% 77.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2496-2559 23 0.07% 77.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2560-2623 11 0.03% 77.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2624-2687 12 0.04% 77.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2688-2751 19 0.06% 77.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2752-2815 8 0.02% 77.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2816-2879 17 0.05% 77.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2880-2943 10 0.03% 77.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2944-3007 5 0.01% 78.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3008-3071 7 0.02% 78.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3072-3135 13 0.04% 78.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3136-3199 2 0.01% 78.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3200-3263 15 0.04% 78.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3264-3327 7 0.02% 78.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3328-3391 12 0.04% 78.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3392-3455 12 0.04% 78.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3456-3519 8 0.02% 78.23% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::3584-3647 11 0.03% 78.29% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::total 34155 # Bytes accessed per row activation
-system.physmem.totQLat 126519681500 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 168380906500 # Sum of mem lat for all requests
-system.physmem.totBusLat 33270500000 # Total cycles spent in databus access
-system.physmem.totBankLat 8590725000 # Total cycles spent in bank access
-system.physmem.avgQLat 19013.79 # Average queueing delay per request
-system.physmem.avgBankLat 1291.04 # Average bank access latency per request
-system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 25304.84 # Average memory access latency
-system.physmem.avgRdBW 356.43 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 44.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 52.02 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 6.00 # Average consumed write bandwidth in MB/s
-system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 3.13 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.14 # Average read queue length over time
-system.physmem.avgWrQLen 14.04 # Average write queue length over time
-system.physmem.readRowHits 6636405 # Number of row buffer hits during reads
-system.physmem.writeRowHits 97666 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 99.73 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 11.89 # Row buffer hit rate for writes
-system.physmem.avgGap 159826.58 # Average gap between requests
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+system.physmem.bytesPerActivate::mean 5772.432765 # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::stdev 13030.260865 # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::49088-49095 6 0.01% 97.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::49152-49159 2103 2.80% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::49792-49799 1 0.00% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 75043 # Bytes accessed per row activation
+system.physmem.totQLat 159590177750 # Total ticks spent queuing
+system.physmem.totMemAccLat 202588661500 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 33271940000 # Total ticks spent in databus transfers
+system.physmem.totBankLat 9726543750 # Total ticks spent accessing banks
+system.physmem.avgQLat 23982.70 # Average queueing delay per DRAM burst
+system.physmem.avgBankLat 1461.67 # Average bank access latency per DRAM burst
+system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
+system.physmem.avgMemAccLat 30444.37 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 356.16 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 6.11 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 51.99 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 6.00 # Average system write bandwidth in MiByte/s
+system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
+system.physmem.busUtil 2.83 # Data bus utilization in percentage
+system.physmem.busUtilRead 2.78 # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen 0.17 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 12.10 # Average write queue length when enqueuing
+system.physmem.readRowHits 6598517 # Number of row buffer hits during reads
+system.physmem.writeRowHits 94894 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 99.16 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 83.19 # Row buffer hit rate for writes
+system.physmem.avgGap 159938.04 # Average gap between requests
+system.physmem.pageHitRate 98.89 # Row buffer hit rate, read and write combined
+system.physmem.prechargeAllPercent 4.89 # Percentage of time for which DRAM has all the banks in precharge state
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
@@ -483,286 +626,286 @@ system.realview.nvmem.bw_inst_read::total 57 # I
system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 60029719 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 7703148 # Transaction distribution
-system.membus.trans_dist::ReadResp 7703148 # Transaction distribution
-system.membus.trans_dist::WriteReq 767203 # Transaction distribution
-system.membus.trans_dist::WriteResp 767203 # Transaction distribution
-system.membus.trans_dist::Writeback 64631 # Transaction distribution
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+system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 62500 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst 233748250 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data 3017365364 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total 9623103408 # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 344713750 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12648858491 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5098250 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154081373749 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 167080044240 # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 16272206162 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 486212000 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total 16758418162 # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 344713750 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data 28921064653 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5098250 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data 154567585749 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 183838462402 # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000853 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001323 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013947 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.038608 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000552 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010625 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.016760 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total 0.018067 # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.755732 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.882138 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.808933 # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.590840 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.830156 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.702922 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.592083 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.496123 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total 0.557684 # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000853 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001323 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013947 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data 0.254389 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000552 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010625 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data 0.229262 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.108667 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000853 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001323 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013947 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data 0.254389 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000552 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010625 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data 0.229262 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.108667 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 63500 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59373.792801 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 63169.701337 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58422.456886 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 67697.542283 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 61549.990959 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10012.407974 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10039.718297 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10024.942342 # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10016.501292 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10015.611691 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10016.009238 # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56187.238680 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 64785.004126 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 58929.114754 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 63500 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59373.792801 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 56833.806114 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58422.456886 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 64903.535470 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 59291.707432 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 63500 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59373.792801 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 56833.806114 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58422.456886 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 64903.535470 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 59291.707432 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
@@ -944,64 +1087,64 @@ system.cf0.dma_read_txs 0 # Nu
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
-system.toL2Bus.throughput 118384606 # Throughput (bytes/s)
-system.toL2Bus.trans_dist::ReadReq 2504676 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 2504676 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 767203 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 767203 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 576006 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 26963 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 16769 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 43732 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 262452 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 262452 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 993712 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2951029 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 5836 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 14921 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 753525 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 2879302 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 6196 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 11995 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 7616516 # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 31376632 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 53718524 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 5760 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 18112 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 24082060 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 27916814 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 7480 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 15128 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size::total 137140510 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus 137140510 # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus 4315312 # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy 4764811697 # Layer occupancy (ticks)
+system.toL2Bus.throughput 118413539 # Throughput (bytes/s)
+system.toL2Bus.trans_dist::ReadReq 2505894 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 2505894 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 767205 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 767205 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 576824 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 26927 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 16847 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 43774 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 262598 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 262598 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 994053 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2951842 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 5908 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 15091 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 754073 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 2881163 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 6136 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 11790 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 7620056 # Packet count per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 31386872 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 53739672 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 6048 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 18760 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 24100876 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 28000722 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 7240 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 14248 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size::total 137274438 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.data_through_bus 137274438 # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus 4319300 # Total snoop data (bytes)
+system.toL2Bus.reqLayer0.occupancy 4769236119 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 2217607730 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 2218068983 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 2471552710 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 2472016836 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 4396500 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy 4396000 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 10394000 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy 10401000 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer4.occupancy 1697838714 # Layer occupancy (ticks)
+system.toL2Bus.respLayer4.occupancy 1698781961 # Layer occupancy (ticks)
system.toL2Bus.respLayer4.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer5.occupancy 2214012427 # Layer occupancy (ticks)
+system.toL2Bus.respLayer5.occupancy 2209782432 # Layer occupancy (ticks)
system.toL2Bus.respLayer5.utilization 0.2 # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy 4326250 # Layer occupancy (ticks)
+system.toL2Bus.respLayer6.occupancy 4326000 # Layer occupancy (ticks)
system.toL2Bus.respLayer6.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy 8213499 # Layer occupancy (ticks)
+system.toL2Bus.respLayer7.occupancy 8228499 # Layer occupancy (ticks)
system.toL2Bus.respLayer7.utilization 0.0 # Layer utilization (%)
-system.iobus.throughput 45439063 # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq 7671399 # Transaction distribution
-system.iobus.trans_dist::ReadResp 7671399 # Transaction distribution
+system.iobus.throughput 45405912 # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq 7671403 # Transaction distribution
+system.iobus.trans_dist::ReadResp 7671403 # Transaction distribution
system.iobus.trans_dist::WriteReq 7946 # Transaction distribution
system.iobus.trans_dist::WriteResp 7946 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30448 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8060 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8066 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 740 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 742 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 496 # Packet count per connected master and slave (bytes)
@@ -1021,14 +1164,14 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 2382562 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 2382570 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12976128 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total 12976128 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 15358690 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 15358698 # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40166 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16120 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16132 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1480 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1484 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 272 # Cumulative packet size per connected master and slave (bytes)
@@ -1048,18 +1191,18 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio
system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total 2389878 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::total 2389894 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 51904512 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::total 51904512 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total 54294390 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus 54294390 # Total data (bytes)
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+system.iobus.data_through_bus 54294406 # Total data (bytes)
system.iobus.reqLayer0.occupancy 21350000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
@@ -1101,32 +1244,32 @@ system.iobus.reqLayer23.occupancy 8000 # La
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 6488064000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 2374616000 # Layer occupancy (ticks)
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system.iobus.respLayer0.utilization 0.2 # Layer utilization (%)
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+system.iobus.respLayer1.occupancy 17778330502 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 1.5 # Layer utilization (%)
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system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 1811 # Number of entries that have been flushed from TLB
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system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions
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system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu0.itb.inst_misses 2205 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
@@ -1143,79 +1286,79 @@ system.cpu0.itb.domain_faults 0 # Nu
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
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system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read
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system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -1224,120 +1367,120 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
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system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
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system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -1346,66 +1489,66 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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-system.cpu0.dcache.overall_mshr_miss_rate::total 0.027398 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12685.907342 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12685.907342 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40423.275666 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40423.275666 # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7956.432896 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7956.432896 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3489.851606 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3489.851606 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10890401466 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 10890401466 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10890401466 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 10890401466 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13765517500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13765517500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 25807250835 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 25807250835 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 39572768335 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 39572768335 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028088 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.028088 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.026487 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.026487 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059640 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059640 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.044629 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.044629 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027424 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.027424 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027424 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.027424 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12858.165854 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12858.165854 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42418.953310 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42418.953310 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7950.100756 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7950.100756 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3502.035695 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3502.035695 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23815.082783 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23815.082783 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23815.082783 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23815.082783 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24709.523970 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24709.523970 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24709.523970 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24709.523970 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
@@ -1415,26 +1558,26 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 5705173 # DTB read hits
-system.cpu1.dtb.read_misses 3576 # DTB read misses
-system.cpu1.dtb.write_hits 3872049 # DTB write hits
-system.cpu1.dtb.write_misses 645 # DTB write misses
+system.cpu1.dtb.read_hits 5708064 # DTB read hits
+system.cpu1.dtb.read_misses 3582 # DTB read misses
+system.cpu1.dtb.write_hits 3874465 # DTB write hits
+system.cpu1.dtb.write_misses 647 # DTB write misses
system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 1989 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 144 # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults 142 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 5708749 # DTB read accesses
-system.cpu1.dtb.write_accesses 3872694 # DTB write accesses
+system.cpu1.dtb.read_accesses 5711646 # DTB read accesses
+system.cpu1.dtb.write_accesses 3875112 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 9577222 # DTB hits
-system.cpu1.dtb.misses 4221 # DTB misses
-system.cpu1.dtb.accesses 9581443 # DTB accesses
-system.cpu1.itb.inst_hits 19377969 # ITB inst hits
+system.cpu1.dtb.hits 9582529 # DTB hits
+system.cpu1.dtb.misses 4229 # DTB misses
+system.cpu1.dtb.accesses 9586758 # DTB accesses
+system.cpu1.itb.inst_hits 19382020 # ITB inst hits
system.cpu1.itb.inst_misses 2171 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
@@ -1451,79 +1594,79 @@ system.cpu1.itb.domain_faults 0 # Nu
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 19380140 # ITB inst accesses
-system.cpu1.itb.hits 19377969 # DTB hits
+system.cpu1.itb.inst_accesses 19384191 # ITB inst accesses
+system.cpu1.itb.hits 19382020 # DTB hits
system.cpu1.itb.misses 2171 # DTB misses
-system.cpu1.itb.accesses 19380140 # DTB accesses
-system.cpu1.numCycles 2388332817 # number of cpu cycles simulated
+system.cpu1.itb.accesses 19384191 # DTB accesses
+system.cpu1.numCycles 2390063941 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 18797412 # Number of instructions committed
-system.cpu1.committedOps 24898830 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 22263010 # Number of integer alu accesses
+system.cpu1.committedInsts 18801432 # Number of instructions committed
+system.cpu1.committedOps 24909061 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 22272671 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses
-system.cpu1.num_func_calls 796668 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 2514459 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 22263010 # number of integer instructions
+system.cpu1.num_func_calls 796781 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 2514806 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 22272671 # number of integer instructions
system.cpu1.num_fp_insts 6793 # number of float instructions
-system.cpu1.num_int_register_reads 130745617 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 23316317 # number of times the integer registers were written
+system.cpu1.num_int_register_reads 130802029 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 23323968 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written
-system.cpu1.num_mem_refs 10012651 # number of memory refs
-system.cpu1.num_load_insts 5981805 # Number of load instructions
-system.cpu1.num_store_insts 4030846 # Number of store instructions
-system.cpu1.num_idle_cycles 1968708722.646828 # Number of idle cycles
-system.cpu1.num_busy_cycles 419624094.353172 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.175697 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.824303 # Percentage of idle cycles
+system.cpu1.num_mem_refs 10017952 # number of memory refs
+system.cpu1.num_load_insts 5984754 # Number of load instructions
+system.cpu1.num_store_insts 4033198 # Number of store instructions
+system.cpu1.num_idle_cycles 1969143633.381917 # Number of idle cycles
+system.cpu1.num_busy_cycles 420920307.618083 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.176113 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.823887 # Percentage of idle cycles
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 39053 # number of quiesce instructions executed
-system.cpu1.icache.tags.replacements 376539 # number of replacements
-system.cpu1.icache.tags.tagsinuse 474.945138 # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs 19000914 # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs 377051 # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs 50.393485 # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle 327002273500 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst 474.945138 # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst 0.927627 # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total 0.927627 # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::cpu1.inst 19000914 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 19000914 # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst 19000914 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 19000914 # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst 19000914 # number of overall hits
-system.cpu1.icache.overall_hits::total 19000914 # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst 377051 # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total 377051 # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst 377051 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 377051 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst 377051 # number of overall misses
-system.cpu1.icache.overall_misses::total 377051 # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5154764964 # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total 5154764964 # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst 5154764964 # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total 5154764964 # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst 5154764964 # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total 5154764964 # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst 19377965 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 19377965 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst 19377965 # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total 19377965 # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst 19377965 # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total 19377965 # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.019458 # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total 0.019458 # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst 0.019458 # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total 0.019458 # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst 0.019458 # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total 0.019458 # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13671.267187 # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 13671.267187 # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13671.267187 # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 13671.267187 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13671.267187 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 13671.267187 # average overall miss latency
+system.cpu1.kern.inst.quiesce 39084 # number of quiesce instructions executed
+system.cpu1.icache.tags.replacements 376793 # number of replacements
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+system.cpu1.icache.tags.total_refs 19004711 # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs 377305 # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs 50.369624 # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle 327169943500 # Cycle when the warmup percentage was hit.
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+system.cpu1.icache.tags.occ_percent::cpu1.inst 0.927553 # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total 0.927553 # Average percentage of cache occupancy
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+system.cpu1.icache.ReadReq_misses::total 377305 # number of ReadReq misses
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+system.cpu1.icache.demand_misses::total 377305 # number of demand (read+write) misses
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+system.cpu1.icache.overall_misses::total 377305 # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5159789711 # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total 5159789711 # number of ReadReq miss cycles
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+system.cpu1.icache.demand_miss_latency::total 5159789711 # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst 5159789711 # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total 5159789711 # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst 19382016 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total 19382016 # number of ReadReq accesses(hits+misses)
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+system.cpu1.icache.overall_accesses::cpu1.inst 19382016 # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total 19382016 # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.019467 # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total 0.019467 # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst 0.019467 # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total 0.019467 # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst 0.019467 # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total 0.019467 # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13675.381219 # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 13675.381219 # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13675.381219 # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 13675.381219 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13675.381219 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 13675.381219 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -1532,120 +1675,120 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 377051 # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total 377051 # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst 377051 # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total 377051 # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst 377051 # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total 377051 # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4398685536 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total 4398685536 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4398685536 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total 4398685536 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4398685536 # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total 4398685536 # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6184500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6184500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6184500 # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total 6184500 # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.019458 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.019458 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.019458 # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total 0.019458 # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.019458 # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total 0.019458 # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11666.022729 # average ReadReq mshr miss latency
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system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -1654,66 +1797,66 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
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+system.cpu1.dcache.overall_mshr_misses::total 246917 # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1388441271 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1388441271 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4117774524 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4117774524 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 58015501 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 58015501 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 30499022 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30499022 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4873705297 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 4873705297 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4873705297 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 4873705297 # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168372112000 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168372112000 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 531034000 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 531034000 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 168903146000 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 168903146000 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.029578 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.029578 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.029784 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.029784 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.117027 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.117027 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.113004 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.113004 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029671 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total 0.029671 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.029671 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.029671 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10325.924612 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10325.924612 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30982.289825 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 30982.289825 # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6004.083308 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6004.083308 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3234.751943 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3234.751943 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5506215795 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 5506215795 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5506215795 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 5506215795 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168382941250 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168382941250 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 531038000 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 531038000 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 168913979250 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 168913979250 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.029635 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.029635 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.029790 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.029790 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.117265 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.117265 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.113346 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.113346 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029706 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.029706 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.029706 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.029706 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10354.547476 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10354.547476 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36496.357468 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 36496.357468 # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 5942.993342 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 5942.993342 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3235.627201 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3235.627201 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19773.388688 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19773.388688 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19773.388688 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19773.388688 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22299.865117 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22299.865117 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22299.865117 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22299.865117 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
@@ -1735,10 +1878,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan #
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 618710198251 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 618710198251 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 618710198251 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 618710198251 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 651875253502 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 651875253502 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 651875253502 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 651875253502 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
index efd49eb78..50a428e90 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
@@ -1,130 +1,132 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 2.615716 # Number of seconds simulated
-sim_ticks 2615716222000 # Number of ticks simulated
-final_tick 2615716222000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.616536 # Number of seconds simulated
+sim_ticks 2616536483000 # Number of ticks simulated
+final_tick 2616536483000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 250038 # Simulator instruction rate (inst/s)
-host_op_rate 318184 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 10864403710 # Simulator tick rate (ticks/s)
-host_mem_usage 394540 # Number of bytes of host memory used
-host_seconds 240.76 # Real time elapsed on the host
-sim_insts 60199078 # Number of instructions simulated
-sim_ops 76605946 # Number of ops (including micro ops) simulated
+host_inst_rate 552343 # Simulator instruction rate (inst/s)
+host_op_rate 702879 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 24008008080 # Simulator tick rate (ticks/s)
+host_mem_usage 395660 # Number of bytes of host memory used
+host_seconds 108.99 # Real time elapsed on the host
+sim_insts 60197580 # Number of instructions simulated
+sim_ops 76603973 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 704928 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9093712 # Number of bytes read from this memory
-system.physmem.bytes_read::total 132482480 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 704928 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 704928 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 3710144 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.inst 703904 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9089744 # Number of bytes read from this memory
+system.physmem.bytes_read::total 132477488 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 703904 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 703904 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 3706176 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6726216 # Number of bytes written to this memory
+system.physmem.bytes_written::total 6722248 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 17217 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 142123 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15494771 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 57971 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu.inst 17201 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 142061 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 15494693 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 57909 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 811989 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 46902409 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 811927 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 46887705 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker 122 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 49 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 269497 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3476567 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 50648644 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 269497 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 269497 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1418405 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 1153058 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2571462 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1418405 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 46902409 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 269021 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3473960 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 50630858 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 269021 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 269021 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1416443 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 1152696 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2569140 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1416443 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 46887705 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 122 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 49 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 269497 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 4629625 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 53220107 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15494771 # Total number of read requests accepted by DRAM controller
-system.physmem.writeReqs 811989 # Total number of write requests accepted by DRAM controller
-system.physmem.readBursts 15494771 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
-system.physmem.writeBursts 811989 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
-system.physmem.bytesRead 991665344 # Total number of bytes read from memory
-system.physmem.bytesWritten 51967296 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 132482480 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 6726216 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 1656 # Number of DRAM read bursts serviced by write Q
-system.physmem.neitherReadNorWrite 4515 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 968108 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 967905 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 967771 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 967944 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 974355 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 968114 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 967591 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 967671 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 968519 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 968300 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 967957 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 967810 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 967935 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 967629 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 967816 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 967690 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 6734 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 6600 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 6526 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 6493 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 6702 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 6993 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 6729 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 6823 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 7180 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 6976 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 6694 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 6614 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 6691 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 6338 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 6636 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 6497 # Track writes on a per bank basis
-system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 2615711849000 # Total gap between requests
-system.physmem.readPktSize::0 0 # Categorize read packet sizes
-system.physmem.readPktSize::1 0 # Categorize read packet sizes
-system.physmem.readPktSize::2 6652 # Categorize read packet sizes
-system.physmem.readPktSize::3 15335424 # Categorize read packet sizes
-system.physmem.readPktSize::4 0 # Categorize read packet sizes
-system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 152695 # Categorize read packet sizes
-system.physmem.writePktSize::0 0 # Categorize write packet sizes
-system.physmem.writePktSize::1 0 # Categorize write packet sizes
-system.physmem.writePktSize::2 754018 # Categorize write packet sizes
-system.physmem.writePktSize::3 0 # Categorize write packet sizes
-system.physmem.writePktSize::4 0 # Categorize write packet sizes
-system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 57971 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 1137574 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 984079 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 1018155 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 3783404 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 2827794 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 2821787 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 2781992 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 18262 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 15752 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 29208 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 42299 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 28515 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 1143 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 1054 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 1034 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 1015 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 48 # What read queue length does an incoming req see
+system.physmem.bw_total::cpu.inst 269021 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 4626657 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 53199998 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 15494693 # Number of read requests accepted
+system.physmem.writeReqs 811927 # Number of write requests accepted
+system.physmem.readBursts 15494693 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 811927 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 991555264 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 105088 # Total number of bytes read from write queue
+system.physmem.bytesWritten 6843648 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 132477488 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 6722248 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 1642 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 704975 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 4515 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 967983 # Per bank write bursts
+system.physmem.perBankRdBursts::1 967714 # Per bank write bursts
+system.physmem.perBankRdBursts::2 967672 # Per bank write bursts
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+system.physmem.perBankRdBursts::4 974609 # Per bank write bursts
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+system.physmem.perBankRdBursts::8 968546 # Per bank write bursts
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+system.physmem.perBankRdBursts::13 967741 # Per bank write bursts
+system.physmem.perBankRdBursts::14 967766 # Per bank write bursts
+system.physmem.perBankRdBursts::15 967796 # Per bank write bursts
+system.physmem.perBankWrBursts::0 6610 # Per bank write bursts
+system.physmem.perBankWrBursts::1 6410 # Per bank write bursts
+system.physmem.perBankWrBursts::2 6422 # Per bank write bursts
+system.physmem.perBankWrBursts::3 6344 # Per bank write bursts
+system.physmem.perBankWrBursts::4 6906 # Per bank write bursts
+system.physmem.perBankWrBursts::5 7096 # Per bank write bursts
+system.physmem.perBankWrBursts::6 6901 # Per bank write bursts
+system.physmem.perBankWrBursts::7 6892 # Per bank write bursts
+system.physmem.perBankWrBursts::8 7193 # Per bank write bursts
+system.physmem.perBankWrBursts::9 6845 # Per bank write bursts
+system.physmem.perBankWrBursts::10 6667 # Per bank write bursts
+system.physmem.perBankWrBursts::11 6550 # Per bank write bursts
+system.physmem.perBankWrBursts::12 6596 # Per bank write bursts
+system.physmem.perBankWrBursts::13 6392 # Per bank write bursts
+system.physmem.perBankWrBursts::14 6532 # Per bank write bursts
+system.physmem.perBankWrBursts::15 6576 # Per bank write bursts
+system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
+system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
+system.physmem.totGap 2616532122000 # Total gap between requests
+system.physmem.readPktSize::0 0 # Read request sizes (log2)
+system.physmem.readPktSize::1 0 # Read request sizes (log2)
+system.physmem.readPktSize::2 6652 # Read request sizes (log2)
+system.physmem.readPktSize::3 15335424 # Read request sizes (log2)
+system.physmem.readPktSize::4 0 # Read request sizes (log2)
+system.physmem.readPktSize::5 0 # Read request sizes (log2)
+system.physmem.readPktSize::6 152617 # Read request sizes (log2)
+system.physmem.writePktSize::0 0 # Write request sizes (log2)
+system.physmem.writePktSize::1 0 # Write request sizes (log2)
+system.physmem.writePktSize::2 754018 # Write request sizes (log2)
+system.physmem.writePktSize::3 0 # Write request sizes (log2)
+system.physmem.writePktSize::4 0 # Write request sizes (log2)
+system.physmem.writePktSize::5 0 # Write request sizes (log2)
+system.physmem.writePktSize::6 57909 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 1265330 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
@@ -140,29 +142,29 @@ system.physmem.rdQLenPdf::28 0 # Wh
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 4662 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
@@ -172,281 +174,478 @@ system.physmem.wrQLenPdf::28 0 # Wh
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 38068 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 26227.310287 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 2428.378300 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 31656.989485 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64-127 5540 14.55% 14.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-191 3323 8.73% 23.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192-255 2175 5.71% 29.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-319 1668 4.38% 33.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320-383 1160 3.05% 36.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-447 1060 2.78% 39.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448-511 828 2.18% 41.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-575 781 2.05% 43.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576-639 514 1.35% 44.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-703 493 1.30% 46.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704-767 417 1.10% 47.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-831 450 1.18% 48.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832-895 283 0.74% 49.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-959 279 0.73% 49.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960-1023 185 0.49% 50.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1087 195 0.51% 50.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088-1151 134 0.35% 51.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152-1215 139 0.37% 51.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216-1279 114 0.30% 51.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280-1343 94 0.25% 52.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1344-1407 76 0.20% 52.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1408-1471 150 0.39% 52.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1472-1535 792 2.08% 54.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1536-1599 203 0.53% 55.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600-1663 136 0.36% 55.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664-1727 113 0.30% 55.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1728-1791 91 0.24% 56.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1792-1855 85 0.22% 56.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856-1919 60 0.16% 56.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1920-1983 34 0.09% 56.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1984-2047 44 0.12% 56.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2048-2111 48 0.13% 56.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2112-2175 31 0.08% 56.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2176-2239 35 0.09% 57.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2240-2303 24 0.06% 57.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2304-2367 25 0.07% 57.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2368-2431 18 0.05% 57.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2432-2495 18 0.05% 57.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2496-2559 21 0.06% 57.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2560-2623 13 0.03% 57.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2624-2687 5 0.01% 57.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2688-2751 11 0.03% 57.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2752-2815 8 0.02% 57.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2816-2879 15 0.04% 57.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2880-2943 17 0.04% 57.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2944-3007 7 0.02% 57.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3008-3071 7 0.02% 57.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3072-3135 18 0.05% 57.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3136-3199 8 0.02% 57.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3200-3263 8 0.02% 57.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3264-3327 10 0.03% 57.69% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::3456-3519 11 0.03% 57.78% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::3712-3775 7 0.02% 57.84% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::9216-9279 3 0.01% 60.37% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::10240-10303 4 0.01% 60.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11520-11583 1 0.00% 60.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11904-11967 1 0.00% 60.38% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::12928-12991 1 0.00% 60.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13056-13119 4 0.01% 60.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13184-13247 1 0.00% 60.41% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::total 38068 # Bytes accessed per row activation
-system.physmem.totQLat 296768605750 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 390592239500 # Sum of mem lat for all requests
-system.physmem.totBusLat 77465575000 # Total cycles spent in databus access
-system.physmem.totBankLat 16358058750 # Total cycles spent in bank access
-system.physmem.avgQLat 19154.87 # Average queueing delay per request
-system.physmem.avgBankLat 1055.83 # Average bank access latency per request
-system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 25210.70 # Average memory access latency
-system.physmem.avgRdBW 379.12 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 19.87 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 50.65 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 2.57 # Average consumed write bandwidth in MB/s
-system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 3.12 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.15 # Average read queue length over time
-system.physmem.avgWrQLen 13.76 # Average write queue length over time
-system.physmem.readRowHits 15468398 # Number of row buffer hits during reads
-system.physmem.writeRowHits 93875 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 99.84 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 11.56 # Row buffer hit rate for writes
-system.physmem.avgGap 160406.60 # Average gap between requests
+system.physmem.bytesPerActivate::samples 89727 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 11127.069087 # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::stdev 16706.873806 # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::36992-36999 2 0.00% 86.31% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::37184-37191 1 0.00% 86.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::37312-37319 1 0.00% 86.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::37376-37383 153 0.17% 86.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::37504-37511 2 0.00% 86.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::37568-37575 2 0.00% 86.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::37632-37639 81 0.09% 86.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::37760-37767 2 0.00% 86.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::37824-37831 1 0.00% 86.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::37888-37895 483 0.54% 87.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::37952-37959 1 0.00% 87.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::38144-38151 12 0.01% 87.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::38400-38407 2 0.00% 87.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::38528-38535 4 0.00% 87.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::38592-38599 1 0.00% 87.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::38656-38663 84 0.09% 87.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::38848-38855 1 0.00% 87.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::38912-38919 271 0.30% 87.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::39040-39047 1 0.00% 87.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::39168-39175 30 0.03% 87.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::39232-39239 1 0.00% 87.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::39296-39303 1 0.00% 87.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::39424-39431 152 0.17% 87.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::39552-39559 3 0.00% 87.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::39616-39623 1 0.00% 87.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::39680-39687 86 0.10% 88.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::39808-39815 1 0.00% 88.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::39936-39943 521 0.58% 88.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::40064-40071 2 0.00% 88.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::40192-40199 77 0.09% 88.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::40448-40455 28 0.03% 88.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::40576-40583 4 0.00% 88.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::40704-40711 10 0.01% 88.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::40960-40967 402 0.45% 89.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::41216-41223 9 0.01% 89.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::41280-41287 1 0.00% 89.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::41408-41415 1 0.00% 89.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::41472-41479 35 0.04% 89.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::41600-41607 4 0.00% 89.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::41728-41735 79 0.09% 89.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::41856-41863 1 0.00% 89.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::41984-41991 523 0.58% 89.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::42240-42247 79 0.09% 89.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::42496-42503 146 0.16% 90.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::42624-42631 4 0.00% 90.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::42752-42759 34 0.04% 90.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::43008-43015 269 0.30% 90.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::43136-43143 1 0.00% 90.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::43200-43207 1 0.00% 90.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::43264-43271 89 0.10% 90.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::43328-43335 1 0.00% 90.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::43520-43527 3 0.00% 90.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::43648-43655 3 0.00% 90.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::43712-43719 1 0.00% 90.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::43776-43783 13 0.01% 90.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::43904-43911 1 0.00% 90.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::44032-44039 482 0.54% 91.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::44160-44167 1 0.00% 91.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::44224-44231 2 0.00% 91.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::44288-44295 78 0.09% 91.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::44544-44551 151 0.17% 91.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::44672-44679 2 0.00% 91.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::44800-44807 138 0.15% 91.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::44928-44935 3 0.00% 91.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::45056-45063 153 0.17% 91.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::45120-45127 2 0.00% 91.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::45184-45191 1 0.00% 91.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::45312-45319 134 0.15% 91.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::45568-45575 77 0.09% 91.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::45696-45703 2 0.00% 91.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::45760-45767 1 0.00% 91.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::45824-45831 82 0.09% 92.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::46080-46087 341 0.38% 92.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::46144-46151 1 0.00% 92.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::46208-46215 2 0.00% 92.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::46336-46343 140 0.16% 92.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::46464-46471 1 0.00% 92.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::46592-46599 93 0.10% 92.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::46720-46727 1 0.00% 92.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::46848-46855 133 0.15% 92.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::46976-46983 3 0.00% 92.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::47104-47111 149 0.17% 93.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::47232-47239 3 0.00% 93.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::47360-47367 156 0.17% 93.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::47616-47623 157 0.17% 93.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::47744-47751 3 0.00% 93.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::47872-47879 88 0.10% 93.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::47936-47943 1 0.00% 93.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::48000-48007 1 0.00% 93.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::48128-48135 298 0.33% 93.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::48192-48199 4 0.00% 93.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::48256-48263 1 0.00% 93.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::48320-48327 3 0.00% 93.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::48384-48391 110 0.12% 93.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::48512-48519 1 0.00% 93.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::48640-48647 200 0.22% 94.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::48768-48775 70 0.08% 94.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::48896-48903 136 0.15% 94.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::48960-48967 5 0.01% 94.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::49024-49031 9 0.01% 94.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::49088-49095 6 0.01% 94.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::49152-49159 5002 5.57% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 89727 # Bytes accessed per row activation
+system.physmem.totQLat 373414318500 # Total ticks spent queuing
+system.physmem.totMemAccLat 469593144750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 77465255000 # Total ticks spent in databus transfers
+system.physmem.totBankLat 18713571250 # Total ticks spent accessing banks
+system.physmem.avgQLat 24102.05 # Average queueing delay per DRAM burst
+system.physmem.avgBankLat 1207.87 # Average bank access latency per DRAM burst
+system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
+system.physmem.avgMemAccLat 30309.92 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 378.96 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 2.62 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 50.63 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 2.57 # Average system write bandwidth in MiByte/s
+system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
+system.physmem.busUtil 2.98 # Data bus utilization in percentage
+system.physmem.busUtilRead 2.96 # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 14.75 # Average write queue length when enqueuing
+system.physmem.readRowHits 15419103 # Number of row buffer hits during reads
+system.physmem.writeRowHits 91153 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 85.23 # Row buffer hit rate for writes
+system.physmem.avgGap 160458.28 # Average gap between requests
+system.physmem.pageHitRate 99.42 # Row buffer hit rate, read and write combined
+system.physmem.prechargeAllPercent 2.19 # Percentage of time for which DRAM has all the banks in precharge state
system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
@@ -459,49 +658,49 @@ system.realview.nvmem.bw_inst_read::cpu.inst 8
system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 54136917 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 16546596 # Transaction distribution
-system.membus.trans_dist::ReadResp 16546596 # Transaction distribution
+system.membus.throughput 54116520 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 16546551 # Transaction distribution
+system.membus.trans_dist::ReadResp 16546551 # Transaction distribution
system.membus.trans_dist::WriteReq 763368 # Transaction distribution
system.membus.trans_dist::WriteResp 763368 # Transaction distribution
-system.membus.trans_dist::Writeback 57971 # Transaction distribution
+system.membus.trans_dist::Writeback 57909 # Transaction distribution
system.membus.trans_dist::UpgradeReq 4515 # Transaction distribution
system.membus.trans_dist::UpgradeResp 4515 # Transaction distribution
-system.membus.trans_dist::ReadExReq 132250 # Transaction distribution
-system.membus.trans_dist::ReadExResp 132250 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382988 # Packet count per connected master and slave (bytes)
+system.membus.trans_dist::ReadExReq 132216 # Transaction distribution
+system.membus.trans_dist::ReadExResp 132216 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382986 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3850 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1893731 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4280581 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1893513 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4280361 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30670848 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 30670848 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 34951429 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390393 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count::total 34951209 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390389 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7700 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16525304 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 18923421 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16516344 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 18914457 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 122683392 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total 122683392 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 141606813 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 141606813 # Total data (bytes)
+system.membus.tot_pkt_size::total 141597849 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 141597849 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 1206151000 # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy 1206149500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 3613000 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 3614000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks)
system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer6.occupancy 17904160000 # Layer occupancy (ticks)
+system.membus.reqLayer6.occupancy 17910601500 # Layer occupancy (ticks)
system.membus.reqLayer6.utilization 0.7 # Layer utilization (%)
-system.membus.respLayer1.occupancy 4944878700 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 4950348835 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
-system.membus.respLayer2.occupancy 34615555500 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 34633819250 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 1.3 # Layer utilization (%)
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
@@ -509,13 +708,13 @@ system.cf0.dma_read_txs 0 # Nu
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
-system.iobus.throughput 47816267 # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq 16518752 # Transaction distribution
-system.iobus.trans_dist::ReadResp 16518752 # Transaction distribution
+system.iobus.throughput 47801275 # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq 16518751 # Transaction distribution
+system.iobus.trans_dist::ReadResp 16518751 # Transaction distribution
system.iobus.trans_dist::WriteReq 8166 # Transaction distribution
system.iobus.trans_dist::WriteResp 8166 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7946 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7944 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 534 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
@@ -537,12 +736,12 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 2382988 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 2382986 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total 30670848 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 33053836 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 33053834 # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15892 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15888 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1068 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
@@ -564,14 +763,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio
system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total 2390393 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::total 2390389 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::total 122683392 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total 125073785 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus 125073785 # Total data (bytes)
+system.iobus.tot_pkt_size::total 125073781 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus 125073781 # Total data (bytes)
system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 3978000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy 3977000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 534000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
@@ -617,32 +816,32 @@ system.iobus.reqLayer23.occupancy 8000 # La
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 15335424000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 2374822000 # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy 2374820000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.iobus.respLayer1.occupancy 42038784500 # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy 42037561750 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 1.6 # Layer utilization (%)
system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 3506 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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+system.cpu.dtb.prefetch_faults 192 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.itb.inst_misses 4471 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
@@ -659,79 +858,79 @@ system.cpu.itb.domain_faults 0 # Nu
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.misses 4471 # DTB misses
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -740,174 +939,174 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
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@@ -1011,79 +1210,79 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf
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-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13804.391304 # average LoadLockedReq miss latency
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-system.cpu.dcache.overall_avg_miss_latency::total 25873.058298 # average overall miss latency
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+system.cpu.dcache.tags.sampled_refs 626653 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 37.748863 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 664004250 # Cycle when the warmup percentage was hit.
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+system.cpu.dcache.StoreCondReq_accesses::total 247778 # number of StoreCondReq accesses(hits+misses)
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+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027135 # miss rate for ReadReq accesses
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+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045948 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045948 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.025990 # miss rate for demand accesses
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+system.cpu.dcache.overall_miss_rate::cpu.data 0.025990 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.025990 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14717.418267 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14717.418267 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46459.223221 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 46459.223221 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13909.859464 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13909.859464 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 27561.070372 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 27561.070372 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 27561.070372 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 27561.070372 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -1092,54 +1291,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 595785 # number of writebacks
-system.cpu.dcache.writebacks::total 595785 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368499 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 368499 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250216 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 250216 # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11500 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total 11500 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 618715 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 618715 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 618715 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 618715 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4642816500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 4642816500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10058410735 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 10058410735 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 135673500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 135673500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14701227235 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 14701227235 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14701227235 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 14701227235 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182050836250 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182050836250 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26234094465 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26234094465 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208284930715 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 208284930715 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027167 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027167 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024476 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024476 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046408 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046408 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026010 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.026010 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026010 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.026010 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12599.264856 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12599.264856 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40198.911081 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40198.911081 # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11797.695652 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11797.695652 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23760.903219 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 23760.903219 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23760.903219 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 23760.903219 # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks 595234 # number of writebacks
+system.cpu.dcache.writebacks::total 595234 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368059 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 368059 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250142 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 250142 # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11385 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total 11385 # number of LoadLockedReq MSHR misses
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+system.cpu.dcache.ReadReq_mshr_miss_latency::total 4678465750 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11069177985 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 11069177985 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 135539250 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 135539250 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15747643735 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 15747643735 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15747643735 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 15747643735 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182050613250 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182050613250 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26234152350 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26234152350 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208284765600 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 208284765600 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027135 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027135 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024469 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024469 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.045948 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.045948 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025990 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.025990 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025990 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.025990 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12711.184212 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12711.184212 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44251.577044 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44251.577044 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11905.072464 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11905.072464 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25473.339149 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 25473.339149 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25473.339149 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 25473.339149 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
@@ -1147,37 +1346,37 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput 53011951 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 2455175 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 2455175 # Transaction distribution
+system.cpu.toL2Bus.throughput 52965120 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 2454582 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 2454582 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 763368 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 763368 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 595785 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 2898 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 2898 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 247318 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 247318 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1725171 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5751163 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12463 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27463 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 7516260 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54755700 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 83692841 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14148 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 34900 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 138497589 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 138497589 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 166632 # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy 3009741500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.trans_dist::Writeback 595234 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 2933 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 2933 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 247209 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 247209 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1725138 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5749352 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12460 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27430 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 7514380 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54754804 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 83615077 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14136 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 34840 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total 138418857 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 138418857 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 166312 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 3008581500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 1296026750 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 1295429750 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 2542955300 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 2534385915 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy 8926500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy 8926000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy 18739250 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy 18720500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 0 # number of replacements
system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
@@ -1193,10 +1392,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan #
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1460469685500 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1460469685500 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1460469685500 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1460469685500 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1538389615750 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1538389615750 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1538389615750 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1538389615750 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency