diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-12-23 09:31:20 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-12-23 09:31:20 -0500 |
| commit | df8df4fd0a95763cb0658cbe77615e7deac391d3 (patch) | |
| tree | 0c8776db2ef482a4f6e5db099133105f9af799d7 /tests/quick/fs/10.linux-boot/ref/arm | |
| parent | b2342c5d9aea0b732f6d5a5b6c9c3961940ed8e7 (diff) | |
| download | gem5-df8df4fd0a95763cb0658cbe77615e7deac391d3.tar.xz | |
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes
Changes due to speculative execution of an unaligned PC, introduction
of TLB stats, changes and re-work of the prefetcher, and the
introduction of rank-wise refresh in the DRAM controller.
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm')
10 files changed, 7477 insertions, 6431 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index a51b2d079..def60114c 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.802895 # Nu sim_ticks 2802895103500 # Number of ticks simulated final_tick 2802895103500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 967895 # Simulator instruction rate (inst/s) -host_op_rate 1179365 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 18476638236 # Simulator tick rate (ticks/s) -host_mem_usage 571628 # Number of bytes of host memory used -host_seconds 151.70 # Real time elapsed on the host +host_inst_rate 834307 # Simulator instruction rate (inst/s) +host_op_rate 1016590 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15926512431 # Simulator tick rate (ticks/s) +host_mem_usage 572876 # Number of bytes of host memory used +host_seconds 175.99 # Real time elapsed on the host sim_insts 146829031 # Number of instructions simulated sim_ops 178908942 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -93,6 +93,14 @@ system.cf0.dma_write_full_pages 540 # Nu system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -114,6 +122,24 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.walker.walks 7967 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 7967 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 7967 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 7967 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 7967 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 5082 77.32% 77.32% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1491 22.68% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6573 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7967 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7967 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6573 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6573 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 14540 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses system.cpu0.dtb.read_hits 20339962 # DTB read hits @@ -135,6 +161,14 @@ system.cpu0.dtb.inst_accesses 0 # IT system.cpu0.dtb.hits 36731133 # DTB hits system.cpu0.dtb.misses 7967 # DTB misses system.cpu0.dtb.accesses 36739100 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -156,6 +190,24 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.itb.walker.walks 3358 # Table walker walks requested +system.cpu0.itb.walker.walksShort 3358 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walkWaitTime::samples 3358 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 3358 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 3358 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walksPending::samples 6702500 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 6702500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 6702500 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 2040 87.11% 87.11% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 302 12.89% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2342 # Table walker page sizes translated +system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3358 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3358 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2342 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2342 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 5700 # Table walker requests started/completed, data/inst system.cpu0.itb.inst_hits 97440315 # ITB inst hits system.cpu0.itb.inst_misses 3358 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits @@ -371,15 +423,12 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped +system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size +system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing system.cpu0.l2cache.tags.replacements 252403 # number of replacements system.cpu0.l2cache.tags.tagsinuse 16129.283805 # Cycle average of tags in use system.cpu0.l2cache.tags.total_refs 1810262 # Total number of references to valid blocks. @@ -544,6 +593,14 @@ system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::total 2656528 # Request fanout histogram +system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -565,6 +622,24 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.walker.walks 3358 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 3358 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walkWaitTime::samples 3358 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 3358 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 3358 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walksPending::samples -1804206736 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -1804206736 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -1804206736 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 1919 74.15% 74.15% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 669 25.85% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2588 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3358 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3358 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2588 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2588 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 5946 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses system.cpu1.dtb.read_hits 12173884 # DTB read hits @@ -586,6 +661,14 @@ system.cpu1.dtb.inst_accesses 0 # IT system.cpu1.dtb.hits 19761077 # DTB hits system.cpu1.dtb.misses 3358 # DTB misses system.cpu1.dtb.accesses 19764435 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -607,6 +690,24 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.itb.walker.walks 1734 # Table walker walks requested +system.cpu1.itb.walker.walksShort 1734 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walkWaitTime::samples 1734 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 1734 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 1734 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walksPending::samples -1804209236 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -1804209236 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -1804209236 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 935 85.39% 85.39% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 160 14.61% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 1095 # Table walker page sizes translated +system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1734 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1734 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1095 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1095 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 2829 # Table walker requests started/completed, data/inst system.cpu1.itb.inst_hits 53671431 # ITB inst hits system.cpu1.itb.inst_misses 1734 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits @@ -820,15 +921,12 @@ system.cpu1.icache.avg_blocked_cycles::no_targets nan system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped +system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size +system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing system.cpu1.l2cache.tags.replacements 48598 # number of replacements system.cpu1.l2cache.tags.tagsinuse 15305.342188 # Cycle average of tags in use system.cpu1.l2cache.tags.total_refs 716678 # Total number of references to valid blocks. diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index 5c160a43e..fb9bec115 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.783867 # Nu sim_ticks 2783867165000 # Number of ticks simulated final_tick 2783867165000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1064003 # Simulator instruction rate (inst/s) -host_op_rate 1295252 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 20746494205 # Simulator tick rate (ticks/s) -host_mem_usage 558936 # Number of bytes of host memory used -host_seconds 134.19 # Real time elapsed on the host +host_inst_rate 1374338 # Simulator instruction rate (inst/s) +host_op_rate 1673035 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 26797569978 # Simulator tick rate (ticks/s) +host_mem_usage 615488 # Number of bytes of host memory used +host_seconds 103.89 # Real time elapsed on the host sim_insts 142773109 # Number of instructions simulated sim_ops 173803334 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -70,6 +70,14 @@ system.cf0.dma_write_full_pages 540 # Nu system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -91,6 +99,24 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 10029 # Table walker walks requested +system.cpu.dtb.walker.walksShort 10029 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walkWaitTime::samples 10029 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 10029 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 10029 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 6354 80.79% 80.79% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1511 19.21% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7865 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 10029 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 10029 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7865 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7865 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 17894 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 31526301 # DTB read hits @@ -112,6 +138,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 54650764 # DTB hits system.cpu.dtb.misses 10029 # DTB misses system.cpu.dtb.accesses 54660793 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -133,6 +167,24 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 4762 # Table walker walks requested +system.cpu.itb.walker.walksShort 4762 # Table walker walks initiated with short descriptors +system.cpu.itb.walker.walkWaitTime::samples 4762 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 4762 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 4762 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walksPending::samples 6702500 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 6702500 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 6702500 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 2798 90.05% 90.05% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::1M 309 9.95% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 3107 # Table walker page sizes translated +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 4762 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 4762 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3107 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 3107 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 7869 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 147039592 # ITB inst hits system.cpu.itb.inst_misses 4762 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index ede2b82db..391769400 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,164 +1,160 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.867049 # Number of seconds simulated -sim_ticks 2867048515500 # Number of ticks simulated -final_tick 2867048515500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.868319 # Number of seconds simulated +sim_ticks 2868318696500 # Number of ticks simulated +final_tick 2868318696500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 753572 # Simulator instruction rate (inst/s) -host_op_rate 911512 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 16376301643 # Simulator tick rate (ticks/s) -host_mem_usage 607016 # Number of bytes of host memory used -host_seconds 175.07 # Real time elapsed on the host -sim_insts 131930165 # Number of instructions simulated -sim_ops 159581077 # Number of ops (including micro ops) simulated +host_inst_rate 534652 # Simulator instruction rate (inst/s) +host_op_rate 646675 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 11631340017 # Simulator tick rate (ticks/s) +host_mem_usage 586476 # Number of bytes of host memory used +host_seconds 246.60 # Real time elapsed on the host +sim_insts 131846562 # Number of instructions simulated +sim_ops 159471778 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 233060 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 810048 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 9243456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 53844 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 455584 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 1704320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1173796 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1283584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8628800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 156308 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 605472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 378048 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12502168 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 233060 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 53844 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 286904 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8696768 # Number of bytes written to this memory +system.physmem.bytes_read::total 12227608 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1173796 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 156308 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1330104 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8654400 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8714512 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 8 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 12095 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 13183 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 144429 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 996 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 7142 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 26630 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8672144 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 26794 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 20582 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 134825 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2597 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 9484 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 5907 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 204504 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 135887 # Number of write requests responded to by this memory +system.physmem.num_reads::total 200214 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 135225 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 140323 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 179 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 81289 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 282537 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 3224032 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 89 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 18780 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 158903 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 594451 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 139661 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 156 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 409228 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 447504 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 3008313 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 22 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 54495 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 211090 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 131801 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 335 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4360641 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 81289 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 18780 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 100069 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3033352 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6175 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4262988 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 409228 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 54495 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 463723 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3017238 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6172 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3039541 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3033352 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 179 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 81289 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 288712 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 3224032 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 89 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 18780 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 158917 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 594451 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3023424 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3017238 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 156 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 409228 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 453676 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 3008313 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 22 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 54495 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 211103 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 131801 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 335 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7400182 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 204505 # Number of read requests accepted -system.physmem.writeReqs 176547 # Number of write requests accepted -system.physmem.readBursts 204505 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 176547 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 13079232 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9088 # Total number of bytes read from write queue -system.physmem.bytesWritten 10932800 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12502232 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 11032848 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 142 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 5691 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 15171 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12666 # Per bank write bursts -system.physmem.perBankRdBursts::1 12263 # Per bank write bursts -system.physmem.perBankRdBursts::2 12897 # Per bank write bursts -system.physmem.perBankRdBursts::3 12449 # Per bank write bursts -system.physmem.perBankRdBursts::4 21010 # Per bank write bursts -system.physmem.perBankRdBursts::5 12626 # Per bank write bursts -system.physmem.perBankRdBursts::6 12991 # Per bank write bursts -system.physmem.perBankRdBursts::7 13024 # Per bank write bursts -system.physmem.perBankRdBursts::8 12039 # Per bank write bursts -system.physmem.perBankRdBursts::9 12109 # Per bank write bursts -system.physmem.perBankRdBursts::10 12276 # Per bank write bursts -system.physmem.perBankRdBursts::11 10996 # Per bank write bursts -system.physmem.perBankRdBursts::12 11725 # Per bank write bursts -system.physmem.perBankRdBursts::13 12231 # Per bank write bursts -system.physmem.perBankRdBursts::14 11672 # Per bank write bursts -system.physmem.perBankRdBursts::15 11389 # Per bank write bursts -system.physmem.perBankWrBursts::0 10702 # Per bank write bursts -system.physmem.perBankWrBursts::1 10814 # Per bank write bursts -system.physmem.perBankWrBursts::2 11122 # Per bank write bursts -system.physmem.perBankWrBursts::3 10684 # Per bank write bursts -system.physmem.perBankWrBursts::4 10817 # Per bank write bursts -system.physmem.perBankWrBursts::5 11014 # Per bank write bursts -system.physmem.perBankWrBursts::6 11094 # Per bank write bursts -system.physmem.perBankWrBursts::7 11085 # Per bank write bursts -system.physmem.perBankWrBursts::8 10650 # Per bank write bursts -system.physmem.perBankWrBursts::9 11040 # Per bank write bursts -system.physmem.perBankWrBursts::10 10845 # Per bank write bursts -system.physmem.perBankWrBursts::11 10150 # Per bank write bursts -system.physmem.perBankWrBursts::12 10760 # Per bank write bursts -system.physmem.perBankWrBursts::13 10359 # Per bank write bursts -system.physmem.perBankWrBursts::14 10115 # Per bank write bursts -system.physmem.perBankWrBursts::15 9574 # Per bank write bursts +system.physmem.bw_total::total 7286412 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 200214 # Number of read requests accepted +system.physmem.writeReqs 175885 # Number of write requests accepted +system.physmem.readBursts 200214 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 175885 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12804096 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9600 # Total number of bytes read from write queue +system.physmem.bytesWritten 10892544 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12227608 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10990480 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 150 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 5671 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 13850 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 12188 # Per bank write bursts +system.physmem.perBankRdBursts::1 12046 # Per bank write bursts +system.physmem.perBankRdBursts::2 12591 # Per bank write bursts +system.physmem.perBankRdBursts::3 12330 # Per bank write bursts +system.physmem.perBankRdBursts::4 20750 # Per bank write bursts +system.physmem.perBankRdBursts::5 12582 # Per bank write bursts +system.physmem.perBankRdBursts::6 12043 # Per bank write bursts +system.physmem.perBankRdBursts::7 12246 # Per bank write bursts +system.physmem.perBankRdBursts::8 12442 # Per bank write bursts +system.physmem.perBankRdBursts::9 12402 # Per bank write bursts +system.physmem.perBankRdBursts::10 11722 # Per bank write bursts +system.physmem.perBankRdBursts::11 11146 # Per bank write bursts +system.physmem.perBankRdBursts::12 11467 # Per bank write bursts +system.physmem.perBankRdBursts::13 11916 # Per bank write bursts +system.physmem.perBankRdBursts::14 10852 # Per bank write bursts +system.physmem.perBankRdBursts::15 11341 # Per bank write bursts +system.physmem.perBankWrBursts::0 10835 # Per bank write bursts +system.physmem.perBankWrBursts::1 11264 # Per bank write bursts +system.physmem.perBankWrBursts::2 11493 # Per bank write bursts +system.physmem.perBankWrBursts::3 10899 # Per bank write bursts +system.physmem.perBankWrBursts::4 10487 # Per bank write bursts +system.physmem.perBankWrBursts::5 11152 # Per bank write bursts +system.physmem.perBankWrBursts::6 11024 # Per bank write bursts +system.physmem.perBankWrBursts::7 10595 # Per bank write bursts +system.physmem.perBankWrBursts::8 10782 # Per bank write bursts +system.physmem.perBankWrBursts::9 10958 # Per bank write bursts +system.physmem.perBankWrBursts::10 10716 # Per bank write bursts +system.physmem.perBankWrBursts::11 10408 # Per bank write bursts +system.physmem.perBankWrBursts::12 10444 # Per bank write bursts +system.physmem.perBankWrBursts::13 9906 # Per bank write bursts +system.physmem.perBankWrBursts::14 9416 # Per bank write bursts +system.physmem.perBankWrBursts::15 9817 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2867048141000 # Total gap between requests +system.physmem.numWrRetry 1 # Number of times write queue was full causing retry +system.physmem.totGap 2868318254500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9742 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 194735 # Read request sizes (log2) +system.physmem.readPktSize::6 190444 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4436 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 172111 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 120800 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 21636 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 13302 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 11154 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 9500 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 8185 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 6994 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 6210 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 5370 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 523 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 257 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 166 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 124 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 70 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 45 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 23 # What read queue length does an incoming req see +system.physmem.writePktSize::6 171449 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 138850 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 16077 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 10399 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9072 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7297 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5697 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4782 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4036 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3549 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 129 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 88 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 52 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 20 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -188,178 +184,179 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2981 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4683 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6009 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 8149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 9072 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 10204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 10828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 11783 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 11696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 12526 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 11858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 11537 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 10823 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 10903 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8826 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8488 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 596 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 465 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2909 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4636 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 8259 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 9096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 10239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 10826 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 11796 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 11771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 12530 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 11837 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 11533 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 10810 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 10665 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8741 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8094 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 533 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 391 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 83 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 26 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 83215 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 288.553362 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 159.296581 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 336.078048 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 39267 47.19% 47.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 16171 19.43% 66.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6480 7.79% 74.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3347 4.02% 78.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3132 3.76% 82.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1913 2.30% 84.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1073 1.29% 85.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1034 1.24% 87.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10798 12.98% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 83215 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7042 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 29.019171 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 531.269210 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 7040 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::57 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 90415 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 262.086778 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 144.561031 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 323.181928 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 46335 51.25% 51.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17813 19.70% 70.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6067 6.71% 77.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3600 3.98% 81.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2534 2.80% 84.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1568 1.73% 86.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1031 1.14% 87.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 985 1.09% 88.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 10482 11.59% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 90415 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7120 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.098736 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 516.724228 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 7117 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 2 0.03% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7042 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7042 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 24.258023 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.337274 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 22.786425 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5509 78.23% 78.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 384 5.45% 83.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 77 1.09% 84.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 222 3.15% 87.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 122 1.73% 89.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 57 0.81% 90.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 43 0.61% 91.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 37 0.53% 91.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 124 1.76% 93.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 15 0.21% 93.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 18 0.26% 93.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 16 0.23% 94.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 34 0.48% 94.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 16 0.23% 94.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 7 0.10% 94.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 27 0.38% 95.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 62 0.88% 96.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 11 0.16% 96.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 6 0.09% 96.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 10 0.14% 96.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 88 1.25% 97.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 4 0.06% 97.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 12 0.17% 98.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 6 0.09% 98.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 19 0.27% 98.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 2 0.03% 98.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 11 0.16% 98.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 4 0.06% 98.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 36 0.51% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 11 0.16% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 4 0.06% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 7 0.10% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 5 0.07% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 2 0.03% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.01% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 7 0.10% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 2 0.03% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 4 0.06% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 4 0.06% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.01% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 2 0.03% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.01% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 2 0.03% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 1 0.01% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::204-207 1 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 2 0.03% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-219 1 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 1 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-235 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-251 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::252-255 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7042 # Writes before turning the bus around for reads -system.physmem.totQLat 5974898500 # Total ticks spent queuing -system.physmem.totMemAccLat 9806704750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1021815000 # Total ticks spent in databus transfers -system.physmem.avgQLat 29236.69 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 7120 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7120 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 23.903933 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.122109 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 22.073987 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5764 80.96% 80.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 237 3.33% 84.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 43 0.60% 84.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 234 3.29% 88.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 121 1.70% 89.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 62 0.87% 90.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 31 0.44% 91.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 36 0.51% 91.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 117 1.64% 93.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 18 0.25% 93.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 25 0.35% 93.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 16 0.22% 94.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 40 0.56% 94.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 10 0.14% 94.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 17 0.24% 95.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 28 0.39% 95.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 58 0.81% 96.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 14 0.20% 96.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 7 0.10% 96.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 6 0.08% 96.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 88 1.24% 97.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 4 0.06% 97.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 12 0.17% 98.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.01% 98.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 15 0.21% 98.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 6 0.08% 98.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 14 0.20% 98.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 9 0.13% 98.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 35 0.49% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 6 0.08% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.01% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 4 0.06% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 8 0.11% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 2 0.03% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 3 0.04% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.01% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 8 0.11% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 2 0.03% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.01% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.01% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 4 0.06% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.01% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.01% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 1 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 1 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 1 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 3 0.04% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 3 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7120 # Writes before turning the bus around for reads +system.physmem.totQLat 4855930250 # Total ticks spent queuing +system.physmem.totMemAccLat 8607130250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1000320000 # Total ticks spent in databus transfers +system.physmem.avgQLat 24271.88 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 47986.69 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.56 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.81 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.36 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.85 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 43021.88 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.46 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.80 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.26 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.83 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.07 # Data bus utilization in percentage -system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.06 # Data bus utilization in percentage +system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 2.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.00 # Average write queue length when enqueuing -system.physmem.readRowHits 174382 # Number of row buffer hits during reads -system.physmem.writeRowHits 117590 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.33 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 68.82 # Row buffer hit rate for writes -system.physmem.avgGap 7524033.84 # Average gap between requests -system.physmem.pageHitRate 77.81 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2731090191250 # Time in different power states -system.physmem.memoryStateTime::REF 95736940000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 40221363750 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 330432480 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 298672920 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 180295500 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 162966375 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 857422800 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 736600800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 565911360 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 541034640 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 187261454640 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 187261454640 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 82724898285 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 81530993385 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1647661560750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1648708845750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1919581975815 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1919240568510 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.533155 # Core power per rank (mW) -system.physmem.averagePower::1 669.414075 # Core power per rank (mW) +system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing +system.physmem.avgWrQLen 22.69 # Average write queue length when enqueuing +system.physmem.readRowHits 167229 # Number of row buffer hits during reads +system.physmem.writeRowHits 112615 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.59 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 66.16 # Row buffer hit rate for writes +system.physmem.avgGap 7626497.96 # Average gap between requests +system.physmem.pageHitRate 75.58 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 354707640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 193540875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 832845000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 568613520 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 187344349920 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 84727272375 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1646666587500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1920687916830 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.622475 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2739235632500 # Time in different power states +system.physmem_0.memoryStateTime::REF 95779320000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 33303656000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 328829760 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 179421000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 727646400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 534256560 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 187344349920 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 83962556955 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1647337390500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1920414451095 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.527135 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2740355751000 # Time in different power states +system.physmem_1.memoryStateTime::REF 95779320000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 32179536500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -385,6 +382,14 @@ system.cf0.dma_write_full_pages 540 # Nu system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -406,27 +411,65 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.walker.walks 7749 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 7749 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1459 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6290 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 7749 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 7749 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 7749 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 6355 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 8363.375452 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 7097.000757 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 5454.838397 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 6203 97.61% 97.61% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 142 2.23% 99.84% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 6 0.09% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::81920-98303 3 0.05% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 6355 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 987959000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 987959000 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 987959000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 4935 77.66% 77.66% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1420 22.34% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6355 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7749 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7749 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6355 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6355 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 14104 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 22739909 # DTB read hits -system.cpu0.dtb.read_misses 4142 # DTB read misses -system.cpu0.dtb.write_hits 16676295 # DTB write hits -system.cpu0.dtb.write_misses 677 # DTB write misses +system.cpu0.dtb.read_hits 19044092 # DTB read hits +system.cpu0.dtb.read_misses 6608 # DTB read misses +system.cpu0.dtb.write_hits 15688894 # DTB write hits +system.cpu0.dtb.write_misses 1141 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2392 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 3442 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1346 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 1734 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 187 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 22744051 # DTB read accesses -system.cpu0.dtb.write_accesses 16676972 # DTB write accesses +system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 19050700 # DTB read accesses +system.cpu0.dtb.write_accesses 15690035 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 39416204 # DTB hits -system.cpu0.dtb.misses 4819 # DTB misses -system.cpu0.dtb.accesses 39421023 # DTB accesses +system.cpu0.dtb.hits 34732986 # DTB hits +system.cpu0.dtb.misses 7749 # DTB misses +system.cpu0.dtb.accesses 34740735 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -448,8 +491,40 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 107931670 # ITB inst hits -system.cpu0.itb.inst_misses 2300 # ITB inst misses +system.cpu0.itb.walker.walks 3348 # Table walker walks requested +system.cpu0.itb.walker.walksShort 3348 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 298 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3050 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 3348 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 3348 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 3348 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2332 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 8781.732419 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 7396.194245 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 5559.104899 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 1469 62.99% 62.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 817 35.03% 98.03% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 4 0.17% 98.20% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 39 1.67% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.04% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::106496-114687 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2332 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 987617000 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 987617000 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 987617000 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 2034 87.22% 87.22% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 298 12.78% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2332 # Table walker page sizes translated +system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3348 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3348 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2332 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2332 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 5680 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 91510827 # ITB inst hits +system.cpu0.itb.inst_misses 3348 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -458,178 +533,179 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1397 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2150 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 107933970 # ITB inst accesses -system.cpu0.itb.hits 107931670 # DTB hits -system.cpu0.itb.misses 2300 # DTB misses -system.cpu0.itb.accesses 107933970 # DTB accesses -system.cpu0.numCycles 5733190951 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 91514175 # ITB inst accesses +system.cpu0.itb.hits 91510827 # DTB hits +system.cpu0.itb.misses 3348 # DTB misses +system.cpu0.itb.accesses 91514175 # DTB accesses +system.cpu0.numCycles 5736637393 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 104697045 # Number of instructions committed -system.cpu0.committedOps 126437300 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 112138973 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 4560 # Number of float alu accesses -system.cpu0.num_func_calls 12218983 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 14112779 # number of instructions that are conditional controls -system.cpu0.num_int_insts 112138973 # number of integer instructions -system.cpu0.num_fp_insts 4560 # number of float instructions -system.cpu0.num_int_register_reads 207168140 # number of times the integer registers were read -system.cpu0.num_int_register_writes 78157614 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3646 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 916 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 458862041 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 46623468 # number of times the CC registers were written -system.cpu0.num_mem_refs 40473955 # number of memory refs -system.cpu0.num_load_insts 22968630 # Number of load instructions -system.cpu0.num_store_insts 17505325 # Number of store instructions -system.cpu0.num_idle_cycles 5494072814.437573 # Number of idle cycles -system.cpu0.num_busy_cycles 239118136.562427 # Number of busy cycles -system.cpu0.not_idle_fraction 0.041708 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.958292 # Percentage of idle cycles -system.cpu0.Branches 26957408 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2171 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 89486890 68.80% 68.80% # Class of executed instruction -system.cpu0.op_class::IntMult 99356 0.08% 68.88% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 6997 0.01% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::MemRead 22968630 17.66% 86.54% # Class of executed instruction -system.cpu0.op_class::MemWrite 17505325 13.46% 100.00% # Class of executed instruction +system.cpu0.committedInsts 89363678 # Number of instructions committed +system.cpu0.committedOps 107297883 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 94350928 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 9820 # Number of float alu accesses +system.cpu0.num_func_calls 6606472 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 12627044 # number of instructions that are conditional controls +system.cpu0.num_int_insts 94350928 # number of integer instructions +system.cpu0.num_fp_insts 9820 # number of float instructions +system.cpu0.num_int_register_reads 169124164 # number of times the integer registers were read +system.cpu0.num_int_register_writes 64348180 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 7560 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 385798415 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 43074064 # number of times the CC registers were written +system.cpu0.num_mem_refs 35866705 # number of memory refs +system.cpu0.num_load_insts 19295047 # Number of load instructions +system.cpu0.num_store_insts 16571658 # Number of store instructions +system.cpu0.num_idle_cycles 5512519658.266078 # Number of idle cycles +system.cpu0.num_busy_cycles 224117734.733922 # Number of busy cycles +system.cpu0.not_idle_fraction 0.039068 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.960932 # Percentage of idle cycles +system.cpu0.Branches 19970568 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 73557669 67.15% 67.15% # Class of executed instruction +system.cpu0.op_class::IntMult 108302 0.10% 67.25% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 8177 0.01% 67.26% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction +system.cpu0.op_class::MemRead 19295047 17.61% 84.87% # Class of executed instruction +system.cpu0.op_class::MemWrite 16571658 15.13% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 130069369 # Class of executed instruction +system.cpu0.op_class::total 109543126 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1990 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 555287 # number of replacements -system.cpu0.dcache.tags.tagsinuse 484.900335 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 38705991 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 555652 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 69.658691 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 1015660000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 484.900335 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.947071 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.947071 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 302 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 63 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.712891 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 79342035 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 79342035 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 21654746 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 21654746 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 16040843 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 16040843 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 304713 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 304713 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 334336 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 334336 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 329300 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 329300 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 37695589 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 37695589 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 38000302 # number of overall hits -system.cpu0.dcache.overall_hits::total 38000302 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 304912 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 304912 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 263418 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 263418 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 92252 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 92252 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20070 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 20070 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20705 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 20705 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 568330 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 568330 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 660582 # number of overall misses -system.cpu0.dcache.overall_misses::total 660582 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3916535020 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 3916535020 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4029841681 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 4029841681 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 322461501 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 322461501 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 462579693 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 462579693 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1480500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1480500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 7946376701 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 7946376701 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 7946376701 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 7946376701 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 21959658 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 21959658 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 16304261 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 16304261 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 396965 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 396965 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 354406 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 354406 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 350005 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 350005 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 38263919 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 38263919 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 38660884 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 38660884 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.013885 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.013885 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.016156 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.016156 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.232393 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.232393 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056630 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056630 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.059156 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.059156 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.014853 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.014853 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.017087 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.017087 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12844.804468 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 12844.804468 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15298.277570 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 15298.277570 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16066.841106 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16066.841106 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22341.448587 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22341.448587 # average StoreCondReq miss latency +system.cpu0.kern.inst.quiesce 1879 # number of quiesce instructions executed +system.cpu0.dcache.tags.replacements 690539 # number of replacements +system.cpu0.dcache.tags.tagsinuse 487.185772 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 33864824 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 691051 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 49.004812 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 1015908000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 487.185772 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.951535 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.951535 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 275 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 126 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 70103571 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 70103571 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 17785791 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 17785791 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 14958877 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 14958877 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 318525 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 318525 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 364927 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 364927 # 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number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 327573000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 444426745 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 444426745 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1572500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1572500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 9935203065 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 9935203065 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 9935203065 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 9935203065 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 18180696 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 18180696 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 15283358 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 15283358 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446257 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 446257 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386637 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 386637 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381712 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 381712 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 33464054 # 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average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15088.576693 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22213.562503 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22213.562503 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13981.976494 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 13981.976494 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12029.356993 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 12029.356993 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13810.670579 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 13810.670579 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 11728.239826 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 11728.239826 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -638,82 +714,82 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 420867 # number of writebacks -system.cpu0.dcache.writebacks::total 420867 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 7211 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 7211 # number of ReadReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14132 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14132 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 7211 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 7211 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 7211 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 7211 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 297701 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 297701 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 263418 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 263418 # 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average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12470.556549 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 12470.556549 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14526.860896 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14526.860896 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20306.221058 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20306.221058 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 504116 # number of writebacks +system.cpu0.dcache.writebacks::total 504116 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25128 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 25128 # 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number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4283066685 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1502769500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1502769500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 90797250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 90797250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 403751255 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 403751255 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1480500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1480500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8142123183 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 8142123183 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 9644892683 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 9644892683 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5991645999 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5991645999 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4628507500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4628507500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10620153499 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10620153499 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.020339 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.020339 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.021231 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021231 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225139 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225139 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016713 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016713 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052414 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052414 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.020746 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.020746 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.023436 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.023436 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10436.172336 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10436.172336 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 13199.745702 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 13199.745702 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 14957.395242 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14957.395242 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14050.951718 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14050.951718 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20180.499575 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20180.499575 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 11987.404274 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11987.404274 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 12049.938620 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12049.938620 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 11727.806065 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11727.806065 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 12136.092705 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12136.092705 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -721,58 +797,58 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 945322 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.483250 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 106985827 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 945834 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 113.112689 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 12806917500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.483250 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998991 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998991 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 1099798 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.479276 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 90410508 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1100310 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 82.168214 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 13323414750 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.479276 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998983 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998983 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 390 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 113 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::4 9 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 206 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 215 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 216809183 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 216809183 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 106985827 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 106985827 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 106985827 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 106985827 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 106985827 # number of overall hits -system.cpu0.icache.overall_hits::total 106985827 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 945843 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 945843 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 945843 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 945843 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 945843 # number of overall misses -system.cpu0.icache.overall_misses::total 945843 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 8025066767 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 8025066767 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 8025066767 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 8025066767 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 8025066767 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 8025066767 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 107931670 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 107931670 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 107931670 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 107931670 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 107931670 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 107931670 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.008763 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.008763 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.008763 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.008763 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.008763 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.008763 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8484.565374 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 8484.565374 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8484.565374 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 8484.565374 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8484.565374 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 8484.565374 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 184121973 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 184121973 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 90410508 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 90410508 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 90410508 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 90410508 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 90410508 # number of overall hits +system.cpu0.icache.overall_hits::total 90410508 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1100319 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1100319 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1100319 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1100319 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1100319 # number of overall misses +system.cpu0.icache.overall_misses::total 1100319 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10739818993 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 10739818993 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 10739818993 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 10739818993 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 10739818993 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 10739818993 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 91510827 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 91510827 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 91510827 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 91510827 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 91510827 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 91510827 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.012024 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.012024 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.012024 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.012024 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.012024 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.012024 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9760.641226 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 9760.641226 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9760.641226 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 9760.641226 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9760.641226 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 9760.641226 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -781,356 +857,353 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 945843 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 945843 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 945843 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 945843 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 945843 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 945843 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 6605629733 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 6605629733 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 6605629733 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 6605629733 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 6605629733 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 6605629733 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1100319 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1100319 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 1100319 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1100319 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 1100319 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1100319 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9082830507 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 9082830507 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9082830507 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 9082830507 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9082830507 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 9082830507 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 719096500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 719096500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 719096500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 719096500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.008763 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.008763 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.008763 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.008763 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.008763 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.008763 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 6983.854332 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6983.854332 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6983.854332 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 6983.854332 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6983.854332 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 6983.854332 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.012024 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.012024 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.012024 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.012024 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.012024 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.012024 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8254.724773 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8254.724773 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8254.724773 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 8254.724773 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8254.724773 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 8254.724773 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 8798864 # number of hwpf identified -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 212139 # number of hwpf that were already in mshr -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 8184021 # number of hwpf that were already in the cache -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 360 # number of hwpf that were already in the prefetch queue -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 34 # number of hwpf removed because MSHR allocated -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 402310 # number of hwpf issued -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 695408 # number of hwpf spanning a virtual page -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # 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number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 268426 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16093.899190 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 1968322 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 284663 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 6.914569 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 6744.420736 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 3.207457 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.111326 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 773.977995 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1150.108298 # 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mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.199105 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.089632 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.753173 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.753173 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.920761 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.920761 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.483452 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.483452 # 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mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.181442 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.098416 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.026912 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.032690 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.042852 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.181442 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.337710 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 14777.142857 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 13642.857143 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 38461.796703 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 20786.539028 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 22948.970488 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41504.638547 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 41504.638547 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16022.760491 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16022.760491 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13487.284200 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13487.284200 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 135061.875000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 135061.875000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 25088.846516 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 25088.846516 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 14777.142857 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 13642.857143 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 38461.796703 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 22295.614310 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 23632.150845 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 14777.142857 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 13642.857143 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 38461.796703 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 22295.614310 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41504.638547 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 37234.830640 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.230973 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 15787.209302 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15241.803279 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 39810.184365 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 21210.648570 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 27355.831422 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56455.149661 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 56455.149661 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16861.304032 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16861.304032 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13443.888901 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13443.888901 # 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average ReadReq mshr uncacheable latency @@ -1140,58 +1213,66 @@ system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 1585084 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1436635 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 26190 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 26190 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 420867 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 537670 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 82377 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43315 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 100677 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadReq 1737767 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1686227 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 27891 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 27891 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 504114 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 316054 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 89164 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42476 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 112407 # Transaction distribution system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 43 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 75 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 246727 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 235853 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1909730 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 1979159 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 7030 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 14021 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 3909940 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 60570040 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 70330266 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10652 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 21224 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 130932182 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 972661 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 2913864 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.296127 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.456548 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 81 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 298764 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 285064 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2218682 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2366147 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10130 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 22028 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 4616987 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 70456504 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 84324454 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 14928 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 31956 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 154827842 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 648932 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 2984532 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 5.180419 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.384536 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 2050990 70.39% 70.39% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 862874 29.61% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::5 2446067 81.96% 81.96% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::6 538465 18.04% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 2913864 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 1492069922 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 2984532 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 1775358935 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 116074499 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 115165999 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1430234267 # Layer occupancy (ticks) -system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 995136418 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 1664866493 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer1.occupancy 1209535062 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 4367000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 6398000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 8715750 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 14039749 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1213,27 +1294,67 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.walker.walks 3332 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 3332 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 642 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2690 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 3332 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 3332 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 3332 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 2562 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 8324.355972 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 7260.502547 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 4990.324891 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 2067 80.68% 80.68% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 375 14.64% 95.32% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-24575 62 2.42% 97.74% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-32767 50 1.95% 99.69% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-40959 4 0.16% 99.84% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::40960-49151 3 0.12% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::81920-90111 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 2562 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 1455144968 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1455144968 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 1455144968 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 1928 75.25% 75.25% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 634 24.75% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2562 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3332 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3332 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2562 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2562 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 5894 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 6438534 # DTB read hits -system.cpu1.dtb.read_misses 5066 # DTB read misses -system.cpu1.dtb.write_hits 5578600 # DTB write hits -system.cpu1.dtb.write_misses 983 # DTB write misses +system.cpu1.dtb.read_hits 10115566 # DTB read hits +system.cpu1.dtb.read_misses 2828 # DTB read misses +system.cpu1.dtb.write_hits 6544640 # DTB write hits +system.cpu1.dtb.write_misses 504 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 3048 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 2029 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 541 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 346 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 258 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 6443600 # DTB read accesses -system.cpu1.dtb.write_accesses 5579583 # DTB write accesses +system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 10118394 # DTB read accesses +system.cpu1.dtb.write_accesses 6545144 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 12017134 # DTB hits -system.cpu1.dtb.misses 6049 # DTB misses -system.cpu1.dtb.accesses 12023183 # DTB accesses +system.cpu1.dtb.hits 16660206 # DTB hits +system.cpu1.dtb.misses 3332 # DTB misses +system.cpu1.dtb.accesses 16663538 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1255,8 +1376,42 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 28023624 # ITB inst hits -system.cpu1.itb.inst_misses 2794 # ITB inst misses +system.cpu1.itb.walker.walks 1746 # Table walker walks requested +system.cpu1.itb.walker.walksShort 1746 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 168 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1578 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 1746 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 1746 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 1746 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 1107 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 8955.736224 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 7685.889357 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 5645.921496 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-4095 191 17.25% 17.25% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 643 58.08% 75.34% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 217 19.60% 94.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 1 0.09% 95.03% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-24575 3 0.27% 95.30% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 27 2.44% 97.74% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 19 1.72% 99.46% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::36864-40959 3 0.27% 99.73% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-45055 3 0.27% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 1107 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 1454651968 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1454651968 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 1454651968 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 939 84.82% 84.82% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 168 15.18% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 1107 # Table walker page sizes translated +system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1746 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1746 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1107 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1107 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 2853 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 44359905 # ITB inst hits +system.cpu1.itb.inst_misses 1746 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1265,179 +1420,178 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1901 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1148 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 28026418 # ITB inst accesses -system.cpu1.itb.hits 28023624 # DTB hits -system.cpu1.itb.misses 2794 # DTB misses -system.cpu1.itb.accesses 28026418 # DTB accesses -system.cpu1.numCycles 5734097031 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 44361651 # ITB inst accesses +system.cpu1.itb.hits 44359905 # DTB hits +system.cpu1.itb.misses 1746 # DTB misses +system.cpu1.itb.accesses 44361651 # DTB accesses +system.cpu1.numCycles 5735725430 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 27233120 # Number of instructions committed -system.cpu1.committedOps 33143777 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 29468029 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 6988 # Number of float alu accesses -system.cpu1.num_func_calls 1518648 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3438745 # number of instructions that are conditional controls -system.cpu1.num_int_insts 29468029 # number of integer instructions -system.cpu1.num_fp_insts 6988 # number of float instructions -system.cpu1.num_int_register_reads 53045981 # number of times the integer registers were read -system.cpu1.num_int_register_writes 20334319 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 5190 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1800 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 119969216 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 12226644 # number of times the CC registers were written -system.cpu1.num_mem_refs 12358568 # number of memory refs -system.cpu1.num_load_insts 6575418 # Number of load instructions -system.cpu1.num_store_insts 5783150 # Number of store instructions -system.cpu1.num_idle_cycles 5655719559.150027 # Number of idle cycles -system.cpu1.num_busy_cycles 78377471.849973 # Number of busy cycles -system.cpu1.not_idle_fraction 0.013669 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.986331 # Percentage of idle cycles -system.cpu1.Branches 5151142 # Number of branches fetched -system.cpu1.op_class::No_OpClass 168 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 21257809 63.16% 63.16% # Class of executed instruction -system.cpu1.op_class::IntMult 38403 0.11% 63.27% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 4420 0.01% 63.28% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 63.28% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 63.28% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 63.28% # Class of executed instruction -system.cpu1.op_class::MemRead 6575418 19.54% 82.82% # Class of executed instruction -system.cpu1.op_class::MemWrite 5783150 17.18% 100.00% # Class of executed instruction +system.cpu1.committedInsts 42482884 # Number of instructions committed +system.cpu1.committedOps 52173895 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 47161467 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 1857 # Number of float alu accesses +system.cpu1.num_func_calls 7121857 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 4915281 # number of instructions that are conditional controls +system.cpu1.num_int_insts 47161467 # number of integer instructions +system.cpu1.num_fp_insts 1857 # number of float instructions +system.cpu1.num_int_register_reads 90906541 # number of times the integer registers were read +system.cpu1.num_int_register_writes 34070734 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 1341 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 192636366 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 15749934 # number of times the CC registers were written +system.cpu1.num_mem_refs 16924073 # number of memory refs +system.cpu1.num_load_insts 10229886 # Number of load instructions +system.cpu1.num_store_insts 6694187 # Number of store instructions +system.cpu1.num_idle_cycles 5637554126.704413 # Number of idle cycles +system.cpu1.num_busy_cycles 98171303.295587 # Number of busy cycles +system.cpu1.not_idle_fraction 0.017116 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.982884 # Percentage of idle cycles +system.cpu1.Branches 12116511 # Number of branches fetched +system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 37117349 68.64% 68.64% # Class of executed instruction +system.cpu1.op_class::IntMult 29132 0.05% 68.70% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 3361 0.01% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::MemRead 10229886 18.92% 87.62% # Class of executed instruction +system.cpu1.op_class::MemWrite 6694187 12.38% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 33659368 # Class of executed instruction +system.cpu1.op_class::total 54073981 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2818 # number of quiesce instructions executed -system.cpu1.dcache.tags.replacements 321673 # number of replacements -system.cpu1.dcache.tags.tagsinuse 481.284483 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 11622088 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 322185 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 36.072716 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 104113347000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 481.284483 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.940009 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.940009 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 275 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 119 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 24380907 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 24380907 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 5961630 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 5961630 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 5307193 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 5307193 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 82380 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 82380 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 110885 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 110885 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 104150 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 104150 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 11268823 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 11268823 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 11351203 # number of overall hits -system.cpu1.dcache.overall_hits::total 11351203 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 210202 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 210202 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 138084 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 138084 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 48251 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 48251 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 19527 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 19527 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23870 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23870 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 348286 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 348286 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 396537 # number of overall misses -system.cpu1.dcache.overall_misses::total 396537 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2787267513 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2787267513 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2672172287 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2672172287 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 339794001 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 339794001 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 550321118 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 550321118 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1627000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1627000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 5459439800 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 5459439800 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 5459439800 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 5459439800 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 6171832 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 6171832 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 5445277 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 5445277 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 130631 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 130631 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 130412 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 130412 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 128020 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 128020 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 11617109 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 11617109 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 11747740 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 11747740 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.034058 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.034058 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.025358 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.025358 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.369369 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.369369 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.149733 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.149733 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.186455 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.186455 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029980 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.029980 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.033754 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.033754 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13259.947636 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 13259.947636 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19351.787948 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 19351.787948 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 17401.239361 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 17401.239361 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23054.927440 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23054.927440 # average StoreCondReq miss latency +system.cpu1.kern.inst.quiesce 2789 # number of quiesce instructions executed +system.cpu1.dcache.tags.replacements 191058 # number of replacements +system.cpu1.dcache.tags.tagsinuse 472.360308 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 16390617 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 191421 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 85.626013 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 104654883500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.360308 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.922579 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.922579 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 363 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 312 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 51 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.708984 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 33541448 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 33541448 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 9797337 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 9797337 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 6353174 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 6353174 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49731 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 49731 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 79655 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 79655 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71640 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 71640 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 16150511 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 16150511 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 16200242 # number of overall hits +system.cpu1.dcache.overall_hits::total 16200242 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 137366 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 137366 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 93147 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 93147 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30426 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 30426 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17223 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 17223 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23379 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23379 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 230513 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 230513 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 260939 # number of overall misses +system.cpu1.dcache.overall_misses::total 260939 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1997360003 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1997360003 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2352005341 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 2352005341 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 320800000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 320800000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 539390293 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 539390293 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1691000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1691000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 4349365344 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 4349365344 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 4349365344 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 4349365344 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 9934703 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 9934703 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 6446321 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 6446321 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80157 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 80157 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96878 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 96878 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 95019 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 95019 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 16381024 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 16381024 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 16461181 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 16461181 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.013827 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.013827 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.014450 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.014450 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.379580 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.379580 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.177780 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.177780 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.246046 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.246046 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.014072 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.014072 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.015852 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.015852 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14540.424872 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14540.424872 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25250.467981 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 25250.467981 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18626.255588 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18626.255588 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23071.572480 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23071.572480 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15675.162941 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 15675.162941 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13767.794178 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 13767.794178 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18868.199815 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 18868.199815 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16668.130651 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 16668.130651 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1446,82 +1600,82 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 197265 # number of writebacks -system.cpu1.dcache.writebacks::total 197265 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 459 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 459 # number of ReadReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13505 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13505 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 459 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 459 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 459 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 459 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 209743 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 209743 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 138084 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 138084 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 46648 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 46648 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 6022 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 6022 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23870 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23870 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 347827 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 347827 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 394475 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 394475 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2356483739 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2356483739 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2388185713 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2388185713 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 637646247 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 637646247 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 87580250 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 87580250 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 501268882 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 501268882 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1557000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1557000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4744669452 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4744669452 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5382315699 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 5382315699 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 968585999 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 968585999 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 845308497 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 845308497 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1813894496 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1813894496 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033984 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033984 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025358 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.025358 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.357097 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.357097 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.046177 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.046177 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.186455 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.186455 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029941 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.029941 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033579 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.033579 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11235.100761 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11235.100761 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17295.166080 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17295.166080 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13669.315876 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 13669.315876 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14543.382597 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14543.382597 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 20999.953163 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20999.953163 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 118649 # number of writebacks +system.cpu1.dcache.writebacks::total 118649 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 239 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 239 # number of ReadReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12076 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12076 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 239 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 239 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 239 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 239 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 137127 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 137127 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 93147 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 93147 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29658 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 29658 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5147 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5147 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23379 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23379 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 230274 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 230274 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 259932 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 259932 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1715737747 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1715737747 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2159697659 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2159697659 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 467259500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 467259500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 82226250 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 82226250 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 491497707 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 491497707 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1621000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1621000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3875435406 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3875435406 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4342694906 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4342694906 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 525084500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 525084500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 379956000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 379956000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 905040500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 905040500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.013803 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.013803 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014450 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014450 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.369999 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.369999 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.053129 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.053129 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.246046 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.246046 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.014057 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.014057 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.015791 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.015791 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12512.034443 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12512.034443 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23185.906782 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23185.906782 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15754.922786 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15754.922786 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15975.568292 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15975.568292 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21023.042346 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21023.042346 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13640.888867 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13640.888867 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13644.250457 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13644.250457 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16829.669898 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16829.669898 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16707.042250 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16707.042250 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1529,58 +1683,58 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 680772 # number of replacements -system.cpu1.icache.tags.tagsinuse 498.691095 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 27342334 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 681284 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 40.133533 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 115083689500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.691095 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974006 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.974006 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 526723 # number of replacements +system.cpu1.icache.tags.tagsinuse 498.608741 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 43832665 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 527235 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 83.136865 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 84507534000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.608741 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973845 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.973845 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 221 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 387 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 122 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::4 3 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 56728523 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 56728523 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 27342334 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 27342334 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 27342334 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 27342334 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 27342334 # number of overall hits -system.cpu1.icache.overall_hits::total 27342334 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 681285 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 681285 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 681285 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 681285 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 681285 # number of overall misses -system.cpu1.icache.overall_misses::total 681285 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5656981010 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 5656981010 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 5656981010 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 5656981010 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 5656981010 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 5656981010 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 28023619 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 28023619 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 28023619 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 28023619 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 28023619 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 28023619 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024311 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.024311 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024311 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.024311 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024311 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.024311 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8303.398739 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8303.398739 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8303.398739 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8303.398739 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8303.398739 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8303.398739 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 89247035 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 89247035 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 43832665 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 43832665 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 43832665 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 43832665 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 43832665 # number of overall hits +system.cpu1.icache.overall_hits::total 43832665 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 527235 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 527235 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 527235 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 527235 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 527235 # number of overall misses +system.cpu1.icache.overall_misses::total 527235 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4617960760 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4617960760 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4617960760 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4617960760 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4617960760 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4617960760 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 44359900 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 44359900 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 44359900 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 44359900 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 44359900 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 44359900 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011885 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.011885 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011885 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.011885 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011885 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.011885 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8758.828151 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 8758.828151 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8758.828151 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8758.828151 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8758.828151 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8758.828151 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1589,361 +1743,347 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 681285 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 681285 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 681285 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 681285 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 681285 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 681285 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4634848490 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 4634848490 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4634848490 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 4634848490 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4634848490 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 4634848490 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13880000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 13880000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 13880000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 13880000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024311 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024311 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024311 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.024311 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024311 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.024311 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6803.097808 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6803.097808 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6803.097808 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 6803.097808 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6803.097808 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 6803.097808 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 527235 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 527235 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 527235 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 527235 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 527235 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 527235 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3826248740 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3826248740 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3826248740 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3826248740 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3826248740 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3826248740 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13994500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 13994500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 13994500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 13994500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011885 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011885 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011885 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.011885 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011885 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.011885 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7257.197910 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7257.197910 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7257.197910 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 7257.197910 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7257.197910 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 7257.197910 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 5735095 # number of hwpf identified -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 38649 # number of hwpf that were already in mshr -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 5537320 # number of hwpf that were already in the cache -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 267 # number of hwpf that were already in the prefetch queue -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 19 # number of hwpf removed because MSHR allocated -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 158840 # number of hwpf issued -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 604377 # number of hwpf spanning a virtual page -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.l2cache.tags.replacements 130093 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15612.463834 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1076740 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 146334 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 7.358099 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.num_hwpf_issued 199846 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 199846 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped +system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size +system.cpu1.l2cache.prefetcher.pfSpanPage 59474 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 47689 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15083.724459 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 731618 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 62301 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 11.743279 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 4806.943324 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.120223 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 1.343631 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 874.835505 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 1500.703163 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 8425.517990 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.293393 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000190 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000082 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.053396 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.091596 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.514253 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.952909 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 7913 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 8324 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 47 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 90 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 2030 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 4783 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 963 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 129 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2875 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4662 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 602 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.482971 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000244 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.508057 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 21325891 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 21325891 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 5234 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2693 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 672894 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 186024 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 866845 # 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number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 384250260 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2023461386 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 814752860 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 3230075506 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12590000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 494236499 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 506826499 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 356773500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 356773500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 12590000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 851009999 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 863599999 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.094080 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.137656 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.026747 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.402554 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.119093 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.936708 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.936708 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.949005 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.949005 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.950208 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.950208 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.962911 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.962911 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.336732 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.336732 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.047498 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.074252 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.010576 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.303847 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.113073 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.047498 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.074252 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.010576 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.303847 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.554427 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.554427 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.094080 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.137656 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.026747 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.443434 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.154991 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.094080 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.137656 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.026747 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.443434 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.263175 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15045.980843 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14613.425926 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 25817.836919 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15289.635066 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16190.977194 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27298.605103 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 27298.605103 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15053.474378 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15053.474378 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13783.958363 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13783.958363 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 255400 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 255400 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 24270.038064 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 24270.038064 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15045.980843 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14613.425926 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 25817.836919 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 18155.154600 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 18603.385918 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15045.980843 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14613.425926 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 25817.836919 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 18155.154600 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27298.605103 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23562.702529 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.186269 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 12841.121495 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 12641.304348 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 27247.926535 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 14329.890366 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16489.633445 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33922.593888 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 33922.593888 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14198.385511 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14198.385511 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13595.618508 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13595.618508 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 447000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 447000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 29385.354164 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 29385.354164 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 12841.121495 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 12641.304348 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 27247.926535 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 19396.677396 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 20293.588805 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 12841.121495 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 12641.304348 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27247.926535 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 19396.677396 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33922.593888 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 22582.097681 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1953,69 +2093,69 @@ system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 1351518 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 1008638 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 4998 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 4998 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 197265 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 224398 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 84264 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42890 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 91097 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 45 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 75 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 123576 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 111434 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1362924 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 1150758 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8243 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 16496 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2538421 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 43602948 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 39320783 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11636 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 21980 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 82957347 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 826396 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 2054321 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.357816 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.479358 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 1051189 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 750269 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 3091 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 3091 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 118649 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 33325 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 74679 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41637 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 85827 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 49 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 81 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 85544 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 68027 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1054824 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 784590 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5329 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9434 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 1854177 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 33743748 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25394480 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8020 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 13648 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 59159896 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 572639 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1437265 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 5.343414 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.474848 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 1319253 64.22% 64.22% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 735068 35.78% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::5 943688 65.66% 65.66% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::6 493577 34.34% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 2054321 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 864974439 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 1437265 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 595732734 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 89802999 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 80038500 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 1022245510 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 791497760 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 593726174 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 388635637 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 5334000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 3324000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 11001001 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 6022000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 31015 # Transaction distribution -system.iobus.trans_dist::ReadResp 31015 # Transaction distribution -system.iobus.trans_dist::WriteReq 59437 # Transaction distribution -system.iobus.trans_dist::WriteResp 23213 # Transaction distribution +system.iobus.trans_dist::ReadReq 31024 # Transaction distribution +system.iobus.trans_dist::ReadResp 31024 # Transaction distribution +system.iobus.trans_dist::WriteReq 59440 # Transaction distribution +system.iobus.trans_dist::WriteResp 23216 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56642 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56656 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 844 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -2031,16 +2171,16 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107950 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72954 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72954 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180904 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71586 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107970 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 180928 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71600 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 446 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2056,11 +2196,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162833 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2484089 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 40126000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 162850 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2484122 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 40136000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -2070,7 +2210,7 @@ system.iobus.reqLayer3.occupancy 12000 # La system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 503000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) @@ -2100,52 +2240,52 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 347096127 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 347109131 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 84737000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 84754000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36842563 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36846525 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36459 # number of replacements -system.iocache.tags.tagsinuse 14.453181 # Cycle average of tags in use +system.iocache.tags.replacements 36445 # number of replacements +system.iocache.tags.tagsinuse 14.387294 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36475 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36461 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 277163175000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.453181 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.903324 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.903324 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 287959539000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.387294 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.899206 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.899206 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328293 # Number of tag accesses -system.iocache.tags.data_accesses 328293 # Number of data accesses -system.iocache.ReadReq_misses::realview.ide 253 # number of ReadReq misses -system.iocache.ReadReq_misses::total 253 # number of ReadReq misses +system.iocache.tags.tag_accesses 328311 # Number of tag accesses +system.iocache.tags.data_accesses 328311 # Number of data accesses +system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses +system.iocache.ReadReq_misses::total 255 # number of ReadReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses -system.iocache.demand_misses::realview.ide 253 # number of demand (read+write) misses -system.iocache.demand_misses::total 253 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 253 # number of overall misses -system.iocache.overall_misses::total 253 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 31619377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 31619377 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9617084187 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 9617084187 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 31619377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 31619377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 31619377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 31619377 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 253 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 253 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::realview.ide 255 # number of demand (read+write) misses +system.iocache.demand_misses::total 255 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 255 # number of overall misses +system.iocache.overall_misses::total 255 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 31782377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 31782377 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9599974229 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 9599974229 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ide 31782377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 31782377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 31782377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 31782377 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 253 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 253 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 253 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 253 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 255 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 255 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 255 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 255 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses @@ -2154,40 +2294,40 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 124977.774704 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 124977.774704 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265489.294032 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 265489.294032 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 124977.774704 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 124977.774704 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 124977.774704 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 124977.774704 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 56586 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 124636.772549 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 124636.772549 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265016.956410 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 265016.956410 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 124636.772549 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 124636.772549 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 124636.772549 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 124636.772549 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 55555 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7227 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7160 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.829805 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.759078 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 36206 # number of writebacks -system.iocache.writebacks::total 36206 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 253 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 253 # number of ReadReq MSHR misses +system.iocache.writebacks::writebacks 36190 # number of writebacks +system.iocache.writebacks::total 36190 # number of writebacks +system.iocache.ReadReq_mshr_misses::realview.ide 255 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 253 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 253 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 253 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 253 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 18462377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 18462377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7733310313 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7733310313 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 18462377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 18462377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 18462377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 18462377 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::realview.ide 255 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 255 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 255 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 255 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 18521377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 18521377 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7716276279 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7716276279 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 18521377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 18521377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 18521377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 18521377 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -2196,517 +2336,491 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72973.822134 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 72973.822134 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213485.819153 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213485.819153 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 72973.822134 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 72973.822134 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 72973.822134 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 72973.822134 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72632.850980 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 72632.850980 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213015.577490 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213015.577490 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 72632.850980 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 72632.850980 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 72632.850980 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 72632.850980 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 132552 # number of replacements -system.l2c.tags.tagsinuse 64217.240538 # Cycle average of tags in use -system.l2c.tags.total_refs 486427 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 197317 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.465206 # Average number of references to valid blocks. +system.l2c.tags.replacements 130735 # number of replacements +system.l2c.tags.tagsinuse 63966.604731 # Cycle average of tags in use +system.l2c.tags.total_refs 343053 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 195063 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 1.758678 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 12673.098262 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.830088 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.037001 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 1135.719993 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 1432.608438 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 38719.774998 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.654088 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.007784 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 545.091140 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 913.810052 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 8789.608693 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.193376 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000074 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.017330 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.021860 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.590817 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000040 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.008317 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.013944 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.134119 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.979877 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 45108 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 19652 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 175 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 5031 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 39902 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 175 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 1352 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 18116 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.688293 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.299866 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 6110572 # Number of tag accesses -system.l2c.tags.data_accesses 6110572 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 83 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 80 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 7661 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 21794 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 138574 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 103 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 107 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 6377 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 17292 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 75612 # number of ReadReq hits -system.l2c.ReadReq_hits::total 267683 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 239712 # number of Writeback hits -system.l2c.Writeback_hits::total 239712 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 8881 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 1415 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 10296 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 213 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 148 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 361 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 3683 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 2891 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 6574 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 83 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 80 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 7661 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 25477 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 138574 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 103 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 107 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 6377 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 20183 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 75612 # number of demand (read+write) hits -system.l2c.demand_hits::total 274257 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 83 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 80 # number of overall hits -system.l2c.overall_hits::cpu0.inst 7661 # number of overall hits -system.l2c.overall_hits::cpu0.data 25477 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 138574 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 103 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 107 # number of overall hits -system.l2c.overall_hits::cpu1.inst 6377 # number of overall hits -system.l2c.overall_hits::cpu1.data 20183 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 75612 # number of overall hits -system.l2c.overall_hits::total 274257 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 8 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 3079 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6828 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 144642 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 4 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 831 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1568 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 26632 # number of ReadReq misses -system.l2c.ReadReq_misses::total 183594 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 7063 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 5704 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 12767 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 818 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1393 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 2211 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 6032 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 5664 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 11696 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 8 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 3079 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 12860 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 144642 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 4 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 831 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 7232 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 26632 # number of demand (read+write) misses -system.l2c.demand_misses::total 195290 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 8 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu0.inst 3079 # number of overall misses -system.l2c.overall_misses::cpu0.data 12860 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 144642 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 4 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 831 # number of overall misses -system.l2c.overall_misses::cpu1.data 7232 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 26632 # 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number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 5708264 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 12563466 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 18271730 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 936966 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2313401 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 3250367 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 478723658 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 408222395 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 886946053 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 598250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 75000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 268856499 # 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number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 23063 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 1031 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 1541 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 2572 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 9715 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 8555 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 18270 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 91 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 81 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 10740 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 38337 # 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number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 107 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 108 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 7208 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 27415 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 102244 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 469547 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.087912 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.012346 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.286685 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.238558 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.510713 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.037383 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.009259 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.115289 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.083139 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.260475 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.406832 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.442988 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.801236 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.553571 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.793404 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.903958 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.859642 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.620896 # 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miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.415912 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.087912 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.012346 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.286685 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.335446 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.510713 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.037383 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.009259 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.115289 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.263797 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.260475 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.415912 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 74781.250000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 75000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 87319.421565 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 82510.215290 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 99352.822977 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 74875 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 74500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 91519.252708 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 83887.116709 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 111502.433801 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 100117.622771 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 808.192553 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2202.571178 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 1431.168638 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1145.435208 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1660.732950 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 1470.089100 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 79364.001658 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 72073.162959 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 75833.280865 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 74781.250000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 87319.421565 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 81034.479627 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 99352.822977 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 74875 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 74500 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 91519.252708 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 74634.595409 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 111502.433801 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 98663.223350 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 74781.250000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 87319.421565 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 81034.479627 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 99352.822977 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 74875 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 74500 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 91519.252708 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 74634.595409 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 111502.433801 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 98663.223350 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 6 # number of cycles access was blocked +system.l2c.tags.occ_blocks::writebacks 12083.139597 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.938906 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 1.007553 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 6678.027236 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2760.487108 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 38360.306045 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.955640 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1552.248405 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 535.801693 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1990.692549 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.184374 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000060 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.101899 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.042122 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.585332 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.023685 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.008176 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.030376 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.976053 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 32989 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 31331 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 170 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 4524 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 28295 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 254 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 1895 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 29170 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.503372 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.000122 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.478073 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 4931105 # Number of tag accesses +system.l2c.tags.data_accesses 4931105 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 82 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 63 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 29372 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 45566 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 45492 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 34 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 41 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 11667 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 8537 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 5785 # number of ReadReq hits +system.l2c.ReadReq_hits::total 146639 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 227719 # number of Writeback hits +system.l2c.Writeback_hits::total 227719 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 2362 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 770 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 3132 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 164 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 164 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 328 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 3862 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 1497 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 5359 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 82 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 63 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 29372 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 49428 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 45492 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 34 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 41 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 11667 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 10034 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 5785 # number of demand (read+write) hits +system.l2c.demand_hits::total 151998 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 82 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 63 # number of overall hits +system.l2c.overall_hits::cpu0.inst 29372 # number of overall hits +system.l2c.overall_hits::cpu0.data 49428 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 45492 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 34 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 41 # number of overall hits +system.l2c.overall_hits::cpu1.inst 11667 # number of overall hits +system.l2c.overall_hits::cpu1.data 10034 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 5785 # number of overall hits +system.l2c.overall_hits::total 151998 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 7 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 17779 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 8894 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 134996 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 2435 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 924 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 5907 # number of ReadReq misses +system.l2c.ReadReq_misses::total 170945 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 8889 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 2898 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 11787 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 758 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 1209 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1967 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 11387 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 8562 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 19949 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 7 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 17779 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 20281 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 134996 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 2435 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 9486 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 5907 # number of demand (read+write) misses +system.l2c.demand_misses::total 190894 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 7 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses +system.l2c.overall_misses::cpu0.inst 17779 # number of overall misses +system.l2c.overall_misses::cpu0.data 20281 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 134996 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses +system.l2c.overall_misses::cpu1.inst 2435 # number of overall misses +system.l2c.overall_misses::cpu1.data 9486 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 5907 # 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number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 2108409 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 7531728 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 679977 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 605974 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 1285951 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 888864663 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 627516972 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1516381635 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 494750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 149500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 1299838245 # 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mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.505217 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.556706 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 58392.857143 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 74894.283534 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 70082.930580 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86919.130959 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60504.907194 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 67212.193389 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 84364.293409 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 79081.226233 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 71413.583546 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99256.705231 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 87711.162986 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10136.063146 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10038.865884 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10092.637660 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10162.975550 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10028.996411 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10078.564450 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 66867.098475 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59414.478284 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 63258.032062 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 62343.750000 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62460.730674 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 72782.231853 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 103009.293889 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 81259.023827 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10136.837890 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10036.709800 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10112.219988 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10172.500000 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10004.720430 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10069.375699 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 65540.206815 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 60643.193880 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 63438.436062 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 58392.857143 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74894.283534 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 68574.540280 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86919.130959 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60504.907194 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 66273.437355 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 84364.293409 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 79081.226233 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62016.054204 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99256.705231 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 86246.639722 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 62343.750000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62460.730674 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61824.462414 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 103009.293889 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 79396.679517 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 58392.857143 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74894.283534 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 68574.540280 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86919.130959 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60504.907194 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 66273.437355 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 84364.293409 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 79081.226233 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62016.054204 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99256.705231 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 86246.639722 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62460.730674 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61824.462414 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 103009.293889 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 79396.679517 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -2721,58 +2835,58 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 228161 # Transaction distribution -system.membus.trans_dist::ReadResp 228160 # Transaction distribution -system.membus.trans_dist::WriteReq 31188 # Transaction distribution -system.membus.trans_dist::WriteResp 31188 # Transaction distribution -system.membus.trans_dist::Writeback 135887 # Transaction distribution +system.membus.trans_dist::ReadReq 215303 # Transaction distribution +system.membus.trans_dist::ReadResp 215303 # Transaction distribution +system.membus.trans_dist::WriteReq 30982 # Transaction distribution +system.membus.trans_dist::WriteResp 30982 # Transaction distribution +system.membus.trans_dist::Writeback 135225 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 85485 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 41282 # Transaction distribution -system.membus.trans_dist::UpgradeResp 15173 # Transaction distribution +system.membus.trans_dist::UpgradeReq 76008 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40410 # Transaction distribution +system.membus.trans_dist::UpgradeResp 13867 # Transaction distribution system.membus.trans_dist::SCUpgradeFailReq 5 # Transaction distribution -system.membus.trans_dist::ReadExReq 28446 # Transaction distribution -system.membus.trans_dist::ReadExResp 11501 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107950 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 40350 # Transaction distribution +system.membus.trans_dist::ReadExResp 19836 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107970 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14612 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 676793 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 799389 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108922 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108922 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 908311 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162833 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13762 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 659440 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 781206 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108908 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108908 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 890114 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162850 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 29224 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18898536 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 19090661 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4636480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 4636480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 23727141 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 129157 # Total snoops (count) -system.membus.snoop_fanout::samples 511174 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27524 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18582632 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18773074 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 23408530 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 123675 # Total snoops (count) +system.membus.snoop_fanout::samples 499419 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 511174 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 499419 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 511174 # Request fanout histogram -system.membus.reqLayer0.occupancy 88144997 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 499419 # Request fanout histogram +system.membus.reqLayer0.occupancy 88165000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 18500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 12118496 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11453500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1838586997 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1828859499 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 1967573382 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1931425684 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38564437 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 38544475 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2805,44 +2919,44 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 630354 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 630338 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 31188 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 31188 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 239712 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 95586 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 41643 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 137229 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 75 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 75 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 39856 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 39856 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1145062 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 504022 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1649084 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 33792786 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 11864019 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 45656805 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 304478 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 1039135 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.035103 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.184041 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 482729 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 482714 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30982 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30982 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 227719 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 79027 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 40738 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 119765 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 81 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 81 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 51496 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 51496 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1065854 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 282098 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1347952 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 31837086 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4944756 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 36781842 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 286323 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 873908 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.041744 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.200003 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 1002658 96.49% 96.49% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 36477 3.51% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 837428 95.83% 95.83% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 36480 4.17% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 1039135 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1515175521 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 873908 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 1446151615 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 1071000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 1080000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1922628953 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1735034184 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1047459467 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 618323353 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 5265a0ac0..b3648bdab 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.902845 # Number of seconds simulated -sim_ticks 2902845442000 # Number of ticks simulated -final_tick 2902845442000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.902862 # Number of seconds simulated +sim_ticks 2902861767000 # Number of ticks simulated +final_tick 2902861767000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 666753 # Simulator instruction rate (inst/s) -host_op_rate 803907 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 17201244826 # Simulator tick rate (ticks/s) -host_mem_usage 558784 # Number of bytes of host memory used -host_seconds 168.76 # Real time elapsed on the host -sim_insts 112519801 # Number of instructions simulated -sim_ops 135665611 # Number of ops (including micro ops) simulated +host_inst_rate 747193 # Simulator instruction rate (inst/s) +host_op_rate 900893 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 19275657141 # Simulator tick rate (ticks/s) +host_mem_usage 615228 # Number of bytes of host memory used +host_seconds 150.60 # Real time elapsed on the host +sim_insts 112525269 # Number of instructions simulated +sim_ops 135672104 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1190500 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1191332 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 8985828 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10177864 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1190500 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1190500 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7575744 # Number of bytes written to this memory +system.physmem.bytes_read::total 10178696 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1191332 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1191332 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7576000 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 7593268 # Number of bytes written to this memory +system.physmem.bytes_written::total 7593524 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 27055 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 27068 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 140923 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 168002 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 118371 # Number of write requests responded to by this memory +system.physmem.num_reads::total 168015 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 118375 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122752 # Number of write requests responded to by this memory +system.physmem.num_writes::total 122756 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 154 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 44 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 410115 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3095524 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 410399 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3095507 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 331 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3506168 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 410115 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 410115 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2609765 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3506435 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 410399 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 410399 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2609838 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6037 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2615802 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2609765 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2615875 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2609838 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 44 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 410115 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3101561 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 410399 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3101543 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 331 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6121970 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 168002 # Number of read requests accepted -system.physmem.writeReqs 158976 # Number of write requests accepted -system.physmem.readBursts 168002 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 158976 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10744064 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8064 # Total number of bytes read from write queue -system.physmem.bytesWritten 9803776 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10177864 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 9911604 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 126 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 5765 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4503 # Number of requests that are neither read nor write +system.physmem.bw_total::total 6122310 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 168015 # Number of read requests accepted +system.physmem.writeReqs 158980 # Number of write requests accepted +system.physmem.readBursts 168015 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 158980 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10745280 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7680 # Total number of bytes read from write queue +system.physmem.bytesWritten 9814400 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10178696 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 9911860 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 120 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 5603 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4500 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 9689 # Per bank write bursts -system.physmem.perBankRdBursts::1 9233 # Per bank write bursts -system.physmem.perBankRdBursts::2 10196 # Per bank write bursts -system.physmem.perBankRdBursts::3 10261 # Per bank write bursts +system.physmem.perBankRdBursts::1 9230 # Per bank write bursts +system.physmem.perBankRdBursts::2 10198 # Per bank write bursts +system.physmem.perBankRdBursts::3 10267 # Per bank write bursts system.physmem.perBankRdBursts::4 18984 # Per bank write bursts -system.physmem.perBankRdBursts::5 10217 # Per bank write bursts -system.physmem.perBankRdBursts::6 10550 # Per bank write bursts -system.physmem.perBankRdBursts::7 10349 # Per bank write bursts -system.physmem.perBankRdBursts::8 9691 # Per bank write bursts +system.physmem.perBankRdBursts::5 10226 # Per bank write bursts +system.physmem.perBankRdBursts::6 10551 # Per bank write bursts +system.physmem.perBankRdBursts::7 10350 # Per bank write bursts +system.physmem.perBankRdBursts::8 9702 # Per bank write bursts system.physmem.perBankRdBursts::9 9930 # Per bank write bursts -system.physmem.perBankRdBursts::10 9906 # Per bank write bursts -system.physmem.perBankRdBursts::11 8846 # Per bank write bursts -system.physmem.perBankRdBursts::12 9937 # Per bank write bursts -system.physmem.perBankRdBursts::13 10409 # Per bank write bursts -system.physmem.perBankRdBursts::14 9928 # Per bank write bursts +system.physmem.perBankRdBursts::10 9908 # Per bank write bursts +system.physmem.perBankRdBursts::11 8848 # Per bank write bursts +system.physmem.perBankRdBursts::12 9929 # Per bank write bursts +system.physmem.perBankRdBursts::13 10408 # Per bank write bursts +system.physmem.perBankRdBursts::14 9925 # Per bank write bursts system.physmem.perBankRdBursts::15 9750 # Per bank write bursts -system.physmem.perBankWrBursts::0 9383 # Per bank write bursts -system.physmem.perBankWrBursts::1 8873 # Per bank write bursts -system.physmem.perBankWrBursts::2 10202 # Per bank write bursts -system.physmem.perBankWrBursts::3 10003 # Per bank write bursts -system.physmem.perBankWrBursts::4 9293 # Per bank write bursts -system.physmem.perBankWrBursts::5 9372 # Per bank write bursts -system.physmem.perBankWrBursts::6 9902 # Per bank write bursts -system.physmem.perBankWrBursts::7 9747 # Per bank write bursts -system.physmem.perBankWrBursts::8 9662 # Per bank write bursts -system.physmem.perBankWrBursts::9 9936 # Per bank write bursts -system.physmem.perBankWrBursts::10 9764 # Per bank write bursts -system.physmem.perBankWrBursts::11 9057 # Per bank write bursts -system.physmem.perBankWrBursts::12 9756 # Per bank write bursts -system.physmem.perBankWrBursts::13 9847 # Per bank write bursts -system.physmem.perBankWrBursts::14 9332 # Per bank write bursts -system.physmem.perBankWrBursts::15 9055 # Per bank write bursts +system.physmem.perBankWrBursts::0 9389 # Per bank write bursts +system.physmem.perBankWrBursts::1 8975 # Per bank write bursts +system.physmem.perBankWrBursts::2 10251 # Per bank write bursts +system.physmem.perBankWrBursts::3 9953 # Per bank write bursts +system.physmem.perBankWrBursts::4 9418 # Per bank write bursts +system.physmem.perBankWrBursts::5 9499 # Per bank write bursts +system.physmem.perBankWrBursts::6 9770 # Per bank write bursts +system.physmem.perBankWrBursts::7 9764 # Per bank write bursts +system.physmem.perBankWrBursts::8 9682 # Per bank write bursts +system.physmem.perBankWrBursts::9 9836 # Per bank write bursts +system.physmem.perBankWrBursts::10 9791 # Per bank write bursts +system.physmem.perBankWrBursts::11 9091 # Per bank write bursts +system.physmem.perBankWrBursts::12 9681 # Per bank write bursts +system.physmem.perBankWrBursts::13 9852 # Per bank write bursts +system.physmem.perBankWrBursts::14 9372 # Per bank write bursts +system.physmem.perBankWrBursts::15 9026 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2902845065500 # Total gap between requests +system.physmem.totGap 2902861390500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9558 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 158430 # Read request sizes (log2) +system.physmem.readPktSize::6 158443 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 154595 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 167074 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 546 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 244 # What read queue length does an incoming req see +system.physmem.writePktSize::6 154599 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 167093 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 544 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 246 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -159,114 +159,135 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4010 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 7794 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 8553 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 8920 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 9728 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 10123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 10886 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 10725 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 11224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10377 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9848 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6857 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6734 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6646 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 405 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 375 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4056 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 7902 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 8734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 8985 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 9766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 10233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 10902 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 10695 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 11219 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 10360 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9893 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8867 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8350 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6866 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6660 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 386 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 329 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 285 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 60629 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 338.910027 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 195.312314 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 353.501529 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 21458 35.39% 35.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14532 23.97% 59.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5550 9.15% 68.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3471 5.72% 74.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2318 3.82% 78.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1576 2.60% 80.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1018 1.68% 82.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1077 1.78% 84.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9629 15.88% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 60629 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6199 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 27.078561 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 543.579220 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6197 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 60962 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 337.252977 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 194.461800 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 352.629111 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 21587 35.41% 35.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14795 24.27% 59.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5550 9.10% 68.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3419 5.61% 74.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2349 3.85% 78.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1576 2.59% 80.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1011 1.66% 82.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1092 1.79% 84.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9583 15.72% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 60962 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6214 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 27.016254 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 542.923852 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6212 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6199 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6199 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 24.711082 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.355367 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 23.633562 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 5127 82.71% 82.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 245 3.95% 86.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 162 2.61% 89.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 57 0.92% 90.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 142 2.29% 92.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 31 0.50% 92.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 44 0.71% 93.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 53 0.85% 94.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 77 1.24% 95.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 20 0.32% 96.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 101 1.63% 97.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 12 0.19% 97.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 30 0.48% 98.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 13 0.21% 98.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 38 0.61% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 11 0.18% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 15 0.24% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 2 0.03% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 3 0.05% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 2 0.03% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 3 0.05% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 2 0.03% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 1 0.02% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 2 0.03% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 2 0.03% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 3 0.05% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-279 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6199 # Writes before turning the bus around for reads -system.physmem.totQLat 1496514000 # Total ticks spent queuing -system.physmem.totMemAccLat 4644189000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 839380000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8914.40 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6214 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6214 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 24.678146 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.366342 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 23.738225 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5089 81.90% 81.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 32 0.51% 82.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 24 0.39% 82.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 212 3.41% 86.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 128 2.06% 88.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 65 1.05% 89.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 41 0.66% 89.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 30 0.48% 90.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 138 2.22% 92.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 16 0.26% 92.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 13 0.21% 93.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 16 0.26% 93.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 29 0.47% 93.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 17 0.27% 94.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 11 0.18% 94.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 29 0.47% 94.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 66 1.06% 95.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 8 0.13% 95.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 3 0.05% 96.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 17 0.27% 96.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 91 1.46% 97.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.02% 97.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 15 0.24% 98.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.03% 98.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 8 0.13% 98.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 6 0.10% 98.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 11 0.18% 98.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 98.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 39 0.63% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 7 0.11% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 2 0.03% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 4 0.06% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 9 0.14% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 3 0.05% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.02% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 5 0.08% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 2 0.03% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 3 0.05% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 5 0.08% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.02% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 3 0.05% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 1 0.02% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 1 0.02% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::220-223 4 0.06% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 2 0.03% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-235 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::252-255 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6214 # Writes before turning the bus around for reads +system.physmem.totQLat 1487834250 # Total ticks spent queuing +system.physmem.totMemAccLat 4635865500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 839475000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8861.69 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27664.40 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 27611.69 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.70 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.38 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.51 # Average system read bandwidth in MiByte/s @@ -276,36 +297,41 @@ system.physmem.busUtil 0.06 # Da system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 27.52 # Average write queue length when enqueuing -system.physmem.readRowHits 138272 # Number of row buffer hits during reads -system.physmem.writeRowHits 122158 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.37 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.73 # Row buffer hit rate for writes -system.physmem.avgGap 8877799.32 # Average gap between requests -system.physmem.pageHitRate 81.11 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2755332461750 # Time in different power states -system.physmem.memoryStateTime::REF 96932160000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 50580729750 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 234216360 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 224138880 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 127796625 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 122298000 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 697936200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 611488800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 497502000 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 495130320 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 189599304960 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 189599304960 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 86744243025 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 85632450615 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1665611854500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1666587111000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1943512853670 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1943271922575 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.521448 # Core power per rank (mW) -system.physmem.averagePower::1 669.438449 # Core power per rank (mW) +system.physmem.avgWrQLen 25.07 # Average write queue length when enqueuing +system.physmem.readRowHits 138089 # Number of row buffer hits during reads +system.physmem.writeRowHits 122193 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.25 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 79.67 # Row buffer hit rate for writes +system.physmem.avgGap 8877387.70 # Average gap between requests +system.physmem.pageHitRate 81.02 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 235320120 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 128398875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 698061000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 499083120 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 189600322080 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 86740865775 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1665624160500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1943526211470 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.522458 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2770750790000 # Time in different power states +system.physmem_0.memoryStateTime::REF 96932680000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 35170942500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 225552600 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 123069375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 611512200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 494624880 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 189600322080 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 85548905145 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1666669740000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1943273726280 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.435479 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2772511956000 # Time in different power states +system.physmem_1.memoryStateTime::REF 96932680000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 33417040500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -325,6 +351,14 @@ system.cf0.dma_write_full_pages 540 # Nu system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -346,11 +380,41 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 9552 # Table walker walks requested +system.cpu.dtb.walker.walksShort 9552 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1261 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8291 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 9552 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 9552 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 9552 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 7388 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 9945.756632 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 7345.780525 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 7322.338006 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-16383 5745 77.76% 77.76% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::16384-32767 1639 22.18% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-81919 2 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::147456-163839 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 7388 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 809108000 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 809108000 100.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 809108000 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 6174 83.57% 83.57% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1214 16.43% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7388 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9552 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9552 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7388 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7388 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 16940 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 24536392 # DTB read hits -system.cpu.dtb.read_misses 8144 # DTB read misses -system.cpu.dtb.write_hits 19617454 # DTB write hits +system.cpu.dtb.read_hits 24537663 # DTB read hits +system.cpu.dtb.read_misses 8142 # DTB read misses +system.cpu.dtb.write_hits 19618927 # DTB write hits system.cpu.dtb.write_misses 1410 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -358,15 +422,23 @@ system.cpu.dtb.flush_tlb_mva_asid 0 # Nu system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_entries 4273 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 1630 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 1664 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 24544536 # DTB read accesses -system.cpu.dtb.write_accesses 19618864 # DTB write accesses +system.cpu.dtb.read_accesses 24545805 # DTB read accesses +system.cpu.dtb.write_accesses 19620337 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 44153846 # DTB hits -system.cpu.dtb.misses 9554 # DTB misses -system.cpu.dtb.accesses 44163400 # DTB accesses +system.cpu.dtb.hits 44156590 # DTB hits +system.cpu.dtb.misses 9552 # DTB misses +system.cpu.dtb.accesses 44166142 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -388,7 +460,37 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 115618887 # ITB inst hits +system.cpu.itb.walker.walks 4762 # Table walker walks requested +system.cpu.itb.walker.walksShort 4762 # Table walker walks initiated with short descriptors +system.cpu.itb.walker.walksShortTerminationLevel::Level1 309 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksShortTerminationLevel::Level2 4453 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 4762 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 4762 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 4762 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 3107 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 9893.949147 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 7210.941913 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 7351.443657 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-8191 1400 45.06% 45.06% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::8192-16383 1004 32.31% 77.37% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-24575 701 22.56% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::73728-81919 1 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::81920-90111 1 0.03% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 3107 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 808810000 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 808810000 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 808810000 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 2798 90.05% 90.05% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::1M 309 9.95% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 3107 # Table walker page sizes translated +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 4762 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 4762 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3107 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 3107 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 7869 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 115624412 # ITB inst hits system.cpu.itb.inst_misses 4762 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -405,38 +507,38 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 115623649 # ITB inst accesses -system.cpu.itb.hits 115618887 # DTB hits +system.cpu.itb.inst_accesses 115629174 # ITB inst accesses +system.cpu.itb.hits 115624412 # DTB hits system.cpu.itb.misses 4762 # DTB misses -system.cpu.itb.accesses 115623649 # DTB accesses -system.cpu.numCycles 5805690884 # number of cpu cycles simulated +system.cpu.itb.accesses 115629174 # DTB accesses +system.cpu.numCycles 5805723534 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 112519801 # Number of instructions committed -system.cpu.committedOps 135665611 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 119963928 # Number of integer alu accesses +system.cpu.committedInsts 112525269 # Number of instructions committed +system.cpu.committedOps 135672104 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 119969678 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 11290 # Number of float alu accesses -system.cpu.num_func_calls 9899743 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 15237612 # number of instructions that are conditional controls -system.cpu.num_int_insts 119963928 # number of integer instructions +system.cpu.num_func_calls 9899985 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 15238216 # number of instructions that are conditional controls +system.cpu.num_int_insts 119969678 # number of integer instructions system.cpu.num_fp_insts 11290 # number of float instructions -system.cpu.num_int_register_reads 218192496 # number of times the integer registers were read -system.cpu.num_int_register_writes 82697523 # number of times the integer registers were written +system.cpu.num_int_register_reads 218203287 # number of times the integer registers were read +system.cpu.num_int_register_writes 82701548 # number of times the integer registers were written system.cpu.num_fp_register_reads 8578 # number of times the floating registers were read system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written -system.cpu.num_cc_register_reads 490031044 # number of times the CC registers were read -system.cpu.num_cc_register_writes 51919223 # number of times the CC registers were written -system.cpu.num_mem_refs 45435185 # number of memory refs -system.cpu.num_load_insts 24859277 # Number of load instructions -system.cpu.num_store_insts 20575908 # Number of store instructions -system.cpu.num_idle_cycles 5386811452.570145 # Number of idle cycles -system.cpu.num_busy_cycles 418879431.429856 # Number of busy cycles -system.cpu.not_idle_fraction 0.072150 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.927850 # Percentage of idle cycles -system.cpu.Branches 25931479 # Number of branches fetched +system.cpu.num_cc_register_reads 490054820 # number of times the CC registers were read +system.cpu.num_cc_register_writes 51921339 # number of times the CC registers were written +system.cpu.num_mem_refs 45438019 # number of memory refs +system.cpu.num_load_insts 24860597 # Number of load instructions +system.cpu.num_store_insts 20577422 # Number of store instructions +system.cpu.num_idle_cycles 5386825418.146145 # Number of idle cycles +system.cpu.num_busy_cycles 418898115.853856 # Number of busy cycles +system.cpu.not_idle_fraction 0.072153 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.927847 # Percentage of idle cycles +system.cpu.Branches 25932360 # Number of branches fetched system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 93227451 67.17% 67.17% # Class of executed instruction -system.cpu.op_class::IntMult 114534 0.08% 67.26% # Class of executed instruction +system.cpu.op_class::IntAlu 93231199 67.17% 67.17% # Class of executed instruction +system.cpu.op_class::IntMult 114517 0.08% 67.26% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 67.26% # Class of executed instruction @@ -460,24 +562,24 @@ system.cpu.op_class::SimdFloatAlu 0 0.00% 67.26% # Cl system.cpu.op_class::SimdFloatCmp 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatCvt 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatDiv 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 8511 0.01% 67.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 8515 0.01% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::MemRead 24859277 17.91% 85.17% # Class of executed instruction -system.cpu.op_class::MemWrite 20575908 14.83% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 24860597 17.91% 85.17% # Class of executed instruction +system.cpu.op_class::MemWrite 20577422 14.83% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 138788018 # Class of executed instruction +system.cpu.op_class::total 138794587 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 3037 # number of quiesce instructions executed -system.cpu.dcache.tags.replacements 823273 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.850546 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 43258722 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 823785 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 52.512151 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 823321 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.850573 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 43261398 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 823833 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 52.512339 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 876905250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.850546 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.850573 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999708 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999708 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -486,168 +588,168 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 368 system.cpu.dcache.tags.age_task_id_blocks_1024::2 82 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 177222055 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 177222055 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23125535 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23125535 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18834160 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18834160 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 392158 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 392158 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 443620 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 443620 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460509 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460509 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41959695 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41959695 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42351853 # number of overall hits -system.cpu.dcache.overall_hits::total 42351853 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 402606 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 402606 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 299098 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 299098 # number of WriteReq misses +system.cpu.dcache.tags.tag_accesses 177233078 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 177233078 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23126684 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23126684 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18835651 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18835651 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 392122 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 392122 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 443636 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 443636 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460570 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460570 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 41962335 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41962335 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42354457 # number of overall hits +system.cpu.dcache.overall_hits::total 42354457 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 402703 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 402703 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 299019 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 299019 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 119172 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 119172 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 22698 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22698 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22743 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22743 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 701704 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 701704 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 820876 # number of overall misses -system.cpu.dcache.overall_misses::total 820876 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5915644250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5915644250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 11659723253 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 11659723253 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 280150250 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 280150250 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 701722 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 701722 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 820894 # number of overall misses +system.cpu.dcache.overall_misses::total 820894 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5916458250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5916458250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 11650381750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 11650381750 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 280295250 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 280295250 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 150000 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 150000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 17575367503 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17575367503 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 17575367503 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17575367503 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23528141 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23528141 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19133258 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19133258 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 511330 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 511330 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466318 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 466318 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 460511 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 460511 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42661399 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42661399 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 43172729 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 43172729 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017112 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.017112 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015632 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.015632 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.233063 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.233063 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048675 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048675 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_latency::cpu.data 17566840000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17566840000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 17566840000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17566840000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23529387 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23529387 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19134670 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19134670 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 511294 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 511294 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466379 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 466379 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 460572 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 460572 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 42664057 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42664057 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 43175351 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 43175351 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017115 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.017115 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015627 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.015627 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.233079 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.233079 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048765 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048765 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.016448 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.016448 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.019014 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.019014 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14693.383233 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14693.383233 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38982.952922 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38982.952922 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12342.508150 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12342.508150 # average LoadLockedReq miss latency +system.cpu.dcache.overall_miss_rate::cpu.data 0.019013 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.019013 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14691.865345 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14691.865345 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38962.011611 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38962.011611 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12324.462472 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12324.462472 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 75000 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 75000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 25046.697045 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 25046.697045 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 21410.502321 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 21410.502321 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 58 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 25033.902315 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 25033.902315 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 21399.644778 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 21399.644778 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 78 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 33 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 34 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 1.757576 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.294118 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 686473 # number of writebacks -system.cpu.dcache.writebacks::total 686473 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 636 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 636 # number of ReadReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14226 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 14226 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 636 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 636 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 636 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 636 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 401970 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 401970 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299098 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 299098 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 686487 # number of writebacks +system.cpu.dcache.writebacks::total 686487 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 629 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 629 # number of ReadReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14254 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 14254 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 629 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 629 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 629 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 629 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 402074 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 402074 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299019 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 299019 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 117021 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 117021 # number of SoftPFReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8472 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 8472 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8489 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 8489 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 701068 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 701068 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 818089 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 818089 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5096620250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5096620250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11004051747 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11004051747 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1414370750 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1414370750 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 99646250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 99646250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 701093 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 701093 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 818114 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 818114 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5098164750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5098164750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10994871250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10994871250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1411142000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1411142000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 100012000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 100012000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 146000 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 146000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16100671997 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16100671997 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17515042747 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 17515042747 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5791399500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5791399500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4429678500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4429678500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10221078000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 10221078000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017085 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017085 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015632 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015632 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228856 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228856 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018168 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018168 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16093036000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16093036000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17504178000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 17504178000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5791398250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5791398250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4429682000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4429682000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10221080250 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 10221080250 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017088 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017088 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015627 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015627 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228872 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228872 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018202 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018202 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016433 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.016433 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018949 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.018949 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12679.106028 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12679.106028 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36790.790132 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36790.790132 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12086.469523 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12086.469523 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11761.833097 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11761.833097 # average LoadLockedReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12679.667797 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12679.667797 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36769.808106 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36769.808106 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12058.878321 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12058.878321 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11781.364118 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11781.364118 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 73000 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 73000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22965.920563 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22965.920563 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21409.703280 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 21409.703280 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22954.210069 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22954.210069 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21395.768805 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 21395.768805 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -655,13 +757,13 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 1700967 # number of replacements -system.cpu.icache.tags.tagsinuse 510.782035 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 113917402 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1701479 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 66.951988 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 1701491 # number of replacements +system.cpu.icache.tags.tagsinuse 510.782044 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 113922403 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1702003 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 66.934314 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 25181626250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.782035 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 510.782044 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.997621 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.997621 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -670,44 +772,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 195 system.cpu.icache.tags.age_task_id_blocks_1024::2 264 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 117320372 # Number of tag accesses -system.cpu.icache.tags.data_accesses 117320372 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 113917402 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 113917402 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 113917402 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 113917402 # 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number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 474215000 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5385925500 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5860140500 # number of ReadReq MSHR uncacheable cycles @@ -966,48 +1068,48 @@ system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4098165500 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 474215000 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9484091000 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9958306000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001003 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001001 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000546 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010603 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.023113 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013503 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991600 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991600 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010607 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.023103 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013504 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991584 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991584 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.439466 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.439466 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001003 # mshr miss rate for demand accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.439589 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.439589 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001001 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000546 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010603 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172890 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.063283 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001003 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010607 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172883 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.063274 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001001 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000546 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010603 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172890 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.063283 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 66714.285714 # average ReadReq mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010607 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172883 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.063274 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 58392.857143 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60265.451774 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63809.880240 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61695.998677 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10058.458564 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10058.458564 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60392.787902 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63605.607515 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61687.002083 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10067.420664 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10067.420664 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 60000 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 60000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56459.475107 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56459.475107 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 66714.285714 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56394.202727 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56394.202727 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 58392.857143 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60265.451774 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57088.613350 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57446.217834 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 66714.285714 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60392.787902 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57011.333680 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57391.819309 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 58392.857143 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60265.451774 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57088.613350 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57446.217834 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60392.787902 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57011.333680 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57391.819309 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1017,54 +1119,54 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2296418 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2296403 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2297061 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2297046 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27618 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27618 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 686473 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 686487 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2738 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2733 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2740 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 296360 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 296360 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3420989 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2457362 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::UpgradeResp 2735 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 296286 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 296286 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3422037 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2457460 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12875 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 24821 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5916047 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108929528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96856201 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 24836 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5917208 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108963064 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96860105 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14640 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27904 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 205828273 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 53126 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3278039 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.011122 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.104872 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27972 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 205865781 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 53107 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3278617 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.011120 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.104863 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 3241581 98.89% 98.89% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 3242159 98.89% 98.89% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::6 36458 1.11% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3278039 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2354969500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3278617 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2355272500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 328500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2566643750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2567431500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1312602003 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1312657000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer2.occupancy 9215000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 17845000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 17843250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 30195 # Transaction distribution system.iobus.trans_dist::ReadResp 30195 # Transaction distribution @@ -1161,23 +1263,23 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 347056142 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 347060139 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36804505 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36804507 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36424 # number of replacements -system.iocache.tags.tagsinuse 1.134557 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.134613 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 298397320000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.134557 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.070910 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.070910 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 298400039000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.134613 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.070913 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.070913 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1193,8 +1295,8 @@ system.iocache.overall_misses::realview.ide 234 # system.iocache.overall_misses::total 234 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ide 28034377 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 28034377 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9588161260 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 9588161260 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9587408255 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 9587408255 # number of WriteInvalidateReq miss cycles system.iocache.demand_miss_latency::realview.ide 28034377 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::total 28034377 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ide 28034377 # number of overall miss cycles @@ -1217,17 +1319,17 @@ system.iocache.overall_miss_rate::realview.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ide 119805.029915 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 119805.029915 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 264690.847504 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 264690.847504 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 264670.060043 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 264670.060043 # average WriteInvalidateReq miss latency system.iocache.demand_avg_miss_latency::realview.ide 119805.029915 # average overall miss latency system.iocache.demand_avg_miss_latency::total 119805.029915 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ide 119805.029915 # average overall miss latency system.iocache.overall_avg_miss_latency::total 119805.029915 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 55275 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 55358 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7147 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7146 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.734014 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.746711 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1243,8 +1345,8 @@ system.iocache.overall_mshr_misses::realview.ide 234 system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ide 15865377 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 15865377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7704503270 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7704503270 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7703746269 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7703746269 # number of WriteInvalidateReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ide 15865377 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 15865377 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ide 15865377 # number of overall MSHR miss cycles @@ -1259,64 +1361,64 @@ system.iocache.overall_mshr_miss_rate::realview.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67800.756410 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 67800.756410 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 212690.571720 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212690.571720 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 212669.673945 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212669.673945 # average WriteInvalidateReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ide 67800.756410 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 67800.756410 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ide 67800.756410 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 67800.756410 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 70650 # Transaction distribution -system.membus.trans_dist::ReadResp 70650 # Transaction distribution +system.membus.trans_dist::ReadReq 70661 # Transaction distribution +system.membus.trans_dist::ReadResp 70661 # Transaction distribution system.membus.trans_dist::WriteReq 27618 # Transaction distribution system.membus.trans_dist::WriteResp 27618 # Transaction distribution -system.membus.trans_dist::Writeback 118371 # Transaction distribution +system.membus.trans_dist::Writeback 118375 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4503 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4500 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4505 # Transaction distribution -system.membus.trans_dist::ReadExReq 128452 # Transaction distribution -system.membus.trans_dist::ReadExResp 128452 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4502 # Transaction distribution +system.membus.trans_dist::ReadExReq 128454 # Transaction distribution +system.membus.trans_dist::ReadExResp 128454 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2122 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 436202 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 543884 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 436226 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 543908 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108887 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 108887 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 652771 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 652795 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4244 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15454012 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15617473 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15455100 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15618561 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20252929 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20254017 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 498 # Total snoops (count) -system.membus.snoop_fanout::samples 318026 # Request fanout histogram +system.membus.snoop_fanout::samples 318040 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 318026 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 318040 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 318026 # Request fanout histogram +system.membus.snoop_fanout::total 318040 # Request fanout histogram system.membus.reqLayer0.occupancy 86773500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1756500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1758500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1589715500 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1589750000 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 1594842247 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1594947750 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38335495 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 38337493 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt index b2b55eb3a..f0c87683a 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.783867 # Nu sim_ticks 2783867165000 # Number of ticks simulated final_tick 2783867165000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1108011 # Simulator instruction rate (inst/s) -host_op_rate 1348825 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 21604583679 # Simulator tick rate (ticks/s) -host_mem_usage 560868 # Number of bytes of host memory used -host_seconds 128.86 # Real time elapsed on the host +host_inst_rate 1311458 # Simulator instruction rate (inst/s) +host_op_rate 1596489 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 25571502260 # Simulator tick rate (ticks/s) +host_mem_usage 616488 # Number of bytes of host memory used +host_seconds 108.87 # Real time elapsed on the host sim_insts 142773109 # Number of instructions simulated sim_ops 173803334 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -87,6 +87,14 @@ system.cf0.dma_write_full_pages 540 # Nu system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -108,6 +116,24 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.walker.walks 5682 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 5682 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 5682 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 5682 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 5682 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 3049 65.42% 65.42% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1612 34.58% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 4661 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 5682 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 5682 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4661 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4661 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 10343 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses system.cpu0.dtb.read_hits 15994592 # DTB read hits @@ -129,6 +155,14 @@ system.cpu0.dtb.inst_accesses 0 # IT system.cpu0.dtb.hits 27280368 # DTB hits system.cpu0.dtb.misses 5682 # DTB misses system.cpu0.dtb.accesses 27286050 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -150,6 +184,24 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.itb.walker.walks 2611 # Table walker walks requested +system.cpu0.itb.walker.walksShort 2611 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walkWaitTime::samples 2611 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 2611 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 2611 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walksPending::samples 6702500 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 6702500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 6702500 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 1374 72.85% 72.85% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 512 27.15% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 1886 # Table walker page sizes translated +system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2611 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2611 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 1886 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 1886 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 4497 # Table walker requests started/completed, data/inst system.cpu0.itb.inst_hits 74779253 # ITB inst hits system.cpu0.itb.inst_misses 2611 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits @@ -408,6 +460,14 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -429,6 +489,24 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.walker.walks 6203 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 6203 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walkWaitTime::samples 6203 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 6203 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 6203 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walksPending::samples 1000002000 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1000002000 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 1000002000 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 3703 73.18% 73.18% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 1357 26.82% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 5060 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 6203 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 6203 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5060 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5060 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 11263 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses system.cpu1.dtb.read_hits 15530019 # DTB read hits @@ -450,6 +528,14 @@ system.cpu1.dtb.inst_accesses 0 # IT system.cpu1.dtb.hits 27368468 # DTB hits system.cpu1.dtb.misses 6203 # DTB misses system.cpu1.dtb.accesses 27374671 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -471,6 +557,24 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.itb.walker.walks 3040 # Table walker walks requested +system.cpu1.itb.walker.walksShort 3040 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walkWaitTime::samples 3040 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 3040 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 3040 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 1720 81.52% 81.52% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 390 18.48% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 2110 # Table walker page sizes translated +system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 3040 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 3040 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2110 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2110 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 5150 # Table walker requests started/completed, data/inst system.cpu1.itb.inst_hits 72259450 # ITB inst hits system.cpu1.itb.inst_misses 3040 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt index 818a22f67..83b8a4ab7 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 47.177080 # Nu sim_ticks 47177080006500 # Number of ticks simulated final_tick 47177080006500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1024538 # Simulator instruction rate (inst/s) -host_op_rate 1205255 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 49483118923 # Simulator tick rate (ticks/s) -host_mem_usage 669884 # Number of bytes of host memory used -host_seconds 953.40 # Real time elapsed on the host +host_inst_rate 1049876 # Simulator instruction rate (inst/s) +host_op_rate 1235062 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 50706899360 # Simulator tick rate (ticks/s) +host_mem_usage 670076 # Number of bytes of host memory used +host_seconds 930.39 # Real time elapsed on the host sim_insts 976792036 # Number of instructions simulated sim_ops 1149086878 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -105,6 +105,14 @@ system.cf0.dma_write_full_pages 1667 # Nu system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -126,6 +134,24 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.walker.walks 123914 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 123914 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 123914 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 123914 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 123914 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 95376 89.74% 89.74% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 10905 10.26% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 106281 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 123914 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 123914 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 106281 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 106281 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 230195 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses system.cpu0.dtb.read_hits 91355479 # DTB read hits @@ -147,6 +173,14 @@ system.cpu0.dtb.inst_accesses 0 # IT system.cpu0.dtb.hits 175957422 # DTB hits system.cpu0.dtb.misses 123914 # DTB misses system.cpu0.dtb.accesses 176081336 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -168,6 +202,24 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.itb.walker.walks 60226 # Table walker walks requested +system.cpu0.itb.walker.walksLong 60226 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walkWaitTime::samples 60226 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 60226 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 60226 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 54190 98.81% 98.81% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 654 1.19% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 54844 # Table walker page sizes translated +system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 60226 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 60226 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 54844 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 54844 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 115070 # Table walker requests started/completed, data/inst system.cpu0.itb.inst_hits 491372488 # ITB inst hits system.cpu0.itb.inst_misses 60226 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits @@ -392,15 +444,12 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped +system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size +system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing system.cpu0.l2cache.tags.replacements 2648971 # number of replacements system.cpu0.l2cache.tags.tagsinuse 16219.904236 # Cycle average of tags in use system.cpu0.l2cache.tags.total_refs 11415809 # Total number of references to valid blocks. @@ -576,6 +625,14 @@ system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::total 20196192 # Request fanout histogram +system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -597,6 +654,24 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.walker.walks 144852 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 144852 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walkWaitTime::samples 144852 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 144852 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 144852 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walksPending::samples -274403872 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -274403872 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -274403872 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 112422 89.02% 89.02% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 13865 10.98% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 126287 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 144852 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 144852 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 126287 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 126287 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 271139 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses system.cpu1.dtb.read_hits 91720002 # DTB read hits @@ -618,6 +693,14 @@ system.cpu1.dtb.inst_accesses 0 # IT system.cpu1.dtb.hits 174219015 # DTB hits system.cpu1.dtb.misses 144852 # DTB misses system.cpu1.dtb.accesses 174363867 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -639,6 +722,24 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.itb.walker.walks 61939 # Table walker walks requested +system.cpu1.itb.walker.walksLong 61939 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walkWaitTime::samples 61939 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 61939 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 61939 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walksPending::samples -274404872 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -274404872 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -274404872 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 54929 99.06% 99.06% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 521 0.94% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 55450 # Table walker page sizes translated +system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 61939 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 61939 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55450 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55450 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 117389 # Table walker requests started/completed, data/inst system.cpu1.itb.inst_hits 485906850 # ITB inst hits system.cpu1.itb.inst_misses 61939 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits @@ -861,15 +962,12 @@ system.cpu1.icache.avg_blocked_cycles::no_targets nan system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped +system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size +system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing system.cpu1.l2cache.tags.replacements 2333825 # number of replacements system.cpu1.l2cache.tags.tagsinuse 13484.024344 # Cycle average of tags in use system.cpu1.l2cache.tags.total_refs 11006559 # Total number of references to valid blocks. diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt index 09df20817..70b8700c6 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 51.111151 # Nu sim_ticks 51111150553500 # Number of ticks simulated final_tick 51111150553500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1176583 # Simulator instruction rate (inst/s) -host_op_rate 1382679 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 61065327647 # Simulator tick rate (ticks/s) -host_mem_usage 656288 # Number of bytes of host memory used -host_seconds 836.99 # Real time elapsed on the host +host_inst_rate 1336104 # Simulator instruction rate (inst/s) +host_op_rate 1570142 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 69344550867 # Simulator tick rate (ticks/s) +host_mem_usage 712616 # Number of bytes of host memory used +host_seconds 737.06 # Real time elapsed on the host sim_insts 984789519 # Number of instructions simulated sim_ops 1157289961 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -74,6 +74,14 @@ system.cf0.dma_write_full_pages 1666 # Nu system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -95,6 +103,24 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 265618 # Table walker walks requested +system.cpu.dtb.walker.walksLong 265618 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walkWaitTime::samples 265618 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 265618 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 265618 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 204344 89.54% 89.54% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 23878 10.46% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 228222 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 265618 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 265618 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 228222 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 228222 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 493840 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 184057973 # DTB read hits @@ -116,6 +142,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 352334273 # DTB hits system.cpu.dtb.misses 265618 # DTB misses system.cpu.dtb.accesses 352599891 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -137,6 +171,24 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 126829 # Table walker walks requested +system.cpu.itb.walker.walksLong 126829 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walkWaitTime::samples 126829 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 126829 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 126829 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 113566 99.02% 99.02% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1125 0.98% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 114691 # Table walker page sizes translated +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 126829 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 126829 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 114691 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 114691 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 241520 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 985266544 # ITB inst hits system.cpu.itb.inst_misses 126829 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt index 2d0abc648..cd0cb8f17 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt @@ -1,172 +1,172 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.398431 # Number of seconds simulated -sim_ticks 47398431268500 # Number of ticks simulated -final_tick 47398431268500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.410782 # Number of seconds simulated +sim_ticks 47410781652000 # Number of ticks simulated +final_tick 47410781652000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 671569 # Simulator instruction rate (inst/s) -host_op_rate 790318 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 37657329129 # Simulator tick rate (ticks/s) -host_mem_usage 861000 # Number of bytes of host memory used -host_seconds 1258.68 # Real time elapsed on the host -sim_insts 845288376 # Number of instructions simulated -sim_ops 994755388 # Number of ops (including micro ops) simulated +host_inst_rate 787433 # Simulator instruction rate (inst/s) +host_op_rate 926573 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 41969003911 # Simulator tick rate (ticks/s) +host_mem_usage 699232 # Number of bytes of host memory used +host_seconds 1129.66 # Real time elapsed on the host +sim_insts 889532971 # Number of instructions simulated +sim_ops 1046714541 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 36416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 41984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 768052 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 7936536 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 44723840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 83456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 97984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 589368 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 8667104 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 21031552 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 441920 # Number of bytes read from this memory -system.physmem.bytes_read::total 84418212 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 768052 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 589368 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1357420 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65101248 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 154432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 156800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3551860 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 14084888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 14587840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 66560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 59904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2809592 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 8562400 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 11943680 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 428992 # Number of bytes read from this memory +system.physmem.bytes_read::total 56406948 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3551860 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2809592 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 6361452 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 74353408 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20812 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 65122064 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 569 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 656 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 52408 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 124030 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 698810 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1304 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1531 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 9297 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 135438 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 328618 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6905 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1359566 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1017207 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 74374224 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2413 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2450 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 95905 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 220098 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 227935 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1040 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 936 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 43988 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 133802 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 186620 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6703 # Number of read requests responded to by this memory +system.physmem.num_reads::total 921890 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1161772 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2602 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1019810 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 768 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 886 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 16204 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 167443 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 943572 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 1761 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 2067 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 12434 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 182856 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 443718 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9324 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1781034 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 16204 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 12434 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 28639 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1373490 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1164375 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3257 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 3307 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 74917 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 297082 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 307690 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 1404 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 1264 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 59261 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 180600 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 251919 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9048 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1189749 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 74917 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 59261 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 134177 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1568281 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 439 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1373929 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1373490 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 768 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 886 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 16204 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 167882 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 943572 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 1761 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 2067 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 12434 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 182856 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 443718 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9324 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3154963 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1359566 # Number of read requests accepted -system.physmem.writeReqs 1139623 # Number of write requests accepted -system.physmem.readBursts 1359566 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1139623 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 86962304 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 49920 # Total number of bytes read from write queue -system.physmem.bytesWritten 72439488 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 84418212 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 72790096 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 780 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 7732 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 85004 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 81504 # Per bank write bursts -system.physmem.perBankRdBursts::1 94599 # Per bank write bursts -system.physmem.perBankRdBursts::2 79086 # Per bank write bursts -system.physmem.perBankRdBursts::3 89082 # Per bank write bursts -system.physmem.perBankRdBursts::4 90127 # Per bank write bursts -system.physmem.perBankRdBursts::5 94039 # Per bank write bursts -system.physmem.perBankRdBursts::6 78740 # Per bank write bursts -system.physmem.perBankRdBursts::7 79772 # Per bank write bursts -system.physmem.perBankRdBursts::8 80197 # Per bank write bursts -system.physmem.perBankRdBursts::9 124149 # Per bank write bursts -system.physmem.perBankRdBursts::10 71869 # Per bank write bursts -system.physmem.perBankRdBursts::11 83577 # Per bank write bursts -system.physmem.perBankRdBursts::12 73174 # Per bank write bursts -system.physmem.perBankRdBursts::13 83519 # Per bank write bursts -system.physmem.perBankRdBursts::14 78794 # Per bank write bursts -system.physmem.perBankRdBursts::15 76558 # Per bank write bursts -system.physmem.perBankWrBursts::0 70549 # Per bank write bursts -system.physmem.perBankWrBursts::1 76959 # Per bank write bursts -system.physmem.perBankWrBursts::2 69527 # Per bank write bursts -system.physmem.perBankWrBursts::3 76268 # Per bank write bursts -system.physmem.perBankWrBursts::4 71760 # Per bank write bursts -system.physmem.perBankWrBursts::5 76111 # Per bank write bursts -system.physmem.perBankWrBursts::6 67646 # Per bank write bursts -system.physmem.perBankWrBursts::7 68141 # Per bank write bursts -system.physmem.perBankWrBursts::8 69345 # Per bank write bursts -system.physmem.perBankWrBursts::9 72887 # Per bank write bursts -system.physmem.perBankWrBursts::10 65485 # Per bank write bursts -system.physmem.perBankWrBursts::11 73987 # Per bank write bursts -system.physmem.perBankWrBursts::12 65828 # Per bank write bursts -system.physmem.perBankWrBursts::13 73935 # Per bank write bursts -system.physmem.perBankWrBursts::14 66021 # Per bank write bursts -system.physmem.perBankWrBursts::15 67418 # Per bank write bursts +system.physmem.bw_write::total 1568720 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1568281 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3257 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 3307 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 74917 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 297521 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 307690 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 1404 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 1264 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 59261 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 180600 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 251919 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9048 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2758469 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 921890 # Number of read requests accepted +system.physmem.writeReqs 1829645 # Number of write requests accepted +system.physmem.readBursts 921890 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1829645 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 58978368 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 22592 # Total number of bytes read from write queue +system.physmem.bytesWritten 116660480 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 56406948 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 116951504 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 353 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 6803 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 114603 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 54393 # Per bank write bursts +system.physmem.perBankRdBursts::1 56084 # Per bank write bursts +system.physmem.perBankRdBursts::2 54659 # Per bank write bursts +system.physmem.perBankRdBursts::3 58883 # Per bank write bursts +system.physmem.perBankRdBursts::4 54974 # Per bank write bursts +system.physmem.perBankRdBursts::5 58047 # Per bank write bursts +system.physmem.perBankRdBursts::6 51881 # Per bank write bursts +system.physmem.perBankRdBursts::7 58759 # Per bank write bursts +system.physmem.perBankRdBursts::8 52533 # Per bank write bursts +system.physmem.perBankRdBursts::9 95950 # Per bank write bursts +system.physmem.perBankRdBursts::10 53815 # Per bank write bursts +system.physmem.perBankRdBursts::11 56993 # Per bank write bursts +system.physmem.perBankRdBursts::12 52328 # Per bank write bursts +system.physmem.perBankRdBursts::13 55917 # Per bank write bursts +system.physmem.perBankRdBursts::14 52932 # Per bank write bursts +system.physmem.perBankRdBursts::15 53389 # Per bank write bursts +system.physmem.perBankWrBursts::0 113787 # Per bank write bursts +system.physmem.perBankWrBursts::1 117144 # Per bank write bursts +system.physmem.perBankWrBursts::2 115098 # Per bank write bursts +system.physmem.perBankWrBursts::3 118536 # Per bank write bursts +system.physmem.perBankWrBursts::4 116769 # Per bank write bursts +system.physmem.perBankWrBursts::5 120895 # Per bank write bursts +system.physmem.perBankWrBursts::6 109520 # Per bank write bursts +system.physmem.perBankWrBursts::7 112924 # Per bank write bursts +system.physmem.perBankWrBursts::8 111914 # Per bank write bursts +system.physmem.perBankWrBursts::9 117541 # Per bank write bursts +system.physmem.perBankWrBursts::10 111832 # Per bank write bursts +system.physmem.perBankWrBursts::11 116807 # Per bank write bursts +system.physmem.perBankWrBursts::12 108182 # Per bank write bursts +system.physmem.perBankWrBursts::13 109739 # Per bank write bursts +system.physmem.perBankWrBursts::14 110202 # Per bank write bursts +system.physmem.perBankWrBursts::15 111930 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 5 # Number of times write queue was full causing retry -system.physmem.totGap 47398428076000 # Total gap between requests +system.physmem.numWrRetry 2 # Number of times write queue was full causing retry +system.physmem.totGap 47410778671000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43195 # Read request sizes (log2) system.physmem.readPktSize::3 37 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1316329 # Read request sizes (log2) +system.physmem.readPktSize::6 878653 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2601 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1137020 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 566894 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 282234 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 134057 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 101972 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 67644 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 58693 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 53670 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 46721 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 35916 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 3762 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1955 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1465 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1125 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 882 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 709 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 471 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 229 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 184 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 107 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 75 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1827042 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 652905 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 75815 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 40303 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 33479 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 29162 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 25818 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 22543 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 19321 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 15689 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2492 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1008 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 754 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 600 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 460 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 351 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 292 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 214 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 179 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 82 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 63 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see @@ -188,158 +188,182 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 16911 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 22466 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 30737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 39170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 44059 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 50283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 58139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 68202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 72051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 76579 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 76851 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 78478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 78341 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 80363 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 74556 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 75992 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 78312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 75395 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 11828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 7611 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 4129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1848 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1099 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 916 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 777 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 712 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 642 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 648 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 562 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 544 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 505 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 463 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 418 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 372 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 356 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 192 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 5 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 648906 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 245.646870 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 142.183985 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 295.195613 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 325424 50.15% 50.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 135792 20.93% 71.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 50411 7.77% 78.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 26706 4.12% 82.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 22287 3.43% 86.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 16108 2.48% 88.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 10950 1.69% 90.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 13619 2.10% 92.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 47609 7.34% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 648906 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 58676 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.156827 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 139.787244 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 58673 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 54841 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 74169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 96317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 106970 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 112981 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 116642 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 107891 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 106380 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 105711 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 108843 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 109894 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 108607 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 105867 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 106408 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 98436 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 96529 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 94372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 91211 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 4176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 3101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1802 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1394 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 899 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 219 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 6 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1000117 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 175.617981 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 106.594305 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 248.236984 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 645970 64.59% 64.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 191036 19.10% 83.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 45051 4.50% 88.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 21747 2.17% 90.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 15328 1.53% 91.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 10644 1.06% 92.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8285 0.83% 93.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 7295 0.73% 94.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 54761 5.48% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1000117 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 87721 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 10.505238 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 108.849756 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 87718 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::24576-25599 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 58676 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 58676 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.290119 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.850822 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 13.308232 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 54948 93.65% 93.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 970 1.65% 95.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 598 1.02% 96.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 219 0.37% 96.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 626 1.07% 97.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 147 0.25% 98.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 195 0.33% 98.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 132 0.22% 98.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 184 0.31% 98.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 81 0.14% 99.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 205 0.35% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 24 0.04% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 63 0.11% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 38 0.06% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 129 0.22% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 15 0.03% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 27 0.05% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 11 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 19 0.03% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 8 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 11 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 2 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 5 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 6 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 3 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 4 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-255 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-279 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 58676 # Writes before turning the bus around for reads -system.physmem.totQLat 69966976258 # Total ticks spent queuing -system.physmem.totMemAccLat 95444213758 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 6793930000 # Total ticks spent in databus transfers -system.physmem.avgQLat 51492.27 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 87721 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 87721 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.779745 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.605058 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 11.125024 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 56948 64.92% 64.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 16031 18.27% 83.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 6972 7.95% 91.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 3738 4.26% 95.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 1084 1.24% 96.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 357 0.41% 97.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 239 0.27% 97.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 271 0.31% 97.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 649 0.74% 98.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 108 0.12% 98.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 85 0.10% 98.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 76 0.09% 98.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 135 0.15% 98.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 76 0.09% 98.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 51 0.06% 98.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 73 0.08% 99.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 134 0.15% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 41 0.05% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 31 0.04% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 49 0.06% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 179 0.20% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 16 0.02% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 31 0.04% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 14 0.02% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 43 0.05% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 12 0.01% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 20 0.02% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 30 0.03% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 97 0.11% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 18 0.02% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 14 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 10 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 13 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 11 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 6 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 6 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 14 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 3 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 12 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::204-207 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::212-215 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::220-223 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 4 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 87721 # Writes before turning the bus around for reads +system.physmem.totQLat 32913462781 # Total ticks spent queuing +system.physmem.totMemAccLat 50192281531 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4607685000 # Total ticks spent in databus transfers +system.physmem.avgQLat 35715.83 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 70242.27 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.83 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.53 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.78 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.54 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 54465.83 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.24 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.46 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.19 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.47 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.73 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.44 # Average write queue length when enqueuing -system.physmem.readRowHits 1114788 # Number of row buffer hits during reads -system.physmem.writeRowHits 726958 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.04 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 64.23 # Row buffer hit rate for writes -system.physmem.avgGap 18965523.65 # Average gap between requests -system.physmem.pageHitRate 73.95 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 45538400789750 # Time in different power states -system.physmem.memoryStateTime::REF 1582737780000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 277292625250 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 2564850960 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 2340878400 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 1399472250 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 1277265000 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 5358202200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 5240320800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 3738707280 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 3595790880 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 3095835097680 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 3095835097680 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 1171174509540 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 1161726671475 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 27411712647750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 27420000225000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 31691783487660 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 31690016249235 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.625157 # Core power per rank (mW) -system.physmem.averagePower::1 668.587872 # Core power per rank (mW) +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.25 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.28 # Average write queue length when enqueuing +system.physmem.readRowHits 687654 # Number of row buffer hits during reads +system.physmem.writeRowHits 1056585 # Number of row buffer hits during writes +system.physmem.readRowHitRate 74.62 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 57.96 # Row buffer hit rate for writes +system.physmem.avgGap 17230665.31 # Average gap between requests +system.physmem.pageHitRate 63.56 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3832851960 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2091337875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3491865000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 5991881040 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3096641673840 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1200455054145 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27393437346750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31705942010610 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.749637 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45570820980751 # Time in different power states +system.physmem_0.memoryStateTime::REF 1583150140000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 256810103749 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 3728032560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2034144750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3696084600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 5819992560 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3096641673840 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1191404828700 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27401376141000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31704700898010 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.723459 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45584059811251 # Time in different power states +system.physmem_1.memoryStateTime::REF 1583150140000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 243570222499 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory @@ -373,6 +397,14 @@ system.cf0.dma_write_full_pages 1670 # Nu system.cf0.dma_write_bytes 6842880 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1673 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -394,27 +426,74 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.walker.walks 107972 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 107972 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9276 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 83163 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 107963 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 107963 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 107963 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 92448 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 17595.764614 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 15306.328665 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 15454.252367 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 91009 98.44% 98.44% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 1235 1.34% 99.78% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 66 0.07% 99.85% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 55 0.06% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 65 0.07% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 12 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 92448 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples -2398441544 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.163884 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.370170 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 -2005375084 83.61% 83.61% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 -393066460 16.39% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total -2398441544 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 83163 89.97% 89.97% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 9276 10.03% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 92439 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 107972 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 107972 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 92439 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 92439 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 200411 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 74706058 # DTB read hits -system.cpu0.dtb.read_misses 64792 # DTB read misses -system.cpu0.dtb.write_hits 67192400 # DTB write hits -system.cpu0.dtb.write_misses 21129 # DTB write misses +system.cpu0.dtb.read_hits 83792624 # DTB read hits +system.cpu0.dtb.read_misses 78614 # DTB read misses +system.cpu0.dtb.write_hits 76883618 # DTB write hits +system.cpu0.dtb.write_misses 29358 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 37660 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1002 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 33482 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 41330 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 38297 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 3817 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 4651 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 8375 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 74770850 # DTB read accesses -system.cpu0.dtb.write_accesses 67213529 # DTB write accesses +system.cpu0.dtb.perms_faults 10679 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 83871238 # DTB read accesses +system.cpu0.dtb.write_accesses 76912976 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 141898458 # DTB hits -system.cpu0.dtb.misses 85921 # DTB misses -system.cpu0.dtb.accesses 141984379 # DTB accesses +system.cpu0.dtb.hits 160676242 # DTB hits +system.cpu0.dtb.misses 107972 # DTB misses +system.cpu0.dtb.accesses 160784214 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -436,201 +515,236 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 397874920 # ITB inst hits -system.cpu0.itb.inst_misses 49120 # ITB inst misses +system.cpu0.itb.walker.walks 64255 # Table walker walks requested +system.cpu0.itb.walker.walksLong 64255 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 637 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 58227 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 64255 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 64255 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 64255 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 58864 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 20635.902164 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 17664.674655 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 19771.927470 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 57276 97.30% 97.30% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 1371 2.33% 99.63% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 47 0.08% 99.71% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 91 0.15% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 53 0.09% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 19 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 5 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 58864 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples -673300296 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 -673300296 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total -673300296 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 58227 98.92% 98.92% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 637 1.08% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 58864 # Table walker page sizes translated +system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 64255 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 64255 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 58864 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 58864 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 123119 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 448595101 # ITB inst hits +system.cpu0.itb.inst_misses 64255 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 37660 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1002 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 23760 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 41330 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 26739 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 397924040 # ITB inst accesses -system.cpu0.itb.hits 397874920 # DTB hits -system.cpu0.itb.misses 49120 # DTB misses -system.cpu0.itb.accesses 397924040 # DTB accesses -system.cpu0.numCycles 94796862537 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 448659356 # ITB inst accesses +system.cpu0.itb.hits 448595101 # DTB hits +system.cpu0.itb.misses 64255 # DTB misses +system.cpu0.itb.accesses 448659356 # DTB accesses +system.cpu0.numCycles 94821563304 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 397643174 # Number of instructions committed -system.cpu0.committedOps 466635553 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 429030148 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 322477 # Number of float alu accesses -system.cpu0.num_func_calls 23930039 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 59901605 # number of instructions that are conditional controls -system.cpu0.num_int_insts 429030148 # number of integer instructions -system.cpu0.num_fp_insts 322477 # number of float instructions -system.cpu0.num_int_register_reads 621630892 # number of times the integer registers were read -system.cpu0.num_int_register_writes 340702516 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 547437 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 211832 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 102593685 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 102325899 # number of times the CC registers were written -system.cpu0.num_mem_refs 141893093 # number of memory refs -system.cpu0.num_load_insts 74704433 # Number of load instructions -system.cpu0.num_store_insts 67188660 # Number of store instructions -system.cpu0.num_idle_cycles 93886429062.298019 # Number of idle cycles -system.cpu0.num_busy_cycles 910433474.701981 # Number of busy cycles -system.cpu0.not_idle_fraction 0.009604 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.990396 # Percentage of idle cycles -system.cpu0.Branches 88352328 # Number of branches fetched -system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 323823287 69.35% 69.35% # Class of executed instruction -system.cpu0.op_class::IntMult 1114929 0.24% 69.59% # Class of executed instruction -system.cpu0.op_class::IntDiv 56737 0.01% 69.61% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 22377 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::MemRead 74704433 16.00% 85.61% # Class of executed instruction -system.cpu0.op_class::MemWrite 67188660 14.39% 100.00% # Class of executed instruction +system.cpu0.committedInsts 448345930 # Number of instructions committed +system.cpu0.committedOps 527651436 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 484594714 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 558267 # Number of float alu accesses +system.cpu0.num_func_calls 26890258 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 68074268 # number of instructions that are conditional controls +system.cpu0.num_int_insts 484594714 # number of integer instructions +system.cpu0.num_fp_insts 558267 # number of float instructions +system.cpu0.num_int_register_reads 706750752 # number of times the integer registers were read +system.cpu0.num_int_register_writes 384547382 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 893879 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 490056 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 117567828 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 117277075 # number of times the CC registers were written +system.cpu0.num_mem_refs 160668093 # number of memory refs +system.cpu0.num_load_insts 83788812 # Number of load instructions +system.cpu0.num_store_insts 76879281 # Number of store instructions +system.cpu0.num_idle_cycles 93729284290.716034 # Number of idle cycles +system.cpu0.num_busy_cycles 1092279013.283977 # Number of busy cycles +system.cpu0.not_idle_fraction 0.011519 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.988481 # Percentage of idle cycles +system.cpu0.Branches 100174256 # Number of branches fetched +system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 365953478 69.32% 69.32% # Class of executed instruction +system.cpu0.op_class::IntMult 1186010 0.22% 69.54% # Class of executed instruction +system.cpu0.op_class::IntDiv 57830 0.01% 69.55% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 21 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 78277 0.01% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::MemRead 83788812 15.87% 85.44% # Class of executed instruction +system.cpu0.op_class::MemWrite 76879281 14.56% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 466910423 # Class of executed instruction +system.cpu0.op_class::total 527943731 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 5105 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 4859280 # number of replacements -system.cpu0.dcache.tags.tagsinuse 480.680410 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 136835586 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 4859789 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 28.156693 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 3644536500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 480.680410 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.938829 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.938829 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 406 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 9 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 288671468 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 288671468 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 69599952 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 69599952 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 63413457 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 63413457 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 173858 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 173858 # number of SoftPFReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 133135 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::total 133135 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1596886 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1596886 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1561841 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1561841 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 133013409 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 133013409 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 133187267 # number of overall hits -system.cpu0.dcache.overall_hits::total 133187267 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 2622769 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 2622769 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1185607 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1185607 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 553155 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 553155 # number of SoftPFReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 697992 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::total 697992 # number of WriteInvalidateReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 145021 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 145021 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 178721 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 178721 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3808376 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3808376 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 4361531 # number of overall misses -system.cpu0.dcache.overall_misses::total 4361531 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 36725560788 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 36725560788 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 18496940456 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 18496940456 # number of WriteReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 11951080104 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 11951080104 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2007745317 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 2007745317 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3807661334 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 3807661334 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 927000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 927000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 55222501244 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 55222501244 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 55222501244 # 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number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 1741907 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1740562 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 1740562 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 136821785 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 136821785 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 137548798 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 137548798 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036315 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.036315 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018353 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.018353 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.760860 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.760860 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.839814 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.839814 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.083254 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.083254 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.102680 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.102680 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027835 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.027835 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.031709 # 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Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 390 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 55 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 327127592 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 327127592 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 77833401 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 77833401 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 72535559 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 72535559 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 180949 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 180949 # 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average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 18056.936792 # average WriteReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 33249.656203 # average WriteInvalidateReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 33249.656203 # average WriteInvalidateReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15096.256661 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15096.256661 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21262.123455 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21262.123455 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14500.275510 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 14500.275510 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12661.265332 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 12661.265332 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15790.900187 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 15790.900187 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13677.300146 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 13677.300146 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -639,92 +753,92 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # 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number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 11524265112 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 11524265112 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 10542114896 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 10542114896 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1234908207 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1234908207 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3440508666 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3440508666 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 879000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 879000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 46208703669 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 46208703669 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 57732968781 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 57732968781 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2384094697 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2384094697 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2386757695 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2386757695 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4770852392 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4770852392 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036027 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036027 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018022 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018022 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.758494 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.758494 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.839814 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.839814 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.062487 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.062487 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.102680 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.102680 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027526 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.027526 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031389 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.031389 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11745.684807 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11745.684807 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 13440.434019 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 13440.434019 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 20898.682731 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 20898.682731 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 15103.489576 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 15103.489576 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11345.358228 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11345.358228 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19250.724123 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19250.724123 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 3895213 # number of writebacks +system.cpu0.dcache.writebacks::total 3895213 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 35120 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 35120 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21470 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 21470 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 46933 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 46933 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 56590 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 56590 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 56590 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 56590 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3044295 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 3044295 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1417652 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1417652 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 692633 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 692633 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 782756 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 782756 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 125972 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 125972 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 200615 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 200615 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 4461947 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 4461947 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 5154580 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 5154580 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 37795344499 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 37795344499 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 22579422262 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 22579422262 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14234213672 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14234213672 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 24458156109 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 24458156109 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1564829744 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1564829744 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3853276103 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3853276103 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2137000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2137000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 60374766761 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 60374766761 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 74608980433 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 74608980433 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2287793998 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2287793998 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2244465248 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2244465248 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4532259246 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4532259246 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.037624 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037624 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019164 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019164 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.787787 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.787787 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.869570 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.869570 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.063415 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.063415 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.101055 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.101055 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028808 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.028808 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.033092 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.033092 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12415.138644 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12415.138644 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15927.337782 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15927.337782 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 20550.874232 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 20550.874232 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 31246.207131 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 31246.207131 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12422.044137 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12422.044137 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19207.318012 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19207.318012 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 12269.565120 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 12269.565120 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13371.668756 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13371.668756 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13531.036286 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13531.036286 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14474.308369 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14474.308369 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -732,59 +846,58 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 4269396 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.932974 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 393605012 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 4269908 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 92.181146 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 18918806750 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.932974 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999869 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999869 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 5166576 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.910022 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 443428013 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 5167088 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 85.817778 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 30209622750 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.910022 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999824 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999824 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 269 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 222 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 324 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 127 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 800019748 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 800019748 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 393605012 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 393605012 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 393605012 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 393605012 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 393605012 # number of overall hits -system.cpu0.icache.overall_hits::total 393605012 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 4269908 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 4269908 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 4269908 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 4269908 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 4269908 # number of overall misses -system.cpu0.icache.overall_misses::total 4269908 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 37643365597 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 37643365597 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 37643365597 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 37643365597 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 37643365597 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 37643365597 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 397874920 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 397874920 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 397874920 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 397874920 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 397874920 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 397874920 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010732 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.010732 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.010732 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.010732 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.010732 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.010732 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8815.966432 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 8815.966432 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8815.966432 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 8815.966432 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8815.966432 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 8815.966432 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 902357290 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 902357290 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 443428013 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 443428013 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 443428013 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 443428013 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 443428013 # number of overall hits +system.cpu0.icache.overall_hits::total 443428013 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 5167088 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 5167088 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 5167088 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 5167088 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 5167088 # number of overall misses +system.cpu0.icache.overall_misses::total 5167088 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 53694723563 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 53694723563 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 53694723563 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 53694723563 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 53694723563 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 53694723563 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 448595101 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 448595101 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 448595101 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 448595101 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 448595101 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 448595101 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011518 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.011518 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011518 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.011518 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011518 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.011518 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10391.679717 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10391.679717 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10391.679717 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10391.679717 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10391.679717 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10391.679717 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -793,384 +906,383 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # 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number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 31235618425 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 5167088 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 5167088 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 5167088 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 5167088 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 5167088 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 5167088 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 45925261947 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 45925261947 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 45925261947 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 45925261947 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 45925261947 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 45925261947 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3405609750 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 3405609750 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 3405609750 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 3405609750 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.010732 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010732 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.010732 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.010732 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.010732 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.010732 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 7315.290733 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7315.290733 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7315.290733 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 7315.290733 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7315.290733 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 7315.290733 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011518 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011518 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011518 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.011518 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011518 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.011518 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8888.035572 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8888.035572 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8888.035572 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 8888.035572 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8888.035572 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 8888.035572 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 45505774 # number of hwpf identified -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 2657797 # number of hwpf that were already in mshr -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 39900232 # number of hwpf that were already in the cache -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 8744 # number of hwpf that were already in the prefetch queue -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 580 # number of hwpf removed because MSHR allocated -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 2938421 # number of hwpf issued -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 3808538 # number of hwpf spanning a virtual page -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.l2cache.tags.replacements 3291824 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16191.272385 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 9909292 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 3307923 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 2.995624 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 16044231500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 5217.724609 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 49.949148 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 58.574202 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 727.292976 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 2667.900561 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 7469.830889 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.318465 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003049 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003575 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.044390 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.162836 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.455922 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.988237 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8632 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 100 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 7367 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 22 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 210 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 1111 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 7012 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 277 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::0 6 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 10 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 7 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 77 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1042 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 1532 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4604 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 127 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.526855 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.006104 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.449646 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 215960486 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 215960486 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 166834 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 106498 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 4104943 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.data 2390641 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 6768916 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 3276433 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 3276433 # number of Writeback hits -system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data 610572 # number of WriteInvalidateReq hits -system.cpu0.l2cache.WriteInvalidateReq_hits::total 610572 # number of WriteInvalidateReq hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 75583 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 75583 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 31346 # 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number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 2994303005 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 2994303005 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 855000 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 855000 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 6538293027 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 6538293027 # number of ReadExReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 247144715 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 215825476 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 4449371565 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 32240016803 # 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number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2268405055 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 2174725243 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 5236589993 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 2129495502 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2129495502 # number of WriteReq MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 3061864750 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 4536939856 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7598804606 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.053612 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.066552 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.032837 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.265568 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.130853 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 4304220745 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7366085495 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.044321 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.056539 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.099515 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.253426 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.160493 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for Writeback accesses +system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000000 # mshr miss rate for Writeback accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.070057 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.070057 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.585799 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.585799 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.824608 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.824608 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.696946 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.696946 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.535384 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.535384 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.828730 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.828730 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.172158 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.172158 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.053612 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.066552 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.032837 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.243863 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.135483 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.053612 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.066552 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.032837 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.243863 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.205407 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.205407 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.044321 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.056539 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.099515 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.242001 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.165588 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.044321 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.056539 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.099515 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.242001 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.469001 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 19129.700667 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 21397.343606 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 21780.932052 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 22395.109853 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 22273.429726 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 43752.426923 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 43752.426923 # average HardPFReq mshr miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 18274.092453 # average WriteInvalidateReq mshr miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 18274.092453 # average WriteInvalidateReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16661.502488 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16661.502488 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13865.687238 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13865.687238 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 687000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 687000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 29683.053592 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 29683.053592 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 19129.700667 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 21397.343606 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 21780.932052 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 23590.654453 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 23328.795643 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 19129.700667 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 21397.343606 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 21780.932052 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 23590.654453 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 43752.426923 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 37852.554233 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.231978 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 31456.355779 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 34671.120177 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 22958.552072 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 26026.451805 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 25072.510487 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49425.192319 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 49425.192319 # average HardPFReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 34326.997887 # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 34326.997887 # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16986.530742 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16986.530742 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13741.236699 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13741.236699 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 214125 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 214125 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 36924.550389 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 36924.550389 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 31456.355779 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 34671.120177 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 22958.552072 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28227.276368 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 26740.395420 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 31456.355779 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 34671.120177 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 22958.552072 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28227.276368 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49425.192319 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 33232.542850 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1180,59 +1292,67 @@ system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 11465749 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 8074092 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 15773 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 15773 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 3276433 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 4228803 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 811507 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 696929 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 407420 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 328722 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 423022 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 30 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 53 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1108208 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 995011 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 8626066 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 14109371 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 260774 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 426575 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 23422786 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 273446612 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 532438419 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 912728 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1410280 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 808208039 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 8581549 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 21569506 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.385644 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.486747 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 11541292 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 9690709 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 15329 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 15329 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 3895213 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 1069383 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1166255 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 781481 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 444610 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 368177 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 498972 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 55 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 100 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1328849 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1215209 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 10420426 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 16690518 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 351532 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 549297 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 28011773 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 330866132 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 630631769 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1276280 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1881728 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 964655909 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 4194903 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 19756578 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 5.197801 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.398341 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 13251364 61.44% 61.44% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 8318142 38.56% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::5 15848715 80.22% 80.22% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::6 3907863 19.78% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 21569506 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 10644176370 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 19756578 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 12645685295 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 173370992 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 194485993 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 6459583336 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 7813325558 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 6973558574 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 8298663367 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 146771777 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 192341003 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 250366041 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 314436506 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1254,27 +1374,82 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.walker.walks 99527 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 99527 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9603 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 74573 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 99518 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 0.271308 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 67.169326 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-2047 99516 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::6144-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::18432-20479 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 99518 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 84185 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 16581.674289 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 15037.130908 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 10932.627488 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-32767 81471 96.78% 96.78% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-65535 2185 2.60% 99.37% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-98303 285 0.34% 99.71% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-131071 159 0.19% 99.90% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-163839 19 0.02% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::163840-196607 14 0.02% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-229375 18 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::229376-262143 4 0.00% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-294911 15 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::294912-327679 5 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-360447 5 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::360448-393215 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 84185 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -1589468256 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.778279 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.415405 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -352419148 22.17% 22.17% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 -1237049108 77.83% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -1589468256 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 74574 88.59% 88.59% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 9603 11.41% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 84177 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 99527 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 99527 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 84177 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 84177 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 183704 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 84980512 # DTB read hits -system.cpu1.dtb.read_misses 74547 # DTB read misses -system.cpu1.dtb.write_hits 77969612 # DTB write hits -system.cpu1.dtb.write_misses 26781 # DTB write misses +system.cpu1.dtb.read_hits 83767099 # DTB read hits +system.cpu1.dtb.read_misses 74857 # DTB read misses +system.cpu1.dtb.write_hits 75685520 # DTB write hits +system.cpu1.dtb.write_misses 24670 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 37660 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1002 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 37319 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 41330 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 36584 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 4156 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 4104 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 10210 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 85055059 # DTB read accesses -system.cpu1.dtb.write_accesses 77996393 # DTB write accesses +system.cpu1.dtb.perms_faults 9015 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 83841956 # DTB read accesses +system.cpu1.dtb.write_accesses 75710190 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 162950124 # DTB hits -system.cpu1.dtb.misses 101328 # DTB misses -system.cpu1.dtb.accesses 163051452 # DTB accesses +system.cpu1.dtb.hits 159452619 # DTB hits +system.cpu1.dtb.misses 99527 # DTB misses +system.cpu1.dtb.accesses 159552146 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1296,201 +1471,239 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 447940407 # ITB inst hits -system.cpu1.itb.inst_misses 68561 # ITB inst misses +system.cpu1.itb.walker.walks 55326 # Table walker walks requested +system.cpu1.itb.walker.walksLong 55326 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 571 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 49211 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 55326 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 55326 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 55326 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 49782 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 18533.691816 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 16693.913266 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 13345.941074 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-32767 47101 94.61% 94.61% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-65535 2168 4.35% 98.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-98303 178 0.36% 99.33% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::98304-131071 248 0.50% 99.83% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-163839 12 0.02% 99.85% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::163840-196607 16 0.03% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-229375 24 0.05% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::229376-262143 6 0.01% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-294911 18 0.04% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::294912-327679 3 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::360448-393215 3 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 49782 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -1199136648 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -1199136648 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -1199136648 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 49211 98.85% 98.85% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 571 1.15% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 49782 # Table walker page sizes translated +system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 55326 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 55326 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 49782 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 49782 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 105108 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 441493680 # ITB inst hits +system.cpu1.itb.inst_misses 55326 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 37660 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1002 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 26339 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 41330 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 25739 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 448008968 # ITB inst accesses -system.cpu1.itb.hits 447940407 # DTB hits -system.cpu1.itb.misses 68561 # DTB misses -system.cpu1.itb.accesses 448008968 # DTB accesses -system.cpu1.numCycles 94796862537 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 441549006 # ITB inst accesses +system.cpu1.itb.hits 441493680 # DTB hits +system.cpu1.itb.misses 55326 # DTB misses +system.cpu1.itb.accesses 441549006 # DTB accesses +system.cpu1.numCycles 94821563303 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 447645202 # Number of instructions committed -system.cpu1.committedOps 528119835 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 486291398 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 624474 # Number of float alu accesses -system.cpu1.num_func_calls 27450761 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 67545606 # number of instructions that are conditional controls -system.cpu1.num_int_insts 486291398 # number of integer instructions -system.cpu1.num_fp_insts 624474 # number of float instructions -system.cpu1.num_int_register_reads 698728829 # number of times the integer registers were read -system.cpu1.num_int_register_writes 384530758 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 985803 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 576512 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 114161169 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 113813296 # number of times the CC registers were written -system.cpu1.num_mem_refs 162934099 # number of memory refs -system.cpu1.num_load_insts 84972579 # Number of load instructions -system.cpu1.num_store_insts 77961520 # Number of store instructions -system.cpu1.num_idle_cycles 93770083152.566025 # Number of idle cycles -system.cpu1.num_busy_cycles 1026779384.433978 # Number of busy cycles -system.cpu1.not_idle_fraction 0.010831 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.989169 # Percentage of idle cycles -system.cpu1.Branches 100081816 # Number of branches fetched -system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 364276895 68.94% 68.94% # Class of executed instruction -system.cpu1.op_class::IntMult 1051011 0.20% 69.14% # Class of executed instruction -system.cpu1.op_class::IntDiv 60606 0.01% 69.15% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 92495 0.02% 69.17% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.17% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.17% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.17% # Class of executed instruction -system.cpu1.op_class::MemRead 84972579 16.08% 85.25% # Class of executed instruction -system.cpu1.op_class::MemWrite 77961520 14.75% 100.00% # Class of executed instruction +system.cpu1.committedInsts 441187041 # Number of instructions committed +system.cpu1.committedOps 519063105 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 477531543 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 364386 # Number of float alu accesses +system.cpu1.num_func_calls 26570520 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 66815511 # number of instructions that are conditional controls +system.cpu1.num_int_insts 477531543 # number of integer instructions +system.cpu1.num_fp_insts 364386 # number of float instructions +system.cpu1.num_int_register_reads 690361032 # number of times the integer registers were read +system.cpu1.num_int_register_writes 378560518 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 602629 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 273816 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 113424708 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 113111436 # number of times the CC registers were written +system.cpu1.num_mem_refs 159443034 # number of memory refs +system.cpu1.num_load_insts 83763663 # Number of load instructions +system.cpu1.num_store_insts 75679371 # Number of store instructions +system.cpu1.num_idle_cycles 93795188251.508850 # Number of idle cycles +system.cpu1.num_busy_cycles 1026375051.491154 # Number of busy cycles +system.cpu1.not_idle_fraction 0.010824 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.989176 # Percentage of idle cycles +system.cpu1.Branches 98214896 # Number of branches fetched +system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 358777055 69.08% 69.08% # Class of executed instruction +system.cpu1.op_class::IntMult 1052972 0.20% 69.28% # Class of executed instruction +system.cpu1.op_class::IntDiv 61499 0.01% 69.29% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 35293 0.01% 69.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.30% # Class of executed instruction +system.cpu1.op_class::MemRead 83763663 16.13% 85.43% # Class of executed instruction +system.cpu1.op_class::MemWrite 75679371 14.57% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 528415149 # Class of executed instruction +system.cpu1.op_class::total 519369853 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 13701 # number of quiesce instructions executed -system.cpu1.dcache.tags.replacements 5194711 # number of replacements -system.cpu1.dcache.tags.tagsinuse 457.134068 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 157559099 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5195223 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 30.327687 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8367548601000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 457.134068 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.892840 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.892840 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 415 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 331059949 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 331059949 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 79405575 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 79405575 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 74066119 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 74066119 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 191889 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 191889 # number of SoftPFReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 197632 # number of WriteInvalidateReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::total 197632 # number of WriteInvalidateReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1669680 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1669680 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1654141 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1654141 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 153471694 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 153471694 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 153663583 # number of overall hits -system.cpu1.dcache.overall_hits::total 153663583 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 2946837 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 2946837 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1283113 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1283113 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 571898 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 571898 # number of SoftPFReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 550709 # number of WriteInvalidateReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::total 550709 # number of WriteInvalidateReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 171203 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 171203 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 185528 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 185528 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 4229950 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 4229950 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 4801848 # number of overall misses -system.cpu1.dcache.overall_misses::total 4801848 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 41215882509 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 41215882509 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 19312866378 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 19312866378 # number of WriteReq miss cycles -system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 6595698094 # number of WriteInvalidateReq miss cycles -system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 6595698094 # number of WriteInvalidateReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2383654561 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 2383654561 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3901847697 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 3901847697 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1095500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1095500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 60528748887 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 60528748887 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 60528748887 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 60528748887 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 82352412 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 82352412 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 75349232 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 75349232 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 763787 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 763787 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 748341 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::total 748341 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1840883 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1840883 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1839669 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1839669 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 157701644 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 157701644 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 158465431 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 158465431 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035783 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.035783 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.017029 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.017029 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.748766 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.748766 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.735906 # miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.735906 # miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.093000 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.093000 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100849 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100849 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026822 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.026822 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.030302 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.030302 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13986.481950 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 13986.481950 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 15051.570967 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 15051.570967 # average WriteReq miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 11976.739247 # average WriteInvalidateReq miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 11976.739247 # average WriteInvalidateReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13922.971916 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13922.971916 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21031.044893 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21031.044893 # average StoreCondReq miss latency +system.cpu1.kern.inst.quiesce 13999 # number of quiesce instructions executed +system.cpu1.dcache.tags.replacements 4977655 # number of replacements +system.cpu1.dcache.tags.tagsinuse 421.597899 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 154271186 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 4978165 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 30.989569 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8379002972500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 421.597899 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.823433 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.823433 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 442 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 323862009 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 323862009 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 78232018 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 78232018 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 71864508 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 71864508 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 191698 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 191698 # number of SoftPFReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 211446 # number of WriteInvalidateReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::total 211446 # number of WriteInvalidateReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1712714 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1712714 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1673213 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1673213 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 150096526 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 150096526 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 150288224 # number of overall hits +system.cpu1.dcache.overall_hits::total 150288224 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 2870044 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 2870044 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1235849 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1235849 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 574884 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 574884 # number of SoftPFReq misses +system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 468795 # number of WriteInvalidateReq misses +system.cpu1.dcache.WriteInvalidateReq_misses::total 468795 # number of WriteInvalidateReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 161452 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 161452 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 199386 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 199386 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 4105893 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 4105893 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 4680777 # number of overall misses +system.cpu1.dcache.overall_misses::total 4680777 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 39400522531 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 39400522531 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 20561069776 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 20561069776 # number of WriteReq miss cycles +system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 12119187041 # number of WriteInvalidateReq miss cycles +system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 12119187041 # number of WriteInvalidateReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2308132257 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 2308132257 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4261474455 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 4261474455 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1966000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1966000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 59961592307 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 59961592307 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 59961592307 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 59961592307 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 81102062 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 81102062 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 73100357 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 73100357 # 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average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 12605.302976 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 12605.302976 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14603.788337 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 14603.788337 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 12810.179230 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 12810.179230 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1499,92 +1712,92 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # 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average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 13014.360756 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20305.114346 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20305.114346 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 9970.174640 # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 9970.174640 # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11226.218917 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11226.218917 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 18980.813155 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 18980.813155 # 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number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 51066568214 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 51066568214 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 61463717473 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 61463717473 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 4074474250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 4074474250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3958410750 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 3958410750 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 8032885000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 8032885000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035243 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035243 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.016902 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.016902 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.749932 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.749932 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.689160 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.689160 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.063309 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.063309 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106476 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106476 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026548 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026548 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030127 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.030127 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11561.350275 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11561.350275 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 14585.485290 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14585.485290 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18085.647294 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 18085.647294 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 23844.142875 # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 23844.142875 # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12025.119602 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12025.119602 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19320.546804 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19320.546804 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12185.511233 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12185.511233 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13155.611705 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13155.611705 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12474.075096 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12474.075096 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13165.060396 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13165.060396 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1592,59 +1805,59 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 5786522 # number of replacements -system.cpu1.icache.tags.tagsinuse 496.339295 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 442153368 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 5787034 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 76.404142 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8367526246000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.339295 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969413 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.969413 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 4937125 # number of replacements +system.cpu1.icache.tags.tagsinuse 496.391317 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 436556038 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 4937637 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 88.413960 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8378975635000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.391317 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969514 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.969514 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 339 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 108 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 239 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 901667853 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 901667853 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 442153368 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 442153368 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 442153368 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 442153368 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 442153368 # number of overall hits -system.cpu1.icache.overall_hits::total 442153368 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 5787039 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 5787039 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 5787039 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 5787039 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 5787039 # number of overall misses -system.cpu1.icache.overall_misses::total 5787039 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 50052191468 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 50052191468 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 50052191468 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 50052191468 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 50052191468 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 50052191468 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 447940407 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 447940407 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 447940407 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 447940407 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 447940407 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 447940407 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.012919 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.012919 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.012919 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.012919 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.012919 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.012919 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8649.015752 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8649.015752 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8649.015752 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8649.015752 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8649.015752 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8649.015752 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 887925002 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 887925002 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 436556038 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 436556038 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 436556038 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 436556038 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 436556038 # number of overall hits +system.cpu1.icache.overall_hits::total 436556038 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 4937642 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 4937642 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 4937642 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 4937642 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 4937642 # number of overall misses +system.cpu1.icache.overall_misses::total 4937642 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 50835870381 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 50835870381 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 50835870381 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 50835870381 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 50835870381 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 50835870381 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 441493680 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 441493680 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 441493680 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 441493680 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 441493680 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 441493680 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011184 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.011184 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011184 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.011184 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011184 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.011184 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10295.576387 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 10295.576387 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10295.576387 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 10295.576387 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10295.576387 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 10295.576387 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1653,384 +1866,377 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5787039 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 5787039 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 5787039 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 5787039 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 5787039 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 5787039 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 41368714588 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 41368714588 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 41368714588 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 41368714588 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 41368714588 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 41368714588 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9075250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9075250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9075250 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 9075250 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.012919 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.012919 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.012919 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.012919 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.012919 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.012919 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7148.511456 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7148.511456 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7148.511456 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 7148.511456 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7148.511456 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 7148.511456 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 4937642 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 4937642 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 4937642 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 4937642 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 4937642 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 4937642 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 43414323627 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 43414323627 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 43414323627 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 43414323627 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 43414323627 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 43414323627 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8951000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8951000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8951000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 8951000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011184 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011184 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011184 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.011184 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011184 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.011184 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8792.521537 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8792.521537 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8792.521537 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8792.521537 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8792.521537 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8792.521537 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 55302288 # number of hwpf identified -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 976452 # number of hwpf that were already in mshr -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 51578919 # number of hwpf that were already in the cache -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 9282 # number of hwpf that were already in the prefetch queue -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 584 # number of hwpf removed because MSHR allocated -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 2737051 # number of hwpf issued -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 4557576 # number of hwpf spanning a virtual page -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.l2cache.tags.replacements 3265247 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13732.593717 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 11929802 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 3281353 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 3.635635 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 9719592338000 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 3548.297662 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 58.425503 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 65.675774 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 758.406628 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2477.157386 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 6824.630764 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.216571 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003566 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004009 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.046289 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.151194 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.416542 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.838171 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 8592 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 40 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 7474 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 93 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 541 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 2721 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 4842 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 395 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 15 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 20 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 810 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 3409 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2963 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 229 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.524414 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002441 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.456177 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 249010603 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 249010603 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 204488 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 158918 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 5602514 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 2695724 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 8661644 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 3397427 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 3397427 # number of Writeback hits -system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 491178 # number of WriteInvalidateReq hits -system.cpu1.l2cache.WriteInvalidateReq_hits::total 491178 # number of WriteInvalidateReq hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 77109 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 77109 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 35497 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 35497 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 899510 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 899510 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 204488 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 158918 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 5602514 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 3595234 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 9561154 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 204488 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 158918 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 5602514 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 3595234 # number of overall hits -system.cpu1.l2cache.overall_hits::total 9561154 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 11072 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9747 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 184525 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 930664 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 1136008 # number of ReadReq misses -system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data 58187 # number of WriteInvalidateReq misses -system.cpu1.l2cache.WriteInvalidateReq_misses::total 58187 # number of WriteInvalidateReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 111708 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 111708 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 150027 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 150027 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 4 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 4 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 196006 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 196006 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 11072 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9747 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 184525 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 1126670 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 1332014 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 11072 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9747 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 184525 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 1126670 # number of overall misses -system.cpu1.l2cache.overall_misses::total 1332014 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 339143470 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 328936960 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 4835548618 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 27845292450 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 33348921498 # number of ReadReq miss cycles -system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.data 1715319866 # number of WriteInvalidateReq miss cycles -system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total 1715319866 # number of WriteInvalidateReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 2196780170 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 2196780170 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3055684059 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3055684059 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1008500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1008500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 6932150792 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 6932150792 # number of ReadExReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 339143470 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 328936960 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 4835548618 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 34777443242 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 40281072290 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 339143470 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 328936960 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 4835548618 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 34777443242 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 40281072290 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 215560 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 168665 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 5787039 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.data 3626388 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 9797652 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 3397427 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 3397427 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data 549365 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.l2cache.WriteInvalidateReq_accesses::total 549365 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 188817 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 188817 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 185524 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 185524 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 4 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 4 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1095516 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 1095516 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 215560 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 168665 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 5787039 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 4721904 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 10893168 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 215560 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 168665 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 5787039 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 4721904 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 10893168 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.051364 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.057789 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.031886 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.256637 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.115947 # miss rate for ReadReq accesses -system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data 0.105917 # miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.105917 # miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.591620 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.591620 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.808666 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.808666 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.prefetcher.num_hwpf_issued 6896094 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 6896721 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 539 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped +system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size +system.cpu1.l2cache.prefetcher.pfSpanPage 853759 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 1907013 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 13040.746764 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 10338978 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 1923015 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 5.376442 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 9789299685500 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 5807.381964 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 61.245810 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 78.947620 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2946.895146 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3156.020749 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 990.255474 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.354454 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003738 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004819 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.179864 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.192628 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.060440 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.795944 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1412 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 94 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14496 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 14 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 26 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 63 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 1121 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 188 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 9 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 79 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1044 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1799 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 10295 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1321 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.086182 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005737 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.884766 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 227501804 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 227501804 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 207163 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 127057 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.inst 4446186 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.data 2697591 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 7477997 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 3230902 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 3230902 # number of Writeback hits +system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 181429 # number of WriteInvalidateReq hits +system.cpu1.l2cache.WriteInvalidateReq_hits::total 181429 # number of WriteInvalidateReq hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 59189 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 59189 # number of UpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 31769 # 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average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16571.950039 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13824.139322 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13824.139322 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 201375 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 201375 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 27369.696466 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 27369.696466 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 23590.774025 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 26697.193393 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 21030.079325 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 23632.313965 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 23342.822566 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 23590.774025 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 26697.193393 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 21030.079325 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 23632.313965 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 25466.057437 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 24782.300723 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.222784 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 22828.151261 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 24354.897355 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22000.738481 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 22345.362493 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 22234.428550 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 46551.597527 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 46551.597527 # average HardPFReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 27079.147948 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 27079.147948 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16917.663474 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16917.663474 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13665.224287 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13665.224287 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 249333.166667 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 249333.166667 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 30989.120825 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 30989.120825 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 22828.151261 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 24354.897355 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22000.738481 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 24006.292202 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 23371.034447 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 22828.151261 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 24354.897355 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22000.738481 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 24006.292202 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 46551.597527 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 30095.390338 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -2040,65 +2246,66 @@ system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 13482596 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 10019474 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 22090 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 22090 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 3397427 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 3948207 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 669175 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 549365 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 394300 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 332875 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 429984 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 28 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 53 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1203009 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1101184 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 11574298 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 14922836 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 373561 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 511408 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 27382103 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 370370936 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 560535931 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1349320 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1724480 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 933980667 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 8332859 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 23404111 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.344949 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.475352 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 11132088 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 9059631 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 23142 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 23142 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 3230902 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 957658 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1110389 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 467130 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 407372 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 365584 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 452132 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 59 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 100 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1208854 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1057926 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 9875504 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 14402767 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 299311 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 504421 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 25082003 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 316009528 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 537745480 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1072416 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1728704 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 856556128 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 4579678 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 18388489 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 5.234421 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.423637 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 15330876 65.51% 65.51% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 8073235 34.49% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::5 14077834 76.56% 76.56% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::6 4310655 23.44% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 23404111 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 11646725084 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 18388489 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 10772824519 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 158989494 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 181931492 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 8682146940 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 7414134377 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7623277083 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7417250282 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 205120292 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 165377004 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 296049290 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 288475000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40487 # Transaction distribution -system.iobus.trans_dist::ReadResp 40487 # Transaction distribution -system.iobus.trans_dist::WriteReq 137083 # Transaction distribution -system.iobus.trans_dist::WriteResp 30163 # Transaction distribution +system.iobus.trans_dist::ReadReq 40416 # Transaction distribution +system.iobus.trans_dist::ReadResp 40416 # Transaction distribution +system.iobus.trans_dist::WriteReq 136984 # Transaction distribution +system.iobus.trans_dist::WriteResp 30064 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 106920 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48390 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48038 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -2108,18 +2315,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29756 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29704 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 123480 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231580 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231580 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 123076 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231644 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231644 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 355140 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48410 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 354800 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48058 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2129,18 +2336,18 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17674 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17645 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 156518 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7351088 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7351088 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 156137 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7351344 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7351344 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7509692 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36789000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7509567 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36527000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -2160,7 +2367,7 @@ system.iobus.reqLayer16.occupancy 12000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 22103000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 22064000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) @@ -2168,71 +2375,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 1044839337 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 1044902599 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 93320000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 93015000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 179372271 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 179432954 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115786 # number of replacements -system.iocache.tags.tagsinuse 11.223287 # Cycle average of tags in use +system.iocache.tags.replacements 115804 # number of replacements +system.iocache.tags.tagsinuse 11.285754 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115802 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115820 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9123835798000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 7.412555 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 3.810732 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.463285 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.238171 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.701455 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9175904776000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.836841 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.448912 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.239803 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.465557 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.705360 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1042467 # Number of tag accesses -system.iocache.tags.data_accesses 1042467 # Number of data accesses +system.iocache.tags.tag_accesses 1042755 # Number of tag accesses +system.iocache.tags.data_accesses 1042755 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8870 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8907 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8902 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8939 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 106920 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 106920 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8870 # number of demand (read+write) misses -system.iocache.demand_misses::total 8910 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8902 # number of demand (read+write) misses +system.iocache.demand_misses::total 8942 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8870 # 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number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 28897474974 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5984000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1958941092 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1964925092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5984000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1958941092 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1964925092 # number of overall miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28987663054 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 28987663054 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 6064000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1942659591 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1948723591 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 6064000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1942659591 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1948723591 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8870 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8907 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8902 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8939 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 106920 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 106920 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8870 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8910 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8902 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8942 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8870 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8910 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8902 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8942 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2246,55 +2453,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 152081.081081 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 220850.179481 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 220564.510161 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 154243.243243 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 218227.318692 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 217962.478018 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 119000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 119000 # average WriteReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270271.932043 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 270271.932043 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 149600 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 220850.179481 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 220530.313356 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 149600 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 220850.179481 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 220530.313356 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 225288 # number of cycles access was blocked +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 271115.441957 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 271115.441957 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 151600 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 218227.318692 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 217929.276560 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 151600 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 218227.318692 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 217929.276560 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 228501 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27401 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27689 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.221890 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.252411 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106886 # number of writebacks -system.iocache.writebacks::total 106886 # number of writebacks +system.iocache.writebacks::writebacks 106887 # number of writebacks +system.iocache.writebacks::total 106887 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8870 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8907 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8902 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8939 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106920 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 106920 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8870 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8910 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8902 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8942 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8870 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8910 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3703000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1497575112 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1501278112 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8902 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8942 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3783000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1479616613 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1483399613 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23337113496 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23337113496 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3904000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1497575112 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1501479112 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3904000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1497575112 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1501479112 # number of overall MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23427435940 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23427435940 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3984000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1479616613 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1483600613 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3984000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1479616613 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1483600613 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -2308,567 +2515,560 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 100081.081081 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 168835.976550 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 168550.366229 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 102243.243243 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 166211.706695 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 165946.930641 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218267.054770 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218267.054770 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 97600 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 168835.976550 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 168516.174186 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 97600 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 168835.976550 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 168516.174186 # average overall mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 219111.821362 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 219111.821362 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 99600 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 166211.706695 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 165913.734399 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 99600 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 166211.706695 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 165913.734399 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1310456 # number of replacements -system.l2c.tags.tagsinuse 64677.337118 # Cycle average of tags in use -system.l2c.tags.total_refs 7257968 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1373726 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 5.283418 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 5621833500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 9998.305247 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 56.991260 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 77.146603 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 791.679733 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4513.780403 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 23818.675732 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 150.211809 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 222.184258 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 784.998757 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 7219.989726 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 17043.373589 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.152562 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000870 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.001177 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.012080 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.068875 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.363444 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002292 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.003390 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.011978 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.110168 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.260061 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.986898 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 38915 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 205 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 24150 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::0 26 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 26 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 487 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 8729 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 29647 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 17 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 188 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 161 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 550 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5282 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 18136 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.593796 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.003128 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.368500 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 74054042 # Number of tag accesses -system.l2c.tags.data_accesses 74054042 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 5514 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4407 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 131001 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 549137 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 1653135 # 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average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 78910.521591 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 143164.885379 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 80811.348926 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 81644.349445 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 88155.649083 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 78013.313403 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 116882.902441 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 122676.753599 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 4412 # number of cycles access was blocked +system.l2c.tags.replacements 1354462 # number of replacements +system.l2c.tags.tagsinuse 64231.297434 # Cycle average of tags in use +system.l2c.tags.total_refs 4107458 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1415378 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.902022 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 9445810500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 19768.926665 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 228.224478 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 327.605712 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4403.400979 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 13076.363837 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 14280.609802 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 81.212634 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 119.963342 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2392.943065 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3574.441825 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 5977.605096 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.301650 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.003482 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.004999 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.067191 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.199529 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.217905 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001239 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.001830 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.036513 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.054542 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.091211 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.980092 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 11341 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 263 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 49312 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 100 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 2022 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 9219 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 259 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 991 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 9958 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 38095 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.173050 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.004013 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.752441 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 56299103 # Number of tag accesses +system.l2c.tags.data_accesses 56299103 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 5350 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 4570 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 461305 # 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mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.170592 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.150672 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.205710 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 69087.434095 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 73156.250000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 78305.495326 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 68538.072262 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130959.913250 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 68277.223160 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 69117.242978 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 75753.096273 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 67290.296268 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 104660.132462 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 113420.305476 # average ReadReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 19988.031585 # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 19972.307777 # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 19983.666335 # average WriteInvalidateReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10132.657589 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10106.550438 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10119.518973 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10124.336608 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10161.007397 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10142.318876 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 61378.878992 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 60517.887969 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 60954.895731 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 69087.434095 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 73156.250000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 78305.495326 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 66345.843103 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130959.913250 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 68277.223160 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 69117.242978 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75753.096273 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 65448.777271 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 104660.132462 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 110391.140090 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 69087.434095 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 73156.250000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 78305.495326 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 66345.843103 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130959.913250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 68277.223160 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 69117.242978 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75753.096273 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 65448.777271 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 104660.132462 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 110391.140090 # average overall mshr miss latency +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3786921248 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6014500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 6832242748 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 12871375746 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.310833 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.349003 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.102691 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.206075 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.443410 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.186815 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.208139 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.089341 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.154495 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.411296 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.229677 # mshr miss rate for ReadReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.776063 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.521612 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.689229 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.584496 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.627511 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.605641 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.632847 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.638128 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.635412 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.589079 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.524669 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.562469 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.310833 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.349003 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.102691 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.265836 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.443410 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.186815 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.208139 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.089341 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.206143 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.411296 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.250858 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.310833 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.349003 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.102691 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.265836 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.443410 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.186815 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.208139 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.089341 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.206143 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.411296 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.250858 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 68440.219644 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 69325.509796 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 64762.763882 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 70801.479758 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 115369.864860 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 68654.805769 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 70250.533120 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 64112.168470 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 70176.265391 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 117769.320522 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 95099.746219 # average ReadReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 22466.608046 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 20243.971628 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 21892.569988 # average WriteInvalidateReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10081.122986 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10172.643319 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10127.734904 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10094.514924 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10170.084593 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10131.367291 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 66785.676932 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 63285.951301 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 65436.965728 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 68440.219644 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 69325.509796 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 64762.763882 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 69412.984539 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 115369.864860 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 68654.805769 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 70250.533120 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 64112.168470 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 67729.415418 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 117769.320522 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 90866.823975 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 68440.219644 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 69325.509796 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 64762.763882 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 69412.984539 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 115369.864860 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 68654.805769 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 70250.533120 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 64112.168470 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 67729.415418 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 117769.320522 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 90866.823975 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -2883,58 +3083,58 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 1327465 # Transaction distribution -system.membus.trans_dist::ReadResp 1327465 # Transaction distribution -system.membus.trans_dist::WriteReq 37863 # Transaction distribution -system.membus.trans_dist::WriteResp 37863 # Transaction distribution -system.membus.trans_dist::Writeback 1017207 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 119813 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 119813 # Transaction distribution -system.membus.trans_dist::UpgradeReq 367379 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 281461 # Transaction distribution -system.membus.trans_dist::UpgradeResp 85028 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution -system.membus.trans_dist::ReadExReq 87184 # Transaction distribution -system.membus.trans_dist::ReadExResp 72708 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123480 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 841910 # Transaction distribution +system.membus.trans_dist::ReadResp 841910 # Transaction distribution +system.membus.trans_dist::WriteReq 38471 # Transaction distribution +system.membus.trans_dist::WriteResp 38471 # Transaction distribution +system.membus.trans_dist::Writeback 1161772 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 665270 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 665270 # Transaction distribution +system.membus.trans_dist::UpgradeReq 386597 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 321242 # Transaction distribution +system.membus.trans_dist::UpgradeResp 114625 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution +system.membus.trans_dist::ReadExReq 138806 # Transaction distribution +system.membus.trans_dist::ReadExResp 121371 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123076 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 22714 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4395675 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4541961 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 336541 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 336541 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4878502 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156518 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25442 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4847759 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4996369 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 336372 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 336372 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5332741 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156137 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 45428 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 143082804 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 143284954 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14125504 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14125504 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 157410458 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 581037 # Total snoops (count) -system.membus.snoop_fanout::samples 3119395 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50884 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 159245812 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 159453037 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14112640 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14112640 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 173565677 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 613627 # Total snoops (count) +system.membus.snoop_fanout::samples 3433927 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3119395 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3433927 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3119395 # Request fanout histogram -system.membus.reqLayer0.occupancy 101251489 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3433927 # Request fanout histogram +system.membus.reqLayer0.occupancy 100976496 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 55500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 19693498 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 22065500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 11963097483 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 18062213474 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 12443113804 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 9212060141 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 187409729 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 187637046 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -2978,45 +3178,45 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 7096727 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 7089473 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 37863 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 37863 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 2477309 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 127465 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 20542 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 430421 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 297353 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 727774 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 53 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 53 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 228196 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 228196 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8832957 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8435767 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 17268724 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 294458407 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 274483891 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 568942298 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1532220 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 10576474 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.010952 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.104077 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 4185645 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4178412 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38471 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38471 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 2302237 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 921111 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 814190 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 436280 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 333774 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 770054 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 100 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 100 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 280654 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 280654 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 7279651 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5709072 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 12988723 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 243910125 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 179631296 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 423541421 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1593139 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 8378399 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.013829 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.116780 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 10460641 98.90% 98.90% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 115833 1.10% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 8262536 98.62% 98.62% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 115863 1.38% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 10576474 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 15316484616 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 8378399 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 16938572035 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 7440499 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 7678500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 16737915607 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 11018810399 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 16438547163 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 9692180196 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt index e087cdc41..11eb5dd0c 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt @@ -1,138 +1,138 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.821204 # Number of seconds simulated -sim_ticks 51821203872000 # Number of ticks simulated -final_tick 51821203872000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.821157 # Number of seconds simulated +sim_ticks 51821157171000 # Number of ticks simulated +final_tick 51821157171000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 797175 # Simulator instruction rate (inst/s) -host_op_rate 936716 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 46008450754 # Simulator tick rate (ticks/s) -host_mem_usage 656028 # Number of bytes of host memory used -host_seconds 1126.34 # Real time elapsed on the host -sim_insts 897890420 # Number of instructions simulated -sim_ops 1055061464 # Number of ops (including micro ops) simulated +host_inst_rate 734878 # Simulator instruction rate (inst/s) +host_op_rate 863519 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 42416153440 # Simulator tick rate (ticks/s) +host_mem_usage 712380 # Number of bytes of host memory used +host_seconds 1221.73 # Real time elapsed on the host +sim_insts 897823750 # Number of instructions simulated +sim_ops 1054987960 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 274944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 280896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 5219828 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 52654408 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 402752 # Number of bytes read from this memory -system.physmem.bytes_read::total 58832828 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5219828 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5219828 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 79485888 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 267456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 270528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 5250612 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 52674824 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 383808 # Number of bytes read from this memory +system.physmem.bytes_read::total 58847228 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5250612 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5250612 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 79637568 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 79506468 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 4296 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 4389 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 121967 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 822738 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6293 # Number of read requests responded to by this memory -system.physmem.num_reads::total 959683 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1241967 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 79658148 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 4179 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 4227 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 122448 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 823057 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 5997 # Number of read requests responded to by this memory +system.physmem.num_reads::total 959908 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1244337 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1244540 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 5306 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 5420 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 100728 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1016078 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 7772 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1135304 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 100728 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 100728 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1533849 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1246910 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 5161 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 5220 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 101322 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1016473 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 7406 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1135583 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 101322 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 101322 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1536777 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 397 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1534246 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1533849 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 5306 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 5420 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 100728 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1016476 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 7772 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2669550 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 959683 # Number of read requests accepted -system.physmem.writeReqs 1860672 # Number of write requests accepted -system.physmem.readBursts 959683 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1860672 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 61376064 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 43648 # Total number of bytes read from write queue -system.physmem.bytesWritten 118595648 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 58832828 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 118938916 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 682 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 7593 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 36288 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 56975 # Per bank write bursts -system.physmem.perBankRdBursts::1 58359 # Per bank write bursts -system.physmem.perBankRdBursts::2 58716 # Per bank write bursts -system.physmem.perBankRdBursts::3 57264 # Per bank write bursts -system.physmem.perBankRdBursts::4 61545 # Per bank write bursts -system.physmem.perBankRdBursts::5 66145 # Per bank write bursts -system.physmem.perBankRdBursts::6 57228 # Per bank write bursts -system.physmem.perBankRdBursts::7 52937 # Per bank write bursts -system.physmem.perBankRdBursts::8 52189 # Per bank write bursts -system.physmem.perBankRdBursts::9 99547 # Per bank write bursts -system.physmem.perBankRdBursts::10 57680 # Per bank write bursts -system.physmem.perBankRdBursts::11 61393 # Per bank write bursts -system.physmem.perBankRdBursts::12 54506 # Per bank write bursts -system.physmem.perBankRdBursts::13 60286 # Per bank write bursts -system.physmem.perBankRdBursts::14 51564 # Per bank write bursts -system.physmem.perBankRdBursts::15 52667 # Per bank write bursts -system.physmem.perBankWrBursts::0 114739 # Per bank write bursts -system.physmem.perBankWrBursts::1 115397 # Per bank write bursts -system.physmem.perBankWrBursts::2 117633 # Per bank write bursts -system.physmem.perBankWrBursts::3 119136 # Per bank write bursts -system.physmem.perBankWrBursts::4 120318 # Per bank write bursts -system.physmem.perBankWrBursts::5 121968 # Per bank write bursts -system.physmem.perBankWrBursts::6 116613 # Per bank write bursts -system.physmem.perBankWrBursts::7 113695 # Per bank write bursts -system.physmem.perBankWrBursts::8 109286 # Per bank write bursts -system.physmem.perBankWrBursts::9 116370 # Per bank write bursts -system.physmem.perBankWrBursts::10 115629 # Per bank write bursts -system.physmem.perBankWrBursts::11 118249 # Per bank write bursts -system.physmem.perBankWrBursts::12 111968 # Per bank write bursts -system.physmem.perBankWrBursts::13 117797 # Per bank write bursts -system.physmem.perBankWrBursts::14 110347 # Per bank write bursts -system.physmem.perBankWrBursts::15 113912 # Per bank write bursts +system.physmem.bw_write::total 1537174 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1536777 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 5161 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 5220 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 101322 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1016870 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 7406 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2672757 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 959908 # Number of read requests accepted +system.physmem.writeReqs 1865455 # Number of write requests accepted +system.physmem.readBursts 959908 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1865455 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 61382336 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 51776 # Total number of bytes read from write queue +system.physmem.bytesWritten 118954432 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 58847228 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 119245028 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 809 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 6774 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 36275 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 56974 # Per bank write bursts +system.physmem.perBankRdBursts::1 60608 # Per bank write bursts +system.physmem.perBankRdBursts::2 56247 # Per bank write bursts +system.physmem.perBankRdBursts::3 58787 # Per bank write bursts +system.physmem.perBankRdBursts::4 55621 # Per bank write bursts +system.physmem.perBankRdBursts::5 61105 # Per bank write bursts +system.physmem.perBankRdBursts::6 53454 # Per bank write bursts +system.physmem.perBankRdBursts::7 55202 # Per bank write bursts +system.physmem.perBankRdBursts::8 54549 # Per bank write bursts +system.physmem.perBankRdBursts::9 101006 # Per bank write bursts +system.physmem.perBankRdBursts::10 57136 # Per bank write bursts +system.physmem.perBankRdBursts::11 59250 # Per bank write bursts +system.physmem.perBankRdBursts::12 54470 # Per bank write bursts +system.physmem.perBankRdBursts::13 61564 # Per bank write bursts +system.physmem.perBankRdBursts::14 57688 # Per bank write bursts +system.physmem.perBankRdBursts::15 55438 # Per bank write bursts +system.physmem.perBankWrBursts::0 113578 # Per bank write bursts +system.physmem.perBankWrBursts::1 118177 # Per bank write bursts +system.physmem.perBankWrBursts::2 119014 # Per bank write bursts +system.physmem.perBankWrBursts::3 122732 # Per bank write bursts +system.physmem.perBankWrBursts::4 115108 # Per bank write bursts +system.physmem.perBankWrBursts::5 118421 # Per bank write bursts +system.physmem.perBankWrBursts::6 110433 # Per bank write bursts +system.physmem.perBankWrBursts::7 110649 # Per bank write bursts +system.physmem.perBankWrBursts::8 111009 # Per bank write bursts +system.physmem.perBankWrBursts::9 115530 # Per bank write bursts +system.physmem.perBankWrBursts::10 116272 # Per bank write bursts +system.physmem.perBankWrBursts::11 116171 # Per bank write bursts +system.physmem.perBankWrBursts::12 116950 # Per bank write bursts +system.physmem.perBankWrBursts::13 121923 # Per bank write bursts +system.physmem.perBankWrBursts::14 117171 # Per bank write bursts +system.physmem.perBankWrBursts::15 115525 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 1 # Number of times write queue was full causing retry -system.physmem.totGap 51821201316000 # Total gap between requests +system.physmem.totGap 51821154615000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43101 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 916567 # Read request sizes (log2) +system.physmem.readPktSize::6 916792 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1858099 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 925038 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 28111 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2104 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 593 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 706 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 405 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 375 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 306 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 221 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 147 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 137 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 124 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 112 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 112 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 109 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 100 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 90 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 88 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 64 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 56 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1862882 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 923488 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 30071 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2080 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 548 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 693 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 382 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 338 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 271 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 197 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 132 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 113 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 103 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 102 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 100 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 96 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 84 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 78 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 56 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 45 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -159,120 +159,140 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 58079 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 70983 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 101652 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 104342 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 108305 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 122410 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 126456 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 111805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 113098 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 110863 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 108761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 105735 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 102887 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 101533 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 96838 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 95973 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 95806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 94380 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3424 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2906 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2427 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1880 # 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What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 68 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 58678 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 72148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 102041 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 104846 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 108153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 122813 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 127000 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 113028 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 114051 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 111714 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 109570 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 106267 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 103051 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 101586 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 96822 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 95736 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 95578 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 94283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 3053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 2654 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2224 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2079 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1599 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 925 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 811 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 637 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 502 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 379 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 307 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 269 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 242 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 1 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 617611 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 291.399266 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 166.446996 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 330.841680 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 256797 41.58% 41.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 151085 24.46% 66.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 51876 8.40% 74.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 29038 4.70% 79.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 19766 3.20% 82.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 13229 2.14% 84.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 10059 1.63% 86.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 9064 1.47% 87.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 76697 12.42% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 617611 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 92036 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 10.419705 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 106.178395 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 92034 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 618930 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 291.368084 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 166.608476 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 330.498173 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 256436 41.43% 41.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 152224 24.59% 66.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 51996 8.40% 74.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 28892 4.67% 79.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 20098 3.25% 82.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 13547 2.19% 84.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 10018 1.62% 86.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 9306 1.50% 87.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 76413 12.35% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 618930 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 92468 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 10.372118 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 105.903641 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 92466 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 92036 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 92036 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.134045 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.130429 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 10.695121 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 84651 91.98% 91.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 3801 4.13% 96.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 1276 1.39% 97.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 446 0.48% 97.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 607 0.66% 98.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 136 0.15% 98.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 198 0.22% 99.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 105 0.11% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 166 0.18% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 53 0.06% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 197 0.21% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 35 0.04% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 54 0.06% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 56 0.06% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 137 0.15% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 24 0.03% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 33 0.04% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 9 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 16 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 5 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 6 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 4 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 8 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-255 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-279 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 92036 # Writes before turning the bus around for reads -system.physmem.totQLat 12714966775 # Total ticks spent queuing -system.physmem.totMemAccLat 30696235525 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4795005000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13258.55 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 92468 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 92468 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.100608 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.118632 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 10.444453 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 55053 59.54% 59.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 30512 33.00% 92.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 2134 2.31% 94.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 1149 1.24% 96.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 862 0.93% 97.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 455 0.49% 97.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 271 0.29% 97.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 154 0.17% 97.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 523 0.57% 98.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 85 0.09% 98.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 63 0.07% 98.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 90 0.10% 98.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 138 0.15% 98.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 53 0.06% 99.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 45 0.05% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 77 0.08% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 126 0.14% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 47 0.05% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 24 0.03% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 42 0.05% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 157 0.17% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 6 0.01% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 21 0.02% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 16 0.02% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 59 0.06% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 9 0.01% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 28 0.03% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 35 0.04% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 128 0.14% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 15 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 2 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 6 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 16 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 15 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 3 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 7 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 10 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 3 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 3 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 5 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 4 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::212-215 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-219 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-251 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 92468 # Writes before turning the bus around for reads +system.physmem.totQLat 12424177254 # Total ticks spent queuing +system.physmem.totMemAccLat 30407283504 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4795495000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12954.01 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32008.55 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 31704.01 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.18 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.29 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 2.30 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.14 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.30 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s @@ -280,36 +300,41 @@ system.physmem.busUtil 0.03 # Da system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.23 # Average write queue length when enqueuing -system.physmem.readRowHits 722338 # Number of row buffer hits during reads -system.physmem.writeRowHits 1472108 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.32 # Row buffer hit rate for reads +system.physmem.avgWrQLen 24.29 # Average write queue length when enqueuing +system.physmem.readRowHits 722238 # Number of row buffer hits during reads +system.physmem.writeRowHits 1476593 # Number of row buffer hits during writes +system.physmem.readRowHitRate 75.30 # Row buffer hit rate for reads system.physmem.writeRowHitRate 79.44 # Row buffer hit rate for writes -system.physmem.avgGap 18373999.48 # Average gap between requests -system.physmem.pageHitRate 78.04 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 49686658091000 # Time in different power states -system.physmem.memoryStateTime::REF 1730423760000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 404121645500 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 2414648880 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 2254490280 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 1317516750 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 1230128625 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 3659518200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 3820650600 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 6087953520 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 5919855840 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 3384708874560 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 3384708874560 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 1312804436175 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 1305168623550 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 29941137312000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 29947835393250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 34652130260085 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 34650938016705 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.686370 # Core power per rank (mW) -system.physmem.averagePower::1 668.663363 # Core power per rank (mW) +system.physmem.avgGap 18341414.75 # Average gap between requests +system.physmem.pageHitRate 78.03 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2336584320 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1274922000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3572345400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 6014165760 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3384705823200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1308692927565 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29944715868000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34651312636245 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.671195 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49815023694250 # Time in different power states +system.physmem_0.memoryStateTime::REF 1730422200000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 275710901250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 2342526480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1278164250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3908587800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 6029970480 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3384705823200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1310912306640 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29942769044250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34651946423100 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.683425 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49811721549250 # Time in different power states +system.physmem_1.memoryStateTime::REF 1730422200000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 279009798250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory @@ -333,6 +358,14 @@ system.cf0.dma_write_full_pages 1666 # Nu system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -354,27 +387,81 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 215397 # Table walker walks requested +system.cpu.dtb.walker.walksLong 215397 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 16603 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 166513 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 14 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 215383 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 0.157858 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 54.935133 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-2047 215381 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::10240-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::22528-24575 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 215383 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 183130 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 21825.061432 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 17519.574906 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 14463.524428 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-32767 181175 98.93% 98.93% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::32768-65535 4 0.00% 98.93% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-98303 1496 0.82% 99.75% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::98304-131071 183 0.10% 99.85% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-163839 74 0.04% 99.89% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::163840-196607 58 0.03% 99.92% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-229375 49 0.03% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::229376-262143 36 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-294911 18 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::294912-327679 14 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-360447 8 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::360448-393215 11 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-491519 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 183130 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 800972760 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 2.488036 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 -1191876296 -148.80% -148.80% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::1 1992849056 248.80% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 800972760 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 166514 90.93% 90.93% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 16603 9.07% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 183117 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 215397 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 215397 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 183117 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 183117 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 398514 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 168646043 # DTB read hits -system.cpu.dtb.read_misses 158497 # DTB read misses -system.cpu.dtb.write_hits 153371607 # DTB write hits -system.cpu.dtb.write_misses 56347 # DTB write misses +system.cpu.dtb.read_hits 168647599 # DTB read hits +system.cpu.dtb.read_misses 158984 # DTB read misses +system.cpu.dtb.write_hits 153347297 # DTB write hits +system.cpu.dtb.write_misses 56413 # DTB write misses system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 43049 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_mva_asid 43021 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 74830 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 74349 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 7977 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 8039 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 19966 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 168804540 # DTB read accesses -system.cpu.dtb.write_accesses 153427954 # DTB write accesses +system.cpu.dtb.perms_faults 19949 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 168806583 # DTB read accesses +system.cpu.dtb.write_accesses 153403710 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 322017650 # DTB hits -system.cpu.dtb.misses 214844 # DTB misses -system.cpu.dtb.accesses 322232494 # DTB accesses +system.cpu.dtb.hits 321994896 # DTB hits +system.cpu.dtb.misses 215397 # DTB misses +system.cpu.dtb.accesses 322210293 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -396,56 +483,91 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 898442559 # ITB inst hits -system.cpu.itb.inst_misses 123457 # ITB inst misses +system.cpu.itb.walker.walks 123370 # Table walker walks requested +system.cpu.itb.walker.walksLong 123370 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1120 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 111048 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 123370 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 123370 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 123370 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 112168 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 24898.509379 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 20785.013360 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 17155.421945 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 109848 97.93% 97.93% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 2031 1.81% 99.74% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 132 0.12% 99.86% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 101 0.09% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 23 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 19 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 7 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::458752-524287 5 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 112168 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples -1257598296 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 -1257598296 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total -1257598296 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 111048 99.00% 99.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1120 1.00% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 112168 # Table walker page sizes translated +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 123370 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 123370 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 112168 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 112168 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 235538 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 898375907 # ITB inst hits +system.cpu.itb.inst_misses 123370 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 43049 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_mva_asid 43021 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 53017 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 52826 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 898566016 # ITB inst accesses -system.cpu.itb.hits 898442559 # DTB hits -system.cpu.itb.misses 123457 # DTB misses -system.cpu.itb.accesses 898566016 # DTB accesses -system.cpu.numCycles 103642407744 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 898499277 # ITB inst accesses +system.cpu.itb.hits 898375907 # DTB hits +system.cpu.itb.misses 123370 # DTB misses +system.cpu.itb.accesses 898499277 # DTB accesses +system.cpu.numCycles 103642314342 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 897890420 # Number of instructions committed -system.cpu.committedOps 1055061464 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 968615704 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 900077 # Number of float alu accesses -system.cpu.num_func_calls 53165114 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 137212632 # number of instructions that are conditional controls -system.cpu.num_int_insts 968615704 # number of integer instructions -system.cpu.num_fp_insts 900077 # number of float instructions -system.cpu.num_int_register_reads 1413530400 # number of times the integer registers were read -system.cpu.num_int_register_writes 768471074 # number of times the integer registers were written -system.cpu.num_fp_register_reads 1450010 # number of times the floating registers were read -system.cpu.num_fp_register_writes 764580 # number of times the floating registers were written -system.cpu.num_cc_register_reads 236283447 # number of times the CC registers were read -system.cpu.num_cc_register_writes 235682818 # number of times the CC registers were written -system.cpu.num_mem_refs 322001322 # number of memory refs -system.cpu.num_load_insts 168639088 # Number of load instructions -system.cpu.num_store_insts 153362234 # Number of store instructions -system.cpu.num_idle_cycles 100472196154.122070 # Number of idle cycles -system.cpu.num_busy_cycles 3170211589.877939 # Number of busy cycles -system.cpu.not_idle_fraction 0.030588 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.969412 # Percentage of idle cycles -system.cpu.Branches 200577010 # Number of branches fetched +system.cpu.committedInsts 897823750 # Number of instructions committed +system.cpu.committedOps 1054987960 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 968534129 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 900653 # Number of float alu accesses +system.cpu.num_func_calls 53156799 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 137185420 # number of instructions that are conditional controls +system.cpu.num_int_insts 968534129 # number of integer instructions +system.cpu.num_fp_insts 900653 # number of float instructions +system.cpu.num_int_register_reads 1413400107 # number of times the integer registers were read +system.cpu.num_int_register_writes 768429309 # number of times the integer registers were written +system.cpu.num_fp_register_reads 1451290 # number of times the floating registers were read +system.cpu.num_fp_register_writes 764324 # number of times the floating registers were written +system.cpu.num_cc_register_reads 236274909 # number of times the CC registers were read +system.cpu.num_cc_register_writes 235673566 # number of times the CC registers were written +system.cpu.num_mem_refs 321978685 # number of memory refs +system.cpu.num_load_insts 168640749 # Number of load instructions +system.cpu.num_store_insts 153337936 # Number of store instructions +system.cpu.num_idle_cycles 100474351324.032059 # Number of idle cycles +system.cpu.num_busy_cycles 3167963017.967939 # Number of busy cycles +system.cpu.not_idle_fraction 0.030566 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.969434 # Percentage of idle cycles +system.cpu.Branches 200551202 # Number of branches fetched system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 731218910 69.27% 69.27% # Class of executed instruction -system.cpu.op_class::IntMult 2226806 0.21% 69.48% # Class of executed instruction -system.cpu.op_class::IntDiv 99223 0.01% 69.49% # Class of executed instruction +system.cpu.op_class::IntAlu 731167173 69.27% 69.27% # Class of executed instruction +system.cpu.op_class::IntMult 2227672 0.21% 69.48% # Class of executed instruction +system.cpu.op_class::IntDiv 99245 0.01% 69.49% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 69.49% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 69.49% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 69.49% # Class of executed instruction @@ -472,122 +594,122 @@ system.cpu.op_class::SimdFloatMisc 110423 0.01% 69.50% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 69.50% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.50% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.50% # Class of executed instruction -system.cpu.op_class::MemRead 168639088 15.97% 85.47% # Class of executed instruction -system.cpu.op_class::MemWrite 153362234 14.53% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 168640749 15.98% 85.47% # Class of executed instruction +system.cpu.op_class::MemWrite 153337936 14.53% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1055656727 # Class of executed instruction +system.cpu.op_class::total 1055583241 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 16365 # number of quiesce instructions executed -system.cpu.dcache.tags.replacements 10282368 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.969706 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 311548704 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 10282880 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 30.297806 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 10281150 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.969700 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 311526777 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 10281662 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 30.299263 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 3093156250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.969706 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.969700 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999941 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999941 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 410 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 401 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 64 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1298012717 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1298012717 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 157556193 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 157556193 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 145511723 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 145511723 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 396994 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 396994 # number of SoftPFReq hits -system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 336687 # number of WriteInvalidateReq hits -system.cpu.dcache.WriteInvalidateReq_hits::total 336687 # number of WriteInvalidateReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3698345 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3698345 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 4003149 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 4003149 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 303067916 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 303067916 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 303464910 # number of overall hits -system.cpu.dcache.overall_hits::total 303464910 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 5344087 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 5344087 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2236666 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2236666 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1310162 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1310162 # number of SoftPFReq misses -system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1231947 # number of WriteInvalidateReq misses -system.cpu.dcache.WriteInvalidateReq_misses::total 1231947 # number of WriteInvalidateReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 306495 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 306495 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 4 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 7580753 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7580753 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 8890915 # number of overall misses -system.cpu.dcache.overall_misses::total 8890915 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 83712196260 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 83712196260 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 64378240535 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 64378240535 # number of WriteReq miss cycles -system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data 27514486506 # number of WriteInvalidateReq miss cycles -system.cpu.dcache.WriteInvalidateReq_miss_latency::total 27514486506 # number of WriteInvalidateReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4474608500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 4474608500 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 251501 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 251501 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 148090436795 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 148090436795 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 148090436795 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 148090436795 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 162900280 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 162900280 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 147748389 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 147748389 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 1707156 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 1707156 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1568634 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::total 1568634 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4004840 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 4004840 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 4003153 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 4003153 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 310648669 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 310648669 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 312355825 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 312355825 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032806 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.032806 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015138 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.015138 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.767453 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.767453 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.785363 # miss rate for WriteInvalidateReq accesses -system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.785363 # miss rate for WriteInvalidateReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.076531 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.076531 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.024403 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.024403 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.028464 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.028464 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15664.452368 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15664.452368 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28783.126553 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 28783.126553 # average WriteReq miss latency -system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 22334.147902 # average WriteInvalidateReq miss latency -system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 22334.147902 # average WriteInvalidateReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14599.287101 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14599.287101 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 62875.250000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 62875.250000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19535.056319 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19535.056319 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16656.377526 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16656.377526 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 1297920552 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1297920552 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 157560037 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 157560037 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 145486469 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 145486469 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 397138 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 397138 # number of SoftPFReq hits +system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 335387 # number of WriteInvalidateReq hits +system.cpu.dcache.WriteInvalidateReq_hits::total 335387 # number of WriteInvalidateReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3699332 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3699332 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 4002690 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 4002690 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 303046506 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 303046506 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 303443644 # number of overall hits +system.cpu.dcache.overall_hits::total 303443644 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 5342305 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 5342305 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2238545 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2238545 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1309963 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1309963 # number of SoftPFReq misses +system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1232790 # number of WriteInvalidateReq misses +system.cpu.dcache.WriteInvalidateReq_misses::total 1232790 # number of WriteInvalidateReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 305057 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 305057 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 7580850 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7580850 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 8890813 # number of overall misses +system.cpu.dcache.overall_misses::total 8890813 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 83595802503 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 83595802503 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 64185055523 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 64185055523 # number of WriteReq miss cycles +system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data 27578524507 # number of WriteInvalidateReq miss cycles +system.cpu.dcache.WriteInvalidateReq_miss_latency::total 27578524507 # number of WriteInvalidateReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4441396750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 4441396750 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 150000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 150000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 147780858026 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 147780858026 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 147780858026 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 147780858026 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 162902342 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 162902342 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 147725014 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 147725014 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 1707101 # 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average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 73000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17384.343160 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 17384.343160 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17023.064030 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 17023.064030 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -685,59 +807,59 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # 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Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 13792174 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 64.136642 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 31822438250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.892960 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999791 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999791 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 251 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 186 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 8 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 254 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 193 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 912299374 # Number of tag accesses -system.cpu.icache.tags.data_accesses 912299374 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 884585744 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 884585744 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 884585744 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 884585744 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 884585744 # number of overall hits -system.cpu.icache.overall_hits::total 884585744 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 13856815 # 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number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 898442559 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 898442559 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 898442559 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 898442559 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 898442559 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015423 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.015423 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.015423 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.015423 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.015423 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.015423 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13370.106441 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13370.106441 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13370.106441 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13370.106441 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13370.106441 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13370.106441 # average overall miss latency +system.cpu.icache.tags.tag_accesses 912168086 # Number of tag accesses +system.cpu.icache.tags.data_accesses 912168086 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 884583728 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 884583728 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 884583728 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 884583728 # 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number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 184446403226 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 184446403226 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 898375907 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 898375907 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 898375907 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 898375907 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 898375907 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 898375907 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015352 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.015352 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.015352 # 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number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 157525292015 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 157525292015 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 157525292015 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 157525292015 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 13792179 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 13792179 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 13792179 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 13792179 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 13792179 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 13792179 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 156833610274 # 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mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.015423 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.015423 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.015423 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.015423 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.015423 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11368.073545 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11368.073545 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11368.073545 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11368.073545 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11368.073545 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11368.073545 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.015352 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.015352 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.015352 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.015352 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.015352 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.015352 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11371.198871 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11371.198871 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11371.198871 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11371.198871 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11371.198871 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11371.198871 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 1326931 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65218.833700 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 27835482 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1389841 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 20.027818 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 1330655 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65236.148872 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 27755474 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1393687 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 19.915142 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 6373825000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 38602.265871 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 305.289253 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 445.157205 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 6377.971996 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 19488.149376 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.589024 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004658 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006793 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.097320 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.297366 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.995160 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 246 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 62664 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 246 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 399 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2454 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5481 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54290 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003754 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.956177 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 266276553 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 266276553 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 378716 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 250963 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 13777936 # 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average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 47500.250000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 47500.250000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61617.263057 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61617.263057 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 65814.594972 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 66260.822511 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62136.636697 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62370.072593 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62384.840746 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 65814.594972 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 66260.822511 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62136.636697 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62370.072593 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62384.840746 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.246111 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.246111 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.010861 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.016551 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005754 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.091088 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.038840 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.010861 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.016551 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005754 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.091088 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.038840 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 65693.527160 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 66687.544358 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61986.826021 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63479.273949 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63225.991053 # average ReadReq mshr miss latency +system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 21565.936570 # average WriteInvalidateReq mshr miss latency +system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 21565.936570 # average WriteInvalidateReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.708273 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.708273 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 60000 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 60000 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61281.495461 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61281.495461 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 65693.527160 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 66687.544358 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61986.826021 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62054.166126 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62086.457372 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 65693.527160 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 66687.544358 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61986.826021 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62054.166126 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62086.457372 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1067,58 +1189,58 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 21819690 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 21811671 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 21752331 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 21744344 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33872 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 33872 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 7918344 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1338611 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1231947 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 45612 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 4 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 45616 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2169953 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2169953 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 27799880 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 28711563 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 624328 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1010117 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 58145888 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 887008660 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1165125804 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2042816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3064096 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2057241376 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 474114 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 33215302 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.003479 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.058876 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::Writeback 7913457 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1339455 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1232790 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 45725 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 45727 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2171658 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2171658 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 27670608 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 28704497 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 624113 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1013195 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 58012413 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 882871956 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1164737260 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2043192 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3078296 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2052730704 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 473368 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 33145716 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.003486 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.058938 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 33099762 99.65% 99.65% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 115540 0.35% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 33030174 99.65% 99.65% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 115542 0.35% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 33215302 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 25772593750 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 33145716 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 25733748000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1282500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1332000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 20852498735 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 20755677476 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14430330552 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14427270036 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 369475750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 369197500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 627605250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 628893000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40402 # Transaction distribution -system.iobus.trans_dist::ReadResp 40402 # Transaction distribution +system.iobus.trans_dist::ReadReq 40403 # Transaction distribution +system.iobus.trans_dist::ReadResp 40403 # Transaction distribution system.iobus.trans_dist::WriteReq 136733 # Transaction distribution system.iobus.trans_dist::WriteResp 30069 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution @@ -1138,11 +1260,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231000 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231000 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231002 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231002 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354270 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 354272 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1159,11 +1281,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334432 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334432 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334440 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334440 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492838 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 7492846 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) @@ -1192,71 +1314,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 1042392405 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 1042395169 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 179042528 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 179037771 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115480 # number of replacements -system.iocache.tags.tagsinuse 10.457351 # Cycle average of tags in use +system.iocache.tags.replacements 115482 # number of replacements +system.iocache.tags.tagsinuse 10.457347 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115496 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115498 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13153949219000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.511147 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.946204 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.219447 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.434138 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13153920852000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.510781 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.946566 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.219424 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.434160 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.653584 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039857 # Number of tag accesses -system.iocache.tags.data_accesses 1039857 # Number of data accesses +system.iocache.tags.tag_accesses 1039866 # Number of tag accesses +system.iocache.tags.data_accesses 1039866 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8836 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8873 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8837 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8874 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8836 # number of demand (read+write) misses -system.iocache.demand_misses::total 8876 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8837 # number of demand (read+write) misses +system.iocache.demand_misses::total 8877 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8836 # number of overall misses -system.iocache.overall_misses::total 8876 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5485000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1916450860 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1921935860 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 8837 # number of overall misses +system.iocache.overall_misses::total 8877 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5479000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1901914612 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1907393612 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 339000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 339000 # number of WriteReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28823836017 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 28823836017 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5824000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1916450860 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1922274860 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5824000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1916450860 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1922274860 # number of overall miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28843036786 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 28843036786 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5818000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1901914612 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1907732612 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5818000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1901914612 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1907732612 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8836 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8873 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8837 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8874 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8836 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8876 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8837 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8877 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8836 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8876 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8837 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8877 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1270,55 +1392,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 148243.243243 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 216891.224536 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 216604.965626 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 148081.081081 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 215221.750820 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 214941.808880 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 113000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 113000 # average WriteReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270230.218415 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 270230.218415 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 145600 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 216891.224536 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 216569.948175 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 145600 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 216891.224536 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 216569.948175 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 223291 # number of cycles access was blocked +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270410.230125 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 270410.230125 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 145450 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 215221.750820 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 214907.357441 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 145450 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 215221.750820 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 214907.357441 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 223600 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27458 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27526 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.132093 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.123229 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106629 # number of writebacks -system.iocache.writebacks::total 106629 # number of writebacks +system.iocache.writebacks::writebacks 106630 # number of writebacks +system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8836 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8873 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8837 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8874 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106664 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 106664 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8836 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8876 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8837 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8877 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8836 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8876 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3561000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1456881862 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1460442862 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8837 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8877 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3555000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1442304112 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1445859112 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 183000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 183000 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23277254071 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23277254071 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3744000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1456881862 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1460625862 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3744000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1456881862 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1460625862 # number of overall MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23296466828 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23296466828 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3738000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1442304112 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1446042112 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3738000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1442304112 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1446042112 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1332,71 +1454,71 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 96243.243243 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 164880.246944 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 164594.033810 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 96081.081081 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 163211.962431 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 162932.061303 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 61000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218229.712658 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218229.712658 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 93600 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 164880.246944 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 164559.020054 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 93600 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 164880.246944 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 164559.020054 # average overall mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218409.836758 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218409.836758 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 93450 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 163211.962431 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 162897.613158 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 93450 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 163211.962431 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 162897.613158 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 462201 # Transaction distribution -system.membus.trans_dist::ReadResp 462201 # Transaction distribution +system.membus.trans_dist::ReadReq 463332 # Transaction distribution +system.membus.trans_dist::ReadResp 463332 # Transaction distribution system.membus.trans_dist::WriteReq 33872 # Transaction distribution system.membus.trans_dist::WriteResp 33872 # Transaction distribution -system.membus.trans_dist::Writeback 1241967 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 616132 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 616132 # Transaction distribution -system.membus.trans_dist::UpgradeReq 36293 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 4 # Transaction distribution -system.membus.trans_dist::UpgradeResp 36297 # Transaction distribution -system.membus.trans_dist::ReadExReq 534513 # Transaction distribution -system.membus.trans_dist::ReadExResp 534513 # Transaction distribution +system.membus.trans_dist::Writeback 1244337 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 618545 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 618545 # Transaction distribution +system.membus.trans_dist::UpgradeReq 36281 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 36283 # Transaction distribution +system.membus.trans_dist::ReadExReq 533903 # Transaction distribution +system.membus.trans_dist::ReadExResp 533903 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 123190 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6942 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4139437 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4269627 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335126 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 335126 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4604753 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4147646 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4277836 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 334832 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 334832 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4612668 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 156320 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13884 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 163718240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 163888576 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14053504 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14053504 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 177942080 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3244 # Total snoops (count) -system.membus.snoop_fanout::samples 2814199 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 164057632 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 164227968 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14034624 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14034624 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 178262592 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3539 # Total snoops (count) +system.membus.snoop_fanout::samples 2819489 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2814199 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2819489 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2814199 # Request fanout histogram -system.membus.reqLayer0.occupancy 106092500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2819489 # Request fanout histogram +system.membus.reqLayer0.occupancy 106085000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 31000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5680000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5679999 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 17856822743 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 17900056737 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 9254301682 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 9260714451 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 186599472 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 186597229 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt index 72bc2e01a..5213927ce 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 51.111151 # Nu sim_ticks 51111150553500 # Number of ticks simulated final_tick 51111150553500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1088550 # Simulator instruction rate (inst/s) -host_op_rate 1279225 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56496360239 # Simulator tick rate (ticks/s) -host_mem_usage 672572 # Number of bytes of host memory used -host_seconds 904.68 # Real time elapsed on the host +host_inst_rate 1151312 # Simulator instruction rate (inst/s) +host_op_rate 1352981 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59753764865 # Simulator tick rate (ticks/s) +host_mem_usage 728116 # Number of bytes of host memory used +host_seconds 855.36 # Real time elapsed on the host sim_insts 984789519 # Number of instructions simulated sim_ops 1157289961 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -92,6 +92,14 @@ system.cf0.dma_write_full_pages 1666 # Nu system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -113,6 +121,24 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.walker.walks 144982 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 144982 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 144982 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 144982 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 144982 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 108340 85.69% 85.69% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 18088 14.31% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 126428 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 144982 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 144982 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 126428 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 126428 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 271410 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses system.cpu0.dtb.read_hits 91965302 # DTB read hits @@ -134,6 +160,14 @@ system.cpu0.dtb.inst_accesses 0 # IT system.cpu0.dtb.hits 176331252 # DTB hits system.cpu0.dtb.misses 144982 # DTB misses system.cpu0.dtb.accesses 176476234 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -155,6 +189,24 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.itb.walker.walks 70785 # Table walker walks requested +system.cpu0.itb.walker.walksLong 70785 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walkWaitTime::samples 70785 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 70785 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 70785 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 62159 96.07% 96.07% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 2545 3.93% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 64704 # Table walker page sizes translated +system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 70785 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 70785 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 64704 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 64704 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 135489 # Table walker requests started/completed, data/inst system.cpu0.itb.inst_hits 493804573 # ITB inst hits system.cpu0.itb.inst_misses 70785 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits @@ -424,6 +476,14 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -445,6 +505,24 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.walker.walks 143312 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 143312 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walkWaitTime::samples 143312 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 143312 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 143312 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walksPending::samples 1000001000 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1000001000 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 1000001000 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 106567 85.62% 85.62% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 17903 14.38% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 124470 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 143312 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 143312 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 124470 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 124470 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 267782 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses system.cpu1.dtb.read_hits 92072581 # DTB read hits @@ -466,6 +544,14 @@ system.cpu1.dtb.inst_accesses 0 # IT system.cpu1.dtb.hits 175979862 # DTB hits system.cpu1.dtb.misses 143312 # DTB misses system.cpu1.dtb.accesses 176123174 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -487,6 +573,24 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.itb.walker.walks 69790 # Table walker walks requested +system.cpu1.itb.walker.walksLong 69790 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walkWaitTime::samples 69790 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 69790 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 69790 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 61179 95.99% 95.99% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 2554 4.01% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 63733 # Table walker page sizes translated +system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 69790 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 69790 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 63733 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 63733 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 133523 # Table walker requests started/completed, data/inst system.cpu1.itb.inst_hits 491448225 # ITB inst hits system.cpu1.itb.inst_misses 69790 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits |