diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:43 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:43 -0600 |
| commit | 4f8d1a4cef2b23b423ea083078cd933c66c88e2a (patch) | |
| tree | c6d7d7567ead8bc2fe34bbf35604cc10d50dd72c /tests/quick/fs/10.linux-boot/ref/arm | |
| parent | 542d0ceebca1d24bfb433ce9fe916b0586f8d029 (diff) | |
| download | gem5-4f8d1a4cef2b23b423ea083078cd933c66c88e2a.tar.xz | |
stats: update stats for insts/ops and master id changes
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm')
12 files changed, 1189 insertions, 2089 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr index 04178bb32..614929bfc 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr @@ -1,18 +1,11 @@ -warn: Sockets disabled, not accepting vnc client connections -warn: Sockets disabled, not accepting terminal connections -warn: Sockets disabled, not accepting gdb connections -warn: The clidr register always reports 0 caches. -warn: clidr LoUIS field of 0b001 to match current ARM implementations. -warn: The csselr register isn't implemented. -warn: The ccsidr register isn't implemented and always reads as 0. -warn: instruction 'mcr bpiallis' unimplemented -warn: instruction 'mcr icialluis' unimplemented -warn: instruction 'mcr dccimvac' unimplemented -warn: instruction 'mcr dccmvau' unimplemented -warn: instruction 'mcr icimvau' unimplemented -warn: instruction 'mcr bpiallis' unimplemented -warn: LCD dual screen mode not supported -warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors -warn: instruction 'mcr icialluis' unimplemented -warn: instruction 'mcr icialluis' unimplemented -hack: be nice to actually delete the event here +Traceback (most recent call last): + File "<string>", line 1, in <module> + File "/tmp/gem5.ali/src/python/m5/main.py", line 357, in main + exec filecode in scope + File "tests/run.py", line 70, in <module> + execfile(joinpath(tests_root, 'configs', test_filename + '.py')) + File "tests/configs/realview-simple-atomic-dual.py", line 86, in <module> + system.l2c.num_cpus = 2 + File "/tmp/gem5.ali/src/python/m5/SimObject.py", line 725, in __setattr__ + % (self.__class__.__name__, attr) +AttributeError: Class L2 has no parameter num_cpus diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout index 417579719..d3606030f 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout @@ -1,12 +1,7 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:21:22 -gem5 started Jan 23 2012 04:25:02 +gem5 compiled Feb 11 2012 13:10:40 +gem5 started Feb 11 2012 15:37:03 gem5 executing on zizzer -command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic-dual -re tests/run.py build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic-dual -Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 -info: Using bootloader at address 0x80000000 -info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2411694099500 because m5_exit instruction encountered +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index 2ca0aa5cb..e69de29bb 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -1,719 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 2.411694 # Number of seconds simulated -sim_ticks 2411694099500 # Number of ticks simulated -final_tick 2411694099500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2039542 # Simulator instruction rate (inst/s) -host_tick_rate 61821688958 # Simulator tick rate (ticks/s) -host_mem_usage 378872 # Number of bytes of host memory used -host_seconds 39.01 # Real time elapsed on the host -sim_insts 79563488 # Number of instructions simulated -system.nvmem.bytes_read 68 # Number of bytes read from this memory -system.nvmem.bytes_inst_read 68 # Number of instructions bytes read from this memory -system.nvmem.bytes_written 0 # Number of bytes written to this memory -system.nvmem.num_reads 17 # Number of read requests responded to by this memory -system.nvmem.num_writes 0 # Number of write requests responded to by this memory -system.nvmem.num_other 0 # Number of other requests responded to by this memory -system.nvmem.bw_read 28 # Total read bandwidth from this memory (bytes/s) -system.nvmem.bw_inst_read 28 # Instruction read bandwidth from this memory (bytes/s) -system.nvmem.bw_total 28 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytes_read 123270308 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1011392 # Number of instructions bytes read from this memory -system.physmem.bytes_written 10185232 # Number of bytes written to this memory -system.physmem.num_reads 14146769 # Number of read requests responded to by this memory -system.physmem.num_writes 869038 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 51113575 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 419370 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 4223269 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 55336844 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 127720 # number of replacements -system.l2c.tagsinuse 25547.920863 # Cycle average of tags in use -system.l2c.total_refs 1498989 # Total number of references to valid blocks. -system.l2c.sampled_refs 156132 # Sample count of references to valid blocks. -system.l2c.avg_refs 9.600780 # Average number of references to valid blocks. -system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 4404.089299 # Average occupied blocks per context -system.l2c.occ_blocks::1 6217.918720 # Average occupied blocks per context -system.l2c.occ_blocks::2 14925.912843 # Average occupied blocks per context -system.l2c.occ_percent::0 0.067201 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.094878 # Average percentage of cache occupancy -system.l2c.occ_percent::2 0.227751 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 706190 # number of ReadReq hits -system.l2c.ReadReq_hits::1 499815 # number of ReadReq hits -system.l2c.ReadReq_hits::2 12920 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1218925 # number of ReadReq hits -system.l2c.Writeback_hits::0 580461 # number of Writeback hits -system.l2c.Writeback_hits::total 580461 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 776 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::1 523 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1299 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::0 147 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::1 202 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 349 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::0 64831 # number of ReadExReq hits -system.l2c.ReadExReq_hits::1 37797 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 102628 # number of ReadExReq hits -system.l2c.demand_hits::0 771021 # number of demand (read+write) hits -system.l2c.demand_hits::1 537612 # number of demand (read+write) hits -system.l2c.demand_hits::2 12920 # number of demand (read+write) hits -system.l2c.demand_hits::total 1321553 # number of demand (read+write) hits -system.l2c.overall_hits::0 771021 # number of overall hits -system.l2c.overall_hits::1 537612 # number of overall hits -system.l2c.overall_hits::2 12920 # number of overall hits -system.l2c.overall_hits::total 1321553 # number of overall hits -system.l2c.ReadReq_misses::0 19675 # number of ReadReq misses -system.l2c.ReadReq_misses::1 15224 # number of ReadReq misses -system.l2c.ReadReq_misses::2 52 # number of ReadReq misses -system.l2c.ReadReq_misses::total 34951 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 6349 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::1 3492 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 9841 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::0 791 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::1 531 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1322 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::0 99048 # number of ReadExReq misses -system.l2c.ReadExReq_misses::1 48785 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 147833 # number of ReadExReq misses -system.l2c.demand_misses::0 118723 # number of demand (read+write) misses -system.l2c.demand_misses::1 64009 # number of demand (read+write) misses -system.l2c.demand_misses::2 52 # number of demand (read+write) misses -system.l2c.demand_misses::total 182784 # number of demand (read+write) misses -system.l2c.overall_misses::0 118723 # number of overall misses -system.l2c.overall_misses::1 64009 # number of overall misses -system.l2c.overall_misses::2 52 # number of overall misses -system.l2c.overall_misses::total 182784 # number of overall misses -system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 0 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 725865 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 515039 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::2 12972 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1253876 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 580461 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 580461 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 7125 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::1 4015 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 11140 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::0 938 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::1 733 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1671 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 163879 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::1 86582 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 250461 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 889744 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 601621 # number of demand (read+write) accesses -system.l2c.demand_accesses::2 12972 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1504337 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 889744 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 601621 # number of overall (read+write) accesses -system.l2c.overall_accesses::2 12972 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1504337 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.027106 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.029559 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::2 0.004009 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.060673 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.891088 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::1 0.869738 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::0 0.843284 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::1 0.724420 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.604397 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::1 0.563454 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.133435 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.106394 # miss rate for demand accesses -system.l2c.demand_miss_rate::2 0.004009 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.243838 # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.133435 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.106394 # miss rate for overall accesses -system.l2c.overall_miss_rate::2 0.004009 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.243838 # miss rate for overall accesses -system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency -system.l2c.demand_avg_miss_latency::2 0 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 0 # average overall miss latency -system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency -system.l2c.overall_avg_miss_latency::2 0 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 0 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 111818 # number of writebacks -system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits 0 # number of overall MSHR hits -system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 0 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::2 0 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::2 0 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0 # mshr miss rate for overall accesses -system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated -system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. -system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. -system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu0.dtb.inst_hits 0 # ITB inst hits -system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 9339288 # DTB read hits -system.cpu0.dtb.read_misses 5153 # DTB read misses -system.cpu0.dtb.write_hits 6907876 # DTB write hits -system.cpu0.dtb.write_misses 1048 # DTB write misses -system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2247 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 150 # Number of TLB faults due to prefetch -system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 9344441 # DTB read accesses -system.cpu0.dtb.write_accesses 6908924 # DTB write accesses -system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 16247164 # DTB hits -system.cpu0.dtb.misses 6201 # DTB misses -system.cpu0.dtb.accesses 16253365 # DTB accesses -system.cpu0.itb.inst_hits 34822552 # ITB inst hits -system.cpu0.itb.inst_misses 2978 # ITB inst misses -system.cpu0.itb.read_hits 0 # DTB read hits -system.cpu0.itb.read_misses 0 # DTB read misses -system.cpu0.itb.write_hits 0 # DTB write hits -system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1462 # Number of entries that have been flushed from TLB -system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu0.itb.read_accesses 0 # DTB read accesses -system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 34825530 # ITB inst accesses -system.cpu0.itb.hits 34822552 # DTB hits -system.cpu0.itb.misses 2978 # DTB misses -system.cpu0.itb.accesses 34825530 # DTB accesses -system.cpu0.numCycles 4823340800 # number of cpu cycles simulated -system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.num_insts 44975797 # Number of instructions executed -system.cpu0.num_int_alu_accesses 39858123 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 4945 # Number of float alu accesses -system.cpu0.num_func_calls 1311755 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4494669 # number of instructions that are conditional controls -system.cpu0.num_int_insts 39858123 # number of integer instructions -system.cpu0.num_fp_insts 4945 # number of float instructions -system.cpu0.num_int_register_reads 202125744 # number of times the integer registers were read -system.cpu0.num_int_register_writes 42204131 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3641 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1308 # number of times the floating registers were written -system.cpu0.num_mem_refs 17030946 # number of memory refs -system.cpu0.num_load_insts 9786549 # Number of load instructions -system.cpu0.num_store_insts 7244397 # Number of store instructions -system.cpu0.num_idle_cycles 4777543068.852608 # Number of idle cycles -system.cpu0.num_busy_cycles 45797731.147393 # Number of busy cycles -system.cpu0.not_idle_fraction 0.009495 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.990505 # Percentage of idle cycles -system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 59311 # number of quiesce instructions executed -system.cpu0.icache.replacements 504460 # number of replacements -system.cpu0.icache.tagsinuse 511.627588 # Cycle average of tags in use -system.cpu0.icache.total_refs 34319155 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 504972 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 67.962491 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 64519524000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::0 511.627588 # Average occupied blocks per context -system.cpu0.icache.occ_percent::0 0.999273 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::0 34319155 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 34319155 # number of ReadReq hits -system.cpu0.icache.demand_hits::0 34319155 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 34319155 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::0 34319155 # number of overall hits -system.cpu0.icache.overall_hits::1 0 # number of overall hits -system.cpu0.icache.overall_hits::total 34319155 # number of overall hits -system.cpu0.icache.ReadReq_misses::0 504973 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 504973 # number of ReadReq misses -system.cpu0.icache.demand_misses::0 504973 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 504973 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::0 504973 # number of overall misses -system.cpu0.icache.overall_misses::1 0 # number of overall misses -system.cpu0.icache.overall_misses::total 504973 # number of overall misses -system.cpu0.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency 0 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::0 34824128 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 34824128 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::0 34824128 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 34824128 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::0 34824128 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 34824128 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::0 0.014501 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::0 0.014501 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::0 0.014501 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.icache.demand_avg_miss_latency::0 0 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::1 no_value # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total no_value # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::0 0 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::1 no_value # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total no_value # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu0.icache.fast_writes 0 # number of fast writes performed -system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks 24728 # number of writebacks -system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu0.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses -system.cpu0.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 380107 # number of replacements -system.cpu0.dcache.tagsinuse 479.716402 # Cycle average of tags in use -system.cpu0.dcache.total_refs 14708286 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 380619 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 38.643068 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 22115000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::0 479.716402 # Average occupied blocks per context -system.cpu0.dcache.occ_percent::0 0.936946 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::0 7803296 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7803296 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::0 6534059 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 6534059 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::0 172314 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 172314 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::0 174866 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 174866 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::0 14337355 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 14337355 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::0 14337355 # number of overall hits -system.cpu0.dcache.overall_hits::1 0 # number of overall hits -system.cpu0.dcache.overall_hits::total 14337355 # number of overall hits -system.cpu0.dcache.ReadReq_misses::0 237350 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 237350 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::0 183580 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 183580 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::0 9878 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 9878 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::0 7293 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7293 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::0 420930 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 420930 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::0 420930 # number of overall misses -system.cpu0.dcache.overall_misses::1 0 # number of overall misses -system.cpu0.dcache.overall_misses::total 420930 # number of overall misses -system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::0 8040646 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8040646 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::0 6717639 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 6717639 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::0 182192 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 182192 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::0 182159 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 182159 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::0 14758285 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 14758285 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::0 14758285 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 14758285 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::0 0.029519 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::0 0.027328 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.054218 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::0 0.040036 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::0 0.028522 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::0 0.028522 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.dcache.demand_avg_miss_latency::0 0 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total no_value # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::0 0 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total no_value # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu0.dcache.fast_writes 0 # number of fast writes performed -system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks 339627 # number of writebacks -system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses -system.cpu0.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dtb.inst_hits 0 # ITB inst hits -system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 6258230 # DTB read hits -system.cpu1.dtb.read_misses 2159 # DTB read misses -system.cpu1.dtb.write_hits 4713962 # DTB write hits -system.cpu1.dtb.write_misses 1181 # DTB write misses -system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1498 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 92 # Number of TLB faults due to prefetch -system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 6260389 # DTB read accesses -system.cpu1.dtb.write_accesses 4715143 # DTB write accesses -system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 10972192 # DTB hits -system.cpu1.dtb.misses 3340 # DTB misses -system.cpu1.dtb.accesses 10975532 # DTB accesses -system.cpu1.itb.inst_hits 27739434 # ITB inst hits -system.cpu1.itb.inst_misses 1388 # ITB inst misses -system.cpu1.itb.read_hits 0 # DTB read hits -system.cpu1.itb.read_misses 0 # DTB read misses -system.cpu1.itb.write_hits 0 # DTB write hits -system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1342 # Number of entries that have been flushed from TLB -system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu1.itb.read_accesses 0 # DTB read accesses -system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 27740822 # ITB inst accesses -system.cpu1.itb.hits 27739434 # DTB hits -system.cpu1.itb.misses 1388 # DTB misses -system.cpu1.itb.accesses 27740822 # DTB accesses -system.cpu1.numCycles 4822838236 # number of cpu cycles simulated -system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.num_insts 34587691 # Number of instructions executed -system.cpu1.num_int_alu_accesses 30998246 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 5772 # Number of float alu accesses -system.cpu1.num_func_calls 758024 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3375080 # number of instructions that are conditional controls -system.cpu1.num_int_insts 30998246 # number of integer instructions -system.cpu1.num_fp_insts 5772 # number of float instructions -system.cpu1.num_int_register_reads 156835040 # number of times the integer registers were read -system.cpu1.num_int_register_writes 33469179 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 3980 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1792 # number of times the floating registers were written -system.cpu1.num_mem_refs 11415835 # number of memory refs -system.cpu1.num_load_insts 6478994 # Number of load instructions -system.cpu1.num_store_insts 4936841 # Number of store instructions -system.cpu1.num_idle_cycles 4787960178.177661 # Number of idle cycles -system.cpu1.num_busy_cycles 34878057.822339 # Number of busy cycles -system.cpu1.not_idle_fraction 0.007232 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.992768 # Percentage of idle cycles -system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 33011 # number of quiesce instructions executed -system.cpu1.icache.replacements 374406 # number of replacements -system.cpu1.icache.tagsinuse 498.143079 # Cycle average of tags in use -system.cpu1.icache.total_refs 27365572 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 374918 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 72.990819 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 69956143000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::0 498.143079 # Average occupied blocks per context -system.cpu1.icache.occ_percent::0 0.972936 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::0 27365572 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 27365572 # number of ReadReq hits -system.cpu1.icache.demand_hits::0 27365572 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 27365572 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::0 27365572 # number of overall hits -system.cpu1.icache.overall_hits::1 0 # number of overall hits -system.cpu1.icache.overall_hits::total 27365572 # number of overall hits -system.cpu1.icache.ReadReq_misses::0 374920 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 374920 # number of ReadReq misses -system.cpu1.icache.demand_misses::0 374920 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 374920 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::0 374920 # number of overall misses -system.cpu1.icache.overall_misses::1 0 # number of overall misses -system.cpu1.icache.overall_misses::total 374920 # number of overall misses -system.cpu1.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency 0 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::0 27740492 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 27740492 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::0 27740492 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 27740492 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::0 27740492 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 27740492 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::0 0.013515 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::0 0.013515 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::0 0.013515 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.icache.demand_avg_miss_latency::0 0 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::1 no_value # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total no_value # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::0 0 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::1 no_value # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total no_value # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu1.icache.fast_writes 0 # number of fast writes performed -system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks 13905 # number of writebacks -system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu1.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses -system.cpu1.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 247434 # number of replacements -system.cpu1.dcache.tagsinuse 444.903488 # Cycle average of tags in use -system.cpu1.dcache.total_refs 9876826 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 247805 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 39.857251 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 69253206000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::0 444.903488 # Average occupied blocks per context -system.cpu1.dcache.occ_percent::0 0.868952 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::0 5955973 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 5955973 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::0 3777038 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 3777038 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::0 59593 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 59593 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::0 60090 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 60090 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::0 9733011 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 9733011 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::0 9733011 # number of overall hits -system.cpu1.dcache.overall_hits::1 0 # number of overall hits -system.cpu1.dcache.overall_hits::total 9733011 # number of overall hits -system.cpu1.dcache.ReadReq_misses::0 165799 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 165799 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::0 111467 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 111467 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::0 10725 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 10725 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::0 10198 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10198 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::0 277266 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 277266 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::0 277266 # number of overall misses -system.cpu1.dcache.overall_misses::1 0 # number of overall misses -system.cpu1.dcache.overall_misses::total 277266 # number of overall misses -system.cpu1.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::0 6121772 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 6121772 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::0 3888505 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 3888505 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::0 70318 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 70318 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::0 70288 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 70288 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::0 10010277 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 10010277 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::0 10010277 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 10010277 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::0 0.027083 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::0 0.028666 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.152521 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::0 0.145089 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::0 0.027698 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::0 0.027698 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.dcache.demand_avg_miss_latency::0 0 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total no_value # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::0 0 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total no_value # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu1.dcache.fast_writes 0 # number of fast writes performed -system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks 202201 # number of writebacks -system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses -system.cpu1.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 0 # number of replacements -system.iocache.tagsinuse 0 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.avg_refs no_value # Average number of references to valid blocks. -system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.iocache.demand_hits::0 0 # number of demand (read+write) hits -system.iocache.demand_hits::1 0 # number of demand (read+write) hits -system.iocache.demand_hits::total 0 # number of demand (read+write) hits -system.iocache.overall_hits::0 0 # number of overall hits -system.iocache.overall_hits::1 0 # number of overall hits -system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.demand_misses::0 0 # number of demand (read+write) misses -system.iocache.demand_misses::1 0 # number of demand (read+write) misses -system.iocache.demand_misses::total 0 # number of demand (read+write) misses -system.iocache.overall_misses::0 0 # number of overall misses -system.iocache.overall_misses::1 0 # number of overall misses -system.iocache.overall_misses::total 0 # number of overall misses -system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency 0 # number of overall miss cycles -system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses -system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses -system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses -system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses -system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency -system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency -system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency -system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency -system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency -system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed -system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks 0 # number of writebacks -system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses 0 # number of overall MSHR misses -system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses -system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated -system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini index 5b5bd9164..5cb72c285 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=true time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,7 +9,6 @@ time_sync_spin_threshold=100000000 [system] type=LinuxArmSystem children=bridge cf0 cpu intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver -boot_cpu_frequency=500 boot_loader=/dist/m5/system/binaries/boot.arm boot_loader_mem=system.nvmem boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 @@ -93,6 +93,7 @@ simulate_inst_stalls=false system=system tracer=system.cpu.tracer width=1 +workload= dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side @@ -107,20 +108,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -152,20 +146,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -217,20 +204,13 @@ is_top_level=false latency=50000 max_miss_count=0 mshrs=20 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=500000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=1024 subblock_size=0 +system=system tgts_per_mshr=12 trace_addr=0 two_queue=false @@ -249,20 +229,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=92 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=4194304 subblock_size=0 +system=system tgts_per_mshr=16 trace_addr=0 two_queue=false @@ -288,7 +261,6 @@ fake_mem=false pio_addr=0 pio_latency=1000 pio_size=8 -platform=system.realview ret_bad_addr=true ret_data16=65535 ret_data32=4294967295 @@ -330,7 +302,6 @@ system=system type=A9SCU pio_addr=520093696 pio_latency=1000 -platform=system.realview system=system pio=system.membus.port[5] @@ -340,7 +311,6 @@ amba_id=0 ignore_access=false pio_addr=268451840 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[24] @@ -410,7 +380,6 @@ max_backoff_delay=10000000 min_backoff_delay=4000 pio_addr=268566528 pio_latency=10000 -platform=system.realview system=system vnc=system.vncserver dma=system.iobus.port[6] @@ -422,7 +391,6 @@ amba_id=0 ignore_access=false pio_addr=268632064 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[12] @@ -432,7 +400,6 @@ fake_mem=true pio_addr=1073741824 pio_latency=1000 pio_size=536870912 -platform=system.realview ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -461,7 +428,6 @@ amba_id=0 ignore_access=false pio_addr=268513280 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[19] @@ -471,7 +437,6 @@ amba_id=0 ignore_access=false pio_addr=268517376 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[20] @@ -481,7 +446,6 @@ amba_id=0 ignore_access=false pio_addr=268521472 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[21] @@ -494,7 +458,6 @@ int_num=52 is_mouse=false pio_addr=268460032 pio_latency=1000 -platform=system.realview system=system vnc=system.vncserver pio=system.iobus.port[7] @@ -508,7 +471,6 @@ int_num=53 is_mouse=true pio_addr=268464128 pio_latency=1000 -platform=system.realview system=system vnc=system.vncserver pio=system.iobus.port[8] @@ -519,7 +481,6 @@ fake_mem=false pio_addr=520101888 pio_latency=1000 pio_size=4095 -platform=system.realview ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -538,7 +499,6 @@ int_num_timer=29 int_num_watchdog=30 pio_addr=520095232 pio_latency=1000 -platform=system.realview system=system pio=system.membus.port[6] @@ -548,7 +508,6 @@ amba_id=0 ignore_access=false pio_addr=268455936 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[25] @@ -557,7 +516,6 @@ type=RealViewCtrl idreg=0 pio_addr=268435456 pio_latency=1000 -platform=system.realview proc_id0=201326592 proc_id1=201327138 system=system @@ -569,7 +527,6 @@ amba_id=266289 ignore_access=false pio_addr=268529664 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[26] @@ -579,7 +536,6 @@ amba_id=0 ignore_access=false pio_addr=268492800 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[23] @@ -589,7 +545,6 @@ amba_id=0 ignore_access=false pio_addr=269357056 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[16] @@ -599,7 +554,6 @@ amba_id=0 ignore_access=true pio_addr=268439552 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[17] @@ -609,7 +563,6 @@ amba_id=0 ignore_access=false pio_addr=268488704 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[22] @@ -623,7 +576,6 @@ int_num0=36 int_num1=36 pio_addr=268505088 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[3] @@ -637,7 +589,6 @@ int_num0=37 int_num1=37 pio_addr=268509184 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[4] @@ -660,7 +611,6 @@ amba_id=0 ignore_access=false pio_addr=268476416 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[13] @@ -670,7 +620,6 @@ amba_id=0 ignore_access=false pio_addr=268480512 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[14] @@ -680,7 +629,6 @@ amba_id=0 ignore_access=false pio_addr=268484608 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[15] @@ -690,7 +638,6 @@ amba_id=0 ignore_access=false pio_addr=268500992 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[18] diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout index e355498ce..31542346f 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:21:22 -gem5 started Jan 23 2012 04:24:55 +gem5 compiled Feb 11 2012 13:10:40 +gem5 started Feb 11 2012 15:36:22 gem5 executing on zizzer -command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index e3050fa31..d895bb120 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -4,11 +4,13 @@ sim_seconds 2.332317 # Nu sim_ticks 2332316587000 # Number of ticks simulated final_tick 2332316587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2072038 # Simulator instruction rate (inst/s) -host_tick_rate 63144661085 # Simulator tick rate (ticks/s) -host_mem_usage 379208 # Number of bytes of host memory used -host_seconds 36.94 # Real time elapsed on the host -sim_insts 76532931 # Number of instructions simulated +host_inst_rate 2011652 # Simulator instruction rate (inst/s) +host_op_rate 2597875 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 79169370264 # Simulator tick rate (ticks/s) +host_mem_usage 376316 # Number of bytes of host memory used +host_seconds 29.46 # Real time elapsed on the host +sim_insts 59262876 # Number of instructions simulated +sim_ops 76532931 # Number of ops (including micro ops) simulated system.nvmem.bytes_read 20 # Number of bytes read from this memory system.nvmem.bytes_inst_read 20 # Number of instructions bytes read from this memory system.nvmem.bytes_written 0 # Number of bytes written to this memory @@ -34,72 +36,92 @@ system.l2c.total_refs 1520830 # To system.l2c.sampled_refs 146847 # Sample count of references to valid blocks. system.l2c.avg_refs 10.356562 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 10591.091336 # Average occupied blocks per context -system.l2c.occ_blocks::1 13649.297042 # Average occupied blocks per context -system.l2c.occ_percent::0 0.161607 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.208272 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 1188216 # number of ReadReq hits -system.l2c.ReadReq_hits::1 10669 # number of ReadReq hits +system.l2c.occ_blocks::writebacks 13639.466210 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 7.864412 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.itb.walker 1.966419 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 5246.411267 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 5344.680069 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.208122 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.dtb.walker 0.000120 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.itb.walker 0.000030 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.inst 0.080054 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.081553 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.369879 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 7522 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.itb.walker 3147 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.inst 831710 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 356506 # number of ReadReq hits system.l2c.ReadReq_hits::total 1198885 # number of ReadReq hits -system.l2c.Writeback_hits::0 604613 # number of Writeback hits +system.l2c.Writeback_hits::writebacks 604613 # number of Writeback hits system.l2c.Writeback_hits::total 604613 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 26 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::0 105791 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu.data 105791 # number of ReadExReq hits system.l2c.ReadExReq_hits::total 105791 # number of ReadExReq hits -system.l2c.demand_hits::0 1294007 # number of demand (read+write) hits -system.l2c.demand_hits::1 10669 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.dtb.walker 7522 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.itb.walker 3147 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.inst 831710 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 462297 # number of demand (read+write) hits system.l2c.demand_hits::total 1304676 # number of demand (read+write) hits -system.l2c.overall_hits::0 1294007 # number of overall hits -system.l2c.overall_hits::1 10669 # number of overall hits +system.l2c.overall_hits::cpu.dtb.walker 7522 # number of overall hits +system.l2c.overall_hits::cpu.itb.walker 3147 # number of overall hits +system.l2c.overall_hits::cpu.inst 831710 # number of overall hits +system.l2c.overall_hits::cpu.data 462297 # number of overall hits system.l2c.overall_hits::total 1304676 # number of overall hits -system.l2c.ReadReq_misses::0 31716 # number of ReadReq misses -system.l2c.ReadReq_misses::1 27 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.dtb.walker 19 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.itb.walker 8 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.inst 14294 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 17422 # number of ReadReq misses system.l2c.ReadReq_misses::total 31743 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 2911 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu.data 2911 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 2911 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::0 141169 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu.data 141169 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 141169 # number of ReadExReq misses -system.l2c.demand_misses::0 172885 # number of demand (read+write) misses -system.l2c.demand_misses::1 27 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.dtb.walker 19 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.itb.walker 8 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.inst 14294 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 158591 # number of demand (read+write) misses system.l2c.demand_misses::total 172912 # number of demand (read+write) misses -system.l2c.overall_misses::0 172885 # number of overall misses -system.l2c.overall_misses::1 27 # number of overall misses +system.l2c.overall_misses::cpu.dtb.walker 19 # number of overall misses +system.l2c.overall_misses::cpu.itb.walker 8 # number of overall misses +system.l2c.overall_misses::cpu.inst 14294 # number of overall misses +system.l2c.overall_misses::cpu.data 158591 # number of overall misses system.l2c.overall_misses::total 172912 # number of overall misses -system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 0 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 1219932 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 10696 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.dtb.walker 7541 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.itb.walker 3155 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.inst 846004 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 373928 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 1230628 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 604613 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 604613 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 604613 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 2937 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu.data 2937 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 2937 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 246960 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu.data 246960 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 246960 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 1466892 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 10696 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.dtb.walker 7541 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.itb.walker 3155 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.inst 846004 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 620888 # number of demand (read+write) accesses system.l2c.demand_accesses::total 1477588 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 1466892 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 10696 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.dtb.walker 7541 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.itb.walker 3155 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.inst 846004 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.data 620888 # number of overall (read+write) accesses system.l2c.overall_accesses::total 1477588 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.025998 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.002524 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.028522 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.991147 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.571627 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.117858 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.002524 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.120382 # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.117858 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.002524 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.120382 # miss rate for overall accesses -system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 0 # average overall miss latency -system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 0 # average overall miss latency +system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.002520 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.002536 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.inst 0.016896 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.046592 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu.data 0.991147 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu.data 0.571627 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu.dtb.walker 0.002520 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.itb.walker 0.002536 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.inst 0.016896 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.255426 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.dtb.walker 0.002520 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.itb.walker 0.002536 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.inst 0.016896 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.255426 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -108,26 +130,8 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 102531 # number of writebacks -system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits 0 # number of overall MSHR hits -system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 0 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0 # mshr miss rate for overall accesses -system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated -system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.writebacks::writebacks 102531 # number of writebacks +system.l2c.writebacks::total 102531 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -180,7 +184,8 @@ system.cpu.itb.accesses 60278360 # DT system.cpu.numCycles 4664556206 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 76532931 # Number of instructions executed +system.cpu.committedInsts 59262876 # Number of instructions committed +system.cpu.committedOps 76532931 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 68161177 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses system.cpu.num_func_calls 1971944 # number of times a function call or return occured @@ -206,47 +211,30 @@ system.cpu.icache.total_refs 59429083 # To system.cpu.icache.sampled_refs 847566 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 70.117351 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 5705452000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 511.678552 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.999372 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::0 59429083 # number of ReadReq hits +system.cpu.icache.occ_blocks::cpu.inst 511.678552 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.999372 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.999372 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 59429083 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 59429083 # number of ReadReq hits -system.cpu.icache.demand_hits::0 59429083 # number of demand (read+write) hits -system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.icache.demand_hits::cpu.inst 59429083 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 59429083 # number of demand (read+write) hits -system.cpu.icache.overall_hits::0 59429083 # number of overall hits -system.cpu.icache.overall_hits::1 0 # number of overall hits +system.cpu.icache.overall_hits::cpu.inst 59429083 # number of overall hits system.cpu.icache.overall_hits::total 59429083 # number of overall hits -system.cpu.icache.ReadReq_misses::0 847566 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::cpu.inst 847566 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 847566 # number of ReadReq misses -system.cpu.icache.demand_misses::0 847566 # number of demand (read+write) misses -system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.icache.demand_misses::cpu.inst 847566 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 847566 # number of demand (read+write) misses -system.cpu.icache.overall_misses::0 847566 # number of overall misses -system.cpu.icache.overall_misses::1 0 # number of overall misses +system.cpu.icache.overall_misses::cpu.inst 847566 # number of overall misses system.cpu.icache.overall_misses::total 847566 # number of overall misses -system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::0 60276649 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::cpu.inst 60276649 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 60276649 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::0 60276649 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::cpu.inst 60276649 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 60276649 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::0 60276649 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 60276649 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 60276649 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::0 0.014061 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::0 0.014061 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::0 0.014061 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.demand_avg_miss_latency::0 0 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::1 no_value # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total no_value # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::0 0 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::1 no_value # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total no_value # average overall miss latency +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014061 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.014061 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.014061 # miss rate for overall accesses system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -255,26 +243,8 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 44721 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses -system.cpu.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.writebacks::writebacks 44721 # number of writebacks +system.cpu.icache.writebacks::total 44721 # number of writebacks system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 622134 # number of replacements system.cpu.dcache.tagsinuse 511.997030 # Cycle average of tags in use @@ -282,65 +252,48 @@ system.cpu.dcache.total_refs 23580069 # To system.cpu.dcache.sampled_refs 622646 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 37.870747 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 21763000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 511.997030 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999994 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::0 13150366 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 511.997030 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 13150366 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 13150366 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::0 9943631 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 9943631 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 9943631 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::0 235999 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 235999 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 235999 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::0 247136 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247136 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 247136 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::0 23093997 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::cpu.data 23093997 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 23093997 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::0 23093997 # number of overall hits -system.cpu.dcache.overall_hits::1 0 # number of overall hits +system.cpu.dcache.overall_hits::cpu.data 23093997 # number of overall hits system.cpu.dcache.overall_hits::total 23093997 # number of overall hits -system.cpu.dcache.ReadReq_misses::0 364548 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 364548 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 364548 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::0 249897 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 249897 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 249897 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::0 11138 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 11138 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 11138 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::0 614445 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::cpu.data 614445 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 614445 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::0 614445 # number of overall misses -system.cpu.dcache.overall_misses::1 0 # number of overall misses +system.cpu.dcache.overall_misses::cpu.data 614445 # number of overall misses system.cpu.dcache.overall_misses::total 614445 # number of overall misses -system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::0 13514914 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 13514914 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 13514914 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::0 10193528 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10193528 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 10193528 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::0 247137 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247137 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 247137 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::0 247136 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247136 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 247136 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::0 23708442 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 23708442 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 23708442 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::0 23708442 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 23708442 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 23708442 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::0 0.026974 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::0 0.024515 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.045068 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::0 0.025917 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::0 0.025917 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.demand_avg_miss_latency::0 0 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total no_value # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::0 0 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total no_value # average overall miss latency +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026974 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024515 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045068 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.025917 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.025917 # miss rate for overall accesses system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -349,26 +302,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 559892 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses -system.cpu.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 559892 # number of writebacks +system.cpu.dcache.writebacks::total 559892 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use @@ -376,38 +311,6 @@ system.iocache.total_refs 0 # To system.iocache.sampled_refs 0 # Sample count of references to valid blocks. system.iocache.avg_refs no_value # Average number of references to valid blocks. system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.iocache.demand_hits::0 0 # number of demand (read+write) hits -system.iocache.demand_hits::1 0 # number of demand (read+write) hits -system.iocache.demand_hits::total 0 # number of demand (read+write) hits -system.iocache.overall_hits::0 0 # number of overall hits -system.iocache.overall_hits::1 0 # number of overall hits -system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.demand_misses::0 0 # number of demand (read+write) misses -system.iocache.demand_misses::1 0 # number of demand (read+write) misses -system.iocache.demand_misses::total 0 # number of demand (read+write) misses -system.iocache.overall_misses::0 0 # number of overall misses -system.iocache.overall_misses::1 0 # number of overall misses -system.iocache.overall_misses::total 0 # number of overall misses -system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency 0 # number of overall miss cycles -system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses -system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses -system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses -system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses -system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency -system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency -system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency -system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency -system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency -system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -416,26 +319,6 @@ system.iocache.avg_blocked_cycles::no_mshrs no_value # system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks 0 # number of writebacks -system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses 0 # number of overall MSHR misses -system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses -system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated -system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini index 82d6c82a5..73f5e0c76 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=true time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,7 +9,6 @@ time_sync_spin_threshold=100000000 [system] type=LinuxArmSystem children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver -boot_cpu_frequency=500 boot_loader=/dist/m5/system/binaries/boot.arm boot_loader_mem=system.nvmem boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 @@ -19,7 +19,7 @@ kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing -memories=system.physmem system.nvmem +memories=system.nvmem system.physmem midr_regval=890224640 num_work_ids=16 physmem=system.physmem @@ -90,6 +90,7 @@ profile=0 progress_interval=0 system=system tracer=system.cpu0.tracer +workload= dcache_port=system.cpu0.dcache.cpu_side icache_port=system.cpu0.icache.cpu_side @@ -104,20 +105,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -149,20 +143,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -214,6 +201,7 @@ profile=0 progress_interval=0 system=system tracer=system.cpu1.tracer +workload= dcache_port=system.cpu1.dcache.cpu_side icache_port=system.cpu1.icache.cpu_side @@ -228,20 +216,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -273,20 +254,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -338,20 +312,13 @@ is_top_level=false latency=50000 max_miss_count=0 mshrs=20 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=500000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=1024 subblock_size=0 +system=system tgts_per_mshr=12 trace_addr=0 two_queue=false @@ -370,20 +337,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=92 -num_cpus=2 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=4194304 subblock_size=0 +system=system tgts_per_mshr=16 trace_addr=0 two_queue=false @@ -409,7 +369,6 @@ fake_mem=false pio_addr=0 pio_latency=1000 pio_size=8 -platform=system.realview ret_bad_addr=true ret_data16=65535 ret_data32=4294967295 @@ -451,7 +410,6 @@ system=system type=A9SCU pio_addr=520093696 pio_latency=1000 -platform=system.realview system=system pio=system.membus.port[5] @@ -461,7 +419,6 @@ amba_id=0 ignore_access=false pio_addr=268451840 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[24] @@ -531,7 +488,6 @@ max_backoff_delay=10000000 min_backoff_delay=4000 pio_addr=268566528 pio_latency=10000 -platform=system.realview system=system vnc=system.vncserver dma=system.iobus.port[6] @@ -543,7 +499,6 @@ amba_id=0 ignore_access=false pio_addr=268632064 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[12] @@ -553,7 +508,6 @@ fake_mem=true pio_addr=1073741824 pio_latency=1000 pio_size=536870912 -platform=system.realview ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -582,7 +536,6 @@ amba_id=0 ignore_access=false pio_addr=268513280 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[19] @@ -592,7 +545,6 @@ amba_id=0 ignore_access=false pio_addr=268517376 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[20] @@ -602,7 +554,6 @@ amba_id=0 ignore_access=false pio_addr=268521472 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[21] @@ -615,7 +566,6 @@ int_num=52 is_mouse=false pio_addr=268460032 pio_latency=1000 -platform=system.realview system=system vnc=system.vncserver pio=system.iobus.port[7] @@ -629,7 +579,6 @@ int_num=53 is_mouse=true pio_addr=268464128 pio_latency=1000 -platform=system.realview system=system vnc=system.vncserver pio=system.iobus.port[8] @@ -640,7 +589,6 @@ fake_mem=false pio_addr=520101888 pio_latency=1000 pio_size=4095 -platform=system.realview ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -659,7 +607,6 @@ int_num_timer=29 int_num_watchdog=30 pio_addr=520095232 pio_latency=1000 -platform=system.realview system=system pio=system.membus.port[6] @@ -669,7 +616,6 @@ amba_id=0 ignore_access=false pio_addr=268455936 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[25] @@ -678,7 +624,6 @@ type=RealViewCtrl idreg=0 pio_addr=268435456 pio_latency=1000 -platform=system.realview proc_id0=201326592 proc_id1=201327138 system=system @@ -690,7 +635,6 @@ amba_id=266289 ignore_access=false pio_addr=268529664 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[26] @@ -700,7 +644,6 @@ amba_id=0 ignore_access=false pio_addr=268492800 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[23] @@ -710,7 +653,6 @@ amba_id=0 ignore_access=false pio_addr=269357056 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[16] @@ -720,7 +662,6 @@ amba_id=0 ignore_access=true pio_addr=268439552 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[17] @@ -730,7 +671,6 @@ amba_id=0 ignore_access=false pio_addr=268488704 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[22] @@ -744,7 +684,6 @@ int_num0=36 int_num1=36 pio_addr=268505088 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[3] @@ -758,7 +697,6 @@ int_num0=37 int_num1=37 pio_addr=268509184 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[4] @@ -781,7 +719,6 @@ amba_id=0 ignore_access=false pio_addr=268476416 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[13] @@ -791,7 +728,6 @@ amba_id=0 ignore_access=false pio_addr=268480512 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[14] @@ -801,7 +737,6 @@ amba_id=0 ignore_access=false pio_addr=268484608 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[15] @@ -811,7 +746,6 @@ amba_id=0 ignore_access=false pio_addr=268500992 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[18] diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout index 2f40c0e53..83064ae1d 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:21:22 -gem5 started Jan 23 2012 04:25:02 +gem5 compiled Feb 11 2012 13:10:40 +gem5 started Feb 11 2012 15:38:22 gem5 executing on zizzer -command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing-dual +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 6f6f084e3..46b5d4b73 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -4,11 +4,13 @@ sim_seconds 2.669611 # Nu sim_ticks 2669611225000 # Number of ticks simulated final_tick 2669611225000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 842154 # Simulator instruction rate (inst/s) -host_tick_rate 28671225175 # Simulator tick rate (ticks/s) -host_mem_usage 380676 # Number of bytes of host memory used -host_seconds 93.11 # Real time elapsed on the host -sim_insts 78413959 # Number of instructions simulated +host_inst_rate 868396 # Simulator instruction rate (inst/s) +host_op_rate 1110924 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 37821516206 # Simulator tick rate (ticks/s) +host_mem_usage 377896 # Number of bytes of host memory used +host_seconds 70.58 # Real time elapsed on the host +sim_insts 61295262 # Number of instructions simulated +sim_ops 78413959 # Number of ops (including micro ops) simulated system.nvmem.bytes_read 68 # Number of bytes read from this memory system.nvmem.bytes_inst_read 68 # Number of instructions bytes read from this memory system.nvmem.bytes_written 0 # Number of bytes written to this memory @@ -34,127 +36,233 @@ system.l2c.total_refs 1540412 # To system.l2c.sampled_refs 157158 # Sample count of references to valid blocks. system.l2c.avg_refs 9.801677 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 6351.465954 # Average occupied blocks per context -system.l2c.occ_blocks::1 4614.904109 # Average occupied blocks per context -system.l2c.occ_blocks::2 15206.143377 # Average occupied blocks per context -system.l2c.occ_percent::0 0.096916 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.070418 # Average percentage of cache occupancy -system.l2c.occ_percent::2 0.232027 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 562859 # number of ReadReq hits -system.l2c.ReadReq_hits::1 656143 # number of ReadReq hits -system.l2c.ReadReq_hits::2 11798 # number of ReadReq hits +system.l2c.occ_blocks::writebacks 15197.869059 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 8.069070 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 0.114155 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 2680.486069 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 3670.979885 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 0.091092 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.itb.walker 0.000002 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 2441.904066 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 2173.000042 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.231901 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.dtb.walker 0.000123 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.040901 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.056015 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.dtb.walker 0.000001 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.037260 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.033157 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.399361 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 4237 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 1502 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 371106 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 191753 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 4185 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 1874 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 499097 # number of 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-system.l2c.UpgradeReq_misses::0 3515 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::1 5223 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu0.data 3515 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 5223 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 8738 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::0 546 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::1 614 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 546 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 614 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 1160 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::0 97324 # number of ReadExReq misses -system.l2c.ReadExReq_misses::1 51524 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu0.data 97324 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 51524 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 148848 # number of ReadExReq misses -system.l2c.demand_misses::0 115979 # number of demand (read+write) misses -system.l2c.demand_misses::1 67558 # number of demand (read+write) misses -system.l2c.demand_misses::2 50 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.dtb.walker 24 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 14 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 7728 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 108251 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 8 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 4 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 7533 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 60025 # number of demand (read+write) misses system.l2c.demand_misses::total 183587 # number of demand (read+write) misses -system.l2c.overall_misses::0 115979 # number of overall misses -system.l2c.overall_misses::1 67558 # number of overall misses -system.l2c.overall_misses::2 50 # number of overall misses +system.l2c.overall_misses::cpu0.dtb.walker 24 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 14 # number of overall misses +system.l2c.overall_misses::cpu0.inst 7728 # number of overall misses +system.l2c.overall_misses::cpu0.data 108251 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 8 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 4 # number of overall misses +system.l2c.overall_misses::cpu1.inst 7533 # number of overall misses +system.l2c.overall_misses::cpu1.data 60025 # number of overall misses system.l2c.overall_misses::total 183587 # number of overall misses -system.l2c.ReadReq_miss_latency 1812504500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency 56471000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency 6300000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 7751543000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 9564047500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 9564047500 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 581514 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 672177 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::2 11848 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 1250500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 728500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 402353500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 568569000 # number of ReadReq miss cycles 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+system.l2c.ReadExReq_miss_latency::cpu0.data 5064009000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 2687534000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7751543000 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 1250500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 728500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 402353500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 5632578000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 416000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 208000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 393731000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 3132782000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 9564047500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 1250500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 728500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 402353500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 5632578000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 416000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 208000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 393731000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 3132782000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 9564047500 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 4261 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 1516 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 378834 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 202680 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 4193 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 1878 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 506630 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 165547 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 1265539 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 589400 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 589400 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 589400 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 4658 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::1 5915 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 4658 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 5915 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 10573 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::0 714 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::1 800 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 714 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 800 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 1514 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 139830 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::1 110078 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 139830 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 110078 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 249908 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 721344 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 782255 # number of demand (read+write) accesses -system.l2c.demand_accesses::2 11848 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.dtb.walker 4261 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 1516 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 378834 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 342510 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 4193 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 1878 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 506630 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 275625 # number of demand (read+write) accesses system.l2c.demand_accesses::total 1515447 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 721344 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 782255 # number of overall (read+write) accesses -system.l2c.overall_accesses::2 11848 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 4261 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 1516 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 378834 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 342510 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 4193 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 1878 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 506630 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 275625 # number of overall (read+write) accesses system.l2c.overall_accesses::total 1515447 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.032080 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.023854 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::2 0.004220 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.060154 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.754616 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::1 0.883009 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::0 0.764706 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::1 0.767500 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.696017 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::1 0.468068 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.160782 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.086363 # miss rate for demand accesses -system.l2c.demand_miss_rate::2 0.004220 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.251365 # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.160782 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.086363 # miss rate for overall accesses -system.l2c.overall_miss_rate::2 0.004220 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.251365 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 97159.179845 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 113041.318448 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::2 36250090 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 36460290.498293 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 16065.718350 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 10811.985449 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::0 11538.461538 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::1 10260.586319 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::2 inf # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 79646.777773 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 150445.287633 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::2 inf # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 82463.614103 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 141567.949022 # average overall miss latency -system.l2c.demand_avg_miss_latency::2 191280950 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 191504981.563124 # average overall miss latency -system.l2c.overall_avg_miss_latency::0 82463.614103 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 141567.949022 # average overall miss latency -system.l2c.overall_avg_miss_latency::2 191280950 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 191504981.563124 # average overall miss latency +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.005632 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.009235 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.020399 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.053913 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.001908 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.002130 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.014869 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.051351 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.754616 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.883009 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.764706 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.767500 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.696017 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.468068 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.005632 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.009235 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.020399 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.316052 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.001908 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.002130 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.014869 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.217778 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.005632 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.009235 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.020399 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.316052 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.001908 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.002130 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.014869 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.217778 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52104.166667 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 52035.714286 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52064.376294 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 52033.403496 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 52000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52267.489712 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 52375.955770 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 7304.694168 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5896.036760 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3047.619048 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 7550.488599 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52032.479142 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52160.818259 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52104.166667 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 52035.714286 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 52064.376294 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 52032.572447 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 52267.489712 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 52191.286964 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52104.166667 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 52035.714286 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 52064.376294 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 52032.572447 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 52267.489712 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 52191.286964 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -163,61 +271,172 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 111955 # number of writebacks -system.l2c.ReadReq_mshr_hits 9 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits 9 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits 9 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 34730 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 8738 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses 1160 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses 148848 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 183578 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 183578 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 1395310000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 350593500 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency 46546000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency 5965367000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 7360677000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 7360677000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency 131926671000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency 31372379500 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency 163299050500 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.059723 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 0.051668 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::2 2.931296 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 3.042688 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::0 1.875912 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 1.477261 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.624650 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::1 1.450000 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::0 1.064493 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::1 1.352205 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::2 inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 0.254494 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 0.234678 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::2 15.494429 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 15.983602 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0.254494 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 0.234678 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::2 15.494429 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 15.983602 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 40175.928592 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40122.854200 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40125.862069 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40076.903956 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40095.637822 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40095.637822 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated -system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.writebacks::writebacks 111955 # number of writebacks +system.l2c.writebacks::total 111955 # number of writebacks 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overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 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system.cpu0.num_func_calls 977479 # number of times a function call or return occured @@ -296,51 +516,39 @@ system.cpu0.icache.total_refs 35367311 # To system.cpu0.icache.sampled_refs 380581 # Sample count of references to valid blocks. system.cpu0.icache.avg_refs 92.929786 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 74921716000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::0 510.849663 # Average occupied blocks per context -system.cpu0.icache.occ_percent::0 0.997753 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::0 35367311 # number of ReadReq hits +system.cpu0.icache.occ_blocks::cpu0.inst 510.849663 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.997753 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.997753 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 35367311 # number of ReadReq hits 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number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::0 35747894 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 35747894 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::total 35747894 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::0 0.010646 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::0 0.010646 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::0 0.010646 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::0 14849.425749 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::0 14849.425749 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::1 inf # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::0 14849.425749 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::1 inf # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010646 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.010646 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.010646 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14849.425749 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14849.425749 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14849.425749 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -349,34 +557,32 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks 12960 # number of writebacks -system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses 380583 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses 380583 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses 380583 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency 4509188500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency 4509188500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency 4509188500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency 351814000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency 351814000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.010646 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::0 0.010646 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::0 0.010646 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11848.108034 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 11848.108034 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 11848.108034 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.icache.writebacks::writebacks 12960 # number of writebacks +system.cpu0.icache.writebacks::total 12960 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 380583 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 380583 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 380583 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 380583 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 380583 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 380583 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4509188500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4509188500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4509188500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4509188500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4509188500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4509188500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 351814000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 351814000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 351814000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 351814000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.010646 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.010646 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.010646 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11848.108034 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11848.108034 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11848.108034 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 334596 # number of replacements system.cpu0.dcache.tagsinuse 450.118381 # Cycle average of tags in use @@ -384,84 +590,69 @@ system.cpu0.dcache.total_refs 12875674 # To system.cpu0.dcache.sampled_refs 335004 # Sample count of references to valid blocks. system.cpu0.dcache.avg_refs 38.434389 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 663204000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::0 450.118381 # Average occupied blocks per context -system.cpu0.dcache.occ_percent::0 0.879137 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::0 7428609 # number of ReadReq hits +system.cpu0.dcache.occ_blocks::cpu0.data 450.118381 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.879137 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.879137 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 7428609 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 7428609 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::0 5172633 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5172633 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::total 5172633 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::0 126778 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 126778 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 126778 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::0 127996 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 127996 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 127996 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::0 12601242 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu0.data 12601242 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::total 12601242 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::0 12601242 # number of overall hits -system.cpu0.dcache.overall_hits::1 0 # number of overall hits +system.cpu0.dcache.overall_hits::cpu0.data 12601242 # number of overall hits system.cpu0.dcache.overall_hits::total 12601242 # number of overall hits -system.cpu0.dcache.ReadReq_misses::0 217330 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu0.data 217330 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 217330 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::0 155538 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 155538 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::total 155538 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::0 9456 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9456 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 9456 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::0 8189 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 8189 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 8189 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::0 372868 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu0.data 372868 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::total 372868 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::0 372868 # number of overall misses -system.cpu0.dcache.overall_misses::1 0 # number of overall misses +system.cpu0.dcache.overall_misses::cpu0.data 372868 # number of overall misses system.cpu0.dcache.overall_misses::total 372868 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency 3330686000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency 6317758500 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency 100249000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency 70240000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency 9648444500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency 9648444500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::0 7645939 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3330686000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 3330686000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6317758500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 6317758500 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 100249000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 100249000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 70240000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 70240000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 9648444500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 9648444500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 9648444500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 9648444500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7645939 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 7645939 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::0 5328171 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5328171 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::total 5328171 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::0 136234 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 136234 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 136234 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::0 136185 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 136185 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 136185 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::0 12974110 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu0.data 12974110 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::total 12974110 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::0 12974110 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12974110 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 12974110 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::0 0.028424 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::0 0.029192 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.069410 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::0 0.060131 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::0 0.028739 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::0 0.028739 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::0 15325.477385 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::0 40618.745901 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 10601.628596 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 8577.359873 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::0 25876.300728 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::1 inf # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::0 25876.300728 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::1 inf # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028424 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.029192 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.069410 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.060131 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.028739 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.028739 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15325.477385 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40618.745901 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10601.628596 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8577.359873 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25876.300728 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 25876.300728 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -470,56 +661,56 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks 294891 # number of writebacks -system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses 217330 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses 155538 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses 9456 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses 8184 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses 372868 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses 372868 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency 2678673500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency 5851029000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 71881000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency 45691000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency 8529702500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency 8529702500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 9171180500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 40129379500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency 49300560000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.028424 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.029192 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.069410 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.060095 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::0 0.028739 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::0 0.028739 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 12325.373855 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 37618.003318 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 7601.628596 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 5582.966764 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 22875.930624 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 22875.930624 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.dcache.writebacks::writebacks 294891 # number of writebacks +system.cpu0.dcache.writebacks::total 294891 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 217330 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 217330 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 155538 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 155538 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9456 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9456 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 8184 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 8184 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 372868 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 372868 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 372868 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 372868 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2678673500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2678673500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5851029000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5851029000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 71881000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 71881000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 45691000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 45691000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8529702500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 8529702500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8529702500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 8529702500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 9171180500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 9171180500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 40129379500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 40129379500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 49300560000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 49300560000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028424 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.029192 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.069410 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.060095 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028739 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028739 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12325.373855 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37618.003318 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7601.628596 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5582.966764 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22875.930624 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22875.930624 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses @@ -566,7 +757,8 @@ system.cpu1.itb.accesses 26851434 # DT system.cpu1.numCycles 5339222450 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.num_insts 34444935 # Number of instructions executed +system.cpu1.committedInsts 25921760 # Number of instructions committed +system.cpu1.committedOps 34444935 # Number of ops (including micro ops) committed system.cpu1.num_int_alu_accesses 31033253 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 5714 # Number of float alu accesses system.cpu1.num_func_calls 1093852 # number of times a function call or return occured @@ -592,51 +784,39 @@ system.cpu1.icache.total_refs 26339543 # To system.cpu1.icache.sampled_refs 508733 # Sample count of references to valid blocks. system.cpu1.icache.avg_refs 51.774788 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 191336880000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::0 497.375159 # Average occupied blocks per context -system.cpu1.icache.occ_percent::0 0.971436 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::0 26339543 # number of ReadReq hits +system.cpu1.icache.occ_blocks::cpu1.inst 497.375159 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.971436 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.971436 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 26339543 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 26339543 # number of ReadReq hits -system.cpu1.icache.demand_hits::0 26339543 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::cpu1.inst 26339543 # number of demand (read+write) hits system.cpu1.icache.demand_hits::total 26339543 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::0 26339543 # number of overall hits -system.cpu1.icache.overall_hits::1 0 # number of overall hits +system.cpu1.icache.overall_hits::cpu1.inst 26339543 # number of overall hits system.cpu1.icache.overall_hits::total 26339543 # number of overall hits -system.cpu1.icache.ReadReq_misses::0 508733 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::cpu1.inst 508733 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 508733 # number of ReadReq misses -system.cpu1.icache.demand_misses::0 508733 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::cpu1.inst 508733 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 508733 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::0 508733 # number of overall misses -system.cpu1.icache.overall_misses::1 0 # number of overall misses +system.cpu1.icache.overall_misses::cpu1.inst 508733 # number of overall misses system.cpu1.icache.overall_misses::total 508733 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency 7436442000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency 7436442000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency 7436442000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::0 26848276 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7436442000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 7436442000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 7436442000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 7436442000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 7436442000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 7436442000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 26848276 # number of ReadReq accesses(hits+misses) system.cpu1.icache.ReadReq_accesses::total 26848276 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::0 26848276 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::cpu1.inst 26848276 # number of demand (read+write) accesses system.cpu1.icache.demand_accesses::total 26848276 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::0 26848276 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 26848276 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::total 26848276 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::0 0.018948 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::0 0.018948 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::0 0.018948 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::0 14617.573462 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::0 14617.573462 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::1 inf # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::0 14617.573462 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::1 inf # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.018948 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.018948 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.018948 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14617.573462 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14617.573462 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14617.573462 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -645,34 +825,32 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks 27998 # number of writebacks -system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses 508733 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses 508733 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses 508733 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency 5908060000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency 5908060000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency 5908060000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency 5250000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency 5250000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.018948 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::0 0.018948 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::0 0.018948 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11613.282409 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 11613.282409 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 11613.282409 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.icache.writebacks::writebacks 27998 # number of writebacks +system.cpu1.icache.writebacks::total 27998 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 508733 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 508733 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 508733 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 508733 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 508733 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 508733 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5908060000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5908060000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5908060000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5908060000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5908060000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5908060000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5250000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5250000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5250000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 5250000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.018948 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.018948 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.018948 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11613.282409 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11613.282409 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11613.282409 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 295754 # number of replacements system.cpu1.dcache.tagsinuse 467.166427 # Cycle average of tags in use @@ -680,84 +858,69 @@ system.cpu1.dcache.total_refs 11737107 # To system.cpu1.dcache.sampled_refs 296266 # Sample count of references to valid blocks. system.cpu1.dcache.avg_refs 39.616787 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 75924171000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::0 467.166427 # Average occupied blocks per context -system.cpu1.dcache.occ_percent::0 0.912434 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::0 6345290 # number of ReadReq hits +system.cpu1.dcache.occ_blocks::cpu1.data 467.166427 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.912434 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.912434 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 6345290 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 6345290 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::0 5152610 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 5152610 # number of WriteReq hits system.cpu1.dcache.WriteReq_hits::total 5152610 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::0 104795 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 104795 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_hits::total 104795 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::0 106403 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 106403 # number of StoreCondReq hits system.cpu1.dcache.StoreCondReq_hits::total 106403 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::0 11497900 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::cpu1.data 11497900 # number of demand (read+write) hits system.cpu1.dcache.demand_hits::total 11497900 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::0 11497900 # number of overall hits -system.cpu1.dcache.overall_hits::1 0 # number of overall hits +system.cpu1.dcache.overall_hits::cpu1.data 11497900 # number of overall hits system.cpu1.dcache.overall_hits::total 11497900 # number of overall hits -system.cpu1.dcache.ReadReq_misses::0 188245 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::cpu1.data 188245 # number of ReadReq misses system.cpu1.dcache.ReadReq_misses::total 188245 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::0 137493 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 137493 # number of WriteReq misses system.cpu1.dcache.WriteReq_misses::total 137493 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::0 11557 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11557 # number of LoadLockedReq misses system.cpu1.dcache.LoadLockedReq_misses::total 11557 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::0 9906 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 9906 # number of StoreCondReq misses system.cpu1.dcache.StoreCondReq_misses::total 9906 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::0 325738 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::cpu1.data 325738 # number of demand (read+write) misses system.cpu1.dcache.demand_misses::total 325738 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::0 325738 # number of overall misses -system.cpu1.dcache.overall_misses::1 0 # number of overall misses +system.cpu1.dcache.overall_misses::cpu1.data 325738 # number of overall misses system.cpu1.dcache.overall_misses::total 325738 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency 2729023500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency 4123985000 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency 131721000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency 82493000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency 6853008500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency 6853008500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::0 6533535 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2729023500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2729023500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4123985000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 4123985000 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 131721000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 131721000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 82493000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 82493000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 6853008500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 6853008500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 6853008500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 6853008500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 6533535 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_accesses::total 6533535 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::0 5290103 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 5290103 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::total 5290103 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::0 116352 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 116352 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::total 116352 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::0 116309 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 116309 # number of StoreCondReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::total 116309 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::0 11823638 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::cpu1.data 11823638 # number of demand (read+write) accesses system.cpu1.dcache.demand_accesses::total 11823638 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::0 11823638 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 11823638 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 11823638 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::0 0.028812 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::0 0.025991 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.099328 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::0 0.085170 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::0 0.027550 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::0 0.027550 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::0 14497.189832 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::0 29994.145156 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 11397.508004 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 8327.579245 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::0 21038.406634 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::1 inf # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::0 21038.406634 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::1 inf # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.028812 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.025991 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.099328 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.085170 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027550 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.027550 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14497.189832 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 29994.145156 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11397.508004 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8327.579245 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21038.406634 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21038.406634 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -766,54 +929,53 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks 253551 # number of writebacks -system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses 188245 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses 137493 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses 11557 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses 9900 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses 325738 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses 325738 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency 2164153000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency 3711466500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 97050000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency 52793000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency 5875619500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency 5875619500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 137931975000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 470526000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency 138402501000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.028812 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.025991 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.099328 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.085118 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::0 0.027550 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::0 0.027550 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 11496.470026 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 26993.857869 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 8397.508004 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 5332.626263 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 18037.869392 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 18037.869392 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.dcache.writebacks::writebacks 253551 # number of writebacks +system.cpu1.dcache.writebacks::total 253551 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 188245 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 188245 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 137493 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 137493 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11557 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11557 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9900 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 9900 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 325738 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 325738 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 325738 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 325738 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2164153000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2164153000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 3711466500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 3711466500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 97050000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 97050000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 52793000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 52793000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5875619500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 5875619500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5875619500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 5875619500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 137931975000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 137931975000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 470526000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 470526000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 138402501000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 138402501000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.028812 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025991 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.099328 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.085118 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027550 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027550 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11496.470026 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26993.857869 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8397.508004 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5332.626263 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18037.869392 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18037.869392 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use @@ -821,38 +983,6 @@ system.iocache.total_refs 0 # To system.iocache.sampled_refs 0 # Sample count of references to valid blocks. system.iocache.avg_refs no_value # Average number of references to valid blocks. system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.iocache.demand_hits::0 0 # number of demand (read+write) hits -system.iocache.demand_hits::1 0 # number of demand (read+write) hits -system.iocache.demand_hits::total 0 # number of demand (read+write) hits -system.iocache.overall_hits::0 0 # number of overall hits -system.iocache.overall_hits::1 0 # number of overall hits -system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.demand_misses::0 0 # number of demand (read+write) misses -system.iocache.demand_misses::1 0 # number of demand (read+write) misses -system.iocache.demand_misses::total 0 # number of demand (read+write) misses -system.iocache.overall_misses::0 0 # number of overall misses -system.iocache.overall_misses::1 0 # number of overall misses -system.iocache.overall_misses::total 0 # number of overall misses -system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency 0 # number of overall miss cycles -system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses -system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses -system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses -system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses -system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency -system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency -system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency -system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency -system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency -system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -861,28 +991,12 @@ system.iocache.avg_blocked_cycles::no_mshrs no_value # system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks 0 # number of writebacks -system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses 0 # number of overall MSHR misses -system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_uncacheable_latency 1342252853622 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency 1342252853622 # number of overall MSHR uncacheable cycles -system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses -system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.iocache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.iocache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated -system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1342252853622 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1342252853622 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1342252853622 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1342252853622 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency +system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini index b4466ea53..49efd7ba0 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=true time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,7 +9,6 @@ time_sync_spin_threshold=100000000 [system] type=LinuxArmSystem children=bridge cf0 cpu intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver -boot_cpu_frequency=500 boot_loader=/dist/m5/system/binaries/boot.arm boot_loader_mem=system.nvmem boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 @@ -90,6 +90,7 @@ profile=0 progress_interval=0 system=system tracer=system.cpu.tracer +workload= dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side @@ -104,20 +105,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -149,20 +143,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -214,20 +201,13 @@ is_top_level=false latency=50000 max_miss_count=0 mshrs=20 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=500000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=1024 subblock_size=0 +system=system tgts_per_mshr=12 trace_addr=0 two_queue=false @@ -246,20 +226,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=92 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=4194304 subblock_size=0 +system=system tgts_per_mshr=16 trace_addr=0 two_queue=false @@ -285,7 +258,6 @@ fake_mem=false pio_addr=0 pio_latency=1000 pio_size=8 -platform=system.realview ret_bad_addr=true ret_data16=65535 ret_data32=4294967295 @@ -327,7 +299,6 @@ system=system type=A9SCU pio_addr=520093696 pio_latency=1000 -platform=system.realview system=system pio=system.membus.port[5] @@ -337,7 +308,6 @@ amba_id=0 ignore_access=false pio_addr=268451840 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[24] @@ -407,7 +377,6 @@ max_backoff_delay=10000000 min_backoff_delay=4000 pio_addr=268566528 pio_latency=10000 -platform=system.realview system=system vnc=system.vncserver dma=system.iobus.port[6] @@ -419,7 +388,6 @@ amba_id=0 ignore_access=false pio_addr=268632064 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[12] @@ -429,7 +397,6 @@ fake_mem=true pio_addr=1073741824 pio_latency=1000 pio_size=536870912 -platform=system.realview ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -458,7 +425,6 @@ amba_id=0 ignore_access=false pio_addr=268513280 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[19] @@ -468,7 +434,6 @@ amba_id=0 ignore_access=false pio_addr=268517376 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[20] @@ -478,7 +443,6 @@ amba_id=0 ignore_access=false pio_addr=268521472 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[21] @@ -491,7 +455,6 @@ int_num=52 is_mouse=false pio_addr=268460032 pio_latency=1000 -platform=system.realview system=system vnc=system.vncserver pio=system.iobus.port[7] @@ -505,7 +468,6 @@ int_num=53 is_mouse=true pio_addr=268464128 pio_latency=1000 -platform=system.realview system=system vnc=system.vncserver pio=system.iobus.port[8] @@ -516,7 +478,6 @@ fake_mem=false pio_addr=520101888 pio_latency=1000 pio_size=4095 -platform=system.realview ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -535,7 +496,6 @@ int_num_timer=29 int_num_watchdog=30 pio_addr=520095232 pio_latency=1000 -platform=system.realview system=system pio=system.membus.port[6] @@ -545,7 +505,6 @@ amba_id=0 ignore_access=false pio_addr=268455936 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[25] @@ -554,7 +513,6 @@ type=RealViewCtrl idreg=0 pio_addr=268435456 pio_latency=1000 -platform=system.realview proc_id0=201326592 proc_id1=201327138 system=system @@ -566,7 +524,6 @@ amba_id=266289 ignore_access=false pio_addr=268529664 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[26] @@ -576,7 +533,6 @@ amba_id=0 ignore_access=false pio_addr=268492800 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[23] @@ -586,7 +542,6 @@ amba_id=0 ignore_access=false pio_addr=269357056 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[16] @@ -596,7 +551,6 @@ amba_id=0 ignore_access=true pio_addr=268439552 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[17] @@ -606,7 +560,6 @@ amba_id=0 ignore_access=false pio_addr=268488704 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[22] @@ -620,7 +573,6 @@ int_num0=36 int_num1=36 pio_addr=268505088 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[3] @@ -634,7 +586,6 @@ int_num0=37 int_num1=37 pio_addr=268509184 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[4] @@ -657,7 +608,6 @@ amba_id=0 ignore_access=false pio_addr=268476416 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[13] @@ -667,7 +617,6 @@ amba_id=0 ignore_access=false pio_addr=268480512 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[14] @@ -677,7 +626,6 @@ amba_id=0 ignore_access=false pio_addr=268484608 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[15] @@ -687,7 +635,6 @@ amba_id=0 ignore_access=false pio_addr=268500992 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[18] diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout index 661533caf..af233a80c 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:21:22 -gem5 started Jan 23 2012 04:25:02 +gem5 compiled Feb 11 2012 13:10:40 +gem5 started Feb 11 2012 15:37:03 gem5 executing on zizzer -command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 543720998..833c19821 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 2.591442 # Nu sim_ticks 2591441692000 # Number of ticks simulated final_tick 2591441692000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 852555 # Simulator instruction rate (inst/s) -host_tick_rate 29271571690 # Simulator tick rate (ticks/s) -host_mem_usage 379496 # Number of bytes of host memory used -host_seconds 88.53 # Real time elapsed on the host -sim_insts 75477515 # Number of instructions simulated +host_inst_rate 874833 # Simulator instruction rate (inst/s) +host_op_rate 1117723 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38375829651 # Simulator tick rate (ticks/s) +host_mem_usage 376612 # Number of bytes of host memory used +host_seconds 67.53 # Real time elapsed on the host +sim_insts 59075683 # Number of instructions simulated +sim_ops 75477515 # Number of ops (including micro ops) simulated system.nvmem.bytes_read 20 # Number of bytes read from this memory system.nvmem.bytes_inst_read 20 # Number of instructions bytes read from this memory system.nvmem.bytes_written 0 # Number of bytes written to this memory @@ -34,84 +36,125 @@ system.l2c.total_refs 1535240 # To system.l2c.sampled_refs 146709 # Sample count of references to valid blocks. system.l2c.avg_refs 10.464525 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 10331.534348 # Average occupied blocks per context -system.l2c.occ_blocks::1 14596.842556 # Average occupied blocks per context -system.l2c.occ_percent::0 0.157647 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.222730 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 1198360 # number of ReadReq hits -system.l2c.ReadReq_hits::1 12495 # number of ReadReq hits +system.l2c.occ_blocks::writebacks 14588.908220 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 6.963925 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.itb.walker 0.970411 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 5158.445831 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 5173.088517 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.222609 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.dtb.walker 0.000106 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.inst 0.078712 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.078935 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.380377 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 8825 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.itb.walker 3670 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.inst 837469 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 360891 # number of ReadReq hits system.l2c.ReadReq_hits::total 1210855 # number of ReadReq hits -system.l2c.Writeback_hits::0 610049 # number of Writeback hits +system.l2c.Writeback_hits::writebacks 610049 # number of Writeback hits system.l2c.Writeback_hits::total 610049 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 26 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::0 106473 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu.data 106473 # number of ReadExReq hits system.l2c.ReadExReq_hits::total 106473 # number of ReadExReq hits -system.l2c.demand_hits::0 1304833 # number of demand (read+write) hits -system.l2c.demand_hits::1 12495 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.dtb.walker 8825 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.itb.walker 3670 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.inst 837469 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 467364 # number of demand (read+write) hits system.l2c.demand_hits::total 1317328 # number of demand (read+write) hits -system.l2c.overall_hits::0 1304833 # number of overall hits -system.l2c.overall_hits::1 12495 # number of overall hits +system.l2c.overall_hits::cpu.dtb.walker 8825 # number of overall hits +system.l2c.overall_hits::cpu.itb.walker 3670 # number of overall hits +system.l2c.overall_hits::cpu.inst 837469 # number of overall hits +system.l2c.overall_hits::cpu.data 467364 # number of overall hits system.l2c.overall_hits::total 1317328 # number of overall hits -system.l2c.ReadReq_misses::0 31685 # number of ReadReq misses -system.l2c.ReadReq_misses::1 37 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.dtb.walker 24 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.itb.walker 13 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.inst 14429 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 17256 # number of ReadReq misses system.l2c.ReadReq_misses::total 31722 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 2875 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu.data 2875 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 2875 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::0 140928 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu.data 140928 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 140928 # number of ReadExReq misses -system.l2c.demand_misses::0 172613 # number of demand (read+write) misses -system.l2c.demand_misses::1 37 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.dtb.walker 24 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.itb.walker 13 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.inst 14429 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 158184 # number of demand (read+write) misses system.l2c.demand_misses::total 172650 # number of demand (read+write) misses -system.l2c.overall_misses::0 172613 # number of overall misses -system.l2c.overall_misses::1 37 # number of overall misses +system.l2c.overall_misses::cpu.dtb.walker 24 # number of overall misses +system.l2c.overall_misses::cpu.itb.walker 13 # number of overall misses +system.l2c.overall_misses::cpu.inst 14429 # number of overall misses +system.l2c.overall_misses::cpu.data 158184 # number of overall misses system.l2c.overall_misses::total 172650 # number of overall misses -system.l2c.ReadReq_miss_latency 1654516000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency 1040000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 7338006500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 8992522500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 8992522500 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 1230045 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 12532 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_miss_latency::cpu.dtb.walker 1250000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.itb.walker 676000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.inst 753120500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.data 899469500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1654516000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu.data 1040000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 1040000 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu.data 7338006500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7338006500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu.dtb.walker 1250000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.itb.walker 676000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.inst 753120500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.data 8237476000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 8992522500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu.dtb.walker 1250000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.itb.walker 676000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.inst 753120500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.data 8237476000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 8992522500 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu.dtb.walker 8849 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.itb.walker 3683 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.inst 851898 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 378147 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 1242577 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 610049 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 610049 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 610049 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 2901 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu.data 2901 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 2901 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 247401 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu.data 247401 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 247401 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 1477446 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 12532 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.dtb.walker 8849 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.itb.walker 3683 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.inst 851898 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 625548 # number of demand (read+write) accesses system.l2c.demand_accesses::total 1489978 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 1477446 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 12532 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.dtb.walker 8849 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.itb.walker 3683 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.inst 851898 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.data 625548 # number of overall (read+write) accesses system.l2c.overall_accesses::total 1489978 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.025759 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.002952 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.028712 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.991038 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.569634 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.116832 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.002952 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.119784 # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.116832 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.002952 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.119784 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 52217.642418 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 44716648.648649 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 44768866.291066 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 361.739130 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 52069.187812 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 52096.438275 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 243041148.648649 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 243093245.086924 # average overall miss latency -system.l2c.overall_avg_miss_latency::0 52096.438275 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 243041148.648649 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 243093245.086924 # average overall miss latency +system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.002712 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.003530 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.inst 0.016937 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.045633 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu.data 0.991038 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu.data 0.569634 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu.dtb.walker 0.002712 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.itb.walker 0.003530 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.inst 0.016937 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.252873 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.dtb.walker 0.002712 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.itb.walker 0.003530 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.inst 0.016937 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.252873 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52083.333333 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.inst 52194.919953 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.data 52125.028975 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu.data 361.739130 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu.data 52069.187812 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52083.333333 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.inst 52194.919953 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.data 52075.279421 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52083.333333 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.inst 52194.919953 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.data 52075.279421 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -120,48 +163,87 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 103410 # number of writebacks -system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits 0 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 31722 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 2875 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses 140928 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 172650 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 172650 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 1273844000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 115156000 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency 5646870000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 6920714000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 6920714000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency 131817513000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency 31206766500 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency 163024279500 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.025789 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 2.531280 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 2.557069 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::0 0.991038 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::0 0.569634 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 0.116857 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 13.776732 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 13.893589 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0.116857 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 13.776732 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 13.893589 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 40156.484459 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40054.260870 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40069.184264 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40085.224443 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40085.224443 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated -system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.writebacks::writebacks 103410 # number of writebacks +system.l2c.writebacks::total 103410 # number of writebacks +system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 24 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.itb.walker 13 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.inst 14429 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.data 17256 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 31722 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu.data 2875 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 2875 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu.data 140928 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 140928 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu.dtb.walker 24 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.itb.walker 13 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.inst 14429 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.data 158184 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 172650 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu.dtb.walker 24 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.itb.walker 13 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.inst 14429 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.data 158184 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 172650 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 962000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 520000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.inst 579966000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.data 692396000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1273844000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 115156000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 115156000 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5646870000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5646870000 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 962000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.itb.walker 520000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.inst 579966000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.data 6339266000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 6920714000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 962000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.itb.walker 520000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.inst 579966000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.data 6339266000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 6920714000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 264840000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131552673000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 131817513000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 31206766500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 31206766500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.inst 264840000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.data 162759439500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 163024279500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.002712 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.003530 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.016937 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.045633 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.991038 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.569634 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.002712 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.003530 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.016937 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.252873 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.002712 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.003530 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.016937 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.252873 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40083.333333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40194.469471 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40124.942049 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40054.260870 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40069.184264 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40083.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40194.469471 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40075.266778 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40083.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40194.469471 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40075.266778 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -214,7 +296,8 @@ system.cpu.itb.accesses 60362193 # DT system.cpu.numCycles 5182883384 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 75477515 # Number of instructions executed +system.cpu.committedInsts 59075683 # Number of instructions committed +system.cpu.committedOps 75477515 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 68255270 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses system.cpu.num_func_calls 1975579 # number of times a function call or return occured @@ -240,51 +323,39 @@ system.cpu.icache.total_refs 59504239 # To system.cpu.icache.sampled_refs 853483 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 69.719302 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 18512998000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 510.943281 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.997936 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::0 59504239 # number of ReadReq hits +system.cpu.icache.occ_blocks::cpu.inst 510.943281 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.997936 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.997936 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 59504239 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 59504239 # number of ReadReq hits -system.cpu.icache.demand_hits::0 59504239 # number of demand (read+write) hits -system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.icache.demand_hits::cpu.inst 59504239 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 59504239 # number of demand (read+write) hits -system.cpu.icache.overall_hits::0 59504239 # number of overall hits -system.cpu.icache.overall_hits::1 0 # number of overall hits +system.cpu.icache.overall_hits::cpu.inst 59504239 # number of overall hits system.cpu.icache.overall_hits::total 59504239 # number of overall hits -system.cpu.icache.ReadReq_misses::0 853483 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::cpu.inst 853483 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 853483 # number of ReadReq misses -system.cpu.icache.demand_misses::0 853483 # number of demand (read+write) misses -system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.icache.demand_misses::cpu.inst 853483 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 853483 # number of demand (read+write) misses -system.cpu.icache.overall_misses::0 853483 # number of overall misses -system.cpu.icache.overall_misses::1 0 # number of overall misses +system.cpu.icache.overall_misses::cpu.inst 853483 # number of overall misses system.cpu.icache.overall_misses::total 853483 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 12547128000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 12547128000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 12547128000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::0 60357722 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12547128000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12547128000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12547128000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12547128000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12547128000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12547128000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 60357722 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 60357722 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::0 60357722 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::cpu.inst 60357722 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 60357722 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::0 60357722 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 60357722 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 60357722 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::0 0.014140 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::0 0.014140 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::0 0.014140 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::0 14701.087192 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::0 14701.087192 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::0 14701.087192 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014140 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.014140 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.014140 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14701.087192 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14701.087192 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14701.087192 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -293,34 +364,32 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 45661 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 853483 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 853483 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 853483 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 9984295500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 9984295500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 9984295500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency 350913000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency 350913000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.014140 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::0 0.014140 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::0 0.014140 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11698.294518 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11698.294518 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11698.294518 # average overall mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.writebacks::writebacks 45661 # number of writebacks +system.cpu.icache.writebacks::total 45661 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 853483 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 853483 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 853483 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 853483 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 853483 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 853483 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9984295500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9984295500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9984295500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9984295500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9984295500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9984295500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 350913000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 350913000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 350913000 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 350913000 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014140 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014140 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014140 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11698.294518 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11698.294518 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11698.294518 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 626903 # number of replacements system.cpu.dcache.tagsinuse 511.875592 # Cycle average of tags in use @@ -328,77 +397,63 @@ system.cpu.dcache.total_refs 23615096 # To system.cpu.dcache.sampled_refs 627415 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 37.638718 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 660309000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 511.875592 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999757 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::0 13170367 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 511.875592 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999757 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999757 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 13170367 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 13170367 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::0 9958094 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 9958094 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 9958094 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::0 236142 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 236142 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 236142 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::0 247592 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247592 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 247592 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::0 23128461 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::cpu.data 23128461 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 23128461 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::0 23128461 # number of overall hits -system.cpu.dcache.overall_hits::1 0 # number of overall hits +system.cpu.dcache.overall_hits::cpu.data 23128461 # number of overall hits system.cpu.dcache.overall_hits::total 23128461 # number of overall hits -system.cpu.dcache.ReadReq_misses::0 368563 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 368563 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 368563 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::0 250302 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 250302 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 250302 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::0 11451 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 11451 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 11451 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::0 618865 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::cpu.data 618865 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 618865 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::0 618865 # number of overall misses -system.cpu.dcache.overall_misses::1 0 # number of overall misses +system.cpu.dcache.overall_misses::cpu.data 618865 # number of overall misses system.cpu.dcache.overall_misses::total 618865 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 5846897000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 9551170500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 186076500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 15398067500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 15398067500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::0 13538930 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5846897000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5846897000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9551170500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9551170500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 186076500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 186076500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 15398067500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 15398067500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 15398067500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 15398067500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13538930 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 13538930 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::0 10208396 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10208396 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 10208396 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::0 247593 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247593 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 247593 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::0 247592 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247592 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 247592 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::0 23747326 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 23747326 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 23747326 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::0 23747326 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 23747326 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 23747326 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::0 0.027222 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::0 0.024519 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.046249 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::0 0.026060 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::0 0.026060 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::0 15864.036813 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::0 38158.586428 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 16249.803511 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::0 24881.141283 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::0 24881.141283 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027222 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024519 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046249 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.026060 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.026060 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15864.036813 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38158.586428 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16249.803511 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 24881.141283 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 24881.141283 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -407,48 +462,47 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 564388 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 368563 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 250302 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses 11451 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses 618865 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 618865 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 4741074500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 8800219500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 151723500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 13541294000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 13541294000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 146946835000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 40367455500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 187314290500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.027222 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.024519 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.046249 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::0 0.026060 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::0 0.026060 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12863.674596 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35158.406645 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 13249.803511 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 21880.852852 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 21880.852852 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 564388 # number of writebacks +system.cpu.dcache.writebacks::total 564388 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368563 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 368563 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250302 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 250302 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11451 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 11451 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 618865 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 618865 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 618865 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 618865 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4741074500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4741074500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8800219500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8800219500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 151723500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 151723500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13541294000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13541294000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13541294000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13541294000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 146946835000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 146946835000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 40367455500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 40367455500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 187314290500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 187314290500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027222 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024519 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046249 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026060 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026060 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12863.674596 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35158.406645 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13249.803511 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21880.852852 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21880.852852 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use @@ -456,38 +510,6 @@ system.iocache.total_refs 0 # To system.iocache.sampled_refs 0 # Sample count of references to valid blocks. system.iocache.avg_refs no_value # Average number of references to valid blocks. system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.iocache.demand_hits::0 0 # number of demand (read+write) hits -system.iocache.demand_hits::1 0 # number of demand (read+write) hits -system.iocache.demand_hits::total 0 # number of demand (read+write) hits -system.iocache.overall_hits::0 0 # number of overall hits -system.iocache.overall_hits::1 0 # number of overall hits -system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.demand_misses::0 0 # number of demand (read+write) misses -system.iocache.demand_misses::1 0 # number of demand (read+write) misses -system.iocache.demand_misses::total 0 # number of demand (read+write) misses -system.iocache.overall_misses::0 0 # number of overall misses -system.iocache.overall_misses::1 0 # number of overall misses -system.iocache.overall_misses::total 0 # number of overall misses -system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency 0 # number of overall miss cycles -system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses -system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses -system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses -system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses -system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency -system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency -system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency -system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency -system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency -system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -496,28 +518,12 @@ system.iocache.avg_blocked_cycles::no_mshrs no_value # system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks 0 # number of writebacks -system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses 0 # number of overall MSHR misses -system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_uncacheable_latency 1341941439938 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency 1341941439938 # number of overall MSHR uncacheable cycles -system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses -system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.iocache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.iocache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated -system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1341941439938 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1341941439938 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1341941439938 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1341941439938 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency +system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |