diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-03-01 13:20:30 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-03-01 13:20:30 -0500 |
| commit | cb9e208a4c1b564556275d9b6ee0257da4208a88 (patch) | |
| tree | 6d1e5d4393ae0758da69261a11c37374c2a47a88 /tests/quick/fs/10.linux-boot/ref/arm | |
| parent | 0facc8e1acb9b5261ac49f87ca489ba823c8e9f3 (diff) | |
| download | gem5-cb9e208a4c1b564556275d9b6ee0257da4208a88.tar.xz | |
stats: Update stats to reflect SimpleDRAM changes
This patch bumps the stats to reflect the slight change in how the
retry is handled, and also the pruning of some redundant stats.
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm')
5 files changed, 1470 insertions, 1545 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index 839e0acab..9a52baa4f 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.912097 # Nu sim_ticks 912096763500 # Number of ticks simulated final_tick 912096763500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1193297 # Simulator instruction rate (inst/s) -host_op_rate 1536367 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 17661410361 # Simulator tick rate (ticks/s) -host_mem_usage 435356 # Number of bytes of host memory used -host_seconds 51.64 # Real time elapsed on the host +host_inst_rate 1025890 # Simulator instruction rate (inst/s) +host_op_rate 1320831 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15183699019 # Simulator tick rate (ticks/s) +host_mem_usage 392232 # Number of bytes of host memory used +host_seconds 60.07 # Real time elapsed on the host sim_insts 61625970 # Number of instructions simulated sim_ops 79343340 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory @@ -117,26 +117,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 0 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see @@ -169,7 +156,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -202,7 +188,6 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see system.physmem.totQLat 0 # Total cycles spent in queuing delays system.physmem.totMemAccLat 0 # Sum of mem lat for all requests system.physmem.totBusLat 0 # Total cycles spent in databus access diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index 9811be55f..9271f187d 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.332810 # Nu sim_ticks 2332810264000 # Number of ticks simulated final_tick 2332810264000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1101050 # Simulator instruction rate (inst/s) -host_op_rate 1415882 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42519386287 # Simulator tick rate (ticks/s) -host_mem_usage 435224 # Number of bytes of host memory used -host_seconds 54.86 # Real time elapsed on the host +host_inst_rate 1712706 # Simulator instruction rate (inst/s) +host_op_rate 2202434 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 66139785958 # Simulator tick rate (ticks/s) +host_mem_usage 391204 # Number of bytes of host memory used +host_seconds 35.27 # Real time elapsed on the host sim_insts 60408639 # Number of instructions simulated sim_ops 77681819 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory @@ -100,26 +100,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 0 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see @@ -152,7 +139,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -185,7 +171,6 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see system.physmem.totQLat 0 # Total cycles spent in queuing delays system.physmem.totMemAccLat 0 # Sum of mem lat for all requests system.physmem.totBusLat 0 # Total cycles spent in databus access diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 13c85b6d1..10f005f3e 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,159 +1,146 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.183003 # Number of seconds simulated -sim_ticks 1183003114000 # Number of ticks simulated -final_tick 1183003114000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.182958 # Number of seconds simulated +sim_ticks 1182958259000 # Number of ticks simulated +final_tick 1182958259000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 673901 # Simulator instruction rate (inst/s) -host_op_rate 858757 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 12970235901 # Simulator tick rate (ticks/s) -host_mem_usage 408748 # Number of bytes of host memory used -host_seconds 91.21 # Real time elapsed on the host -sim_insts 61465824 # Number of instructions simulated -sim_ops 78326377 # Number of ops (including micro ops) simulated +host_inst_rate 332432 # Simulator instruction rate (inst/s) +host_op_rate 423606 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6399087906 # Simulator tick rate (ticks/s) +host_mem_usage 408760 # Number of bytes of host memory used +host_seconds 184.86 # Real time elapsed on the host +sim_insts 61454647 # Number of instructions simulated +sim_ops 78309315 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 379748 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4530164 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 393380 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4709236 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 336668 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4964784 # Number of bytes read from this memory -system.physmem.bytes_read::total 62116388 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 379748 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 336668 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 716416 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4089728 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 323164 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4815472 # Number of bytes read from this memory +system.physmem.bytes_read::total 62146212 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 393380 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 323164 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 716544 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4116096 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7117072 # Number of bytes written to this memory +system.physmem.bytes_written::total 7143440 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 12152 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 70856 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 12365 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 73654 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 5342 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 77601 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6654023 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 63902 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.inst 5131 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 75268 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6654489 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 64314 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 820738 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43875212 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 821150 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43876875 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 54 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 162 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 321003 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3829376 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 108 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 332539 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3980898 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 216 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 284588 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4196763 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52507375 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 321003 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 284588 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 605591 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3457073 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 14370 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2544663 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6016106 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3457073 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43875212 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 273183 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4070703 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52534577 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 332539 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 273183 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 605722 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3479494 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 14371 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2544759 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6038624 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3479494 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43876875 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 54 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 162 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 321003 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3843746 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 108 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 332539 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3995269 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 216 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 284588 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 6741426 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 58523481 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6654023 # Total number of read requests seen -system.physmem.writeReqs 820738 # Total number of write requests seen -system.physmem.cpureqs 272097 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 425857472 # Total number of bytes read from memory -system.physmem.bytesWritten 52527232 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 62116388 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7117072 # bytesWritten derated as per pkt->getSize() +system.physmem.bw_total::cpu1.inst 273183 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 6615462 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 58573201 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 6654489 # Total number of read requests seen +system.physmem.writeReqs 821150 # Total number of write requests seen +system.physmem.cpureqs 235683 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 425887296 # Total number of bytes read from memory +system.physmem.bytesWritten 52553600 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 62146212 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7143440 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 112 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 11760 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 422267 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 415727 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 415213 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 415818 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 415767 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 415004 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 415107 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 415928 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 415784 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 415110 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 415164 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 415654 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 415632 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 415090 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 415000 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 415646 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 51297 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 51187 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50850 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51382 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 51290 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50625 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50696 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51406 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51898 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51190 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51285 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51758 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51708 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51260 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51138 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51768 # Track writes on a per bank basis +system.physmem.neitherReadNorWrite 11769 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 422283 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 415708 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 415257 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 415923 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 415836 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 415086 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 415138 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 415982 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 415774 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 415145 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 415183 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 415686 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 415664 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 415065 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 414968 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 415679 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 51312 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 51158 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50892 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51475 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51354 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50696 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50735 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51449 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51887 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51225 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 51295 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51778 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51726 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 51254 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51118 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51796 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 1182998675500 # Total gap between requests +system.physmem.totGap 1182953705000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 6825 # Categorize read packet sizes system.physmem.readPktSize::3 6488064 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 159134 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 756836 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 63902 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 11760 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 570635 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 408572 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 415826 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1537846 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1165216 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1169840 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1140716 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 29537 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 27577 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 48457 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 69066 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 48178 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 5864 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 5691 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 5515 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 5307 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 68 # What read queue length does an incoming req see +system.physmem.readPktSize::6 159600 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 756836 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 64314 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 571059 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 408588 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 415867 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1537787 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1165425 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1169620 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1140545 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 29607 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 27579 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 48460 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 69110 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 48185 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 5882 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 5724 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 5512 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 5352 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 75 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -169,61 +156,59 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 35513 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 35658 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 35664 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 35672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 35674 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 35678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 35678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 35681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 35681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 35451 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 35680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 35684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 35689 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 35694 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 35695 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 35698 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 35700 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 35702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 146986341539 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 189297882789 # Sum of mem lat for all requests -system.physmem.totBusLat 33269555000 # Total cycles spent in databus access -system.physmem.totBankLat 9041986250 # Total cycles spent in bank access -system.physmem.avgQLat 22090.22 # Average queueing delay per request -system.physmem.avgBankLat 1358.90 # Average bank access latency per request +system.physmem.wrQLenPdf::29 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.totQLat 147016739500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 189339617000 # Sum of mem lat for all requests +system.physmem.totBusLat 33271885000 # Total cycles spent in databus access +system.physmem.totBankLat 9050992500 # Total cycles spent in bank access +system.physmem.avgQLat 22093.24 # Average queueing delay per request +system.physmem.avgBankLat 1360.16 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28449.12 # Average memory access latency -system.physmem.avgRdBW 359.98 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 44.40 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 52.51 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 6.02 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 28453.39 # Average memory access latency +system.physmem.avgRdBW 360.02 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 44.43 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 52.53 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 6.04 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.16 # Data bus utilization in percentage system.physmem.avgRdQLen 0.16 # Average read queue length over time -system.physmem.avgWrQLen 12.54 # Average write queue length over time -system.physmem.readRowHits 6611960 # Number of row buffer hits during reads -system.physmem.writeRowHits 800133 # Number of row buffer hits during writes +system.physmem.avgWrQLen 12.52 # Average write queue length over time +system.physmem.readRowHits 6612346 # Number of row buffer hits during reads +system.physmem.writeRowHits 800481 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.37 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 97.49 # Row buffer hit rate for writes -system.physmem.avgGap 158265.75 # Average gap between requests +system.physmem.writeRowHitRate 97.48 # Row buffer hit rate for writes +system.physmem.avgGap 158241.15 # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -242,237 +227,237 @@ system.realview.nvmem.bw_inst_read::total 57 # I system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 41 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 69015 # number of replacements -system.l2c.tagsinuse 53041.665406 # Cycle average of tags in use -system.l2c.total_refs 1678594 # Total number of references to valid blocks. -system.l2c.sampled_refs 134211 # Sample count of references to valid blocks. -system.l2c.avg_refs 12.507127 # Average number of references to valid blocks. +system.l2c.replacements 69480 # number of replacements +system.l2c.tagsinuse 53041.287373 # Cycle average of tags in use +system.l2c.total_refs 1677464 # Total number of references to valid blocks. +system.l2c.sampled_refs 134656 # Sample count of references to valid blocks. +system.l2c.avg_refs 12.457403 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 40191.767552 # Average occupied blocks per requestor +system.l2c.occ_blocks::writebacks 40190.252096 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.dtb.walker 0.000406 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.003100 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 3723.993423 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 4235.450091 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 2.742043 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 2826.235882 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 2061.472909 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.613278 # Average percentage of cache occupancy +system.l2c.occ_blocks::cpu0.itb.walker 0.001419 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 3727.107062 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 4236.234020 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 2.741995 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 2823.629298 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 2061.321078 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.613255 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.056824 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.064628 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.056871 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.064640 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.043125 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.031456 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.809352 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 3013 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 1662 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 349398 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 169915 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 6389 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1943 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 534803 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 180813 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1247936 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 573205 # number of Writeback hits -system.l2c.Writeback_hits::total 573205 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1121 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 611 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1732 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 229 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 78 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 307 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 47508 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 62580 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 110088 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 3013 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 1662 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 349398 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 217423 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 6389 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 1943 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 534803 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 243393 # number of demand (read+write) hits -system.l2c.demand_hits::total 1358024 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 3013 # 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average ReadReq mshr uncacheable latency @@ -656,27 +641,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 5883553 # DTB read hits -system.cpu0.dtb.read_misses 2148 # DTB read misses -system.cpu0.dtb.write_hits 4842455 # DTB write hits -system.cpu0.dtb.write_misses 405 # DTB write misses +system.cpu0.dtb.read_hits 7073604 # DTB read hits +system.cpu0.dtb.read_misses 3763 # DTB read misses +system.cpu0.dtb.write_hits 5658971 # DTB write hits +system.cpu0.dtb.write_misses 806 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1536 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 1807 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 91 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 143 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 203 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 5885701 # DTB read accesses -system.cpu0.dtb.write_accesses 4842860 # DTB write accesses +system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 7077367 # DTB read accesses +system.cpu0.dtb.write_accesses 5659777 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 10726008 # DTB hits -system.cpu0.dtb.misses 2553 # DTB misses -system.cpu0.dtb.accesses 10728561 # DTB accesses -system.cpu0.itb.inst_hits 24779849 # ITB inst hits -system.cpu0.itb.inst_misses 1350 # ITB inst misses +system.cpu0.dtb.hits 12732575 # DTB hits +system.cpu0.dtb.misses 4569 # DTB misses +system.cpu0.dtb.accesses 12737144 # DTB accesses +system.cpu0.itb.inst_hits 29573368 # ITB inst hits +system.cpu0.itb.inst_misses 2205 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -685,86 +670,86 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1347 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1332 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 24781199 # ITB inst accesses -system.cpu0.itb.hits 24779849 # DTB hits -system.cpu0.itb.misses 1350 # DTB misses -system.cpu0.itb.accesses 24781199 # DTB accesses -system.cpu0.numCycles 2364565551 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 29575573 # ITB inst accesses +system.cpu0.itb.hits 29573368 # DTB hits +system.cpu0.itb.misses 2205 # DTB misses +system.cpu0.itb.accesses 29575573 # DTB accesses +system.cpu0.numCycles 2365916518 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 24381823 # Number of instructions committed -system.cpu0.committedOps 31476006 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 28075203 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 4364 # Number of float alu accesses -system.cpu0.num_func_calls 1070639 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 3752398 # number of instructions that are conditional controls -system.cpu0.num_int_insts 28075203 # number of integer instructions -system.cpu0.num_fp_insts 4364 # number of float instructions -system.cpu0.num_int_register_reads 160702802 # number of times the integer registers were read -system.cpu0.num_int_register_writes 30522196 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3980 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 384 # number of times the floating registers were written -system.cpu0.num_mem_refs 11318426 # number of memory refs -system.cpu0.num_load_insts 6163151 # Number of load instructions -system.cpu0.num_store_insts 5155275 # Number of store instructions -system.cpu0.num_idle_cycles 2243464250.276980 # Number of idle cycles -system.cpu0.num_busy_cycles 121101300.723020 # Number of busy cycles -system.cpu0.not_idle_fraction 0.051215 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.948785 # Percentage of idle cycles +system.cpu0.committedInsts 28875412 # Number of instructions committed +system.cpu0.committedOps 37222765 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 33109279 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses +system.cpu0.num_func_calls 1241807 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4373656 # number of instructions that are conditional controls +system.cpu0.num_int_insts 33109279 # number of integer instructions +system.cpu0.num_fp_insts 3860 # number of float instructions +system.cpu0.num_int_register_reads 190112848 # number of times the integer registers were read +system.cpu0.num_int_register_writes 36234022 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written +system.cpu0.num_mem_refs 13400902 # number of memory refs +system.cpu0.num_load_insts 7411207 # Number of load instructions +system.cpu0.num_store_insts 5989695 # Number of store instructions +system.cpu0.num_idle_cycles 2224988060.360119 # Number of idle cycles +system.cpu0.num_busy_cycles 140928457.639881 # Number of busy cycles +system.cpu0.not_idle_fraction 0.059566 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.940434 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 38919 # number of quiesce instructions executed -system.cpu0.icache.replacements 354669 # number of replacements -system.cpu0.icache.tagsinuse 509.601981 # Cycle average of tags in use -system.cpu0.icache.total_refs 24424650 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 355181 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 68.766770 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 46697 # number of quiesce instructions executed +system.cpu0.icache.replacements 425482 # number of replacements +system.cpu0.icache.tagsinuse 509.601890 # Cycle average of tags in use +system.cpu0.icache.total_refs 29147356 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 425994 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 68.421987 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 74995953000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 509.601981 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu0.inst 509.601890 # Average occupied blocks per requestor system.cpu0.icache.occ_percent::cpu0.inst 0.995316 # Average percentage of cache occupancy system.cpu0.icache.occ_percent::total 0.995316 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 24424650 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 24424650 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 24424650 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 24424650 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 24424650 # number of overall hits -system.cpu0.icache.overall_hits::total 24424650 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 355182 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 355182 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 355182 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 355182 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 355182 # number of overall misses -system.cpu0.icache.overall_misses::total 355182 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 4877233500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 4877233500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 4877233500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 4877233500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 4877233500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 4877233500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 24779832 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 24779832 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 24779832 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 24779832 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 24779832 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 24779832 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014334 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014334 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014334 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014334 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014334 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014334 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13731.646029 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13731.646029 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13731.646029 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13731.646029 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13731.646029 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13731.646029 # average overall miss latency +system.cpu0.icache.ReadReq_hits::cpu0.inst 29147356 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 29147356 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 29147356 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 29147356 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 29147356 # number of overall hits +system.cpu0.icache.overall_hits::total 29147356 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 425995 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 425995 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 425995 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 425995 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 425995 # number of overall misses +system.cpu0.icache.overall_misses::total 425995 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5809941500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5809941500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5809941500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5809941500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5809941500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5809941500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 29573351 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 29573351 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 29573351 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 29573351 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 29573351 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 29573351 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014405 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014405 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014405 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014405 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014405 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014405 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13638.520405 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13638.520405 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13638.520405 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13638.520405 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13638.520405 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13638.520405 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -773,120 +758,120 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 355182 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 355182 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 355182 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 355182 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 355182 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 355182 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4166869500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4166869500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4166869500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4166869500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4166869500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4166869500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 425995 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 425995 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 425995 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 425995 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 425995 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 425995 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4957951500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4957951500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4957951500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4957951500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4957951500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4957951500 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 299599000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 299599000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 299599000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 299599000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014334 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014334 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014334 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014334 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014334 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014334 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11731.646029 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11731.646029 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11731.646029 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11731.646029 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11731.646029 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11731.646029 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014405 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014405 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014405 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014405 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014405 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014405 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11638.520405 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11638.520405 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11638.520405 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11638.520405 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11638.520405 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11638.520405 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 279602 # number of replacements -system.cpu0.dcache.tagsinuse 452.516720 # Cycle average of tags in use -system.cpu0.dcache.total_refs 10326636 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 279931 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 36.889934 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 331027 # number of replacements +system.cpu0.dcache.tagsinuse 453.640914 # Cycle average of tags in use +system.cpu0.dcache.total_refs 12276777 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 331539 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 37.029662 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 473552000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 452.516720 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.883822 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.883822 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 5477555 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5477555 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4571792 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4571792 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 129360 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 129360 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 130225 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 130225 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10049347 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10049347 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10049347 # number of overall hits -system.cpu0.dcache.overall_hits::total 10049347 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 191756 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 191756 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 126522 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 126522 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8645 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 8645 # 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Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.886017 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.886017 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6603200 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6603200 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5353855 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5353855 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147936 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 147936 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149699 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 149699 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 11957055 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 11957055 # 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miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029995 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.029995 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029995 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.029995 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13797.498992 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13797.498992 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 29171.841693 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 29171.841693 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9486.560291 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9486.560291 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5943.057410 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5943.057410 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19688.484132 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 19688.484132 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 19688.484132 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 19688.484132 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -895,66 +880,66 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # 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number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 5852308000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 5852308000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 5852308000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 5852308000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 12211047000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 12211047000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1122364500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1122364500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 13333411500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 13333411500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033824 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033824 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.026929 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.026929 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.062643 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.062643 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.055826 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.055826 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030699 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.030699 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030699 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.030699 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11969.414256 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11969.414256 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 28114.486018 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 28114.486018 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7098.380567 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7098.380567 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3923.116883 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3923.116883 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6540175500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 6540175500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6540175500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 6540175500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13562243000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13562243000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1128446000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1128446000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14690689000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14690689000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033386 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033386 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025780 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025780 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059374 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059374 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047631 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047631 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029995 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029995 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029995 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.029995 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11797.498992 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11797.498992 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27171.841693 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27171.841693 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7486.560291 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7486.560291 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3945.705890 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3945.705890 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18387.409749 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18387.409749 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18387.409749 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18387.409749 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17688.484132 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17688.484132 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17688.484132 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17688.484132 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -964,27 +949,27 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 9504194 # DTB read hits -system.cpu1.dtb.read_misses 5263 # DTB read misses -system.cpu1.dtb.write_hits 6646220 # DTB write hits -system.cpu1.dtb.write_misses 1833 # DTB write misses +system.cpu1.dtb.read_hits 8309714 # DTB read hits +system.cpu1.dtb.read_misses 3643 # DTB read misses +system.cpu1.dtb.write_hits 5826503 # DTB write hits +system.cpu1.dtb.write_misses 1435 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2237 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1965 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 191 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 140 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 249 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 9509457 # DTB read accesses -system.cpu1.dtb.write_accesses 6648053 # DTB write accesses +system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 8313357 # DTB read accesses +system.cpu1.dtb.write_accesses 5827938 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 16150414 # DTB hits -system.cpu1.dtb.misses 7096 # DTB misses -system.cpu1.dtb.accesses 16157510 # DTB accesses -system.cpu1.itb.inst_hits 37994467 # ITB inst hits -system.cpu1.itb.inst_misses 3017 # ITB inst misses +system.cpu1.dtb.hits 14136217 # DTB hits +system.cpu1.dtb.misses 5078 # DTB misses +system.cpu1.dtb.accesses 14141295 # DTB accesses +system.cpu1.itb.inst_hits 33189716 # ITB inst hits +system.cpu1.itb.inst_misses 2171 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -993,86 +978,86 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1458 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1495 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 37997484 # ITB inst accesses -system.cpu1.itb.hits 37994467 # DTB hits -system.cpu1.itb.misses 3017 # DTB misses -system.cpu1.itb.accesses 37997484 # DTB accesses -system.cpu1.numCycles 2366006228 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 33191887 # ITB inst accesses +system.cpu1.itb.hits 33189716 # DTB hits +system.cpu1.itb.misses 2171 # DTB misses +system.cpu1.itb.accesses 33191887 # DTB accesses +system.cpu1.numCycles 2364475282 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 37084001 # Number of instructions committed -system.cpu1.committedOps 46850371 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 42360540 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 5457 # Number of float alu accesses -system.cpu1.num_func_calls 1133542 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 4355119 # number of instructions that are conditional controls -system.cpu1.num_int_insts 42360540 # number of integer instructions -system.cpu1.num_fp_insts 5457 # number of float instructions -system.cpu1.num_int_register_reads 243148462 # number of times the integer registers were read -system.cpu1.num_int_register_writes 45181015 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 3577 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1884 # number of times the floating registers were written -system.cpu1.num_mem_refs 16764021 # number of memory refs -system.cpu1.num_load_insts 9884261 # Number of load instructions -system.cpu1.num_store_insts 6879760 # Number of store instructions -system.cpu1.num_idle_cycles 1849775265.196436 # Number of idle cycles -system.cpu1.num_busy_cycles 516230962.803564 # Number of busy cycles -system.cpu1.not_idle_fraction 0.218187 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.781813 # Percentage of idle cycles +system.cpu1.committedInsts 32579235 # Number of instructions committed +system.cpu1.committedOps 41086550 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 37310899 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses +system.cpu1.num_func_calls 962009 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3732730 # number of instructions that are conditional controls +system.cpu1.num_int_insts 37310899 # number of integer instructions +system.cpu1.num_fp_insts 6793 # number of float instructions +system.cpu1.num_int_register_reads 213650265 # number of times the integer registers were read +system.cpu1.num_int_register_writes 39453467 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written +system.cpu1.num_mem_refs 14673985 # number of memory refs +system.cpu1.num_load_insts 8631614 # Number of load instructions +system.cpu1.num_store_insts 6042371 # Number of store instructions +system.cpu1.num_idle_cycles 1868339828.826306 # Number of idle cycles +system.cpu1.num_busy_cycles 496135453.173694 # Number of busy cycles +system.cpu1.not_idle_fraction 0.209829 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.790171 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 51687 # number of quiesce instructions executed -system.cpu1.icache.replacements 540342 # number of replacements -system.cpu1.icache.tagsinuse 478.756805 # Cycle average of tags in use -system.cpu1.icache.total_refs 37453609 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 540854 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 69.249019 # Average number of references to valid blocks. +system.cpu1.kern.inst.quiesce 43883 # number of quiesce instructions executed +system.cpu1.icache.replacements 469209 # number of replacements +system.cpu1.icache.tagsinuse 478.755545 # Cycle average of tags in use +system.cpu1.icache.total_refs 32719991 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 469721 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 69.658353 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 92137748500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 478.756805 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.935072 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.935072 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 37453609 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 37453609 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 37453609 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 37453609 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 37453609 # number of overall hits -system.cpu1.icache.overall_hits::total 37453609 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 540854 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 540854 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 540854 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 540854 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 540854 # number of overall misses -system.cpu1.icache.overall_misses::total 540854 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7301553500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 7301553500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 7301553500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 7301553500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 7301553500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 7301553500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 37994463 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 37994463 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 37994463 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 37994463 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 37994463 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 37994463 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014235 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.014235 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014235 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.014235 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014235 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.014235 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13500.045299 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13500.045299 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13500.045299 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13500.045299 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13500.045299 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13500.045299 # average overall miss latency +system.cpu1.icache.occ_blocks::cpu1.inst 478.755545 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.935069 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.935069 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 32719991 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 32719991 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 32719991 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 32719991 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 32719991 # number of overall hits +system.cpu1.icache.overall_hits::total 32719991 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 469721 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 469721 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 469721 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 469721 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 469721 # number of overall misses +system.cpu1.icache.overall_misses::total 469721 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6363755000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 6363755000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 6363755000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 6363755000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 6363755000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 6363755000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 33189712 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 33189712 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 33189712 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 33189712 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 33189712 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 33189712 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014153 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.014153 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014153 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.014153 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014153 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.014153 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13547.946547 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13547.946547 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13547.946547 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13547.946547 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13547.946547 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13547.946547 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1081,120 +1066,120 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 540854 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 540854 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 540854 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 540854 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 540854 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 540854 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6219845500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 6219845500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6219845500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 6219845500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6219845500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 6219845500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 469721 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 469721 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 469721 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 469721 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 469721 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 469721 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5424313000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5424313000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5424313000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5424313000 # 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mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014153 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.014153 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014153 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.014153 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11547.946547 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11547.946547 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11547.946547 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11547.946547 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11547.946547 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11547.946547 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 343957 # number of replacements -system.cpu1.dcache.tagsinuse 473.088021 # Cycle average of tags in use -system.cpu1.dcache.total_refs 13916365 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 344469 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 40.399470 # Average number of references to valid blocks. +system.cpu1.dcache.replacements 292184 # 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Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.922136 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.922136 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 6945060 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 6945060 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4826351 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4826351 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 81758 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 81758 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 82709 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 82709 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 11771411 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 11771411 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 11771411 # number of overall hits +system.cpu1.dcache.overall_hits::total 11771411 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 170725 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 170725 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 149867 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 149867 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11052 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 11052 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10028 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10028 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 320592 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 320592 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 320592 # number of overall misses +system.cpu1.dcache.overall_misses::total 320592 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2168241500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2168241500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4524943000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 4524943000 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 92270500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 92270500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 51657000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 51657000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 6693184500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 6693184500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 6693184500 # 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miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.026513 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026513 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.026513 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12700.199151 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12700.199151 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 30193.057845 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 30193.057845 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8348.760405 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8348.760405 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5151.276426 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5151.276426 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20877.578043 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 20877.578043 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20877.578043 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 20877.578043 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1203,66 +1188,66 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 315665 # number of writebacks -system.cpu1.dcache.writebacks::total 315665 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 207178 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 207178 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 165249 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 165249 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11790 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11790 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9830 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 9830 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 372427 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 372427 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 372427 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 372427 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2224779500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2224779500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4504444000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4504444000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 79540000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 79540000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 30847000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30847000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.writebacks::writebacks 265550 # number of writebacks +system.cpu1.dcache.writebacks::total 265550 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170725 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 170725 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 149867 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 149867 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11052 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11052 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10024 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10024 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 320592 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 320592 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 320592 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 320592 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1826791500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1826791500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4225209000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4225209000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 70166500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 70166500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31611000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31611000 # number of StoreCondReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6729223500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 6729223500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6729223500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 6729223500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169996101000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169996101000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 17674592500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 17674592500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 187670693500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 187670693500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025015 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025015 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028607 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028607 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.105151 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.105151 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.087730 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.087730 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026491 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026491 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026491 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026491 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10738.492987 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10738.492987 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27258.525014 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27258.525014 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6746.395250 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6746.395250 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3138.046796 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3138.046796 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6052000500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 6052000500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6052000500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 6052000500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168642802500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168642802500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 17668343500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 17668343500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 186311146000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 186311146000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023992 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023992 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030117 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030117 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119082 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119082 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108091 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108091 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026513 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026513 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026513 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026513 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10700.199151 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10700.199151 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28193.057845 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28193.057845 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6348.760405 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6348.760405 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3153.531524 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3153.531524 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18068.570485 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18068.570485 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18068.570485 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18068.570485 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18877.578043 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18877.578043 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18877.578043 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18877.578043 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1284,10 +1269,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 509652310593 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 509652310593 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 509652310593 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 509652310593 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 509685021664 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 509685021664 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 509685021664 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 509685021664 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 73585121b..4975edc6e 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,61 +1,61 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.603665 # Number of seconds simulated -sim_ticks 2603664815000 # Number of ticks simulated -final_tick 2603664815000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.603674 # Number of seconds simulated +sim_ticks 2603674284000 # Number of ticks simulated +final_tick 2603674284000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 536000 # Simulator instruction rate (inst/s) -host_op_rate 682052 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 23183028791 # Simulator tick rate (ticks/s) -host_mem_usage 404656 # Number of bytes of host memory used -host_seconds 112.31 # Real time elapsed on the host -sim_insts 60197643 # Number of instructions simulated -sim_ops 76600583 # Number of ops (including micro ops) simulated +host_inst_rate 271279 # Simulator instruction rate (inst/s) +host_op_rate 345198 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 11733407598 # Simulator tick rate (ticks/s) +host_mem_usage 403640 # Number of bytes of host memory used +host_seconds 221.90 # Real time elapsed on the host +sim_insts 60197457 # Number of instructions simulated +sim_ops 76600355 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 704800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9050128 # Number of bytes read from this memory -system.physmem.bytes_read::total 132438832 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 704800 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 704800 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3677504 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 705120 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9050192 # Number of bytes read from this memory +system.physmem.bytes_read::total 132439216 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 705120 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 705120 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3677632 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6693576 # Number of bytes written to this memory +system.physmem.bytes_written::total 6693704 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 17215 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141442 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15494089 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57461 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 17220 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141443 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15494095 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57463 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811479 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47119503 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 811481 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47119332 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 123 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 74 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 270695 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3475919 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50866314 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 270695 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 270695 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1412434 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1158395 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2570829 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1412434 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47119503 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 270817 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3475931 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50866276 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 270817 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 270817 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1412478 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1158391 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2570868 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1412478 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47119332 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 123 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 74 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 270695 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4634314 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53437143 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15494089 # Total number of read requests seen -system.physmem.writeReqs 811479 # Total number of write requests seen -system.physmem.cpureqs 213984 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 991621696 # Total number of bytes read from memory -system.physmem.bytesWritten 51934656 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 132438832 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6693576 # bytesWritten derated as per pkt->getSize() +system.physmem.bw_total::cpu.inst 270817 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4634322 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53437145 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15494095 # Total number of read requests seen +system.physmem.writeReqs 811481 # Total number of write requests seen +system.physmem.cpureqs 213992 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 991622080 # Total number of bytes read from memory +system.physmem.bytesWritten 51934784 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 132439216 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6693704 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 336 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 4510 # Reqs where no action is needed system.physmem.perBankRdReqs::0 974844 # Track reads on a per bank basis @@ -66,13 +66,13 @@ system.physmem.perBankRdReqs::4 968387 # Tr system.physmem.perBankRdReqs::5 967635 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 967737 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 968249 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 968097 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 968100 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 967668 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 967710 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 968007 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 968101 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 967570 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 967431 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 967434 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 968087 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 50753 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 50356 # Track writes on a per bank basis @@ -82,61 +82,48 @@ system.physmem.perBankWrReqs::4 50784 # Tr system.physmem.perBankWrReqs::5 50139 # Track writes on a per bank basis system.physmem.perBankWrReqs::6 50212 # Track writes on a per bank basis system.physmem.perBankWrReqs::7 50710 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51141 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51142 # Track writes on a per bank basis system.physmem.perBankWrReqs::9 50687 # Track writes on a per bank basis system.physmem.perBankWrReqs::10 50724 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 51058 # Track writes on a per bank basis system.physmem.perBankWrReqs::12 51155 # Track writes on a per bank basis system.physmem.perBankWrReqs::13 50650 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 50586 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 50587 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 51214 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 2603660455000 # Total gap between requests +system.physmem.totGap 2603669924000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 6652 # Categorize read packet sizes system.physmem.readPktSize::3 15335424 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 152013 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 754018 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 57461 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 4510 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1115727 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 960917 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 976016 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3645957 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2755251 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2758222 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2725008 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 64130 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 62311 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 112850 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 163186 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 112416 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 10693 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 10526 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 10327 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 10120 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 96 # What read queue length does an incoming req see +system.physmem.readPktSize::6 152019 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 754018 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 57463 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1115862 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 960938 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 976049 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3645924 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2755202 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2757935 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2724600 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 64133 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 62351 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 112886 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 163253 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 112534 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 10838 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 10625 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 10371 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 10165 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 93 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -152,15 +139,14 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 35112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 35261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 35264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 35271 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 35275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 35275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 35279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 35281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 35038 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 35268 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 35271 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 35273 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 35278 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 35278 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 35280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 35280 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 35282 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 35282 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 35282 # What write queue length does an incoming req see @@ -169,44 +155,43 @@ system.physmem.wrQLenPdf::12 35282 # Wh system.physmem.wrQLenPdf::13 35282 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 35282 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 35282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35282 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 35281 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 35281 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 35281 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 35281 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 35281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 341507754589 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 436421735839 # Sum of mem lat for all requests -system.physmem.totBusLat 77468765000 # Total cycles spent in databus access -system.physmem.totBankLat 17445216250 # Total cycles spent in bank access -system.physmem.avgQLat 22041.64 # Average queueing delay per request -system.physmem.avgBankLat 1125.95 # Average bank access latency per request +system.physmem.totQLat 341488215750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 436408620750 # Sum of mem lat for all requests +system.physmem.totBusLat 77468795000 # Total cycles spent in databus access +system.physmem.totBankLat 17451610000 # Total cycles spent in bank access +system.physmem.avgQLat 22040.37 # Average queueing delay per request +system.physmem.avgBankLat 1126.36 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28167.59 # Average memory access latency -system.physmem.avgRdBW 380.86 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 28166.74 # Average memory access latency +system.physmem.avgRdBW 380.85 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 19.95 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 50.87 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 2.57 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.13 # Data bus utilization in percentage system.physmem.avgRdQLen 0.17 # Average read queue length over time -system.physmem.avgWrQLen 12.39 # Average write queue length over time -system.physmem.readRowHits 15418905 # Number of row buffer hits during reads -system.physmem.writeRowHits 794060 # Number of row buffer hits during writes +system.physmem.avgWrQLen 12.40 # Average write queue length over time +system.physmem.readRowHits 15418728 # Number of row buffer hits during reads +system.physmem.writeRowHits 794030 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads system.physmem.writeRowHitRate 97.85 # Row buffer hit rate for writes -system.physmem.avgGap 159679.22 # Average gap between requests +system.physmem.avgGap 159679.73 # Average gap between requests system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -227,9 +212,9 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 14995667 # DTB read hits +system.cpu.dtb.read_hits 14995645 # DTB read hits system.cpu.dtb.read_misses 7332 # DTB read misses -system.cpu.dtb.write_hits 11230865 # DTB write hits +system.cpu.dtb.write_hits 11230857 # DTB write hits system.cpu.dtb.write_misses 2203 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -240,13 +225,13 @@ system.cpu.dtb.align_faults 0 # Nu system.cpu.dtb.prefetch_faults 184 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 15002999 # DTB read accesses -system.cpu.dtb.write_accesses 11233068 # DTB write accesses +system.cpu.dtb.read_accesses 15002977 # DTB read accesses +system.cpu.dtb.write_accesses 11233060 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 26226532 # DTB hits +system.cpu.dtb.hits 26226502 # DTB hits system.cpu.dtb.misses 9535 # DTB misses -system.cpu.dtb.accesses 26236067 # DTB accesses -system.cpu.itb.inst_hits 61491584 # ITB inst hits +system.cpu.dtb.accesses 26236037 # DTB accesses +system.cpu.itb.inst_hits 61491397 # ITB inst hits system.cpu.itb.inst_misses 4471 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -263,79 +248,79 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 61496055 # ITB inst accesses -system.cpu.itb.hits 61491584 # DTB hits +system.cpu.itb.inst_accesses 61495868 # ITB inst accesses +system.cpu.itb.hits 61491397 # DTB hits system.cpu.itb.misses 4471 # DTB misses -system.cpu.itb.accesses 61496055 # DTB accesses -system.cpu.numCycles 5207329630 # number of cpu cycles simulated +system.cpu.itb.accesses 61495868 # DTB accesses +system.cpu.numCycles 5207348568 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60197643 # Number of instructions committed -system.cpu.committedOps 76600583 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 68868344 # Number of integer alu accesses +system.cpu.committedInsts 60197457 # Number of instructions committed +system.cpu.committedOps 76600355 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 68868122 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses -system.cpu.num_func_calls 2139730 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7947806 # number of instructions that are conditional controls -system.cpu.num_int_insts 68868344 # number of integer instructions +system.cpu.num_func_calls 2139722 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7947784 # number of instructions that are conditional controls +system.cpu.num_int_insts 68868122 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions -system.cpu.num_int_register_reads 394756284 # number of times the integer registers were read -system.cpu.num_int_register_writes 74176271 # number of times the integer registers were written +system.cpu.num_int_register_reads 394755172 # number of times the integer registers were read +system.cpu.num_int_register_writes 74176013 # number of times the integer registers were written system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written -system.cpu.num_mem_refs 27393912 # number of memory refs -system.cpu.num_load_insts 15659685 # Number of load instructions -system.cpu.num_store_insts 11734227 # Number of store instructions -system.cpu.num_idle_cycles 4579092870.576241 # Number of idle cycles -system.cpu.num_busy_cycles 628236759.423759 # Number of busy cycles -system.cpu.not_idle_fraction 0.120645 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.879355 # Percentage of idle cycles +system.cpu.num_mem_refs 27393871 # number of memory refs +system.cpu.num_load_insts 15659652 # Number of load instructions +system.cpu.num_store_insts 11734219 # Number of store instructions +system.cpu.num_idle_cycles 4579092042.576241 # Number of idle cycles +system.cpu.num_busy_cycles 628256525.423759 # Number of busy cycles +system.cpu.not_idle_fraction 0.120648 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.879352 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 83000 # number of quiesce instructions executed -system.cpu.icache.replacements 855486 # number of replacements -system.cpu.icache.tagsinuse 510.979431 # Cycle average of tags in use -system.cpu.icache.total_refs 60635586 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 855998 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 70.836130 # Average number of references to valid blocks. +system.cpu.icache.replacements 855484 # number of replacements +system.cpu.icache.tagsinuse 510.979435 # Cycle average of tags in use +system.cpu.icache.total_refs 60635401 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 855996 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 70.836080 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 18713179000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.979431 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 510.979435 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.998007 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.998007 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 60635586 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 60635586 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 60635586 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 60635586 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 60635586 # number of overall hits -system.cpu.icache.overall_hits::total 60635586 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 855998 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 855998 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 855998 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 855998 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 855998 # number of overall misses -system.cpu.icache.overall_misses::total 855998 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11569304000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11569304000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11569304000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11569304000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11569304000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11569304000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 61491584 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 61491584 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 61491584 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 61491584 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 61491584 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 61491584 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_hits::cpu.inst 60635401 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 60635401 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 60635401 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 60635401 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 60635401 # number of overall hits +system.cpu.icache.overall_hits::total 60635401 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 855996 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 855996 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 855996 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 855996 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 855996 # number of overall misses +system.cpu.icache.overall_misses::total 855996 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11568776000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11568776000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11568776000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11568776000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11568776000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11568776000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 61491397 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 61491397 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 61491397 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 61491397 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 61491397 # 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average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -615,79 +600,79 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 627291 # number of replacements +system.cpu.dcache.replacements 627296 # number of replacements system.cpu.dcache.tagsinuse 511.912639 # Cycle average of tags in use -system.cpu.dcache.total_refs 23655046 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 627803 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 37.679090 # Average number of references to valid blocks. +system.cpu.dcache.total_refs 23655010 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 627808 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 37.678733 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 472186000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 511.912639 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999829 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999829 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13195134 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13195134 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 9973055 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 9973055 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 236278 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 236278 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 13195118 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13195118 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 9973036 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 9973036 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 236277 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 236277 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 247678 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 247678 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 23168189 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 23168189 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 23168189 # number of overall hits -system.cpu.dcache.overall_hits::total 23168189 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 368792 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 368792 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 250511 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 250511 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 11401 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 11401 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 619303 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 619303 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 619303 # number of overall misses -system.cpu.dcache.overall_misses::total 619303 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5222508000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5222508000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8035214500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8035214500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 155940000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 155940000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 13257722500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 13257722500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 13257722500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 13257722500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13563926 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13563926 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10223566 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10223566 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 23168154 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 23168154 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 23168154 # number of overall hits +system.cpu.dcache.overall_hits::total 23168154 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 368785 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 368785 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 250522 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 250522 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 11402 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 11402 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 619307 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 619307 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 619307 # number of overall misses +system.cpu.dcache.overall_misses::total 619307 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5224078000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5224078000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8042704500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8042704500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 155711000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 155711000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 13266782500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 13266782500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 13266782500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 13266782500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13563903 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13563903 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10223558 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10223558 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247679 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 247679 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 247678 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 247678 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 23787492 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 23787492 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 23787492 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 23787492 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 23787461 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 23787461 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 23787461 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 23787461 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027189 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.027189 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024503 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.024503 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046031 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046031 # miss rate for LoadLockedReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024504 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.024504 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046035 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046035 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.026035 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.026035 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.026035 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.026035 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14161.120632 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14161.120632 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 32075.296095 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 32075.296095 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13677.747566 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13677.747566 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 21407.489549 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 21407.489549 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 21407.489549 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 21407.489549 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14165.646650 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14165.646650 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 32103.785296 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 32103.785296 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13656.463778 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13656.463778 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 21421.980536 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 21421.980536 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 21421.980536 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 21421.980536 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -696,54 +681,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 596039 # number of writebacks -system.cpu.dcache.writebacks::total 596039 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368792 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 368792 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250511 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 250511 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11401 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 11401 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 619303 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 619303 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 619303 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 619303 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4484924000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4484924000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7534192500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7534192500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 133138000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 133138000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12019116500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12019116500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12019116500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12019116500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182082004500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182082004500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 18708047000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 18708047000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 200790051500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 200790051500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.writebacks::writebacks 596040 # number of writebacks +system.cpu.dcache.writebacks::total 596040 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368785 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 368785 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250522 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 250522 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11402 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 11402 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 619307 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 619307 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 619307 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 619307 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4486508000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4486508000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7541660500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7541660500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 132907000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 132907000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12028168500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12028168500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12028168500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12028168500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182082624500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182082624500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 18709226000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 18709226000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 200791850500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 200791850500 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027189 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027189 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024503 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024503 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046031 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046031 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024504 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024504 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046035 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046035 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026035 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.026035 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026035 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.026035 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12161.120632 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12161.120632 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30075.296095 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30075.296095 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11677.747566 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11677.747566 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19407.489549 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19407.489549 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19407.489549 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19407.489549 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12165.646650 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12165.646650 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30103.785296 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30103.785296 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11656.463778 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11656.463778 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19421.980536 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19421.980536 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19421.980536 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19421.980536 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -765,10 +750,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1199398748332 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1199398748332 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1199398748332 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1199398748332 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1199377224257 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1199377224257 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1199377224257 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1199377224257 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt index 9d3d17a68..8816091ac 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.332810 # Nu sim_ticks 2332810256000 # Number of ticks simulated final_tick 2332810256000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1011951 # Simulator instruction rate (inst/s) -host_op_rate 1301307 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 39078665084 # Simulator tick rate (ticks/s) -host_mem_usage 435224 # Number of bytes of host memory used -host_seconds 59.70 # Real time elapsed on the host +host_inst_rate 685945 # Simulator instruction rate (inst/s) +host_op_rate 882083 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 26489224850 # Simulator tick rate (ticks/s) +host_mem_usage 391216 # Number of bytes of host memory used +host_seconds 88.07 # Real time elapsed on the host sim_insts 60408639 # Number of instructions simulated sim_ops 77681819 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory @@ -113,26 +113,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 0 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see @@ -165,7 +152,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -198,7 +184,6 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see system.physmem.totQLat 0 # Total cycles spent in queuing delays system.physmem.totMemAccLat 0 # Sum of mem lat for all requests system.physmem.totBusLat 0 # Total cycles spent in databus access |