diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-06-29 11:19:03 -0400 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-06-29 11:19:03 -0400 |
| commit | 3965ecc36b3d928cf8f6a66e50eed3c6de1a54c0 (patch) | |
| tree | 63ce098bc690eb5b58b3297b747794d623cface4 /tests/quick/fs/10.linux-boot/ref/arm | |
| parent | af2b14a362281f36347728e13dcd6b2c4d3c4991 (diff) | |
| download | gem5-3965ecc36b3d928cf8f6a66e50eed3c6de1a54c0.tar.xz | |
Stats: Update stats for RAS and LRU fixes.
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm')
12 files changed, 1852 insertions, 1874 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini index 31269f9bd..e2b1a3bea 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini @@ -22,6 +22,7 @@ machine_type=RealView_PBX mem_mode=atomic memories=system.realview.nvmem system.physmem midr_regval=890224640 +multi_proc=true num_work_ids=16 readfile=tests/halt.sh symbolfile= diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout index be4dcf157..50982556e 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 17:25:17 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 00:36:18 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index 002831edb..c0313feaf 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.911654 # Nu sim_ticks 911653589000 # Number of ticks simulated final_tick 911653589000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1520101 # Simulator instruction rate (inst/s) -host_op_rate 1964640 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 22862175544 # Simulator tick rate (ticks/s) -host_mem_usage 382804 # Number of bytes of host memory used -host_seconds 39.88 # Real time elapsed on the host +host_inst_rate 2171864 # Simulator instruction rate (inst/s) +host_op_rate 2807005 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 32664627860 # Simulator tick rate (ticks/s) +host_mem_usage 382740 # Number of bytes of host memory used +host_seconds 27.91 # Real time elapsed on the host sim_insts 60615585 # Number of instructions simulated sim_ops 78342060 # Number of ops (including micro ops) simulated system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory @@ -30,237 +30,237 @@ system.realview.nvmem.bw_total::cpu0.inst 22 # T system.realview.nvmem.bw_total::cpu1.inst 53 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 75 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 661924 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 6760756 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 1152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 341852 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 3873968 # Number of bytes read from this memory -system.physmem.bytes_read::total 50963556 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 661924 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 341852 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1003776 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7197696 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 506468 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 6290740 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 210652 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 3309616 # Number of bytes read from this memory +system.physmem.bytes_read::total 49639524 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 506468 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 210652 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 717120 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4196032 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010088 # Number of bytes written to this memory -system.physmem.bytes_written::total 10224784 # Number of bytes written to this memory +system.physmem.bytes_written::total 7223120 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 4915200 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 12 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 8 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 16561 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 105709 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 16 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 18 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 5423 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 60557 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5103504 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 112464 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 14132 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 98365 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 3373 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 51739 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5082816 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 65563 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752522 # Number of write requests responded to by this memory -system.physmem.num_writes::total 869236 # Number of write requests responded to by this memory +system.physmem.num_writes::total 822335 # Number of write requests responded to by this memory system.physmem.bw_read::realview.clcd 43132173 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 842 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 562 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 726070 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 7415926 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 1123 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 1264 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 374980 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4249386 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 55902326 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 726070 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 374980 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1101050 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 7895209 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 70 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 140 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 555549 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 6900362 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 211 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 70 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 231066 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 3630344 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 54449985 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 555549 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 231066 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 786615 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4602661 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 18647 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 3301789 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 11215646 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 7895209 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 7923097 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4602661 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.clcd 43132173 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 842 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 562 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 726070 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 7434574 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 1123 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 1264 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 374980 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 7551175 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 67117972 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 127935 # number of replacements -system.l2c.tagsinuse 26245.835103 # Cycle average of tags in use -system.l2c.total_refs 1477463 # Total number of references to valid blocks. -system.l2c.sampled_refs 156884 # Sample count of references to valid blocks. -system.l2c.avg_refs 9.417551 # Average number of references to valid blocks. +system.physmem.bw_total::cpu0.dtb.walker 70 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 140 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 555549 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 6919010 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 211 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 70 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 231066 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 6932133 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 62373082 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 70681 # number of replacements +system.l2c.tagsinuse 51554.827924 # Cycle average of tags in use +system.l2c.total_refs 1661073 # Total number of references to valid blocks. +system.l2c.sampled_refs 135855 # Sample count of references to valid blocks. +system.l2c.avg_refs 12.226808 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 16687.001530 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 1.397314 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.122168 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 2780.380300 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 1123.317941 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 4.426009 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.itb.walker 0.092136 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 1942.464102 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 3706.633603 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.254623 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000021 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.042425 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.017140 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000068 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.itb.walker 0.000001 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.029640 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.056559 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.400480 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 5294 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 2199 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 485527 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 213776 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 4291 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1552 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 359854 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 128180 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1200673 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 578200 # number of Writeback hits -system.l2c.Writeback_hits::total 578200 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 835 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 757 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1592 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 134 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 214 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 348 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 68011 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 33233 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 101244 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 5294 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 2199 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 485527 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 281787 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 4291 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 1552 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 359854 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 161413 # number of demand (read+write) hits -system.l2c.demand_hits::total 1301917 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 5294 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 2199 # number of overall hits -system.l2c.overall_hits::cpu0.inst 485527 # number of overall hits -system.l2c.overall_hits::cpu0.data 281787 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 4291 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 1552 # number of overall hits -system.l2c.overall_hits::cpu1.inst 359854 # number of overall hits -system.l2c.overall_hits::cpu1.data 161413 # number of overall hits -system.l2c.overall_hits::total 1301917 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 12 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 8 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 9928 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 9109 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 16 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 18 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 5336 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 10106 # number of ReadReq misses -system.l2c.ReadReq_misses::total 34533 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 6262 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 3142 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 9404 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 731 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 408 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1139 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 98092 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 50861 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 148953 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 12 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 8 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 9928 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 107201 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 16 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 18 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 5336 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 60967 # number of demand (read+write) misses -system.l2c.demand_misses::total 183486 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 12 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 8 # number of overall misses -system.l2c.overall_misses::cpu0.inst 9928 # number of overall misses -system.l2c.overall_misses::cpu0.data 107201 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 16 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 18 # number of overall misses -system.l2c.overall_misses::cpu1.inst 5336 # number of overall misses -system.l2c.overall_misses::cpu1.data 60967 # number of overall misses -system.l2c.overall_misses::total 183486 # number of overall misses -system.l2c.ReadReq_accesses::cpu0.dtb.walker 5306 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 2207 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 495455 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 222885 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 4307 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 1570 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 365190 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 138286 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1235206 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 578200 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 578200 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 7097 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 3899 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 10996 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 865 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 622 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1487 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 166103 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 84094 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 250197 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 5306 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 2207 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 495455 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 388988 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 4307 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 1570 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 365190 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 222380 # 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number of demand (read+write) misses +system.l2c.demand_misses::total 163339 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses +system.l2c.overall_misses::cpu0.inst 7499 # number of overall misses +system.l2c.overall_misses::cpu0.data 100252 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 3 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses +system.l2c.overall_misses::cpu1.inst 3286 # number of overall misses +system.l2c.overall_misses::cpu1.data 52295 # number of overall misses +system.l2c.overall_misses::total 163339 # number of overall misses +system.l2c.ReadReq_accesses::cpu0.dtb.walker 5303 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 2204 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 495240 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 217934 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 4300 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 1569 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 365119 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 135511 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1227180 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 613260 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 613260 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 7090 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 3758 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 10848 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 857 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 537 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1394 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 165376 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 83237 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 248613 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 5303 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 2204 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 495240 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 383310 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 4300 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 1569 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 365119 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 218748 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1475793 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 5303 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 2204 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 495240 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 383310 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 4300 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 1569 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 365119 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 218748 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1475793 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000189 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000907 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.015142 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.029284 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000698 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000637 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.009000 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.038846 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.018284 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.883357 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.800426 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.854628 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.856476 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.901304 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.873745 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.567616 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.565025 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.566748 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000189 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000907 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.015142 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.261543 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000698 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.000637 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.009000 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.239065 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.110679 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000189 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000907 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.015142 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.261543 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000698 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.000637 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.009000 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.239065 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.110679 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -269,8 +269,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 112464 # number of writebacks -system.l2c.writebacks::total 112464 # number of writebacks +system.l2c.writebacks::writebacks 65563 # number of writebacks +system.l2c.writebacks::total 65563 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -327,7 +327,7 @@ system.cpu0.committedInsts 33900598 # Nu system.cpu0.committedOps 44786074 # Number of ops (including micro ops) committed system.cpu0.num_int_alu_accesses 39685287 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 5074 # Number of float alu accesses -system.cpu0.num_func_calls 1296918 # number of times a function call or return occured +system.cpu0.num_func_calls 1436598 # number of times a function call or return occured system.cpu0.num_conditional_control_insts 4494112 # number of instructions that are conditional controls system.cpu0.num_int_insts 39685287 # number of integer instructions system.cpu0.num_fp_insts 5074 # number of float instructions @@ -344,15 +344,15 @@ system.cpu0.not_idle_fraction 0.025030 # Pe system.cpu0.idle_fraction 0.974970 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 58955 # number of quiesce instructions executed -system.cpu0.icache.replacements 497177 # number of replacements -system.cpu0.icache.tagsinuse 511.014795 # Cycle average of tags in use +system.cpu0.icache.replacements 497178 # number of replacements +system.cpu0.icache.tagsinuse 511.019581 # Cycle average of tags in use system.cpu0.icache.total_refs 34187980 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 497689 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 68.693461 # Average number of references to valid blocks. +system.cpu0.icache.sampled_refs 497690 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 68.693323 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 64536851000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.014795 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.998076 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.998076 # Average percentage of cache occupancy +system.cpu0.icache.occ_blocks::cpu0.inst 511.019581 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.998085 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.998085 # Average percentage of cache occupancy system.cpu0.icache.ReadReq_hits::cpu0.inst 34187980 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 34187980 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 34187980 # number of demand (read+write) hits @@ -385,42 +385,42 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 26062 # number of writebacks -system.cpu0.icache.writebacks::total 26062 # number of writebacks +system.cpu0.icache.writebacks::writebacks 31457 # number of writebacks +system.cpu0.icache.writebacks::total 31457 # number of writebacks system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 385595 # number of replacements -system.cpu0.dcache.tagsinuse 475.569441 # Cycle average of tags in use -system.cpu0.dcache.total_refs 14667576 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 386107 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 37.988371 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 380425 # number of replacements +system.cpu0.dcache.tagsinuse 495.308430 # Cycle average of tags in use +system.cpu0.dcache.total_refs 14671885 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 380937 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 38.515253 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 22115000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 475.569441 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.928847 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.928847 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 7775792 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7775792 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 6519223 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 6519223 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 172927 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 172927 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 175483 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 175483 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 14295015 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 14295015 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 14295015 # number of overall hits -system.cpu0.dcache.overall_hits::total 14295015 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 240570 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 240570 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 186007 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 186007 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9987 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 9987 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7377 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7377 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 426577 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 426577 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 426577 # number of overall misses -system.cpu0.dcache.overall_misses::total 426577 # number of overall misses +system.cpu0.dcache.occ_blocks::cpu0.data 495.308430 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.967399 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.967399 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 7779192 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7779192 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 6519856 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 6519856 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 173153 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 173153 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 175464 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 175464 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 14299048 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 14299048 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 14299048 # number of overall hits +system.cpu0.dcache.overall_hits::total 14299048 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 237170 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 237170 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 185374 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 185374 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9761 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 9761 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7396 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7396 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 422544 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 422544 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 422544 # number of overall misses +system.cpu0.dcache.overall_misses::total 422544 # number of overall misses system.cpu0.dcache.ReadReq_accesses::cpu0.data 8016362 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 8016362 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 6705230 # number of WriteReq accesses(hits+misses) @@ -433,18 +433,18 @@ system.cpu0.dcache.demand_accesses::cpu0.data 14721592 system.cpu0.dcache.demand_accesses::total 14721592 # number of demand (read+write) accesses system.cpu0.dcache.overall_accesses::cpu0.data 14721592 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 14721592 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.030010 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.030010 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027741 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.027741 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054599 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054599 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.040342 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.040342 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.028976 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.028976 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.028976 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.028976 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029586 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.029586 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027646 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.027646 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.053364 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.053364 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.040446 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.040446 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.028702 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.028702 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.028702 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.028702 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -453,8 +453,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 342703 # number of writebacks -system.cpu0.dcache.writebacks::total 342703 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 353901 # number of writebacks +system.cpu0.dcache.writebacks::total 353901 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses @@ -505,7 +505,7 @@ system.cpu1.committedInsts 26714987 # Nu system.cpu1.committedOps 33555986 # Number of ops (including micro ops) committed system.cpu1.num_int_alu_accesses 30087808 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 5643 # Number of float alu accesses -system.cpu1.num_func_calls 723750 # number of times a function call or return occured +system.cpu1.num_func_calls 761024 # number of times a function call or return occured system.cpu1.num_conditional_control_insts 3301562 # number of instructions that are conditional controls system.cpu1.num_int_insts 30087808 # number of integer instructions system.cpu1.num_fp_insts 5643 # number of float instructions @@ -563,42 +563,42 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 12806 # number of writebacks -system.cpu1.icache.writebacks::total 12806 # number of writebacks +system.cpu1.icache.writebacks::writebacks 15197 # number of writebacks +system.cpu1.icache.writebacks::total 15197 # number of writebacks system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 240038 # number of replacements -system.cpu1.dcache.tagsinuse 389.638585 # Cycle average of tags in use -system.cpu1.dcache.total_refs 9512122 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 240396 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 39.568554 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 69263687500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 389.638585 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.761013 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.761013 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 5740038 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 5740038 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 3634687 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 3634687 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 56514 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 56514 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 57060 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 57060 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 9374725 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 9374725 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 9374725 # number of overall hits -system.cpu1.dcache.overall_hits::total 9374725 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 161066 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 161066 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 108913 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 108913 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 10616 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 10616 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10014 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10014 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 269979 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 269979 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 269979 # number of overall misses -system.cpu1.dcache.overall_misses::total 269979 # number of overall misses +system.cpu1.dcache.replacements 236700 # number of replacements +system.cpu1.dcache.tagsinuse 447.071707 # Cycle average of tags in use +system.cpu1.dcache.total_refs 9515102 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 237061 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 40.137779 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 67292773000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 447.071707 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.873187 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.873187 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 5742078 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 5742078 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 3635346 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 3635346 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 56591 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 56591 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 56639 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 56639 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 9377424 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 9377424 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 9377424 # number of overall hits +system.cpu1.dcache.overall_hits::total 9377424 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 159026 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 159026 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 108254 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 108254 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 10539 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 10539 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10435 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10435 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 267280 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 267280 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 267280 # number of overall misses +system.cpu1.dcache.overall_misses::total 267280 # number of overall misses system.cpu1.dcache.ReadReq_accesses::cpu1.data 5901104 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_accesses::total 5901104 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::cpu1.data 3743600 # number of WriteReq accesses(hits+misses) @@ -611,18 +611,18 @@ system.cpu1.dcache.demand_accesses::cpu1.data 9644704 system.cpu1.dcache.demand_accesses::total 9644704 # number of demand (read+write) accesses system.cpu1.dcache.overall_accesses::cpu1.data 9644704 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 9644704 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.027294 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.027294 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.029093 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.029093 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.158141 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.158141 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.149298 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.149298 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027992 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.027992 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.027992 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.027992 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.026949 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.026949 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.028917 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.028917 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.156994 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.156994 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.155574 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.155574 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027713 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.027713 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.027713 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.027713 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -631,8 +631,8 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 196629 # number of writebacks -system.cpu1.dcache.writebacks::total 196629 # number of writebacks +system.cpu1.dcache.writebacks::writebacks 212705 # number of writebacks +system.cpu1.dcache.writebacks::total 212705 # number of writebacks system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini index 99dc32f6e..f14835c6b 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini @@ -22,6 +22,7 @@ machine_type=RealView_PBX mem_mode=atomic memories=system.physmem system.realview.nvmem midr_regval=890224640 +multi_proc=true num_work_ids=16 readfile=tests/halt.sh symbolfile= diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout index f08c091ef..4dbfc774f 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 17:24:24 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 00:35:36 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index 154c8ff44..176436ee7 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -4,51 +4,51 @@ sim_seconds 2.332330 # Nu sim_ticks 2332330037000 # Number of ticks simulated final_tick 2332330037000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1412842 # Simulator instruction rate (inst/s) -host_op_rate 1823742 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 55482154888 # Simulator tick rate (ticks/s) -host_mem_usage 382804 # Number of bytes of host memory used -host_seconds 42.04 # Real time elapsed on the host +host_inst_rate 1988795 # Simulator instruction rate (inst/s) +host_op_rate 2567201 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 78099767101 # Simulator tick rate (ticks/s) +host_mem_usage 382744 # Number of bytes of host memory used +host_seconds 29.86 # Real time elapsed on the host sim_insts 59392246 # Number of instructions simulated sim_ops 76665494 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 1536 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 941920 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10043536 # Number of bytes read from this memory -system.physmem.bytes_read::total 122661296 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 941920 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 941920 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6574400 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 704992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9071568 # Number of bytes read from this memory +system.physmem.bytes_read::total 121450416 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 704992 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 704992 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3703040 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3015816 # Number of bytes written to this memory -system.physmem.bytes_written::total 9590216 # Number of bytes written to this memory +system.physmem.bytes_written::total 6718856 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 13959168 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 24 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 20920 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 156964 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14137091 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 102725 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 17218 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141777 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14118171 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57860 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 753954 # Number of write requests responded to by this memory -system.physmem.num_writes::total 856679 # Number of write requests responded to by this memory +system.physmem.num_writes::total 811814 # Number of write requests responded to by this memory system.physmem.bw_read::realview.clcd 47880592 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 659 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 412 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 403854 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 4306224 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52591740 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 403854 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 403854 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2818812 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 137 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 82 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 302269 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3889487 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52072569 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 302269 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 302269 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1587700 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 1293049 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4111861 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2818812 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2880748 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1587700 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.clcd 47880592 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 659 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 412 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 403854 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5599273 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 56703601 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 137 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 82 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 302269 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5182536 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54953317 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -61,103 +61,103 @@ system.realview.nvmem.bw_inst_read::cpu.inst 9 system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 9 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 117012 # number of replacements -system.l2c.tagsinuse 24288.656748 # Cycle average of tags in use -system.l2c.total_refs 1527554 # Total number of references to valid blocks. -system.l2c.sampled_refs 146810 # Sample count of references to valid blocks. -system.l2c.avg_refs 10.404972 # Average number of references to valid blocks. -system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 13693.996987 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 7.872000 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.itb.walker 1.975558 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 5248.163956 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 5336.648246 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.208954 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.dtb.walker 0.000120 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.itb.walker 0.000030 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.080081 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.081431 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.370615 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 7515 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 3139 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 835264 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 357385 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1203303 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 605735 # number of Writeback hits -system.l2c.Writeback_hits::total 605735 # number of Writeback hits +system.l2c.replacements 62240 # number of replacements +system.l2c.tagsinuse 50004.786190 # Cycle average of tags in use +system.l2c.total_refs 1717775 # Total number of references to valid blocks. +system.l2c.sampled_refs 127625 # Sample count of references to valid blocks. +system.l2c.avg_refs 13.459549 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2316513323500 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 36897.037256 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 2.960071 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.itb.walker 0.993930 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 7014.608709 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 6089.186223 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.563004 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.inst 0.107034 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.092914 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.763012 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 7534 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.itb.walker 3151 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.inst 838895 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 364444 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1214024 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 642748 # number of Writeback hits +system.l2c.Writeback_hits::total 642748 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 106156 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 106156 # number of ReadExReq hits -system.l2c.demand_hits::cpu.dtb.walker 7515 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.itb.walker 3139 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.inst 835264 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 463541 # number of demand (read+write) hits -system.l2c.demand_hits::total 1309459 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.dtb.walker 7515 # number of overall hits -system.l2c.overall_hits::cpu.itb.walker 3139 # number of overall hits -system.l2c.overall_hits::cpu.inst 835264 # number of overall hits -system.l2c.overall_hits::cpu.data 463541 # number of overall hits -system.l2c.overall_hits::total 1309459 # number of overall hits -system.l2c.ReadReq_misses::cpu.dtb.walker 24 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.itb.walker 15 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.inst 14304 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 17465 # number of ReadReq misses -system.l2c.ReadReq_misses::total 31808 # number of ReadReq misses +system.l2c.ReadExReq_hits::cpu.data 113737 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 113737 # number of ReadExReq hits +system.l2c.demand_hits::cpu.dtb.walker 7534 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.itb.walker 3151 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.inst 838895 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 478181 # number of demand (read+write) hits +system.l2c.demand_hits::total 1327761 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.dtb.walker 7534 # number of overall hits +system.l2c.overall_hits::cpu.itb.walker 3151 # number of overall hits +system.l2c.overall_hits::cpu.inst 838895 # number of overall hits +system.l2c.overall_hits::cpu.data 478181 # number of overall hits +system.l2c.overall_hits::total 1327761 # number of overall hits +system.l2c.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.inst 10602 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 9870 # number of ReadReq misses +system.l2c.ReadReq_misses::total 20480 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu.data 2918 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 2918 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 141050 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 141050 # number of ReadExReq misses -system.l2c.demand_misses::cpu.dtb.walker 24 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.itb.walker 15 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.inst 14304 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 158515 # number of demand (read+write) misses -system.l2c.demand_misses::total 172858 # number of demand (read+write) misses -system.l2c.overall_misses::cpu.dtb.walker 24 # number of overall misses -system.l2c.overall_misses::cpu.itb.walker 15 # number of overall misses -system.l2c.overall_misses::cpu.inst 14304 # number of overall misses -system.l2c.overall_misses::cpu.data 158515 # number of overall misses -system.l2c.overall_misses::total 172858 # number of overall misses +system.l2c.ReadExReq_misses::cpu.data 133469 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 133469 # number of ReadExReq misses +system.l2c.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.inst 10602 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 143339 # number of demand (read+write) misses +system.l2c.demand_misses::total 153949 # number of demand (read+write) misses +system.l2c.overall_misses::cpu.dtb.walker 5 # number of overall misses +system.l2c.overall_misses::cpu.itb.walker 3 # number of overall misses +system.l2c.overall_misses::cpu.inst 10602 # number of overall misses +system.l2c.overall_misses::cpu.data 143339 # number of overall misses +system.l2c.overall_misses::total 153949 # number of overall misses system.l2c.ReadReq_accesses::cpu.dtb.walker 7539 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu.itb.walker 3154 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.inst 849568 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 374850 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1235111 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 605735 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 605735 # number of Writeback accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.inst 849497 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 374314 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1234504 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 642748 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 642748 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu.data 2944 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 2944 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu.data 247206 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 247206 # number of ReadExReq accesses(hits+misses) system.l2c.demand_accesses::cpu.dtb.walker 7539 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu.itb.walker 3154 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.inst 849568 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 622056 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1482317 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.inst 849497 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 621520 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1481710 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu.dtb.walker 7539 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu.itb.walker 3154 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.inst 849568 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 622056 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1482317 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.003183 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.004756 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.016837 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.046592 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.025753 # miss rate for ReadReq accesses +system.l2c.overall_accesses::cpu.inst 849497 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.data 621520 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1481710 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000663 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000951 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.inst 0.012480 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.026368 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.016590 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu.data 0.991168 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 0.991168 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.570577 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.570577 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.dtb.walker 0.003183 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.itb.walker 0.004756 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.inst 0.016837 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.254824 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.116613 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.dtb.walker 0.003183 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.itb.walker 0.004756 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.inst 0.016837 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.254824 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.116613 # miss rate for overall accesses +system.l2c.ReadExReq_miss_rate::cpu.data 0.539910 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.539910 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu.dtb.walker 0.000663 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.itb.walker 0.000951 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.inst 0.012480 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.230627 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.103900 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.dtb.walker 0.000663 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.itb.walker 0.000951 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.inst 0.012480 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.230627 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.103900 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -166,8 +166,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 102725 # number of writebacks -system.l2c.writebacks::total 102725 # number of writebacks +system.l2c.writebacks::writebacks 57860 # number of writebacks +system.l2c.writebacks::total 57860 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -224,7 +224,7 @@ system.cpu.committedInsts 59392246 # Nu system.cpu.committedOps 76665494 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 68281415 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses -system.cpu.num_func_calls 1972385 # number of times a function call or return occured +system.cpu.num_func_calls 2136013 # number of times a function call or return occured system.cpu.num_conditional_control_insts 7647793 # number of instructions that are conditional controls system.cpu.num_int_insts 68281415 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions @@ -282,8 +282,8 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 44595 # number of writebacks -system.cpu.icache.writebacks::total 44595 # number of writebacks +system.cpu.icache.writebacks::writebacks 50093 # number of writebacks +system.cpu.icache.writebacks::total 50093 # number of writebacks system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 623347 # number of replacements system.cpu.dcache.tagsinuse 511.997030 # Cycle average of tags in use @@ -346,8 +346,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 561140 # number of writebacks -system.cpu.dcache.writebacks::total 561140 # number of writebacks +system.cpu.dcache.writebacks::writebacks 592655 # number of writebacks +system.cpu.dcache.writebacks::total 592655 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini index 08257cec9..f78b6a8fb 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini @@ -22,6 +22,7 @@ machine_type=RealView_PBX mem_mode=timing memories=system.realview.nvmem system.physmem midr_regval=890224640 +multi_proc=true num_work_ids=16 readfile=tests/halt.sh symbolfile= diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout index dc9f6d387..ccc6b6e90 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 17:26:08 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 00:37:10 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1169707043000 because m5_exit instruction encountered +Exiting @ tick 1169301297000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index c1f17df29..a92b3a054 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.169707 # Number of seconds simulated -sim_ticks 1169707043000 # Number of ticks simulated -final_tick 1169707043000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.169301 # Number of seconds simulated +sim_ticks 1169301297000 # Number of ticks simulated +final_tick 1169301297000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 657704 # Simulator instruction rate (inst/s) -host_op_rate 841119 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 12730829062 # Simulator tick rate (ticks/s) -host_mem_usage 382856 # Number of bytes of host memory used -host_seconds 91.88 # Real time elapsed on the host -sim_insts 60429704 # Number of instructions simulated -sim_ops 77281862 # Number of ops (including micro ops) simulated +host_inst_rate 971844 # Simulator instruction rate (inst/s) +host_op_rate 1242825 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 18805861990 # Simulator tick rate (ticks/s) +host_mem_usage 384788 # Number of bytes of host memory used +host_seconds 62.18 # Real time elapsed on the host +sim_insts 60426768 # Number of instructions simulated +sim_ops 77275723 # Number of ops (including micro ops) simulated system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -30,309 +30,291 @@ system.realview.nvmem.bw_total::cpu0.inst 17 # T system.realview.nvmem.bw_total::cpu1.inst 41 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 58 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 50331648 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 534756 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5211316 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 470236 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5348464 # Number of bytes read from this memory -system.physmem.bytes_read::total 61898788 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 534756 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 470236 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1004992 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7051584 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 394404 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4694964 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 322780 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4800816 # Number of bytes read from this memory +system.physmem.bytes_read::total 60545060 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 394404 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 322780 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 717184 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4092224 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 10078928 # Number of bytes written to this memory +system.physmem.bytes_written::total 7119568 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6291456 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 10 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 14574 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 81499 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 18 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 7429 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 83596 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6478591 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 110181 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 12381 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 73431 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 5125 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 75039 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6457439 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 63941 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 867017 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43029277 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 547 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 219 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 457171 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 4455232 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 985 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 274 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 402012 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4572482 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52918197 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 457171 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 402012 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 859183 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 6028504 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 14534 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2573588 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 8616626 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 6028504 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43029277 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 547 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 219 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 457171 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 4469765 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 985 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 274 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 402012 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 7146070 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 61534823 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 125934 # number of replacements -system.l2c.tagsinuse 27532.100282 # Cycle average of tags in use -system.l2c.total_refs 1500548 # Total number of references to valid blocks. -system.l2c.sampled_refs 155551 # Sample count of references to valid blocks. -system.l2c.avg_refs 9.646663 # Average number of references to valid blocks. +system.physmem.num_writes::total 820777 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43044208 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 55 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 109 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 337299 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 4015188 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 219 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 276045 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4105713 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51778836 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 337299 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 276045 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 613344 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3499717 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 14539 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2574481 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6088737 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3499717 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43044208 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 55 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 109 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 337299 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 4029726 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 219 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 276045 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 6680194 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 57867573 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 69045 # number of replacements +system.l2c.tagsinuse 52660.415221 # Cycle average of tags in use +system.l2c.total_refs 1684870 # Total number of references to valid blocks. +system.l2c.sampled_refs 134185 # Sample count of references to valid blocks. +system.l2c.avg_refs 12.556321 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 17789.012398 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 1.363432 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.117594 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 2294.743571 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 2778.537805 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 5.252408 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.itb.walker 0.023319 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 2406.434925 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 2256.614830 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.271439 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000021 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.035015 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.042397 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000080 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.036719 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.034433 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.420107 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 4097 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 1763 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 399350 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 205866 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 5680 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1949 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 446193 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 140780 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1205678 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 577354 # number of Writeback hits -system.l2c.Writeback_hits::total 577354 # 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average ReadExReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40135.003479 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40027.198780 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40750 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40262.207225 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40169.925640 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40131.482146 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40029.329908 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40048.630520 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40037.701540 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40017.699115 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40091.295117 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40051.158301 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40032.856544 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40114.530881 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40075.350086 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40151.618184 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40050.655795 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40222.222222 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40272.541542 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40120.061509 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40096.193198 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40135.003479 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40032.260655 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40750 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40262.207225 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40117.173336 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40083.092535 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40151.618184 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40050.655795 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40222.222222 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40272.541542 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40120.061509 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40096.193198 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40135.003479 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40032.260655 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40750 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40262.207225 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40117.173336 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40083.092535 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -528,26 +498,26 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7070142 # DTB read hits -system.cpu0.dtb.read_misses 3739 # DTB read misses -system.cpu0.dtb.write_hits 5655287 # DTB write hits -system.cpu0.dtb.write_misses 802 # DTB write misses +system.cpu0.dtb.read_hits 7070010 # DTB read hits +system.cpu0.dtb.read_misses 3742 # DTB read misses +system.cpu0.dtb.write_hits 5655317 # DTB write hits +system.cpu0.dtb.write_misses 808 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1791 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 1790 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 143 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 141 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7073881 # DTB read accesses -system.cpu0.dtb.write_accesses 5656089 # DTB write accesses +system.cpu0.dtb.read_accesses 7073752 # DTB read accesses +system.cpu0.dtb.write_accesses 5656125 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12725429 # DTB hits -system.cpu0.dtb.misses 4541 # DTB misses -system.cpu0.dtb.accesses 12729970 # DTB accesses -system.cpu0.itb.inst_hits 29439632 # ITB inst hits +system.cpu0.dtb.hits 12725327 # DTB hits +system.cpu0.dtb.misses 4550 # DTB misses +system.cpu0.dtb.accesses 12729877 # DTB accesses +system.cpu0.itb.inst_hits 29439174 # ITB inst hits system.cpu0.itb.inst_misses 2205 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -564,79 +534,79 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 29441837 # ITB inst accesses -system.cpu0.itb.hits 29439632 # DTB hits +system.cpu0.itb.inst_accesses 29441379 # ITB inst accesses +system.cpu0.itb.hits 29439174 # DTB hits system.cpu0.itb.misses 2205 # DTB misses -system.cpu0.itb.accesses 29441837 # DTB accesses -system.cpu0.numCycles 2339414086 # number of cpu cycles simulated +system.cpu0.itb.accesses 29441379 # DTB accesses +system.cpu0.numCycles 2338602594 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 28747266 # Number of instructions committed -system.cpu0.committedOps 37085213 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 33031535 # Number of integer alu accesses +system.cpu0.committedInsts 28746820 # Number of instructions committed +system.cpu0.committedOps 37084824 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 33031249 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses -system.cpu0.num_func_calls 1116936 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4321526 # number of instructions that are conditional controls -system.cpu0.num_int_insts 33031535 # number of integer instructions +system.cpu0.num_func_calls 1241704 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4321371 # number of instructions that are conditional controls +system.cpu0.num_int_insts 33031249 # number of integer instructions system.cpu0.num_fp_insts 3860 # number of float instructions -system.cpu0.num_int_register_reads 189616194 # number of times the integer registers were read -system.cpu0.num_int_register_writes 36089294 # number of times the integer registers were written +system.cpu0.num_int_register_reads 189614137 # number of times the integer registers were read +system.cpu0.num_int_register_writes 36088732 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written -system.cpu0.num_mem_refs 13393398 # number of memory refs -system.cpu0.num_load_insts 7407664 # Number of load instructions -system.cpu0.num_store_insts 5985734 # Number of store instructions -system.cpu0.num_idle_cycles 2203122575.338117 # Number of idle cycles -system.cpu0.num_busy_cycles 136291510.661883 # Number of busy cycles -system.cpu0.not_idle_fraction 0.058259 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.941741 # Percentage of idle cycles +system.cpu0.num_mem_refs 13393278 # number of memory refs +system.cpu0.num_load_insts 7407523 # Number of load instructions +system.cpu0.num_store_insts 5985755 # Number of store instructions +system.cpu0.num_idle_cycles 2203295398.340116 # Number of idle cycles +system.cpu0.num_busy_cycles 135307195.659884 # Number of busy cycles +system.cpu0.not_idle_fraction 0.057858 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.942142 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 46688 # number of quiesce instructions executed -system.cpu0.icache.replacements 408172 # number of replacements -system.cpu0.icache.tagsinuse 509.512645 # Cycle average of tags in use -system.cpu0.icache.total_refs 29030930 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 408684 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 71.035152 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 74928815000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 509.512645 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.995142 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.995142 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 29030930 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 29030930 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 29030930 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 29030930 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 29030930 # number of overall hits -system.cpu0.icache.overall_hits::total 29030930 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 408685 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 408685 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 408685 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 408685 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 408685 # number of overall misses -system.cpu0.icache.overall_misses::total 408685 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6059464500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6059464500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 6059464500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6059464500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 6059464500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6059464500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 29439615 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 29439615 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 29439615 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 29439615 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 29439615 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 29439615 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013882 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.013882 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013882 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.013882 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013882 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.013882 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14826.735750 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14826.735750 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14826.735750 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14826.735750 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14826.735750 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14826.735750 # average overall miss latency +system.cpu0.kern.inst.quiesce 46685 # number of quiesce instructions executed +system.cpu0.icache.replacements 408143 # number of replacements +system.cpu0.icache.tagsinuse 509.526052 # Cycle average of tags in use +system.cpu0.icache.total_refs 29030502 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 408655 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 71.039145 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 74905211000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 509.526052 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.995168 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.995168 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 29030502 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 29030502 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 29030502 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 29030502 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 29030502 # number of overall hits +system.cpu0.icache.overall_hits::total 29030502 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 408655 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 408655 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 408655 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 408655 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 408655 # number of overall misses +system.cpu0.icache.overall_misses::total 408655 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5965025000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5965025000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5965025000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5965025000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5965025000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5965025000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 29439157 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 29439157 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 29439157 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 29439157 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 29439157 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 29439157 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013881 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.013881 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013881 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.013881 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013881 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.013881 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14596.725845 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14596.725845 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14596.725845 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14596.725845 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14596.725845 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14596.725845 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -645,122 +615,122 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # 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number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4832163500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4832163500 # number of overall MSHR miss cycles +system.cpu0.icache.writebacks::writebacks 20759 # number of writebacks +system.cpu0.icache.writebacks::total 20759 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 408655 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 408655 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 408655 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 408655 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 408655 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 408655 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4737808500 # 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average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11823.686947 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013881 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013881 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013881 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.013881 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013881 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.013881 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11593.663359 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11593.663359 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11593.663359 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11593.663359 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11593.663359 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11593.663359 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 335831 # number of replacements -system.cpu0.dcache.tagsinuse 404.122879 # Cycle average of tags in use -system.cpu0.dcache.total_refs 12265513 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 336343 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 36.467276 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 330129 # number of replacements +system.cpu0.dcache.tagsinuse 459.697251 # Cycle average of tags in use +system.cpu0.dcache.total_refs 12270461 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 330641 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 37.111130 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 663204000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 404.122879 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.789302 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.789302 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6596660 # 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miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.030342 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.030342 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15320.382890 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15320.382890 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35592.072418 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 35592.072418 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11039.558127 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11039.558127 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9145.766345 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9145.766345 # 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number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7489 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7489 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 368966 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 368966 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 368966 # number of overall misses +system.cpu0.dcache.overall_misses::total 368966 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3341792500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 3341792500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4877331500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 4877331500 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 98417500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 98417500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 68140000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 68140000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 8219124000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 8219124000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 8219124000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 8219124000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6827715 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6827715 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5491890 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5491890 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157225 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 157225 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157166 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 157166 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12319605 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12319605 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12319605 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12319605 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033316 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.033316 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025765 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.025765 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059164 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059164 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047650 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047650 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029949 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.029949 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029949 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.029949 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14691.135095 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14691.135095 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34469.748261 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 34469.748261 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10580.251559 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10580.251559 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9098.678061 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9098.678061 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 22276.101321 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 22276.101321 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 22276.101321 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 22276.101321 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -769,62 +739,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 287163 # number of writebacks -system.cpu0.dcache.writebacks::total 287163 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 231189 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 231189 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 142616 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 142616 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9505 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9505 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7461 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7461 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 373805 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 373805 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 373805 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 373805 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2848236000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2848236000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4648049500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4648049500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 76416000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 76416000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 45881000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 45881000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7496285500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 7496285500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7496285500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 7496285500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 10423748000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 10423748000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 822757000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 822757000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11246505000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11246505000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033860 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033860 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025969 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025969 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.060456 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.060456 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047474 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047474 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030342 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.030342 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030342 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.030342 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12319.946018 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12319.946018 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32591.360717 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32591.360717 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8039.558127 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8039.558127 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6149.443774 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6149.443774 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20054.000080 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20054.000080 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20054.000080 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20054.000080 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 306018 # number of writebacks +system.cpu0.dcache.writebacks::total 306018 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 227470 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 227470 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141496 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 141496 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9302 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9302 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7484 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7484 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 368966 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 368966 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 368966 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 368966 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2659287000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2659287000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4452739000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4452739000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 70511500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 70511500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 45688000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 45688000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7112026000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 7112026000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7112026000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 7112026000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 10424499500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 10424499500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 822589000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 822589000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11247088500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11247088500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033316 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033316 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025765 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025765 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059164 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059164 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047618 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047618 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029949 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029949 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029949 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.029949 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11690.715259 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11690.715259 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31469.009725 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31469.009725 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7580.251559 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7580.251559 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6104.756815 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6104.756815 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19275.559266 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19275.559266 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19275.559266 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19275.559266 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -834,26 +804,26 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 8313009 # DTB read hits -system.cpu1.dtb.read_misses 3663 # DTB read misses -system.cpu1.dtb.write_hits 5829499 # DTB write hits -system.cpu1.dtb.write_misses 1439 # DTB write misses +system.cpu1.dtb.read_hits 8311514 # DTB read hits +system.cpu1.dtb.read_misses 3660 # DTB read misses +system.cpu1.dtb.write_hits 5828200 # DTB write hits +system.cpu1.dtb.write_misses 1442 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu1.dtb.flush_entries 1967 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 136 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 134 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 8316672 # DTB read accesses -system.cpu1.dtb.write_accesses 5830938 # DTB write accesses +system.cpu1.dtb.read_accesses 8315174 # DTB read accesses +system.cpu1.dtb.write_accesses 5829642 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 14142508 # DTB hits +system.cpu1.dtb.hits 14139714 # DTB hits system.cpu1.dtb.misses 5102 # DTB misses -system.cpu1.dtb.accesses 14147610 # DTB accesses -system.cpu1.itb.inst_hits 32286240 # ITB inst hits +system.cpu1.dtb.accesses 14144816 # DTB accesses +system.cpu1.itb.inst_hits 32283727 # ITB inst hits system.cpu1.itb.inst_misses 2171 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -870,79 +840,79 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 32288411 # ITB inst accesses -system.cpu1.itb.hits 32286240 # DTB hits +system.cpu1.itb.inst_accesses 32285898 # ITB inst accesses +system.cpu1.itb.hits 32283727 # DTB hits system.cpu1.itb.misses 2171 # DTB misses -system.cpu1.itb.accesses 32288411 # DTB accesses -system.cpu1.numCycles 2338003468 # number of cpu cycles simulated +system.cpu1.itb.accesses 32285898 # DTB accesses +system.cpu1.numCycles 2337184534 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 31682438 # Number of instructions committed -system.cpu1.committedOps 40196649 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 36868206 # Number of integer alu accesses +system.cpu1.committedInsts 31679948 # Number of instructions committed +system.cpu1.committedOps 40190899 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 36862651 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses -system.cpu1.num_func_calls 909270 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3487065 # number of instructions that are conditional controls -system.cpu1.num_int_insts 36868206 # number of integer instructions +system.cpu1.num_func_calls 962114 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3486829 # number of instructions that are conditional controls +system.cpu1.num_int_insts 36862651 # number of integer instructions system.cpu1.num_fp_insts 6793 # number of float instructions -system.cpu1.num_int_register_reads 210764243 # number of times the integer registers were read -system.cpu1.num_int_register_writes 38547083 # number of times the integer registers were written +system.cpu1.num_int_register_reads 210732518 # number of times the integer registers were read +system.cpu1.num_int_register_writes 38542658 # number of times the integer registers were written system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written -system.cpu1.num_mem_refs 14680299 # number of memory refs -system.cpu1.num_load_insts 8634860 # Number of load instructions -system.cpu1.num_store_insts 6045439 # Number of store instructions -system.cpu1.num_idle_cycles 1858954745.472398 # Number of idle cycles -system.cpu1.num_busy_cycles 479048722.527602 # Number of busy cycles -system.cpu1.not_idle_fraction 0.204896 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.795104 # Percentage of idle cycles +system.cpu1.num_mem_refs 14677413 # number of memory refs +system.cpu1.num_load_insts 8633313 # Number of load instructions +system.cpu1.num_store_insts 6044100 # Number of store instructions +system.cpu1.num_idle_cycles 1859139408.190032 # Number of idle cycles +system.cpu1.num_busy_cycles 478045125.809968 # Number of busy cycles +system.cpu1.not_idle_fraction 0.204539 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.795461 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 43911 # number of quiesce instructions executed -system.cpu1.icache.replacements 454317 # number of replacements -system.cpu1.icache.tagsinuse 478.423780 # Cycle average of tags in use -system.cpu1.icache.total_refs 31831407 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 454829 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 69.985438 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 91926225000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 478.423780 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.934421 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.934421 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 31831407 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 31831407 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 31831407 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 31831407 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 31831407 # number of overall hits -system.cpu1.icache.overall_hits::total 31831407 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 454829 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 454829 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 454829 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 454829 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 454829 # number of overall misses -system.cpu1.icache.overall_misses::total 454829 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6679957000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 6679957000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 6679957000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 6679957000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 6679957000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 6679957000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 32286236 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 32286236 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 32286236 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 32286236 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 32286236 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 32286236 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014087 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.014087 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014087 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.014087 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014087 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.014087 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14686.743809 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 14686.743809 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14686.743809 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 14686.743809 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14686.743809 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 14686.743809 # average overall miss latency +system.cpu1.kern.inst.quiesce 43902 # number of quiesce instructions executed +system.cpu1.icache.replacements 454250 # number of replacements +system.cpu1.icache.tagsinuse 478.426272 # Cycle average of tags in use +system.cpu1.icache.total_refs 31828961 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 454762 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 69.990371 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 91827158000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 478.426272 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.934426 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.934426 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 31828961 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 31828961 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 31828961 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 31828961 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 31828961 # number of overall hits +system.cpu1.icache.overall_hits::total 31828961 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 454762 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 454762 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 454762 # 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average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 14467.467598 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14467.467598 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 14467.467598 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14467.467598 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 14467.467598 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -951,122 +921,122 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # 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number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5314262500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5314262500 # number of overall MSHR miss cycles +system.cpu1.icache.writebacks::writebacks 23283 # number of writebacks +system.cpu1.icache.writebacks::total 23283 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 454762 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 454762 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 454762 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 454762 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 454762 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 454762 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5213754000 # 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average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11464.796971 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11464.796971 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11464.796971 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 294642 # number of replacements -system.cpu1.dcache.tagsinuse 457.752328 # Cycle average of tags in use -system.cpu1.dcache.total_refs 11964721 # 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number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 75382000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 7413117000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 7413117000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 7413117000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 7413117000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 7117524 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 7117524 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 4977844 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 4977844 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 92876 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 92876 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92807 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 92807 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 12095368 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 12095368 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 12095368 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 12095368 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023966 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.023966 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030146 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.030146 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119094 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119094 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108149 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108149 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026509 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.026509 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026509 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.026509 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13444.591006 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13444.591006 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34118.212715 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 34118.212715 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9235.150529 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9235.150529 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7510.411478 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7510.411478 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23119.967440 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 23119.967440 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23119.967440 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 23119.967440 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1075,62 +1045,66 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 254584 # number of writebacks -system.cpu1.dcache.writebacks::total 254584 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 172105 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 172105 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 150416 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 150416 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11123 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11123 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9710 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 9710 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 322521 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 322521 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 322521 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 322521 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1979754000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1979754000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4836439500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4836439500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 91205500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 91205500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 44502000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 44502000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6816193500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 6816193500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6816193500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 6816193500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 136553272000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 136553272000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 39714562000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 39714562000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 176267834000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 176267834000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024175 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.024175 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030209 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030209 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119732 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119732 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.104604 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.104604 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026659 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026659 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026659 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026659 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11503.175387 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11503.175387 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32153.756914 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32153.756914 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8199.721298 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8199.721298 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4583.110196 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4583.110196 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 21134.107546 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 21134.107546 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21134.107546 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21134.107546 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 265856 # number of writebacks +system.cpu1.dcache.writebacks::total 265856 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170577 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 170577 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 150060 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 150060 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11061 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11061 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10033 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10033 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 320637 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 320637 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 320637 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 320637 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1781497000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1781497000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4669562000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4669562000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 68967000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 68967000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 45286000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 45286000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6451059000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 6451059000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6451059000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 6451059000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 136551200000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 136551200000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 39714194000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 39714194000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 176265394000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 176265394000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023966 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023966 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030146 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030146 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119094 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119094 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108106 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108106 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026509 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026509 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026509 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026509 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10443.946136 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10443.946136 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31117.966147 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31117.966147 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6235.150529 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6235.150529 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4513.704774 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4513.704774 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20119.508977 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20119.508977 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20119.508977 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20119.508977 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1152,10 +1126,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 550616164273 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 550616164273 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 550616164273 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 550616164273 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 550273882646 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 550273882646 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 550273882646 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 550273882646 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini index 6a942652a..d41ee2fc6 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini @@ -22,6 +22,7 @@ machine_type=RealView_PBX mem_mode=timing memories=system.physmem system.realview.nvmem midr_regval=890224640 +multi_proc=true num_work_ids=16 readfile=tests/halt.sh symbolfile= diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout index b6cf436ae..4f563f8f5 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 17:25:42 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 00:36:57 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2591419000000 because m5_exit instruction encountered +Exiting @ tick 2591087067000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 20ffbfc50..f1beadd55 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,54 +1,54 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.591419 # Number of seconds simulated -sim_ticks 2591419000000 # Number of ticks simulated -final_tick 2591419000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.591087 # Number of seconds simulated +sim_ticks 2591087067000 # Number of ticks simulated +final_tick 2591087067000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 555808 # Simulator instruction rate (inst/s) -host_op_rate 709857 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 24337050134 # Simulator tick rate (ticks/s) -host_mem_usage 383104 # Number of bytes of host memory used -host_seconds 106.48 # Real time elapsed on the host -sim_insts 59182652 # Number of instructions simulated -sim_ops 75585847 # Number of ops (including micro ops) simulated +host_inst_rate 814871 # Simulator instruction rate (inst/s) +host_op_rate 1040723 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 35675794467 # Simulator tick rate (ticks/s) +host_mem_usage 385812 # Number of bytes of host memory used +host_seconds 72.63 # Real time elapsed on the host +sim_insts 59182970 # Number of instructions simulated +sim_ops 75586355 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 1408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 955744 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9990864 # Number of bytes read from this memory -system.physmem.bytes_read::total 133632176 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 955744 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 955744 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6584000 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 706144 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9051344 # Number of bytes read from this memory +system.physmem.bytes_read::total 132441392 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 706144 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 706144 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3678592 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 9600072 # Number of bytes written to this memory +system.physmem.bytes_written::total 6694664 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 22 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 12 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 21136 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 156141 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15512735 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 102875 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 17236 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141461 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15494129 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57478 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 856893 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47342167 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 543 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 296 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 368811 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3855364 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51567182 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 368811 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 368811 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2540693 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1163869 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3704562 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2540693 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47342167 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 543 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 296 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 368811 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5019233 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 55271744 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_writes::total 811496 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47348232 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 124 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 74 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 272528 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3493261 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51114219 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 272528 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 272528 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1419710 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1164018 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2583728 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1419710 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47348232 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 124 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 74 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 272528 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4657279 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53697947 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -61,141 +61,141 @@ system.realview.nvmem.bw_inst_read::cpu.inst 8 system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 117210 # number of replacements -system.l2c.tagsinuse 24850.634634 # Cycle average of tags in use -system.l2c.total_refs 1536782 # Total number of references to valid blocks. -system.l2c.sampled_refs 146347 # Sample count of references to valid blocks. -system.l2c.avg_refs 10.500946 # Average number of references to valid blocks. -system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 14582.980264 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 6.964045 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.itb.walker 0.968003 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 5130.485110 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 5129.237211 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.222519 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.dtb.walker 0.000106 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.078285 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.078266 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.379191 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 8714 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 3541 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 839785 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 361146 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1213186 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 611793 # number of Writeback hits -system.l2c.Writeback_hits::total 611793 # number of Writeback hits +system.l2c.replacements 61946 # number of replacements +system.l2c.tagsinuse 50741.194054 # Cycle average of tags in use +system.l2c.total_refs 1730603 # Total number of references to valid blocks. +system.l2c.sampled_refs 127327 # Sample count of references to valid blocks. +system.l2c.avg_refs 13.591799 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2543210574000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 37737.574743 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 3.884961 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.itb.walker 0.001325 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 6978.831431 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 6020.901593 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.575830 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.inst 0.106489 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.091872 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.774249 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 8734 # 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average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40203.512397 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40075.855073 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40086.598680 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40175.800377 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40135.277384 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40138.070359 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -307,9 +307,9 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 14995950 # DTB read hits -system.cpu.dtb.read_misses 7342 # DTB read misses -system.cpu.dtb.write_hits 11230967 # DTB write hits +system.cpu.dtb.read_hits 14996145 # DTB read hits +system.cpu.dtb.read_misses 7343 # DTB read misses +system.cpu.dtb.write_hits 11231074 # DTB write hits system.cpu.dtb.write_misses 2209 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -320,13 +320,13 @@ system.cpu.dtb.align_faults 0 # Nu system.cpu.dtb.prefetch_faults 184 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 15003292 # DTB read accesses -system.cpu.dtb.write_accesses 11233176 # DTB write accesses +system.cpu.dtb.read_accesses 15003488 # DTB read accesses +system.cpu.dtb.write_accesses 11233283 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 26226917 # DTB hits -system.cpu.dtb.misses 9551 # DTB misses -system.cpu.dtb.accesses 26236468 # DTB accesses -system.cpu.itb.inst_hits 60464458 # ITB inst hits +system.cpu.dtb.hits 26227219 # DTB hits +system.cpu.dtb.misses 9552 # DTB misses +system.cpu.dtb.accesses 26236771 # DTB accesses +system.cpu.itb.inst_hits 60464772 # ITB inst hits system.cpu.itb.inst_misses 4471 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -343,79 +343,79 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 60468929 # ITB inst accesses -system.cpu.itb.hits 60464458 # DTB hits +system.cpu.itb.inst_accesses 60469243 # ITB inst accesses +system.cpu.itb.hits 60464772 # DTB hits system.cpu.itb.misses 4471 # DTB misses -system.cpu.itb.accesses 60468929 # DTB accesses -system.cpu.numCycles 5182838000 # number of cpu cycles simulated +system.cpu.itb.accesses 60469243 # DTB accesses +system.cpu.numCycles 5182174134 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 59182652 # Number of instructions committed -system.cpu.committedOps 75585847 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 68355333 # Number of integer alu accesses +system.cpu.committedInsts 59182970 # Number of instructions committed +system.cpu.committedOps 75586355 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 68355817 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses -system.cpu.num_func_calls 1976025 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7653656 # number of instructions that are conditional controls -system.cpu.num_int_insts 68355333 # number of integer instructions +system.cpu.num_func_calls 2139775 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7653714 # number of instructions that are conditional controls +system.cpu.num_int_insts 68355817 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions -system.cpu.num_int_register_reads 391421263 # number of times the integer registers were read -system.cpu.num_int_register_writes 73137347 # number of times the integer registers were written +system.cpu.num_int_register_reads 391424329 # number of times the integer registers were read +system.cpu.num_int_register_writes 73137723 # number of times the integer registers were written system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written -system.cpu.num_mem_refs 27394170 # number of memory refs -system.cpu.num_load_insts 15659823 # Number of load instructions -system.cpu.num_store_insts 11734347 # Number of store instructions -system.cpu.num_idle_cycles 4573988502.570235 # Number of idle cycles -system.cpu.num_busy_cycles 608849497.429765 # Number of busy cycles -system.cpu.not_idle_fraction 0.117474 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.882526 # Percentage of idle cycles +system.cpu.num_mem_refs 27394520 # number of memory refs +system.cpu.num_load_insts 15660068 # Number of load instructions +system.cpu.num_store_insts 11734452 # Number of store instructions +system.cpu.num_idle_cycles 4574883884.570234 # Number of idle cycles +system.cpu.num_busy_cycles 607290249.429766 # Number of busy cycles +system.cpu.not_idle_fraction 0.117188 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.882812 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 82997 # number of quiesce instructions executed -system.cpu.icache.replacements 855402 # number of replacements -system.cpu.icache.tagsinuse 510.943261 # Cycle average of tags in use -system.cpu.icache.total_refs 59608544 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 855914 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 69.643146 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 18524424000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.943261 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.997936 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.997936 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 59608544 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 59608544 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 59608544 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 59608544 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 59608544 # number of overall hits -system.cpu.icache.overall_hits::total 59608544 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 855914 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 855914 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 855914 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 855914 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 855914 # number of overall misses -system.cpu.icache.overall_misses::total 855914 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12584924000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12584924000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12584924000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12584924000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12584924000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12584924000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 60464458 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 60464458 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 60464458 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 60464458 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 60464458 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 60464458 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014156 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.014156 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.014156 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.014156 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.014156 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.014156 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14703.491239 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14703.491239 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14703.491239 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14703.491239 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14703.491239 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14703.491239 # average overall miss latency +system.cpu.icache.replacements 855597 # number of replacements +system.cpu.icache.tagsinuse 510.944278 # Cycle average of tags in use +system.cpu.icache.total_refs 59608663 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 856109 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 69.627422 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 18496284000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.944278 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.997938 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.997938 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 59608663 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 59608663 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 59608663 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 59608663 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 59608663 # number of overall hits +system.cpu.icache.overall_hits::total 59608663 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 856109 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 856109 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 856109 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 856109 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 856109 # number of overall misses +system.cpu.icache.overall_misses::total 856109 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12422495000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12422495000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12422495000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12422495000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12422495000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12422495000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 60464772 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 60464772 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 60464772 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 60464772 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 60464772 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 60464772 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014159 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.014159 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.014159 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.014159 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.014159 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.014159 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14510.412810 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14510.412810 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14510.412810 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14510.412810 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14510.412810 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14510.412810 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -424,114 +424,114 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 45705 # number of writebacks -system.cpu.icache.writebacks::total 45705 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855914 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 855914 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 855914 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 855914 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 855914 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 855914 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10014791000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 10014791000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10014791000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 10014791000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10014791000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 10014791000 # number of overall MSHR miss cycles +system.cpu.icache.writebacks::writebacks 50189 # number of writebacks +system.cpu.icache.writebacks::total 50189 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856109 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 856109 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 856109 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 856109 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 856109 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 856109 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9851777000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9851777000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9851777000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9851777000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9851777000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9851777000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 350913000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 350913000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 350913000 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 350913000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014156 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014156 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014156 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.014156 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014156 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.014156 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11700.697734 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11700.697734 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11700.697734 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11700.697734 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11700.697734 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11700.697734 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014159 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014159 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014159 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.014159 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014159 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.014159 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11507.619941 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11507.619941 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11507.619941 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11507.619941 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11507.619941 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11507.619941 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 627094 # number of replacements -system.cpu.dcache.tagsinuse 511.875591 # Cycle average of tags in use -system.cpu.dcache.total_refs 23655637 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 627606 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 37.691859 # Average number of references to valid blocks. +system.cpu.dcache.replacements 627131 # number of replacements +system.cpu.dcache.tagsinuse 511.875575 # Cycle average of tags in use +system.cpu.dcache.total_refs 23655898 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 627643 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 37.690053 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 660309000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.875591 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 511.875575 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999757 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999757 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13195546 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13195546 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 9973168 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 9973168 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 236327 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 236327 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247699 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247699 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 23168714 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 23168714 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 23168714 # number of overall hits -system.cpu.dcache.overall_hits::total 23168714 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 368647 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 368647 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 250483 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 250483 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 11373 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 11373 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 619130 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 619130 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 619130 # number of overall misses -system.cpu.dcache.overall_misses::total 619130 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5836151500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5836151500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9546175500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9546175500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 185299500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 185299500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 15382327000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 15382327000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 15382327000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 15382327000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13564193 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13564193 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10223651 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10223651 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247700 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 247700 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 247699 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 247699 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 23787844 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 23787844 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 23787844 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 23787844 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027178 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.027178 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024500 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.024500 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045914 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045914 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.026027 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.026027 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.026027 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.026027 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15831.273549 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15831.273549 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38111.071410 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38111.071410 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16292.930625 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16292.930625 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 24845.068079 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 24845.068079 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 24845.068079 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 24845.068079 # average overall miss latency +system.cpu.dcache.ReadReq_hits::cpu.data 13195741 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13195741 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 9973243 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 9973243 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 236320 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 236320 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247701 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247701 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 23168984 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 23168984 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 23168984 # number of overall hits +system.cpu.dcache.overall_hits::total 23168984 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 368641 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 368641 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 250513 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 250513 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 11382 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 11382 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 619154 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 619154 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 619154 # number of overall misses +system.cpu.dcache.overall_misses::total 619154 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5550266500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5550266500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9238505500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9238505500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 165952500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 165952500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 14788772000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 14788772000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 14788772000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14788772000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13564382 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13564382 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10223756 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10223756 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247702 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 247702 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247701 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247701 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 23788138 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 23788138 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 23788138 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 23788138 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027177 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.027177 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024503 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.024503 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045950 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045950 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.026028 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.026028 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.026028 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.026028 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15056.020627 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15056.020627 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36878.347631 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 36878.347631 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14580.258303 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14580.258303 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23885.450146 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23885.450146 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23885.450146 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23885.450146 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -540,54 +540,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 566088 # number of writebacks -system.cpu.dcache.writebacks::total 566088 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368647 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 368647 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250483 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 250483 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11373 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 11373 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 619130 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 619130 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 619130 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 619130 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4730079000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4730079000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8794683000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8794683000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 151180500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 151180500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13524762000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13524762000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13524762000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13524762000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 146938040000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 146938040000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 40368528500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 40368528500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 187306568500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 187306568500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027178 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027178 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024500 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024500 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.045914 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.045914 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026027 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.026027 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026027 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.026027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12830.916839 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12830.916839 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35110.897746 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35110.897746 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13292.930625 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13292.930625 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21844.785425 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 21844.785425 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21844.785425 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 21844.785425 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 595911 # number of writebacks +system.cpu.dcache.writebacks::total 595911 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368641 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 368641 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250513 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 250513 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11382 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 11382 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 619154 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 619154 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 619154 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 619154 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4444216000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4444216000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8486921500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8486921500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 131806500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 131806500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12931137500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12931137500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12931137500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12931137500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 146935431000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 146935431000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 40367480000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 40367480000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 187302911000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 187302911000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027177 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027177 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024503 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024503 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.045950 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.045950 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026028 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.026028 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026028 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.026028 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12055.674762 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12055.674762 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33878.167999 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33878.167999 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11580.258303 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11580.258303 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20885.171541 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20885.171541 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20885.171541 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20885.171541 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -609,10 +609,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1342278175263 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1342278175263 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1342278175263 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1342278175263 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1341944663355 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1341944663355 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1341944663355 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1341944663355 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency |