diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-03-23 11:12:19 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-03-23 11:12:19 -0400 |
| commit | 8b4b1dcb86b0799a8c32056427581a8b6249a3bf (patch) | |
| tree | 96016b415513dc6c2c29877e1a76220e0edae629 /tests/quick/fs/10.linux-boot/ref/arm | |
| parent | a00383a40aeb8347af7e05f3966ab141484921a5 (diff) | |
| download | gem5-8b4b1dcb86b0799a8c32056427581a8b6249a3bf.tar.xz | |
stats: Update stats for DRAM changes
This patch updates the stats to reflect the changes to the DRAM
controller.
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt | 2773 | ||||
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt | 1668 |
2 files changed, 1862 insertions, 2579 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 786f029ca..789d25c60 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.196143 # Number of seconds simulated -sim_ticks 1196142873000 # Number of ticks simulated -final_tick 1196142873000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.196225 # Number of seconds simulated +sim_ticks 1196225147500 # Number of ticks simulated +final_tick 1196225147500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 497666 # Simulator instruction rate (inst/s) -host_op_rate 634118 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9685782626 # Simulator tick rate (ticks/s) -host_mem_usage 425428 # Number of bytes of host memory used -host_seconds 123.49 # Real time elapsed on the host -sim_insts 61459155 # Number of instructions simulated -sim_ops 78310163 # Number of ops (including micro ops) simulated +host_inst_rate 669591 # Simulator instruction rate (inst/s) +host_op_rate 853186 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 13029857543 # Simulator tick rate (ticks/s) +host_mem_usage 426076 # Number of bytes of host memory used +host_seconds 91.81 # Real time elapsed on the host +sim_insts 61472758 # Number of instructions simulated +sim_ops 78327958 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory @@ -33,142 +33,138 @@ system.realview.nvmem.bw_total::cpu1.inst 40 # T system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 393356 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4724988 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 378508 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4532924 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 324292 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4798584 # Number of bytes read from this memory -system.physmem.bytes_read::total 62146244 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 393356 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 324292 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 717648 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4113152 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 337988 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4964984 # Number of bytes read from this memory +system.physmem.bytes_read::total 62119428 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 378508 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 337988 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 716496 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4092288 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7140496 # Number of bytes written to this memory +system.physmem.bytes_written::total 7119632 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 12374 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 73902 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 12142 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 70901 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 5158 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 75006 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6654512 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 64268 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.inst 5372 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 77606 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6654093 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 63942 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 821104 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43393238 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 820778 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43390253 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 54 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 107 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 328854 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3950187 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 161 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 316419 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3789357 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 214 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 54 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 271115 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4011715 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51955536 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 328854 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 271115 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 599968 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3438680 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 14212 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2516709 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 5969601 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3438680 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43393238 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 282545 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4150543 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51929545 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 316419 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 282545 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 598964 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3421001 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 14211 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2516536 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 5951749 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3421001 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43390253 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 54 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 107 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 328854 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3964399 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 161 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 316419 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3803568 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 214 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 54 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 271115 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 6528424 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 57925137 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6654512 # Number of read requests accepted -system.physmem.writeReqs 821104 # Number of write requests accepted -system.physmem.readBursts 6654512 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 821104 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 425857728 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 31040 # Total number of bytes read from write queue -system.physmem.bytesWritten 7268800 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 62146244 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7140496 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 485 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 707525 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 12040 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 415388 # Per bank write bursts -system.physmem.perBankRdBursts::1 415219 # Per bank write bursts -system.physmem.perBankRdBursts::2 415339 # Per bank write bursts -system.physmem.perBankRdBursts::3 415675 # Per bank write bursts -system.physmem.perBankRdBursts::4 422392 # Per bank write bursts +system.physmem.bw_total::cpu1.inst 282545 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 6667079 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 57881294 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 6654093 # Number of read requests accepted +system.physmem.writeReqs 820778 # Number of write requests accepted +system.physmem.readBursts 6654093 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 820778 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 425823936 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 38016 # Total number of bytes read from write queue +system.physmem.bytesWritten 7142848 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 62119428 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7119632 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 594 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 709146 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 11979 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 415258 # Per bank write bursts +system.physmem.perBankRdBursts::1 415304 # Per bank write bursts +system.physmem.perBankRdBursts::2 415298 # Per bank write bursts +system.physmem.perBankRdBursts::3 415715 # Per bank write bursts +system.physmem.perBankRdBursts::4 422332 # Per bank write bursts system.physmem.perBankRdBursts::5 415542 # Per bank write bursts -system.physmem.perBankRdBursts::6 415783 # Per bank write bursts -system.physmem.perBankRdBursts::7 415483 # Per bank write bursts -system.physmem.perBankRdBursts::8 416074 # Per bank write bursts -system.physmem.perBankRdBursts::9 415577 # Per bank write bursts -system.physmem.perBankRdBursts::10 415249 # Per bank write bursts -system.physmem.perBankRdBursts::11 414844 # Per bank write bursts -system.physmem.perBankRdBursts::12 415143 # Per bank write bursts -system.physmem.perBankRdBursts::13 415555 # Per bank write bursts -system.physmem.perBankRdBursts::14 415561 # Per bank write bursts -system.physmem.perBankRdBursts::15 415203 # Per bank write bursts -system.physmem.perBankWrBursts::0 6999 # Per bank write bursts -system.physmem.perBankWrBursts::1 6843 # Per bank write bursts -system.physmem.perBankWrBursts::2 7018 # Per bank write bursts -system.physmem.perBankWrBursts::3 7170 # Per bank write bursts -system.physmem.perBankWrBursts::4 7419 # Per bank write bursts -system.physmem.perBankWrBursts::5 7182 # Per bank write bursts -system.physmem.perBankWrBursts::6 7433 # Per bank write bursts -system.physmem.perBankWrBursts::7 7180 # Per bank write bursts -system.physmem.perBankWrBursts::8 7611 # Per bank write bursts -system.physmem.perBankWrBursts::9 7217 # Per bank write bursts -system.physmem.perBankWrBursts::10 7107 # Per bank write bursts -system.physmem.perBankWrBursts::11 6660 # Per bank write bursts -system.physmem.perBankWrBursts::12 6804 # Per bank write bursts -system.physmem.perBankWrBursts::13 7009 # Per bank write bursts -system.physmem.perBankWrBursts::14 7096 # Per bank write bursts -system.physmem.perBankWrBursts::15 6827 # Per bank write bursts +system.physmem.perBankRdBursts::6 415821 # Per bank write bursts +system.physmem.perBankRdBursts::7 415579 # Per bank write bursts +system.physmem.perBankRdBursts::8 415943 # Per bank write bursts +system.physmem.perBankRdBursts::9 415582 # Per bank write bursts +system.physmem.perBankRdBursts::10 415396 # Per bank write bursts +system.physmem.perBankRdBursts::11 414885 # Per bank write bursts +system.physmem.perBankRdBursts::12 414891 # Per bank write bursts +system.physmem.perBankRdBursts::13 415396 # Per bank write bursts +system.physmem.perBankRdBursts::14 415532 # Per bank write bursts +system.physmem.perBankRdBursts::15 415025 # Per bank write bursts +system.physmem.perBankWrBursts::0 6797 # Per bank write bursts +system.physmem.perBankWrBursts::1 6838 # Per bank write bursts +system.physmem.perBankWrBursts::2 6874 # Per bank write bursts +system.physmem.perBankWrBursts::3 7108 # Per bank write bursts +system.physmem.perBankWrBursts::4 7245 # Per bank write bursts +system.physmem.perBankWrBursts::5 7088 # Per bank write bursts +system.physmem.perBankWrBursts::6 7332 # Per bank write bursts +system.physmem.perBankWrBursts::7 7150 # Per bank write bursts +system.physmem.perBankWrBursts::8 7392 # Per bank write bursts +system.physmem.perBankWrBursts::9 7114 # Per bank write bursts +system.physmem.perBankWrBursts::10 7008 # Per bank write bursts +system.physmem.perBankWrBursts::11 6578 # Per bank write bursts +system.physmem.perBankWrBursts::12 6732 # Per bank write bursts +system.physmem.perBankWrBursts::13 6801 # Per bank write bursts +system.physmem.perBankWrBursts::14 7004 # Per bank write bursts +system.physmem.perBankWrBursts::15 6546 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1196138285000 # Total gap between requests +system.physmem.totGap 1196220625500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 6849 # Read request sizes (log2) system.physmem.readPktSize::3 6488064 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 159599 # Read request sizes (log2) +system.physmem.readPktSize::6 159180 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 756836 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 64268 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 628282 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 475071 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 476093 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1580129 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1132007 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1126499 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1123122 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 25082 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 24371 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 9325 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 9268 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 9185 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 8944 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 8860 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 8817 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 8783 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 173 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 16 # What read queue length does an incoming req see +system.physmem.writePktSize::6 63942 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 568386 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 406756 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 406740 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 413202 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 408903 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 410926 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1188562 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1189774 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1562236 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 22558 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 14685 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 15166 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 13714 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 12546 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 9828 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 9386 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 119 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -183,758 +179,434 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 5162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 5163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 74541 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 5810.577695 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 397.196541 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 13066.067638 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 25758 34.56% 34.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 15237 20.44% 55.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 3243 4.35% 59.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 2416 3.24% 62.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 1619 2.17% 64.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 1307 1.75% 66.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 1041 1.40% 67.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 1103 1.48% 69.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 718 0.96% 70.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 614 0.82% 71.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 577 0.77% 71.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 705 0.95% 72.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 343 0.46% 73.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 280 0.38% 73.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 211 0.28% 74.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 365 0.49% 74.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 178 0.24% 74.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 141 0.19% 74.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 142 0.19% 75.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 160 0.21% 75.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 121 0.16% 75.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 2248 3.02% 78.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 145 0.19% 78.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 165 0.22% 78.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 59 0.08% 79.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 66 0.09% 79.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 46 0.06% 79.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 116 0.16% 79.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 53 0.07% 79.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 27 0.04% 79.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 17 0.02% 79.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 120 0.16% 79.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 17 0.02% 79.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 20 0.03% 79.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 29 0.04% 79.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 31 0.04% 79.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 12 0.02% 79.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 26 0.03% 79.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 23 0.03% 79.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 90 0.12% 79.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 24 0.03% 79.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 12 0.02% 79.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 29 0.04% 80.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 36 0.05% 80.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 10 0.01% 80.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 25 0.03% 80.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3015 10 0.01% 80.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 133 0.18% 80.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 21 0.03% 80.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 12 0.02% 80.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 14 0.02% 80.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 45 0.06% 80.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 4 0.01% 80.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 9 0.01% 80.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 21 0.03% 80.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 88 0.12% 80.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 4 0.01% 80.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 17 0.02% 80.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 31 0.04% 80.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 79 0.11% 80.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 18 0.02% 80.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 3 0.00% 80.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4039 4 0.01% 80.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4103 183 0.25% 81.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4167 2 0.00% 81.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 2 0.00% 81.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4295 17 0.02% 81.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4359 24 0.03% 81.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 3 0.00% 81.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 18 0.02% 81.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4551 3 0.00% 81.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 17 0.02% 81.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4679 18 0.02% 81.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4743 2 0.00% 81.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4807 4 0.01% 81.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 95 0.13% 81.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 11 0.01% 81.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4999 5 0.01% 81.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5063 15 0.02% 81.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 100 0.13% 81.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 3 0.00% 81.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5255 19 0.03% 81.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5319 4 0.01% 81.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5383 16 0.02% 81.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5447 174 0.23% 81.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 59 0.08% 81.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 9 0.01% 81.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5703 1 0.00% 81.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5895 93 0.12% 82.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6023 3 0.00% 82.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6151 214 0.29% 82.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6407 32 0.04% 82.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6535 2 0.00% 82.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6599 2 0.00% 82.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6663 12 0.02% 82.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6919 17 0.02% 82.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7047 1 0.00% 82.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7175 160 0.21% 82.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7239 1 0.00% 82.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7367 1 0.00% 82.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7431 23 0.03% 82.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7623 1 0.00% 82.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7687 12 0.02% 82.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7751 1 0.00% 82.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7943 24 0.03% 82.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8007 1 0.00% 82.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8199 265 0.36% 83.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8455 29 0.04% 83.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8640-8647 1 0.00% 83.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8711 17 0.02% 83.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8967 27 0.04% 83.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9088-9095 1 0.00% 83.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9223 153 0.21% 83.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9479 18 0.02% 83.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9664-9671 1 0.00% 83.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9735 16 0.02% 83.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9991 33 0.04% 83.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10048-10055 1 0.00% 83.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10176-10183 1 0.00% 83.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10247 214 0.29% 83.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10368-10375 1 0.00% 83.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10503 86 0.12% 83.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10560-10567 1 0.00% 83.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10624-10631 2 0.00% 83.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10759 12 0.02% 83.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11015 17 0.02% 83.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11136-11143 1 0.00% 83.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11271 106 0.14% 84.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11328-11335 1 0.00% 84.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11392-11399 1 0.00% 84.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11527 81 0.11% 84.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11783 14 0.02% 84.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12039 16 0.02% 84.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12096-12103 3 0.00% 84.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12224-12231 1 0.00% 84.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12295 158 0.21% 84.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12416-12423 1 0.00% 84.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12480-12487 1 0.00% 84.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12551 76 0.10% 84.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12807 84 0.11% 84.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13063 29 0.04% 84.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13184-13191 1 0.00% 84.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13319 105 0.14% 84.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13376-13383 1 0.00% 84.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13575 26 0.03% 84.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13831 82 0.11% 84.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14087 13 0.02% 84.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14343 92 0.12% 85.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14599 80 0.11% 85.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14855 81 0.11% 85.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14912-14919 1 0.00% 85.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15111 16 0.02% 85.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15367 110 0.15% 85.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15488-15495 1 0.00% 85.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15623 77 0.10% 85.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15808-15815 1 0.00% 85.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15879 13 0.02% 85.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16135 82 0.11% 85.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16256-16263 3 0.00% 85.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16391 155 0.21% 85.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16647 83 0.11% 86.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16903 8 0.01% 86.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17024-17031 2 0.00% 86.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17159 77 0.10% 86.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17415 119 0.16% 86.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17671 21 0.03% 86.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17927 82 0.11% 86.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17984-17991 1 0.00% 86.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18183 80 0.11% 86.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18368-18375 1 0.00% 86.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18439 83 0.11% 86.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18496-18503 3 0.00% 86.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18695 10 0.01% 86.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18880-18887 1 0.00% 86.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18944-18951 83 0.11% 86.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19207 26 0.03% 86.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19328-19335 2 0.00% 86.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19463 103 0.14% 86.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19584-19591 1 0.00% 86.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19648-19655 1 0.00% 86.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19719 25 0.03% 87.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19904-19911 1 0.00% 87.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-19975 80 0.11% 87.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20160-20167 1 0.00% 87.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20231 73 0.10% 87.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20487 155 0.21% 87.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20608-20615 1 0.00% 87.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20743 19 0.03% 87.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-20999 16 0.02% 87.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21255 81 0.11% 87.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21376-21383 2 0.00% 87.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21511 95 0.13% 87.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21767 10 0.01% 87.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22023 9 0.01% 87.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22279 89 0.12% 87.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22400-22407 1 0.00% 87.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22464-22471 1 0.00% 87.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22535 219 0.29% 88.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22791 30 0.04% 88.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22912-22919 1 0.00% 88.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23040-23047 13 0.02% 88.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23303 21 0.03% 88.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23424-23431 2 0.00% 88.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23559 145 0.19% 88.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23680-23687 1 0.00% 88.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23808-23815 22 0.03% 88.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23872-23879 1 0.00% 88.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24000-24007 1 0.00% 88.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24071 13 0.02% 88.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24327 23 0.03% 88.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24384-24391 3 0.00% 88.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24583 273 0.37% 88.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24839 26 0.03% 88.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24896-24903 2 0.00% 88.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24960-24967 1 0.00% 88.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25095 15 0.02% 88.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25344-25351 24 0.03% 88.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25472-25479 2 0.00% 88.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25607 143 0.19% 89.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25664-25671 1 0.00% 89.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25863 19 0.03% 89.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26119 12 0.02% 89.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26375 28 0.04% 89.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26432-26439 1 0.00% 89.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26496-26503 2 0.00% 89.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26631 214 0.29% 89.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26880-26887 90 0.12% 89.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27143 12 0.02% 89.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27200-27207 1 0.00% 89.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27264-27271 1 0.00% 89.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27399 13 0.02% 89.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27456-27463 1 0.00% 89.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27584-27591 1 0.00% 89.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27655 92 0.12% 89.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27911 79 0.11% 89.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28160-28167 14 0.02% 89.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28352-28359 1 0.00% 89.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28423 19 0.03% 89.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28480-28487 1 0.00% 89.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28608-28615 1 0.00% 89.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28679 159 0.21% 90.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28800-28807 1 0.00% 90.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28935 74 0.10% 90.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29120-29127 1 0.00% 90.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29191 82 0.11% 90.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29447 26 0.03% 90.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29504-29511 2 0.00% 90.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29703 92 0.12% 90.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29888-29895 1 0.00% 90.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-29959 27 0.04% 90.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30215 80 0.11% 90.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30272-30279 1 0.00% 90.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30471 9 0.01% 90.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30528-30535 2 0.00% 90.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30727 85 0.11% 90.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-30983 81 0.11% 90.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31104-31111 1 0.00% 90.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31239 79 0.11% 91.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31495 18 0.02% 91.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31552-31559 1 0.00% 91.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31616-31623 1 0.00% 91.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31751 112 0.15% 91.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31936-31943 1 0.00% 91.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32000-32007 76 0.10% 91.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32263 8 0.01% 91.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32320-32327 1 0.00% 91.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32384-32391 1 0.00% 91.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32448-32455 1 0.00% 91.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32519 82 0.11% 91.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32775 154 0.21% 91.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33031 83 0.11% 91.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33088-33095 1 0.00% 91.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33152-33159 1 0.00% 91.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33216-33223 2 0.00% 91.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33287 23 0.03% 91.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33344-33351 1 0.00% 91.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33543 76 0.10% 91.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33600-33607 1 0.00% 91.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33799 112 0.15% 92.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33920-33927 2 0.00% 92.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33984-33991 1 0.00% 92.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34048-34055 18 0.02% 92.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34304-34311 79 0.11% 92.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34432-34439 1 0.00% 92.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34560-34567 80 0.11% 92.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34823 78 0.10% 92.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34880-34887 1 0.00% 92.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35008-35015 2 0.00% 92.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35072-35079 8 0.01% 92.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35328-35335 80 0.11% 92.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35584-35591 27 0.04% 92.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35648-35655 1 0.00% 92.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35847 91 0.12% 92.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36032-36039 1 0.00% 92.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36096-36103 24 0.03% 92.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36224-36231 1 0.00% 92.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36352-36359 82 0.11% 92.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36608-36615 73 0.10% 92.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36871 149 0.20% 93.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37120-37127 15 0.02% 93.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37376-37383 14 0.02% 93.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37632-37639 80 0.11% 93.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37895 93 0.12% 93.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37952-37959 1 0.00% 93.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38080-38087 1 0.00% 93.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38144-38151 10 0.01% 93.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38272-38279 1 0.00% 93.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38336-38343 1 0.00% 93.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38400-38407 11 0.01% 93.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38528-38535 1 0.00% 93.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38656-38663 90 0.12% 93.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38912-38919 212 0.28% 93.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39040-39047 1 0.00% 93.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39104-39111 1 0.00% 93.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39168-39175 27 0.04% 93.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39424-39431 11 0.01% 93.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39552-39559 1 0.00% 93.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39680-39687 20 0.03% 93.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39872-39879 1 0.00% 93.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39936-39943 144 0.19% 94.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40192-40199 21 0.03% 94.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40448-40455 14 0.02% 94.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40576-40583 1 0.00% 94.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40640-40647 1 0.00% 94.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40704-40711 25 0.03% 94.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-40967 269 0.36% 94.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41152-41159 2 0.00% 94.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41216-41223 23 0.03% 94.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41472-41479 10 0.01% 94.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41600-41607 1 0.00% 94.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41728-41735 23 0.03% 94.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41856-41863 1 0.00% 94.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-41991 146 0.20% 94.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42240-42247 21 0.03% 94.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42496-42503 11 0.01% 94.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42624-42631 1 0.00% 94.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42688-42695 1 0.00% 94.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42752-42759 31 0.04% 94.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43015 219 0.29% 95.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43072-43079 1 0.00% 95.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43264-43271 87 0.12% 95.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43520-43527 9 0.01% 95.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43648-43655 1 0.00% 95.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43776-43783 11 0.01% 95.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44032-44039 92 0.12% 95.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44288-44295 80 0.11% 95.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44544-44551 18 0.02% 95.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44800-44807 17 0.02% 95.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44928-44935 1 0.00% 95.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45056-45063 149 0.20% 95.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45312-45319 71 0.10% 95.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45568-45575 78 0.10% 96.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45696-45703 1 0.00% 96.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45824-45831 27 0.04% 96.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45888-45895 1 0.00% 96.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45952-45959 1 0.00% 96.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46087 99 0.13% 96.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46336-46343 27 0.04% 96.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46592-46599 83 0.11% 96.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46656-46663 1 0.00% 96.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46848-46855 11 0.01% 96.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47104-47111 90 0.12% 96.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47168-47175 1 0.00% 96.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47367 82 0.11% 96.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47552-47559 1 0.00% 96.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47623 83 0.11% 96.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47680-47687 1 0.00% 96.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47872-47879 18 0.02% 96.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48000-48007 1 0.00% 96.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48135 130 0.17% 96.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48192-48199 2 0.00% 96.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48256-48263 1 0.00% 96.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48320-48327 2 0.00% 96.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48391 100 0.13% 97.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48576-48583 1 0.00% 97.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48640-48647 6 0.01% 97.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48768-48775 13 0.02% 97.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48903 79 0.11% 97.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48960-48967 5 0.01% 97.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49024-49031 5 0.01% 97.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49088-49095 6 0.01% 97.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49159 2052 2.75% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 74541 # Bytes accessed per row activation -system.physmem.totQLat 159547739500 # Total ticks spent queuing -system.physmem.totMemAccLat 202481649500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 33270135000 # Total ticks spent in databus transfers -system.physmem.totBankLat 9663775000 # Total ticks spent accessing banks -system.physmem.avgQLat 23977.62 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1452.32 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2656 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3656 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5316 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5217 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1090 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1087 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1087 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1076 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1076 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1074 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1072 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1074 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1072 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1070 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1069 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1069 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1067 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1067 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1065 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1065 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1064 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1064 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1064 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1064 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 427748 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 996.884371 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 962.233746 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 147.681447 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 5003 1.17% 1.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 3928 0.92% 2.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 2092 0.49% 2.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1312 0.31% 2.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1079 0.25% 3.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 787 0.18% 3.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 742 0.17% 3.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 447 0.10% 3.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 412358 96.40% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 427748 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5121 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 1299.254638 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 29808.283067 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-65535 5114 99.86% 99.86% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::196608-262143 3 0.06% 99.92% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::589824-655359 1 0.02% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::786432-851967 1 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::983040-1.04858e+06 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1.57286e+06-1.6384e+06 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 5121 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5121 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 21.793986 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.383938 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 9.006526 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2131 41.61% 41.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 296 5.78% 47.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 286 5.58% 52.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1314 25.66% 78.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 15 0.29% 78.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 5 0.10% 79.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 2 0.04% 79.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 2 0.04% 79.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 1 0.02% 79.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 3 0.06% 79.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34 1 0.02% 79.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 1 0.02% 79.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::39 953 18.61% 97.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40 61 1.19% 99.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::41 17 0.33% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42 33 0.64% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5121 # Writes before turning the bus around for reads +system.physmem.totQLat 249828830750 # Total ticks spent queuing +system.physmem.totMemAccLat 297299498250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 33267495000 # Total ticks spent in databus transfers +system.physmem.totBankLat 14203172500 # Total ticks spent accessing banks +system.physmem.avgQLat 37548.49 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 2134.69 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30429.94 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 356.03 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 6.08 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 51.96 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 5.97 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 44683.18 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 355.97 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 5.97 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 51.93 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 5.95 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.83 # Data bus utilization in percentage system.physmem.busUtilRead 2.78 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.17 # Average read queue length when enqueuing -system.physmem.avgWrQLen 12.60 # Average write queue length when enqueuing -system.physmem.readRowHits 6598250 # Number of row buffer hits during reads -system.physmem.writeRowHits 94811 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.16 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 83.48 # Row buffer hit rate for writes -system.physmem.avgGap 160005.31 # Average gap between requests -system.physmem.pageHitRate 98.90 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 4.94 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 59942042 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 7703387 # Transaction distribution -system.membus.trans_dist::ReadResp 7703387 # Transaction distribution -system.membus.trans_dist::WriteReq 767577 # Transaction distribution -system.membus.trans_dist::WriteResp 767577 # Transaction distribution -system.membus.trans_dist::Writeback 64268 # Transaction distribution -system.membus.trans_dist::UpgradeReq 31533 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 17272 # Transaction distribution -system.membus.trans_dist::UpgradeResp 12040 # Transaction distribution -system.membus.trans_dist::ReadExReq 137758 # Transaction distribution -system.membus.trans_dist::ReadExResp 137334 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382660 # Packet count per connected master and slave (bytes) +system.physmem.avgRdQLen 4.56 # Average read queue length when enqueuing +system.physmem.avgWrQLen 29.44 # Average write queue length when enqueuing +system.physmem.readRowHits 6202256 # Number of row buffer hits during reads +system.physmem.writeRowHits 93908 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.22 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 84.12 # Row buffer hit rate for writes +system.physmem.avgGap 160032.28 # Average gap between requests +system.physmem.pageHitRate 93.07 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 6.14 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 59898120 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 7703395 # Transaction distribution +system.membus.trans_dist::ReadResp 7703395 # Transaction distribution +system.membus.trans_dist::WriteReq 767585 # Transaction distribution +system.membus.trans_dist::WriteResp 767585 # Transaction distribution +system.membus.trans_dist::Writeback 63942 # Transaction distribution +system.membus.trans_dist::UpgradeReq 31730 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 17317 # Transaction distribution +system.membus.trans_dist::UpgradeResp 11979 # Transaction distribution +system.membus.trans_dist::ReadExReq 137317 # Transaction distribution +system.membus.trans_dist::ReadExResp 136921 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382690 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 10292 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 10302 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 910 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1972105 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4366005 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 914 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1971094 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4365038 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12976128 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 12976128 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 17342133 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390026 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 17341166 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390070 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 20584 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 20604 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1820 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17382228 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 19794734 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1828 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17334548 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 19747126 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 51904512 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 51904512 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 71699246 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 71699246 # Total data (bytes) +system.membus.tot_pkt_size::total 71651638 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 71651638 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1224801500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1224825500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 18000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 9220500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 9234000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 782500 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 786000 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 9211496500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 9208108500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 5081612097 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 5075173558 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.respLayer2.occupancy 14657936499 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 1.2 # Layer utilization (%) +system.membus.respLayer2.occupancy 16181474500 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 1.4 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 69480 # number of replacements -system.l2c.tags.tagsinuse 52958.538682 # Cycle average of tags in use -system.l2c.tags.total_refs 1674406 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 134639 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 12.436263 # Average number of references to valid blocks. +system.l2c.tags.replacements 69062 # number of replacements +system.l2c.tags.tagsinuse 52959.899517 # Cycle average of tags in use +system.l2c.tags.total_refs 1674433 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 134270 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 12.470641 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 40140.336267 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000411 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001545 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3711.388388 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4232.378884 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.742427 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.001688 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2812.770235 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2058.918835 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.612493 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 40142.433744 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000410 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.003238 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3707.808501 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4231.213775 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.742447 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2816.465022 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2059.232379 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.612525 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.056631 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.064581 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.056577 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.064563 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.042919 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.031417 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.808083 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.042976 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.031421 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.808104 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65154 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65203 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1929 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 8108 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55070 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1924 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 7908 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 55276 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.994171 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 17216542 # Number of tag accesses -system.l2c.tags.data_accesses 17216542 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 3810 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 1731 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 419647 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 206017 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 5550 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1931 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 464603 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 143237 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1246526 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 570959 # number of Writeback hits -system.l2c.Writeback_hits::total 570959 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1148 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 589 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1737 # number of UpgradeReq hits +system.l2c.tags.occ_task_id_percent::1024 0.994919 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 17240213 # Number of tag accesses +system.l2c.tags.data_accesses 17240213 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 2997 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 1656 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 349452 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 169925 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 6371 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 1905 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 535287 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 180837 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1248430 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 572475 # number of Writeback hits +system.l2c.Writeback_hits::total 572475 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 1043 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 587 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1630 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu0.data 220 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 100 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 320 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 56693 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 52725 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 109418 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 3810 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 1731 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 419647 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 262710 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 5550 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 1931 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 464603 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 195962 # number of demand (read+write) hits -system.l2c.demand_hits::total 1355944 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 3810 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 1731 # number of overall hits -system.l2c.overall_hits::cpu0.inst 419647 # number of overall hits -system.l2c.overall_hits::cpu0.data 262710 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 5550 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 1931 # number of overall hits -system.l2c.overall_hits::cpu1.inst 464603 # number of overall hits -system.l2c.overall_hits::cpu1.data 195962 # number of overall hits -system.l2c.overall_hits::total 1355944 # number of overall hits +system.l2c.SCUpgradeReq_hits::cpu1.data 84 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 304 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 47236 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 62412 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 109648 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 2997 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 1656 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 349452 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 217161 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 6371 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 1905 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 535287 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 243249 # number of demand (read+write) hits +system.l2c.demand_hits::total 1358078 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 2997 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 1656 # number of overall hits +system.l2c.overall_hits::cpu0.inst 349452 # number of overall hits +system.l2c.overall_hits::cpu0.data 217161 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 6371 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 1905 # number of overall hits +system.l2c.overall_hits::cpu1.inst 535287 # number of overall hits +system.l2c.overall_hits::cpu1.data 243249 # number of overall hits +system.l2c.overall_hits::total 1358078 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 5732 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 7847 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 5500 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 7825 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 4 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 5061 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 3618 # number of ReadReq misses -system.l2c.ReadReq_misses::total 22266 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 4882 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 3680 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 8562 # number of UpgradeReq misses +system.l2c.ReadReq_misses::cpu1.inst 5275 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 3652 # number of ReadReq misses +system.l2c.ReadReq_misses::total 22260 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 3753 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 4772 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 8525 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu0.data 571 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 474 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1045 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 67309 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 72458 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 139767 # number of ReadExReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 460 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1031 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 63889 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 75455 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 139344 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 5732 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 75156 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 5500 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 71714 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 4 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 5061 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 76076 # number of demand (read+write) misses -system.l2c.demand_misses::total 162033 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 5275 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 79107 # number of demand (read+write) misses +system.l2c.demand_misses::total 161604 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 5732 # number of overall misses -system.l2c.overall_misses::cpu0.data 75156 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses +system.l2c.overall_misses::cpu0.inst 5500 # number of overall misses +system.l2c.overall_misses::cpu0.data 71714 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 4 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 5061 # number of overall misses -system.l2c.overall_misses::cpu1.data 76076 # number of overall misses -system.l2c.overall_misses::total 162033 # number of overall misses +system.l2c.overall_misses::cpu1.inst 5275 # number of overall misses +system.l2c.overall_misses::cpu1.data 79107 # number of overall misses +system.l2c.overall_misses::total 161604 # number of overall misses system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 32000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 149500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 403588750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 587952999 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 347000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 74500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 364948250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 284058750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1641151749 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 13131433 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 12135478 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 25266911 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1819924 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2531891 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 4351815 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 4527558160 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 5454938401 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 9982496561 # number of ReadExReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 224500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 385138750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 587705249 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 334500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 381420250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 283658250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1638513499 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 11041523 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 13954898 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 24996421 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1841422 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2322900 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 4164322 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 4291032858 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 5578462720 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 9869495578 # number of ReadExReq miss cycles system.l2c.demand_miss_latency::cpu0.dtb.walker 32000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 149500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 403588750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 5115511159 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 347000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 74500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 364948250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 5738997151 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 11623648310 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 224500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 385138750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 4878738107 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 334500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 381420250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 5862120970 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 11508009077 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu0.dtb.walker 32000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 149500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 403588750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 5115511159 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 347000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 74500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 364948250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 5738997151 # number of overall miss cycles -system.l2c.overall_miss_latency::total 11623648310 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 3811 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 1733 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 425379 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 213864 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 5554 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 1932 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 469664 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 146855 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1268792 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 570959 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 570959 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 6030 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 4269 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 10299 # number of UpgradeReq accesses(hits+misses) +system.l2c.overall_miss_latency::cpu0.itb.walker 224500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 385138750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 4878738107 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 334500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 381420250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 5862120970 # number of overall miss cycles +system.l2c.overall_miss_latency::total 11508009077 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 2998 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 1659 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 354952 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 177750 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 6375 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 1905 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 540562 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 184489 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1270690 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 572475 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 572475 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 4796 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 5359 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 10155 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu0.data 791 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 574 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1365 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 124002 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 125183 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 249185 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 3811 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 1733 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 425379 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 337866 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 5554 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 1932 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 469664 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 272038 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1517977 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 3811 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 1733 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 425379 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 337866 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 5554 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 1932 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 469664 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 272038 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1517977 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000262 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001154 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.013475 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.036692 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000720 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000518 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.010776 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.024637 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.017549 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.809619 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.862029 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.831343 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_accesses::cpu1.data 544 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1335 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 111125 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 137867 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 248992 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 2998 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 1659 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 354952 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 288875 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 6375 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 1905 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 540562 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 322356 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1519682 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 2998 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 1659 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 354952 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 288875 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 6375 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 1905 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 540562 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 322356 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1519682 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000334 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001808 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.015495 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.044023 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000627 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.009758 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.019795 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.017518 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.782527 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.890465 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.839488 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.721871 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.825784 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.765568 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.542806 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.578817 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.560897 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000262 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.001154 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.013475 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.222443 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000720 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.000518 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.010776 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.279652 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.106743 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000262 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.001154 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.013475 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.222443 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000720 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.000518 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.010776 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.279652 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.106743 # miss rate for overall accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.845588 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.772285 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.574929 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.547303 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.559632 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000334 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.001808 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.015495 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.248253 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000627 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.009758 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.245403 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.106341 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000334 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.001808 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.015495 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.248253 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000627 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.009758 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.245403 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.106341 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 32000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 74750 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 70409.760991 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 74927.105773 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 86750 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 74500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72109.909109 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 78512.645108 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 73706.626650 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2689.765055 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3297.684239 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 2951.052441 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3187.257443 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5341.542194 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 4164.416268 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 67265.271509 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 75284.142552 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 71422.414168 # average ReadExReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 74833.333333 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 70025.227273 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 75106.102109 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 83625 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72307.156398 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 77672.029025 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 73607.973899 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2942.052491 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2924.329003 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 2932.131496 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3224.907180 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5049.782609 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 4039.109602 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 67163.875753 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 73930.988271 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 70828.278060 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 32000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 74750 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 70409.760991 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 68065.239755 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 86750 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 74500 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 72109.909109 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 75437.682725 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 71736.302543 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 74833.333333 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 70025.227273 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 68030.483685 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 83625 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 72307.156398 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 74103.694616 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 71211.164804 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 32000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 74750 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 70409.760991 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 68065.239755 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 86750 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 74500 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 72109.909109 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 75437.682725 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 71736.302543 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 74833.333333 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 70025.227273 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 68030.483685 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 83625 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 72307.156398 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 74103.694616 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 71211.164804 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -943,8 +615,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 64268 # number of writebacks -system.l2c.writebacks::total 64268 # number of writebacks +system.l2c.writebacks::writebacks 63942 # number of writebacks +system.l2c.writebacks::total 63942 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits @@ -952,162 +624,150 @@ system.l2c.demand_mshr_hits::total 1 # nu system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 5731 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 7847 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 3 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 5499 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 7825 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 4 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 5061 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 3618 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 22265 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 4882 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 3680 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 8562 # number of UpgradeReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 5275 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 3652 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 22259 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 3753 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 4772 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 8525 # number of UpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 571 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 474 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1045 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 67309 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 72458 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 139767 # number of ReadExReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 460 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1031 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 63889 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 75455 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 139344 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu0.dtb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 5731 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 75156 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 3 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 5499 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 71714 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.dtb.walker 4 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 5061 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 76076 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 162032 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 5275 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 79107 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 161603 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0.dtb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 5731 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 75156 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 3 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 5499 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 71714 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.dtb.walker 4 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 5061 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 76076 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 162032 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 5275 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 79107 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 161603 # number of overall MSHR misses system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 20000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 125000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 330890500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 490057499 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 297000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 62500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 300853250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 239085250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1361390999 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 48852378 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 36863673 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 85716051 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 5720067 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4752971 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 10473038 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3658860326 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4532497595 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 8191357921 # number of ReadExReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 187500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 315394500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 490118749 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 284500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 314655750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 238278250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1358939249 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 37548751 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 47763765 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 85312516 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 5717068 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4604958 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 10322026 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3469064140 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4618288780 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 8087352920 # number of ReadExReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 20000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 125000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 330890500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 4148917825 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 297000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 62500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 300853250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 4771582845 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 9552748920 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 187500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 315394500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 3959182889 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 284500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 314655750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 4856567030 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 9446292169 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 20000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 125000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 330890500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 4148917825 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 297000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 62500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 300853250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 4771582845 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 9552748920 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 345201250 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12458267494 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5350750 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154290476246 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 167099295740 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1046790495 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 15722211628 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 16769002123 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 345201250 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13505057989 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5350750 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 170012687874 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 183868297863 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000262 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001154 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013473 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036692 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000720 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000518 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010776 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.024637 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.017548 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.809619 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.862029 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.831343 # mshr miss rate for UpgradeReq accesses +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 187500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 315394500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 3959182889 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 284500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 314655750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 4856567030 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 9446292169 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 352326000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 11221595994 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5508250 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 155529668246 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 167109098490 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1041121994 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 15728911223 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 16770033217 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 352326000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 12262717988 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5508250 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 171258579469 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 183879131707 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000334 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001808 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015492 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.044023 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000627 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009758 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.019795 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.017517 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.782527 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.890465 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.839488 # mshr miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.721871 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.825784 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.765568 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.542806 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.578817 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.560897 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000262 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001154 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013473 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.222443 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000720 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000518 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010776 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.279652 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.106742 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000262 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001154 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013473 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.222443 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000720 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000518 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010776 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.279652 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.106742 # mshr miss rate for overall accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.845588 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.772285 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.574929 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.547303 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.559632 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000334 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001808 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015492 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.248253 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000627 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009758 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.245403 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.106340 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000334 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001808 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015492 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.248253 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000627 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009758 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.245403 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.106340 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 20000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 57736.956901 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 62451.573722 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 74250 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59445.415926 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 66082.158651 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 61144.891040 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10006.632118 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10017.302446 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10011.218290 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10017.630473 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10027.364979 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10022.045933 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 54359.154437 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62553.446065 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 58607.238626 # average ReadExReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 57354.882706 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 62634.983898 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 71125 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59650.379147 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65245.961117 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 61051.226425 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10004.996270 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10009.171207 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10007.333255 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10012.378284 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10010.778261 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10011.664403 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 54298.300803 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61205.868133 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 58038.759616 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 20000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 57736.956901 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 55204.079847 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 74250 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59445.415926 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62721.263539 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 58955.940308 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 57354.882706 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 55207.949480 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 71125 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59650.379147 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61392.380320 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 58453.693118 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 20000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 57736.956901 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 55204.079847 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 74250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59445.415926 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62721.263539 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 58955.940308 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 57354.882706 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 55207.949480 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 71125 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59650.379147 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61392.380320 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 58453.693118 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -1128,62 +788,62 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 119544694 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2535779 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2535779 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 767577 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 767577 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 570959 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 30837 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 17592 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 48429 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 260947 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 260947 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 864602 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1227966 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 6129 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 12680 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 940064 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4600791 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 6258 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 15477 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7673967 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 27250848 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 41432384 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 6932 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 15244 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 30058932 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 39583066 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 7728 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 22216 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 138377350 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 138377350 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 4615184 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4759626187 # Layer occupancy (ticks) +system.toL2Bus.throughput 119642613 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2536412 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2536412 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 767585 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 767585 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 572475 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 30937 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 17621 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 48558 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 260776 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 260776 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 723469 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1059051 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 4339 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 7907 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1082141 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4772543 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 7929 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 20256 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7677635 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 22743520 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 35146882 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 6636 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 11992 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 34596404 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 46050592 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 7620 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 25500 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 138589146 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 138589146 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 4530356 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4766758175 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1926082966 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1756498781 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1607753214 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 1517597206 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 4396000 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 2680000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 8869000 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 4909499 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 2116921475 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.occupancy 2437223968 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 2926499865 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer8.occupancy 4326000 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 3163938724 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 0.3 # Layer utilization (%) +system.toL2Bus.respLayer8.occupancy 6024000 # Layer occupancy (ticks) system.toL2Bus.respLayer8.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer9.occupancy 9923499 # Layer occupancy (ticks) +system.toL2Bus.respLayer9.occupancy 13881500 # Layer occupancy (ticks) system.toL2Bus.respLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 45391348 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 7671431 # Transaction distribution -system.iobus.trans_dist::ReadResp 7671431 # Transaction distribution -system.iobus.trans_dist::WriteReq 7963 # Transaction distribution -system.iobus.trans_dist::WriteResp 7963 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30550 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8056 # Packet count per connected master and slave (bytes) +system.iobus.throughput 45388263 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7671442 # Transaction distribution +system.iobus.trans_dist::ReadResp 7671442 # Transaction distribution +system.iobus.trans_dist::WriteReq 7967 # Transaction distribution +system.iobus.trans_dist::WriteResp 7967 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30566 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8070 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 742 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -1205,12 +865,12 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382660 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382690 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12976128 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 12976128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 15358788 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40319 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16112 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 15358818 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40335 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16140 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1484 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -1232,14 +892,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390026 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390070 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 51904512 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 51904512 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 54294538 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 54294538 # Total data (bytes) -system.iobus.reqLayer0.occupancy 21418000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::total 54294582 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 54294582 # Total data (bytes) +system.iobus.reqLayer0.occupancy 21430000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 4034000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 4041000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1285,10 +945,10 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 6488064000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374697000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374723000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.2 # Layer utilization (%) -system.iobus.respLayer1.occupancy 17777962501 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) +system.iobus.respLayer1.occupancy 16195242500 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 1.4 # Layer utilization (%) system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1312,25 +972,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7070497 # DTB read hits -system.cpu0.dtb.read_misses 3747 # DTB read misses -system.cpu0.dtb.write_hits 5655659 # DTB write hits -system.cpu0.dtb.write_misses 806 # DTB write misses +system.cpu0.dtb.read_hits 5879584 # DTB read hits +system.cpu0.dtb.read_misses 2138 # DTB read misses +system.cpu0.dtb.write_hits 4838515 # DTB write hits +system.cpu0.dtb.write_misses 406 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1708 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 1387 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 142 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 88 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7074244 # DTB read accesses -system.cpu0.dtb.write_accesses 5656465 # DTB write accesses +system.cpu0.dtb.perms_faults 203 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 5881722 # DTB read accesses +system.cpu0.dtb.write_accesses 4838921 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12726156 # DTB hits -system.cpu0.dtb.misses 4553 # DTB misses -system.cpu0.dtb.accesses 12730709 # DTB accesses +system.cpu0.dtb.hits 10718099 # DTB hits +system.cpu0.dtb.misses 2544 # DTB misses +system.cpu0.dtb.accesses 10720643 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1352,8 +1012,8 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 29571351 # ITB inst hits -system.cpu0.itb.inst_misses 2205 # ITB inst misses +system.cpu0.itb.inst_hits 24773464 # ITB inst hits +system.cpu0.itb.inst_misses 1350 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -1362,95 +1022,94 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1181 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 963 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 29573556 # ITB inst accesses -system.cpu0.itb.hits 29571351 # DTB hits -system.cpu0.itb.misses 2205 # DTB misses -system.cpu0.itb.accesses 29573556 # DTB accesses -system.cpu0.numCycles 2392285746 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 24774814 # ITB inst accesses +system.cpu0.itb.hits 24773464 # DTB hits +system.cpu0.itb.misses 1350 # DTB misses +system.cpu0.itb.accesses 24774814 # DTB accesses +system.cpu0.numCycles 2391604989 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 28873226 # Number of instructions committed -system.cpu0.committedOps 37212709 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 33137047 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses -system.cpu0.num_func_calls 1242091 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4373605 # number of instructions that are conditional controls -system.cpu0.num_int_insts 33137047 # number of integer instructions -system.cpu0.num_fp_insts 3860 # number of float instructions -system.cpu0.num_int_register_reads 192300691 # number of times the integer registers were read -system.cpu0.num_int_register_writes 36265278 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written -system.cpu0.num_mem_refs 13394015 # number of memory refs -system.cpu0.num_load_insts 7407936 # Number of load instructions -system.cpu0.num_store_insts 5986079 # Number of store instructions -system.cpu0.num_idle_cycles 2246427166.466122 # Number of idle cycles -system.cpu0.num_busy_cycles 145858579.533878 # Number of busy cycles -system.cpu0.not_idle_fraction 0.060970 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.939030 # Percentage of idle cycles -system.cpu0.Branches 5601726 # Number of branches fetched +system.cpu0.committedInsts 24375312 # Number of instructions committed +system.cpu0.committedOps 31460856 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 28085533 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 4364 # Number of float alu accesses +system.cpu0.num_func_calls 1070699 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 3751745 # number of instructions that are conditional controls +system.cpu0.num_int_insts 28085533 # number of integer instructions +system.cpu0.num_fp_insts 4364 # number of float instructions +system.cpu0.num_int_register_reads 162520351 # number of times the integer registers were read +system.cpu0.num_int_register_writes 30535592 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3980 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 384 # number of times the floating registers were written +system.cpu0.num_mem_refs 11309766 # number of memory refs +system.cpu0.num_load_insts 6158982 # Number of load instructions +system.cpu0.num_store_insts 5150784 # Number of store instructions +system.cpu0.num_idle_cycles 2265857607.135565 # Number of idle cycles +system.cpu0.num_busy_cycles 125747381.864435 # Number of busy cycles +system.cpu0.not_idle_fraction 0.052579 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.947421 # Percentage of idle cycles +system.cpu0.Branches 4778581 # Number of branches fetched system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 46915 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 425414 # number of replacements -system.cpu0.icache.tags.tagsinuse 509.356883 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 29145407 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 425926 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 68.428335 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 76234819000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.356883 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994838 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.994838 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 39137 # number of quiesce instructions executed +system.cpu0.icache.tags.replacements 354708 # number of replacements +system.cpu0.icache.tags.tagsinuse 509.352361 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 24418226 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 355220 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 68.741135 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 76254991000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.352361 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994829 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.994829 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 266 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 464 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 47 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 29997261 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 29997261 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 29145407 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 29145407 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 29145407 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 29145407 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 29145407 # number of overall hits -system.cpu0.icache.overall_hits::total 29145407 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 425927 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 425927 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 425927 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 425927 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 425927 # number of overall misses -system.cpu0.icache.overall_misses::total 425927 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5899388216 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5899388216 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5899388216 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5899388216 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5899388216 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5899388216 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 29571334 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 29571334 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 29571334 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 29571334 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 29571334 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 29571334 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014403 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014403 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014403 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014403 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014403 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014403 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13850.702623 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13850.702623 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13850.702623 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13850.702623 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13850.702623 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13850.702623 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 25128668 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 25128668 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 24418226 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 24418226 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 24418226 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 24418226 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 24418226 # number of overall hits +system.cpu0.icache.overall_hits::total 24418226 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 355221 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 355221 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 355221 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 355221 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 355221 # number of overall misses +system.cpu0.icache.overall_misses::total 355221 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 4963623214 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 4963623214 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 4963623214 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 4963623214 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 4963623214 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 4963623214 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 24773447 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 24773447 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 24773447 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 24773447 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 24773447 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 24773447 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014339 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014339 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014339 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014339 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014339 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014339 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13973.338327 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13973.338327 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13973.338327 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13973.338327 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13973.338327 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13973.338327 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1459,128 +1118,126 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 425927 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 425927 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 425927 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 425927 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 425927 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 425927 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5045293784 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 5045293784 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5045293784 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 5045293784 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5045293784 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 5045293784 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 437016250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 437016250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 437016250 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 437016250 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014403 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014403 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014403 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014403 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014403 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014403 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11845.442491 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11845.442491 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11845.442491 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11845.442491 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11845.442491 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11845.442491 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 355221 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 355221 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 355221 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 355221 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 355221 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 355221 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4251043786 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4251043786 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4251043786 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4251043786 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4251043786 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4251043786 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 443885000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 443885000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 443885000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 443885000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014339 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014339 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014339 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014339 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014339 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014339 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11967.321149 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11967.321149 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11967.321149 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11967.321149 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11967.321149 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11967.321149 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 330503 # number of replacements -system.cpu0.dcache.tags.tagsinuse 455.093016 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 12270625 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 331015 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 37.069695 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 667204250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 455.093016 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.888854 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.888854 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 345 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 95 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 50903218 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 50903218 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6600273 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6600273 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5350518 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5350518 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147975 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 147975 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149621 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 149621 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 11950791 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 11950791 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11950791 # number of overall hits -system.cpu0.dcache.overall_hits::total 11950791 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 227769 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 227769 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 141711 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 141711 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9370 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 9370 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7532 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7532 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 369480 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 369480 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 369480 # number of overall misses -system.cpu0.dcache.overall_misses::total 369480 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3309712250 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 3309712250 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5686464712 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 5686464712 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 92538750 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 92538750 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44740069 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 44740069 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 8996176962 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 8996176962 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 8996176962 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 8996176962 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6828042 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6828042 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5492229 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5492229 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157345 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 157345 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157153 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 157153 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12320271 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12320271 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12320271 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12320271 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033358 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.033358 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025802 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.025802 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059551 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059551 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047928 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047928 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029990 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.029990 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029990 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.029990 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14531.004000 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14531.004000 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40127.193457 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 40127.193457 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9876.067236 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9876.067236 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5939.998540 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5939.998540 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24348.210896 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 24348.210896 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 24348.210896 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 24348.210896 # average overall miss latency +system.cpu0.dcache.tags.replacements 278858 # number of replacements +system.cpu0.dcache.tags.tagsinuse 453.142717 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 10319958 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 279247 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 36.956379 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 673996250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 453.142717 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.885044 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.885044 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 389 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 379 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.759766 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 42855830 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 42855830 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 5473702 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5473702 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4567964 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4567964 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 129389 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 129389 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 130155 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 130155 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10041666 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10041666 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10041666 # number of overall hits +system.cpu0.dcache.overall_hits::total 10041666 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 191503 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 191503 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 126416 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 126416 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8708 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 8708 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7742 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7742 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 317919 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 317919 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 317919 # number of overall misses +system.cpu0.dcache.overall_misses::total 317919 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2845005745 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 2845005745 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5278408391 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 5278408391 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 82648500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 82648500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 45599070 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 45599070 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 8123414136 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 8123414136 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 8123414136 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 8123414136 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 5665205 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 5665205 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4694380 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4694380 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 138097 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 138097 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 137897 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 137897 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 10359585 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 10359585 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 10359585 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 10359585 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033803 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.033803 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.026929 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.026929 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.063057 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.063057 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.056143 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.056143 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.030688 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.030688 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.030688 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.030688 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14856.194133 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14856.194133 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41754.274704 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 41754.274704 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9491.100138 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9491.100138 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5889.830793 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5889.830793 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25551.835958 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 25551.835958 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 25551.835958 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 25551.835958 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1589,62 +1246,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 306085 # number of writebacks -system.cpu0.dcache.writebacks::total 306085 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 227769 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 227769 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141711 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 141711 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9370 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9370 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7530 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7530 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 369480 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 369480 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 369480 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 369480 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2852244750 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2852244750 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5372105288 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5372105288 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 73750250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 73750250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 29678931 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29678931 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8224350038 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 8224350038 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8224350038 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 8224350038 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13565968500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13565968500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1170779500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1170779500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14736748000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14736748000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033358 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033358 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025802 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025802 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059551 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059551 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047915 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047915 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029990 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029990 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029990 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.029990 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12522.532698 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12522.532698 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37908.879960 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37908.879960 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7870.891142 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7870.891142 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3941.425100 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3941.425100 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22259.256355 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22259.256355 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22259.256355 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22259.256355 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 257140 # number of writebacks +system.cpu0.dcache.writebacks::total 257140 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 191503 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 191503 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 126416 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 126416 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8708 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8708 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7738 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7738 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 317919 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 317919 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 317919 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 317919 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2460118255 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2460118255 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4997663609 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4997663609 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 65185500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 65185500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 30121930 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 30121930 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7457781864 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 7457781864 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7457781864 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 7457781864 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 12214482000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 12214482000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1164635000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1164635000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 13379117000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 13379117000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033803 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033803 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.026929 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.026929 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.063057 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.063057 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.056114 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.056114 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030688 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.030688 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030688 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.030688 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12846.369274 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12846.369274 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39533.473682 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39533.473682 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7485.702802 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7485.702802 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3892.728095 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3892.728095 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23458.119408 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23458.119408 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23458.119408 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23458.119408 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1675,25 +1332,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 8312417 # DTB read hits -system.cpu1.dtb.read_misses 3644 # DTB read misses -system.cpu1.dtb.write_hits 5828126 # DTB write hits -system.cpu1.dtb.write_misses 1438 # DTB write misses +system.cpu1.dtb.read_hits 9507781 # DTB read hits +system.cpu1.dtb.read_misses 5255 # DTB read misses +system.cpu1.dtb.write_hits 6647969 # DTB write hits +system.cpu1.dtb.write_misses 1834 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1864 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 2187 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 139 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 188 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 8316061 # DTB read accesses -system.cpu1.dtb.write_accesses 5829564 # DTB write accesses +system.cpu1.dtb.perms_faults 249 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 9513036 # DTB read accesses +system.cpu1.dtb.write_accesses 6649803 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 14140543 # DTB hits -system.cpu1.dtb.misses 5082 # DTB misses -system.cpu1.dtb.accesses 14145625 # DTB accesses +system.cpu1.dtb.hits 16155750 # DTB hits +system.cpu1.dtb.misses 7089 # DTB misses +system.cpu1.dtb.accesses 16162839 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1715,8 +1372,8 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 33196912 # ITB inst hits -system.cpu1.itb.inst_misses 2171 # ITB inst misses +system.cpu1.itb.inst_hits 38008437 # ITB inst hits +system.cpu1.itb.inst_misses 3017 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1725,94 +1382,95 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1276 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1485 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 33199083 # ITB inst accesses -system.cpu1.itb.hits 33196912 # DTB hits -system.cpu1.itb.misses 2171 # DTB misses -system.cpu1.itb.accesses 33199083 # DTB accesses -system.cpu1.numCycles 2390815191 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 38011454 # ITB inst accesses +system.cpu1.itb.hits 38008437 # DTB hits +system.cpu1.itb.misses 3017 # DTB misses +system.cpu1.itb.accesses 38011454 # DTB accesses +system.cpu1.numCycles 2392450295 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 32585929 # Number of instructions committed -system.cpu1.committedOps 41097454 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 37620588 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses -system.cpu1.num_func_calls 962436 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3733629 # number of instructions that are conditional controls -system.cpu1.num_int_insts 37620588 # number of integer instructions -system.cpu1.num_fp_insts 6793 # number of float instructions -system.cpu1.num_int_register_reads 218203394 # number of times the integer registers were read -system.cpu1.num_int_register_writes 39762349 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written -system.cpu1.num_mem_refs 14678716 # number of memory refs -system.cpu1.num_load_insts 8634369 # Number of load instructions -system.cpu1.num_store_insts 6044347 # Number of store instructions -system.cpu1.num_idle_cycles 1874341984.155535 # Number of idle cycles -system.cpu1.num_busy_cycles 516473206.844465 # Number of busy cycles -system.cpu1.not_idle_fraction 0.216024 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.783976 # Percentage of idle cycles -system.cpu1.Branches 4945874 # Number of branches fetched +system.cpu1.committedInsts 37097446 # Number of instructions committed +system.cpu1.committedOps 46867102 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 42687988 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 5457 # Number of float alu accesses +system.cpu1.num_func_calls 1134316 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 4357000 # number of instructions that are conditional controls +system.cpu1.num_int_insts 42687988 # number of integer instructions +system.cpu1.num_fp_insts 5457 # number of float instructions +system.cpu1.num_int_register_reads 248074220 # number of times the integer registers were read +system.cpu1.num_int_register_writes 45509439 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 3577 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1884 # number of times the floating registers were written +system.cpu1.num_mem_refs 16770062 # number of memory refs +system.cpu1.num_load_insts 9887948 # Number of load instructions +system.cpu1.num_store_insts 6882114 # Number of store instructions +system.cpu1.num_idle_cycles 1855714829.552449 # Number of idle cycles +system.cpu1.num_busy_cycles 536735465.447551 # Number of busy cycles +system.cpu1.not_idle_fraction 0.224346 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.775654 # Percentage of idle cycles +system.cpu1.Branches 5771094 # Number of branches fetched system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 44317 # number of quiesce instructions executed -system.cpu1.icache.tags.replacements 469670 # number of replacements -system.cpu1.icache.tags.tagsinuse 478.560169 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 32726726 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 470182 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 69.604379 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 94003216500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 478.560169 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.934688 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.934688 # Average percentage of cache occupancy +system.cpu1.kern.inst.quiesce 52097 # number of quiesce instructions executed +system.cpu1.icache.tags.replacements 540849 # number of replacements +system.cpu1.icache.tags.tagsinuse 478.554171 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 37467072 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 541361 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 69.209034 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 94011084500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 478.554171 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.934676 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.934676 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 448 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 63 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 244 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 203 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 33667090 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 33667090 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 32726726 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 32726726 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 32726726 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 32726726 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 32726726 # number of overall hits -system.cpu1.icache.overall_hits::total 32726726 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 470182 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 470182 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 470182 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 470182 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 470182 # number of overall misses -system.cpu1.icache.overall_misses::total 470182 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6443403725 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 6443403725 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 6443403725 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 6443403725 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 6443403725 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 6443403725 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 33196908 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 33196908 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 33196908 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 33196908 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 33196908 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 33196908 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014163 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.014163 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014163 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.014163 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014163 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.014163 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13704.062948 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13704.062948 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13704.062948 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13704.062948 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13704.062948 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13704.062948 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 38549794 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 38549794 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 37467072 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 37467072 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 37467072 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 37467072 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 37467072 # number of overall hits +system.cpu1.icache.overall_hits::total 37467072 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 541361 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 541361 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 541361 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 541361 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 541361 # number of overall misses +system.cpu1.icache.overall_misses::total 541361 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7383473218 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 7383473218 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 7383473218 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 7383473218 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 7383473218 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 7383473218 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 38008433 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 38008433 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 38008433 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 38008433 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 38008433 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 38008433 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014243 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.014243 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014243 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.014243 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014243 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.014243 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13638.723916 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13638.723916 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13638.723916 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13638.723916 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13638.723916 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13638.723916 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1821,126 +1479,127 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 470182 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 470182 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 470182 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 470182 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 470182 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 470182 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5501099275 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5501099275 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5501099275 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5501099275 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5501099275 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5501099275 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6820250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6820250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6820250 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 6820250 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014163 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014163 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014163 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.014163 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014163 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.014163 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11699.935929 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11699.935929 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11699.935929 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11699.935929 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11699.935929 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11699.935929 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 541361 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 541361 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 541361 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 541361 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 541361 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 541361 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6298814782 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 6298814782 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6298814782 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 6298814782 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6298814782 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 6298814782 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6977250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6977250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6977250 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 6977250 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014243 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014243 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014243 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.014243 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014243 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.014243 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11635.146939 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11635.146939 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11635.146939 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11635.146939 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11635.146939 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11635.146939 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 292321 # number of replacements -system.cpu1.dcache.tags.tagsinuse 471.500981 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 11963226 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 292696 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 40.872530 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 85292295250 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 471.500981 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.920900 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.920900 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 375 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 361 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.732422 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 49443351 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 49443351 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 6947316 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 6947316 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4827697 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4827697 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 82016 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 82016 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 82738 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 82738 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 11775013 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 11775013 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 11775013 # number of overall hits -system.cpu1.dcache.overall_hits::total 11775013 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 170735 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 170735 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 150073 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 150073 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11224 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 11224 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10063 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10063 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 320808 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 320808 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 320808 # number of overall misses -system.cpu1.dcache.overall_misses::total 320808 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2220021998 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2220021998 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 6568353267 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 6568353267 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 96536250 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 96536250 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 52014971 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 52014971 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 8788375265 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 8788375265 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 8788375265 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 8788375265 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 7118051 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 7118051 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 4977770 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 4977770 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 93240 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 93240 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92801 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 92801 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 12095821 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 12095821 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 12095821 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 12095821 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023986 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.023986 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030149 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.030149 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.120378 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.120378 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108436 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108436 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026522 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.026522 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026522 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.026522 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13002.735221 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 13002.735221 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 43767.721489 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 43767.721489 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8600.877584 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8600.877584 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5168.932823 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5168.932823 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 27394.501587 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 27394.501587 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 27394.501587 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 27394.501587 # average overall miss latency +system.cpu1.dcache.tags.replacements 343803 # number of replacements +system.cpu1.dcache.tags.tagsinuse 472.607785 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 13921652 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 344315 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 40.432894 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 85311468250 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.607785 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923062 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.923062 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 377 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 57519242 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 57519242 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 8078143 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 8078143 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 5612875 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 5612875 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 100617 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 100617 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 102310 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 102310 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 13691018 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 13691018 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 13691018 # number of overall hits +system.cpu1.dcache.overall_hits::total 13691018 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 207066 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 207066 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 165297 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 165297 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11987 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 11987 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 9884 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 9884 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 372363 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 372363 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 372363 # number of overall misses +system.cpu1.dcache.overall_misses::total 372363 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2696827750 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2696827750 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 6860807042 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 6860807042 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 107474000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 107474000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 50841959 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 50841959 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 9557634792 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 9557634792 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 9557634792 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 9557634792 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 8285209 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 8285209 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 5778172 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 5778172 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 112604 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 112604 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 112194 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 112194 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 14063381 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 14063381 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 14063381 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 14063381 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.024992 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.024992 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.028607 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.028607 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.106453 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.106453 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.088097 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.088097 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026477 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.026477 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026477 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.026477 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13024.000802 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13024.000802 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41505.938051 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 41505.938051 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8965.879703 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8965.879703 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5143.864731 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5143.864731 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 25667.520113 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 25667.520113 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 25667.520113 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 25667.520113 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1949,62 +1608,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 264874 # number of writebacks -system.cpu1.dcache.writebacks::total 264874 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170735 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 170735 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 150073 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 150073 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11224 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11224 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10062 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10062 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 320808 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 320808 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 320808 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 320808 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1877877002 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1877877002 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 6244849733 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 6244849733 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 74077750 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 74077750 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31889029 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31889029 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8122726735 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 8122726735 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8122726735 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 8122726735 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168606064250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168606064250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25182609871 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25182609871 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 193788674121 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 193788674121 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023986 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023986 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030149 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030149 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.120378 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.120378 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108426 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108426 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026522 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026522 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026522 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026522 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10998.781749 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10998.781749 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 41612.080341 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 41612.080341 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6599.942088 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6599.942088 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3169.253528 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3169.253528 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 25319.589084 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 25319.589084 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 25319.589084 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 25319.589084 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 315335 # number of writebacks +system.cpu1.dcache.writebacks::total 315335 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 207066 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 207066 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 165297 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 165297 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11987 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11987 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9883 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 9883 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 372363 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 372363 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 372363 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 372363 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2282040250 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2282040250 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 6506824958 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 6506824958 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 83489000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 83489000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31075041 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31075041 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8788865208 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 8788865208 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8788865208 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 8788865208 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169960243250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169960243250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25194386277 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25194386277 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 195154629527 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 195154629527 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024992 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.024992 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028607 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028607 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.106453 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.106453 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.088088 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.088088 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026477 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026477 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026477 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026477 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11020.835144 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11020.835144 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 39364.446772 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 39364.446772 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6964.962042 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6964.962042 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3144.292320 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3144.292320 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23602.949831 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23602.949831 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23602.949831 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23602.949831 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -2028,10 +1687,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 651823594501 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 651823594501 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 651823594501 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 651823594501 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 746722879500 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 746722879500 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 746722879500 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 746722879500 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 524da38ff..823848f29 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,146 +1,134 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.616552 # Number of seconds simulated -sim_ticks 2616552083000 # Number of ticks simulated -final_tick 2616552083000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.616536 # Number of seconds simulated +sim_ticks 2616536215000 # Number of ticks simulated +final_tick 2616536215000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 423166 # Simulator instruction rate (inst/s) -host_op_rate 538494 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 18392483259 # Simulator tick rate (ticks/s) -host_mem_usage 421292 # Number of bytes of host memory used -host_seconds 142.26 # Real time elapsed on the host -sim_insts 60200379 # Number of instructions simulated -sim_ops 76607188 # Number of ops (including micro ops) simulated +host_inst_rate 594955 # Simulator instruction rate (inst/s) +host_op_rate 757104 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 25859148121 # Simulator tick rate (ticks/s) +host_mem_usage 420956 # Number of bytes of host memory used +host_seconds 101.18 # Real time elapsed on the host +sim_insts 60200059 # Number of instructions simulated +sim_ops 76606878 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 703944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9089880 # Number of bytes read from this memory -system.physmem.bytes_read::total 132477664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9089816 # Number of bytes read from this memory +system.physmem.bytes_read::total 132477600 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 703944 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 703944 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3706304 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 3706240 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6722376 # Number of bytes written to this memory +system.physmem.bytes_written::total 6722312 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 17211 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142065 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15494707 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57911 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.data 142064 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15494706 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57910 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811929 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 46887426 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 811928 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46887710 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 122 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 269035 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3473992 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50630624 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 269035 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 269035 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1416484 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1152689 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2569173 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1416484 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 46887426 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 269037 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3473988 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50630906 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 269037 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 269037 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1416468 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1152696 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2569165 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1416468 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46887710 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 122 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 269035 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4626681 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53199797 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15494707 # Number of read requests accepted -system.physmem.writeReqs 811929 # Number of write requests accepted -system.physmem.readBursts 15494707 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 811929 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 991550144 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 111104 # Total number of bytes read from write queue -system.physmem.bytesWritten 6844864 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 132477664 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6722376 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1736 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 704958 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_total::cpu.inst 269037 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4626685 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53200071 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15494706 # Number of read requests accepted +system.physmem.writeReqs 811928 # Number of write requests accepted +system.physmem.readBursts 15494706 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 811928 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 991531648 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 129536 # Total number of bytes read from write queue +system.physmem.bytesWritten 6740736 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 132477600 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6722312 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 2024 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 706583 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 4515 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 967983 # Per bank write bursts +system.physmem.perBankRdBursts::0 967775 # Per bank write bursts system.physmem.perBankRdBursts::1 967715 # Per bank write bursts system.physmem.perBankRdBursts::2 967672 # Per bank write bursts -system.physmem.perBankRdBursts::3 967769 # Per bank write bursts -system.physmem.perBankRdBursts::4 974609 # Per bank write bursts -system.physmem.perBankRdBursts::5 968229 # Per bank write bursts -system.physmem.perBankRdBursts::6 967819 # Per bank write bursts -system.physmem.perBankRdBursts::7 967736 # Per bank write bursts -system.physmem.perBankRdBursts::8 968546 # Per bank write bursts +system.physmem.perBankRdBursts::3 967748 # Per bank write bursts +system.physmem.perBankRdBursts::4 974561 # Per bank write bursts +system.physmem.perBankRdBursts::5 968173 # Per bank write bursts +system.physmem.perBankRdBursts::6 967769 # Per bank write bursts +system.physmem.perBankRdBursts::7 967703 # Per bank write bursts +system.physmem.perBankRdBursts::8 968545 # Per bank write bursts system.physmem.perBankRdBursts::9 968137 # Per bank write bursts system.physmem.perBankRdBursts::10 967949 # Per bank write bursts system.physmem.perBankRdBursts::11 967746 # Per bank write bursts system.physmem.perBankRdBursts::12 967851 # Per bank write bursts system.physmem.perBankRdBursts::13 967741 # Per bank write bursts -system.physmem.perBankRdBursts::14 967672 # Per bank write bursts +system.physmem.perBankRdBursts::14 967800 # Per bank write bursts system.physmem.perBankRdBursts::15 967797 # Per bank write bursts -system.physmem.perBankWrBursts::0 6609 # Per bank write bursts -system.physmem.perBankWrBursts::1 6410 # Per bank write bursts -system.physmem.perBankWrBursts::2 6425 # Per bank write bursts -system.physmem.perBankWrBursts::3 6343 # Per bank write bursts -system.physmem.perBankWrBursts::4 6914 # Per bank write bursts -system.physmem.perBankWrBursts::5 7103 # Per bank write bursts -system.physmem.perBankWrBursts::6 6905 # Per bank write bursts -system.physmem.perBankWrBursts::7 6899 # Per bank write bursts -system.physmem.perBankWrBursts::8 7185 # Per bank write bursts -system.physmem.perBankWrBursts::9 6844 # Per bank write bursts -system.physmem.perBankWrBursts::10 6668 # Per bank write bursts -system.physmem.perBankWrBursts::11 6551 # Per bank write bursts -system.physmem.perBankWrBursts::12 6595 # Per bank write bursts -system.physmem.perBankWrBursts::13 6390 # Per bank write bursts -system.physmem.perBankWrBursts::14 6535 # Per bank write bursts -system.physmem.perBankWrBursts::15 6575 # Per bank write bursts +system.physmem.perBankWrBursts::0 6510 # Per bank write bursts +system.physmem.perBankWrBursts::1 6313 # Per bank write bursts +system.physmem.perBankWrBursts::2 6323 # Per bank write bursts +system.physmem.perBankWrBursts::3 6241 # Per bank write bursts +system.physmem.perBankWrBursts::4 6804 # Per bank write bursts +system.physmem.perBankWrBursts::5 6995 # Per bank write bursts +system.physmem.perBankWrBursts::6 6800 # Per bank write bursts +system.physmem.perBankWrBursts::7 6791 # Per bank write bursts +system.physmem.perBankWrBursts::8 7084 # Per bank write bursts +system.physmem.perBankWrBursts::9 6747 # Per bank write bursts +system.physmem.perBankWrBursts::10 6568 # Per bank write bursts +system.physmem.perBankWrBursts::11 6457 # Per bank write bursts +system.physmem.perBankWrBursts::12 6495 # Per bank write bursts +system.physmem.perBankWrBursts::13 6295 # Per bank write bursts +system.physmem.perBankWrBursts::14 6428 # Per bank write bursts +system.physmem.perBankWrBursts::15 6473 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2616547722000 # Total gap between requests +system.physmem.totGap 2616531854000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 6664 # Read request sizes (log2) system.physmem.readPktSize::3 15335424 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 152619 # Read request sizes (log2) +system.physmem.readPktSize::6 152618 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754018 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 57911 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1246677 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1099488 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1103361 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3738048 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2684438 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2678406 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2686634 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 54458 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 57693 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 20801 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 20770 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 20680 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 20429 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 20361 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 20300 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 20267 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 160 # What read queue length does an incoming req see +system.physmem.writePktSize::6 57910 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1116573 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 960474 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 961347 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 975907 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 963056 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 965451 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2812276 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2805674 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3709925 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 42008 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 34639 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 36264 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 33338 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 31474 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 22310 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 21858 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 108 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -156,563 +144,198 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4864 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4863 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4863 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4863 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4863 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4863 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 89706 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 11129.630393 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 1027.657053 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 16709.623735 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 23265 25.93% 25.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 14539 16.21% 42.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 2841 3.17% 45.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 2049 2.28% 47.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 1384 1.54% 49.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 1206 1.34% 50.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 956 1.07% 51.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 1124 1.25% 52.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 653 0.73% 53.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 549 0.61% 54.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 562 0.63% 54.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 672 0.75% 55.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 328 0.37% 55.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 247 0.28% 56.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 203 0.23% 56.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 737 0.82% 57.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 166 0.19% 57.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 154 0.17% 57.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 147 0.16% 57.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 151 0.17% 57.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 100 0.11% 58.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 2290 2.55% 60.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 108 0.12% 60.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 177 0.20% 60.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 64 0.07% 60.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 54 0.06% 61.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 47 0.05% 61.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 132 0.15% 61.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 30 0.03% 61.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 28 0.03% 61.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 20 0.02% 61.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 301 0.34% 61.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 24 0.03% 61.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 30 0.03% 61.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 15 0.02% 61.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 101 0.11% 61.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 18 0.02% 61.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 16 0.02% 61.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 24 0.03% 61.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 89 0.10% 61.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 8 0.01% 61.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 22 0.02% 62.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 13 0.01% 62.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 154 0.17% 62.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 15 0.02% 62.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 13 0.01% 62.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3015 13 0.01% 62.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 380 0.42% 62.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 14 0.02% 62.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 15 0.02% 62.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 13 0.01% 62.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 154 0.17% 62.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 16 0.02% 62.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 17 0.02% 62.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 10 0.01% 62.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 98 0.11% 63.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 14 0.02% 63.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 13 0.01% 63.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 34 0.04% 63.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 92 0.10% 63.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 11 0.01% 63.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 10 0.01% 63.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4039 9 0.01% 63.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4103 228 0.25% 63.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4167 7 0.01% 63.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 8 0.01% 63.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4295 6 0.01% 63.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4359 164 0.18% 63.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 10 0.01% 63.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 9 0.01% 63.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4551 9 0.01% 63.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 80 0.09% 63.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4679 9 0.01% 63.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4743 6 0.01% 63.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4807 8 0.01% 63.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 90 0.10% 63.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 8 0.01% 63.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4999 8 0.01% 63.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5063 9 0.01% 63.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 436 0.49% 64.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 10 0.01% 64.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5255 7 0.01% 64.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5319 8 0.01% 64.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5383 28 0.03% 64.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5447 18 0.02% 64.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 68 0.08% 64.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5575 11 0.01% 64.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 279 0.31% 64.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5703 1 0.00% 64.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5767 1 0.00% 64.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5895 70 0.08% 65.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6023 2 0.00% 65.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6151 270 0.30% 65.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6343 1 0.00% 65.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6407 20 0.02% 65.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6535 3 0.00% 65.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6599 1 0.00% 65.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6663 82 0.09% 65.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6791 3 0.00% 65.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6919 143 0.16% 65.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6983 1 0.00% 65.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7047 2 0.00% 65.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7175 411 0.46% 66.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7239 1 0.00% 66.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7431 87 0.10% 66.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7687 21 0.02% 66.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7751 1 0.00% 66.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7815 1 0.00% 66.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7943 78 0.09% 66.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8071 2 0.00% 66.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8199 402 0.45% 66.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8256-8263 2 0.00% 66.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8455 81 0.09% 66.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8711 23 0.03% 66.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8832-8839 1 0.00% 66.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8967 84 0.09% 66.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9024-9031 1 0.00% 66.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9088-9095 5 0.01% 66.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9223 405 0.45% 67.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9479 148 0.16% 67.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9735 87 0.10% 67.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9991 20 0.02% 67.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10048-10055 1 0.00% 67.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10112-10119 2 0.00% 67.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10247 273 0.30% 68.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10304-10311 1 0.00% 68.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10503 69 0.08% 68.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10624-10631 1 0.00% 68.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10759 145 0.16% 68.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10816-10823 1 0.00% 68.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11015 18 0.02% 68.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11072-11079 1 0.00% 68.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11136-11143 7 0.01% 68.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11271 431 0.48% 68.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11527 83 0.09% 68.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11783 80 0.09% 68.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12039 159 0.18% 69.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12160-12167 2 0.00% 69.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12295 208 0.23% 69.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12480-12487 3 0.00% 69.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12551 82 0.09% 69.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12807 88 0.10% 69.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12928-12935 2 0.00% 69.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12992-12999 1 0.00% 69.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13063 148 0.16% 69.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13184-13191 3 0.00% 69.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13319 354 0.39% 70.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13440-13447 2 0.00% 70.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13575 141 0.16% 70.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13632-13639 1 0.00% 70.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13831 73 0.08% 70.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14087 83 0.09% 70.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14215 3 0.00% 70.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14272-14279 1 0.00% 70.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14343 279 0.31% 70.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14400-14407 1 0.00% 70.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14464-14471 1 0.00% 70.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14599 93 0.10% 70.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14656-14663 1 0.00% 70.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14855 91 0.10% 70.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-14983 1 0.00% 70.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15111 15 0.02% 70.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15239 4 0.00% 70.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15367 490 0.55% 71.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15424-15431 1 0.00% 71.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15552-15559 1 0.00% 71.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15623 72 0.08% 71.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15744-15751 2 0.00% 71.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15879 143 0.16% 71.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16135 77 0.09% 71.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16256-16263 10 0.01% 71.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16391 534 0.60% 72.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16647 75 0.08% 72.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16704-16711 1 0.00% 72.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16768-16775 2 0.00% 72.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16903 145 0.16% 72.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17159 76 0.08% 72.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17280-17287 3 0.00% 72.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17415 492 0.55% 73.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17472-17479 1 0.00% 73.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17671 16 0.02% 73.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17856-17863 2 0.00% 73.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17927 87 0.10% 73.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18048-18055 2 0.00% 73.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18183 95 0.11% 73.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18240-18247 2 0.00% 73.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18304-18311 4 0.00% 73.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18439 275 0.31% 73.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18560-18567 1 0.00% 73.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18695 81 0.09% 73.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18944-18951 73 0.08% 74.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19072-19079 1 0.00% 74.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19207 143 0.16% 74.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19328-19335 2 0.00% 74.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19392-19399 1 0.00% 74.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19463 347 0.39% 74.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19584-19591 2 0.00% 74.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19719 136 0.15% 74.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19776-19783 1 0.00% 74.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-19975 88 0.10% 74.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20032-20039 1 0.00% 74.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20160-20167 2 0.00% 74.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20231 84 0.09% 74.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20352-20359 5 0.01% 74.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20487 216 0.24% 75.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20544-20551 1 0.00% 75.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20743 155 0.17% 75.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-20999 77 0.09% 75.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21184-21191 1 0.00% 75.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21255 79 0.09% 75.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21376-21383 5 0.01% 75.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21440-21447 1 0.00% 75.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21511 419 0.47% 76.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21632-21639 1 0.00% 76.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21696-21703 1 0.00% 76.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21767 21 0.02% 76.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21888-21895 1 0.00% 76.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22023 147 0.16% 76.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22279 72 0.08% 76.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22336-22343 1 0.00% 76.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22400-22407 4 0.00% 76.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22535 265 0.30% 76.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22791 21 0.02% 76.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23040-23047 84 0.09% 76.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23168-23175 1 0.00% 76.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23303 141 0.16% 76.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23424-23431 5 0.01% 76.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23488-23495 1 0.00% 76.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23559 410 0.46% 77.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23680-23687 1 0.00% 77.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23808-23815 87 0.10% 77.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24071 18 0.02% 77.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24327 80 0.09% 77.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24384-24391 1 0.00% 77.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24448-24455 3 0.00% 77.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24583 395 0.44% 78.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24704-24711 2 0.00% 78.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24839 76 0.08% 78.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24896-24903 1 0.00% 78.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25095 19 0.02% 78.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25280-25287 1 0.00% 78.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25344-25351 88 0.10% 78.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25472-25479 2 0.00% 78.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25607 409 0.46% 78.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25728-25735 1 0.00% 78.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25863 141 0.16% 78.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25920-25927 2 0.00% 78.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25984-25991 1 0.00% 78.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26119 88 0.10% 78.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26240-26247 1 0.00% 78.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26304-26311 1 0.00% 78.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26375 20 0.02% 78.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26496-26503 3 0.00% 78.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26631 274 0.31% 79.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26688-26695 1 0.00% 79.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26880-26887 69 0.08% 79.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27008-27015 2 0.00% 79.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27143 144 0.16% 79.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27399 23 0.03% 79.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27456-27463 1 0.00% 79.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27520-27527 1 0.00% 79.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27655 414 0.46% 79.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27776-27783 1 0.00% 79.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27911 80 0.09% 80.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28032-28039 2 0.00% 80.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28160-28167 76 0.08% 80.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28288-28295 1 0.00% 80.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28352-28359 1 0.00% 80.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28423 158 0.18% 80.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28480-28487 1 0.00% 80.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28544-28551 2 0.00% 80.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28679 213 0.24% 80.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28935 78 0.09% 80.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28992-28999 1 0.00% 80.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29191 89 0.10% 80.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29248-29255 1 0.00% 80.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29312-29319 2 0.00% 80.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29447 137 0.15% 80.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29504-29511 1 0.00% 80.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29568-29575 1 0.00% 80.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29703 346 0.39% 81.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29824-29831 1 0.00% 81.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29888-29895 2 0.00% 81.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-29959 142 0.16% 81.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30080-30087 1 0.00% 81.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30215 72 0.08% 81.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30336-30343 1 0.00% 81.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30400-30407 2 0.00% 81.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30471 82 0.09% 81.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30592-30599 4 0.00% 81.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30727 276 0.31% 81.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30784-30791 1 0.00% 81.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30848-30855 1 0.00% 81.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-30983 91 0.10% 82.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31168-31175 1 0.00% 82.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31239 88 0.10% 82.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31495 20 0.02% 82.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31616-31623 5 0.01% 82.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31680-31687 1 0.00% 82.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31751 482 0.54% 82.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32000-32007 73 0.08% 82.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32128-32135 1 0.00% 82.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32263 142 0.16% 82.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32320-32327 2 0.00% 82.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32384-32391 2 0.00% 82.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32519 83 0.09% 83.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32640-32647 1 0.00% 83.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32704-32711 1 0.00% 83.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32775 535 0.60% 83.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32832-32839 1 0.00% 83.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32896-32903 1 0.00% 83.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33031 89 0.10% 83.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33287 149 0.17% 83.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33408-33415 5 0.01% 83.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33543 76 0.08% 84.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33799 481 0.54% 84.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33856-33863 1 0.00% 84.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34048-34055 15 0.02% 84.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34304-34311 88 0.10% 84.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34368-34375 1 0.00% 84.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34432-34439 2 0.00% 84.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34560-34567 92 0.10% 84.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34624-34631 1 0.00% 84.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34688-34695 3 0.00% 84.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34823 267 0.30% 85.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34944-34951 2 0.00% 85.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35072-35079 81 0.09% 85.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35136-35143 1 0.00% 85.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35200-35207 1 0.00% 85.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35328-35335 74 0.08% 85.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35584-35591 144 0.16% 85.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35648-35655 1 0.00% 85.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35712-35719 2 0.00% 85.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35847 346 0.39% 85.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36032-36039 1 0.00% 85.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36096-36103 134 0.15% 85.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36288-36295 1 0.00% 85.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36352-36359 86 0.10% 86.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36480-36487 1 0.00% 86.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36544-36551 1 0.00% 86.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36608-36615 79 0.09% 86.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36736-36743 1 0.00% 86.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36871 207 0.23% 86.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36992-36999 2 0.00% 86.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37056-37063 1 0.00% 86.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37120-37127 154 0.17% 86.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37184-37191 1 0.00% 86.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37376-37383 75 0.08% 86.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37504-37511 2 0.00% 86.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37632-37639 87 0.10% 86.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37895 418 0.47% 87.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38016-38023 2 0.00% 87.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38080-38087 1 0.00% 87.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38144-38151 20 0.02% 87.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38208-38215 1 0.00% 87.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38400-38407 142 0.16% 87.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38528-38535 3 0.00% 87.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38656-38663 69 0.08% 87.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38848-38855 1 0.00% 87.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38912-38919 267 0.30% 87.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39040-39047 1 0.00% 87.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39168-39175 18 0.02% 87.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39232-39239 1 0.00% 87.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39296-39303 2 0.00% 87.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39424-39431 85 0.09% 87.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39552-39559 1 0.00% 87.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39616-39623 2 0.00% 87.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39680-39687 145 0.16% 88.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39936-39943 411 0.46% 88.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40192-40199 83 0.09% 88.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40256-40263 1 0.00% 88.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40320-40327 2 0.00% 88.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40448-40455 16 0.02% 88.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40576-40583 3 0.00% 88.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40640-40647 1 0.00% 88.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40704-40711 79 0.09% 88.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-40967 395 0.44% 89.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41152-41159 1 0.00% 89.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41216-41223 77 0.09% 89.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41344-41351 1 0.00% 89.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41472-41479 17 0.02% 89.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41600-41607 3 0.00% 89.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41728-41735 89 0.10% 89.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-41991 405 0.45% 89.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42048-42055 1 0.00% 89.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42112-42119 2 0.00% 89.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42240-42247 142 0.16% 89.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42368-42375 1 0.00% 89.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42496-42503 82 0.09% 90.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42624-42631 4 0.00% 90.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42752-42759 22 0.02% 90.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43015 265 0.30% 90.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43136-43143 1 0.00% 90.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43200-43207 1 0.00% 90.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43264-43271 69 0.08% 90.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43520-43527 144 0.16% 90.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43648-43655 4 0.00% 90.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43776-43783 21 0.02% 90.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43840-43847 1 0.00% 90.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44032-44039 417 0.46% 91.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44096-44103 1 0.00% 91.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44160-44167 1 0.00% 91.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44288-44295 79 0.09% 91.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44544-44551 77 0.09% 91.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44672-44679 4 0.00% 91.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44800-44807 154 0.17% 91.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45056-45063 203 0.23% 91.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45184-45191 1 0.00% 91.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45312-45319 82 0.09% 91.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45440-45447 1 0.00% 91.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45504-45511 1 0.00% 91.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45568-45575 88 0.10% 91.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45696-45703 2 0.00% 91.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45760-45767 1 0.00% 91.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45824-45831 135 0.15% 92.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45952-45959 2 0.00% 92.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46087 348 0.39% 92.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46336-46343 145 0.16% 92.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46592-46599 73 0.08% 92.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46720-46727 2 0.00% 92.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46848-46855 84 0.09% 92.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46976-46983 3 0.00% 92.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47104-47111 268 0.30% 93.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47232-47239 2 0.00% 93.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47296-47303 1 0.00% 93.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47367 92 0.10% 93.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47424-47431 1 0.00% 93.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47623 87 0.10% 93.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47680-47687 1 0.00% 93.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47744-47751 4 0.00% 93.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47872-47879 19 0.02% 93.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48064-48071 1 0.00% 93.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48135 511 0.57% 93.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48192-48199 2 0.00% 93.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48256-48263 1 0.00% 93.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48320-48327 2 0.00% 93.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48391 90 0.10% 94.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48640-48647 140 0.16% 94.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48768-48775 73 0.08% 94.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48903 73 0.08% 94.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48960-48967 6 0.01% 94.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49024-49031 6 0.01% 94.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49088-49095 7 0.01% 94.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49159 5078 5.66% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 89706 # Bytes accessed per row activation -system.physmem.totQLat 373696644500 # Total ticks spent queuing -system.physmem.totMemAccLat 469604897000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 77464855000 # Total ticks spent in databus transfers -system.physmem.totBankLat 18443397500 # Total ticks spent accessing banks -system.physmem.avgQLat 24120.40 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1190.44 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2541 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4807 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4786 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4793 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4827 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4839 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5981 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4975 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5804 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4869 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4878 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4878 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4793 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1099 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1078 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1070 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1076 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1063 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1063 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1060 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1060 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1060 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1060 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1060 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1060 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1060 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1060 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1060 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1059 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1059 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1059 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1059 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1058 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1058 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 977394 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 1014.625651 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 1002.644045 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 87.222028 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 3543 0.36% 0.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 3286 0.34% 0.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 1787 0.18% 0.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1165 0.12% 1.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 902 0.09% 1.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 711 0.07% 1.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 580 0.06% 1.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 432 0.04% 1.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 964988 98.73% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 977394 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4784 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 3238.435619 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 134294.504205 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-524287 4779 99.90% 99.90% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::524288-1.04858e+06 3 0.06% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1.04858e+06-1.57286e+06 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::8.9129e+06-9.43718e+06 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 4784 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4784 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.015886 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.524536 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 9.242033 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2224 46.49% 46.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 36 0.75% 47.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 227 4.74% 51.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1224 25.59% 77.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 8 0.17% 77.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 4 0.08% 77.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 1 0.02% 77.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 1 0.02% 77.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34 1 0.02% 77.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::39 945 19.75% 97.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40 67 1.40% 99.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::41 15 0.31% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42 31 0.65% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4784 # Writes before turning the bus around for reads +system.physmem.totQLat 588095657500 # Total ticks spent queuing +system.physmem.totMemAccLat 694960871250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 77463410000 # Total ticks spent in databus transfers +system.physmem.totBankLat 29401803750 # Total ticks spent accessing banks +system.physmem.avgQLat 37959.58 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1897.79 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30310.84 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 44857.36 # Average memory access latency per DRAM burst system.physmem.avgRdBW 378.95 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.62 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 2.58 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 50.63 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.57 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.98 # Data bus utilization in percentage system.physmem.busUtilRead 2.96 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing -system.physmem.avgWrQLen 14.55 # Average write queue length when enqueuing -system.physmem.readRowHits 15419069 # Number of row buffer hits during reads -system.physmem.writeRowHits 91147 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 85.21 # Row buffer hit rate for writes -system.physmem.avgGap 160459.07 # Average gap between requests -system.physmem.pageHitRate 99.42 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 2.19 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 54116372 # Throughput (bytes/s) +system.physmem.avgRdQLen 7.03 # Average read queue length when enqueuing +system.physmem.avgWrQLen 29.46 # Average write queue length when enqueuing +system.physmem.readRowHits 14490606 # Number of row buffer hits during reads +system.physmem.writeRowHits 90101 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.53 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 85.53 # Row buffer hit rate for writes +system.physmem.avgGap 160458.12 # Average gap between requests +system.physmem.pageHitRate 93.48 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 3.85 # Percentage of time for which DRAM has all the banks in precharge state +system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 54116651 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 16546597 # Transaction distribution system.membus.trans_dist::ReadResp 16546597 # Transaction distribution system.membus.trans_dist::WriteReq 763385 # Transaction distribution system.membus.trans_dist::WriteResp 763385 # Transaction distribution -system.membus.trans_dist::Writeback 57911 # Transaction distribution +system.membus.trans_dist::Writeback 57910 # Transaction distribution system.membus.trans_dist::UpgradeReq 4515 # Transaction distribution system.membus.trans_dist::UpgradeResp 4515 # Transaction distribution -system.membus.trans_dist::ReadExReq 132218 # Transaction distribution -system.membus.trans_dist::ReadExResp 132218 # Transaction distribution +system.membus.trans_dist::ReadExReq 132217 # Transaction distribution +system.membus.trans_dist::ReadExResp 132217 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383088 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3850 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1893543 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4280493 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1893540 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4280490 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30670848 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30670848 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34951341 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 34951338 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390542 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7700 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16516648 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 18914914 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16516520 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 18914786 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 122683392 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 122683392 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 141598306 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 141598306 # Total data (bytes) +system.membus.tot_pkt_size::total 141598178 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 141598178 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1206226000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1206225000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3614000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3615000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17910626500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17911294000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4950468826 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4951349139 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 34635984750 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 1.3 # Layer utilization (%) +system.membus.respLayer2.occupancy 38238689000 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 1.5 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 47801049 # Throughput (bytes/s) +system.iobus.throughput 47801339 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 16518785 # Transaction distribution system.iobus.trans_dist::ReadResp 16518785 # Transaction distribution system.iobus.trans_dist::WriteReq 8183 # Transaction distribution @@ -822,8 +445,8 @@ system.iobus.reqLayer25.occupancy 15335424000 # La system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) system.iobus.respLayer0.occupancy 2374905000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42035727250 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) +system.iobus.respLayer1.occupancy 38265059000 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -848,25 +471,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 14996193 # DTB read hits -system.cpu.dtb.read_misses 7334 # DTB read misses -system.cpu.dtb.write_hits 11230326 # DTB write hits -system.cpu.dtb.write_misses 2212 # DTB write misses +system.cpu.dtb.read_hits 14996179 # DTB read hits +system.cpu.dtb.read_misses 7337 # DTB read misses +system.cpu.dtb.write_hits 11230334 # DTB write hits +system.cpu.dtb.write_misses 2213 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3405 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 3411 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 192 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 194 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 15003527 # DTB read accesses -system.cpu.dtb.write_accesses 11232538 # DTB write accesses +system.cpu.dtb.read_accesses 15003516 # DTB read accesses +system.cpu.dtb.write_accesses 11232547 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 26226519 # DTB hits -system.cpu.dtb.misses 9546 # DTB misses -system.cpu.dtb.accesses 26236065 # DTB accesses +system.cpu.dtb.hits 26226513 # DTB hits +system.cpu.dtb.misses 9550 # DTB misses +system.cpu.dtb.accesses 26236063 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -888,7 +511,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 61494253 # ITB inst hits +system.cpu.itb.inst_hits 61493932 # ITB inst hits system.cpu.itb.inst_misses 4471 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -905,88 +528,88 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 61498724 # ITB inst accesses -system.cpu.itb.hits 61494253 # DTB hits +system.cpu.itb.inst_accesses 61498403 # ITB inst accesses +system.cpu.itb.hits 61493932 # DTB hits system.cpu.itb.misses 4471 # DTB misses -system.cpu.itb.accesses 61498724 # DTB accesses -system.cpu.numCycles 5233104166 # number of cpu cycles simulated +system.cpu.itb.accesses 61498403 # DTB accesses +system.cpu.numCycles 5233072430 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60200379 # Number of instructions committed -system.cpu.committedOps 76607188 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 69208982 # Number of integer alu accesses +system.cpu.committedInsts 60200059 # Number of instructions committed +system.cpu.committedOps 76606878 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 69208659 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses -system.cpu.num_func_calls 2140473 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7948700 # number of instructions that are conditional controls -system.cpu.num_int_insts 69208982 # number of integer instructions +system.cpu.num_func_calls 2140468 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7948676 # number of instructions that are conditional controls +system.cpu.num_int_insts 69208659 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions -system.cpu.num_int_register_reads 401369988 # number of times the integer registers were read -system.cpu.num_int_register_writes 74519463 # number of times the integer registers were written +system.cpu.num_int_register_reads 401368432 # number of times the integer registers were read +system.cpu.num_int_register_writes 74518953 # number of times the integer registers were written system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written -system.cpu.num_mem_refs 27394064 # number of memory refs -system.cpu.num_load_insts 15660288 # Number of load instructions -system.cpu.num_store_insts 11733776 # Number of store instructions -system.cpu.num_idle_cycles 4581523252.608249 # Number of idle cycles -system.cpu.num_busy_cycles 651580913.391751 # Number of busy cycles -system.cpu.not_idle_fraction 0.124511 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.875489 # Percentage of idle cycles -system.cpu.Branches 10308817 # Number of branches fetched +system.cpu.num_mem_refs 27394027 # number of memory refs +system.cpu.num_load_insts 15660244 # Number of load instructions +system.cpu.num_store_insts 11733783 # Number of store instructions +system.cpu.num_idle_cycles 4581664281.608249 # Number of idle cycles +system.cpu.num_busy_cycles 651408148.391751 # Number of busy cycles +system.cpu.not_idle_fraction 0.124479 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.875521 # Percentage of idle cycles +system.cpu.Branches 10308791 # Number of branches fetched system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 83016 # number of quiesce instructions executed -system.cpu.icache.tags.replacements 856260 # number of replacements -system.cpu.icache.tags.tagsinuse 510.867590 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 60637481 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 856772 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 70.774350 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 19998571250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.867590 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997788 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997788 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 856277 # number of replacements +system.cpu.icache.tags.tagsinuse 510.865256 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 60637143 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 856789 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 70.772551 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 20019652250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.865256 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997784 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997784 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 267 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 62351025 # Number of tag accesses -system.cpu.icache.tags.data_accesses 62351025 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 60637481 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 60637481 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 60637481 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 60637481 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 60637481 # number of overall hits -system.cpu.icache.overall_hits::total 60637481 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 856772 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 856772 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 856772 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 856772 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 856772 # number of overall misses -system.cpu.icache.overall_misses::total 856772 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11774299750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11774299750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11774299750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11774299750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11774299750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11774299750 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 61494253 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 61494253 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 61494253 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 61494253 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 61494253 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 61494253 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 62350721 # Number of tag accesses +system.cpu.icache.tags.data_accesses 62350721 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 60637143 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 60637143 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 60637143 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 60637143 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 60637143 # number of overall hits +system.cpu.icache.overall_hits::total 60637143 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 856789 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 856789 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 856789 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 856789 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 856789 # number of overall misses +system.cpu.icache.overall_misses::total 856789 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11768796500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11768796500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11768796500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11768796500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11768796500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11768796500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 61493932 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 61493932 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 61493932 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 61493932 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 61493932 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 61493932 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013933 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.013933 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.013933 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.013933 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.013933 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.013933 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13742.629019 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13742.629019 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13742.629019 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13742.629019 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13742.629019 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13742.629019 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13735.933234 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13735.933234 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13735.933234 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13735.933234 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13735.933234 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13735.933234 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -995,186 +618,186 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856772 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 856772 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 856772 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 856772 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 856772 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 856772 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10056704250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 10056704250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10056704250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 10056704250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10056704250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 10056704250 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 435943750 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 435943750 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 435943750 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 435943750 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856789 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 856789 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 856789 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 856789 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 856789 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 856789 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10051259500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 10051259500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10051259500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 10051259500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10051259500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 10051259500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 442799750 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 442799750 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 442799750 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 442799750 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013933 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.013933 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.013933 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11737.900223 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11737.900223 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11737.900223 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11737.900223 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11737.900223 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11737.900223 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11731.312494 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11731.312494 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11731.312494 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11731.312494 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11731.312494 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11731.312494 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 62511 # number of replacements -system.cpu.l2cache.tags.tagsinuse 50754.773862 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1682280 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 127893 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 13.153808 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 2565659385000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 37718.578019 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.884348 # Average occupied blocks per requestor +system.cpu.l2cache.tags.replacements 62510 # number of replacements +system.cpu.l2cache.tags.tagsinuse 50754.341814 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1682268 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 127892 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 13.153817 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 2565667436000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 37718.224228 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.884316 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000703 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 6993.361988 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 6038.948805 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.575540 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 6993.295627 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 6038.936941 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.575534 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.106710 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.106709 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.092147 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.774456 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.774450 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_blocks::1024 65378 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2163 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6898 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56267 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2162 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6903 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56263 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997589 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 17137404 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 17137404 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8705 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3532 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 844551 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 369636 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1226424 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 595238 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 595238 # number of Writeback hits +system.cpu.l2cache.tags.tag_accesses 17138143 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 17138143 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8709 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3533 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 844568 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 369661 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1226471 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 595273 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 595273 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 113388 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 113388 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 8705 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 3532 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 844551 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 483024 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1339812 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 8705 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 3532 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 844551 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 483024 # number of overall hits -system.cpu.l2cache.overall_hits::total 1339812 # number of overall hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 113398 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 113398 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 8709 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 3533 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 844568 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 483059 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1339869 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 8709 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 3533 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 844568 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 483059 # number of overall hits +system.cpu.l2cache.overall_hits::total 1339869 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.inst 10585 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 9809 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 20401 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 2908 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2908 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 133825 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133825 # number of ReadExReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 2905 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 2905 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 133827 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 133827 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.inst 10585 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 143634 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 154226 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 143636 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 154228 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 5 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses system.cpu.l2cache.overall_misses::cpu.inst 10585 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 143634 # number of overall misses -system.cpu.l2cache.overall_misses::total 154226 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 305250 # number of ReadReq miss cycles +system.cpu.l2cache.overall_misses::cpu.data 143636 # number of overall misses +system.cpu.l2cache.overall_misses::total 154228 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 397250 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 150000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 752786250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 737923500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1491165000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 747154500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 739313250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1487015000 # number of ReadReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 469980 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 469980 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9621111643 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 9621111643 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 305250 # number of demand (read+write) miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9526600640 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 9526600640 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 397250 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 150000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 752786250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10359035143 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 11112276643 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 305250 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 747154500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10265913890 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 11013615640 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 397250 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 150000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 752786250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10359035143 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 11112276643 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8710 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3534 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 855136 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 379445 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1246825 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 595238 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 595238 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2934 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2934 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 247213 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 247213 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 8710 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 3534 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 855136 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 626658 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1494038 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 8710 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 3534 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 855136 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 626658 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1494038 # number of overall (read+write) accesses +system.cpu.l2cache.overall_miss_latency::cpu.inst 747154500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10265913890 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 11013615640 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8714 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3535 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 855153 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 379470 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1246872 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 595273 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 595273 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2931 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2931 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 247225 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 247225 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 8714 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 3535 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 855153 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 626695 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1494097 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 8714 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 3535 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 855153 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 626695 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1494097 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000574 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000566 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012378 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025851 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025849 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.016362 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991138 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991138 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541335 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.541335 # miss rate for ReadExReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991129 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991129 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541317 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.541317 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000574 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000566 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012378 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.229206 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.103228 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.229196 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.103225 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000574 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000566 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012378 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.229206 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.103228 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 61050 # average ReadReq miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.229196 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.103225 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 79450 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 75000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71118.209731 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75229.228260 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 73092.740552 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 161.616231 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 161.616231 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71893.231033 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71893.231033 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 61050 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70586.159660 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75370.909369 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 72889.319151 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 161.783133 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 161.783133 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71185.938861 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71185.938861 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 79450 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 75000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71118.209731 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72121.051722 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72051.902033 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 61050 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70586.159660 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71471.733340 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71411.258915 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 79450 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 75000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71118.209731 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72121.051722 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72051.902033 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70586.159660 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71471.733340 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71411.258915 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1183,92 +806,92 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 57911 # number of writebacks -system.cpu.l2cache.writebacks::total 57911 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 57910 # number of writebacks +system.cpu.l2cache.writebacks::total 57910 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 5 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10585 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 9809 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 20401 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2908 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 2908 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133825 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 133825 # number of ReadExReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2905 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 2905 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133827 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 133827 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 5 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 10585 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 143634 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 154226 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 143636 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 154228 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 5 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 10585 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 143634 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 154226 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 242750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 143636 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 154228 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 335750 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 125000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 620216750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 615039000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1235623500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29085908 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29085908 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7946453357 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7946453357 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 242750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 614626500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 616437250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1231524500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29056905 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29056905 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7852026860 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7852026860 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 335750 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 125000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 620216750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8561492357 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9182076857 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 242750 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 614626500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8468464110 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9083551360 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 335750 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 125000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 620216750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8561492357 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9182076857 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 344358750 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166664193250 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167008552000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 16706218159 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 16706218159 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 344358750 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 183370411409 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 183714770159 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 614626500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8468464110 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9083551360 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 351469750 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166664489250 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167015959000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 16706272596 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 16706272596 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 351469750 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 183370761846 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 183722231596 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000566 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012378 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025851 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025849 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016362 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991138 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991138 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541335 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541335 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991129 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991129 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541317 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541317 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000566 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012378 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229206 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.103228 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229196 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.103225 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000566 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012378 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229206 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.103228 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average ReadReq mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229196 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.103225 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 67150 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58593.930090 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62701.498624 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60566.810450 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.031637 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.031637 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59379.438498 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59379.438498 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58065.800661 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62844.046284 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60365.888927 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.376936 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.376936 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58672.964798 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58672.964798 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 67150 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58593.930090 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59606.307399 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59536.503942 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58065.800661 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58957.810786 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58896.901730 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 67150 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58593.930090 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59606.307399 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59536.503942 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58065.800661 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58957.810786 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58896.901730 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1278,86 +901,87 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 626146 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.876591 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 23656108 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 626658 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37.749631 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 664772250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.876591 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999759 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999759 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 626183 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.875243 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 23656065 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 626695 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37.747333 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 671680250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.875243 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999756 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999756 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 109 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 108 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 97757722 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 97757722 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 13196248 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13196248 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 9972755 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 9972755 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 236393 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 236393 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 97757735 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 97757735 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 13196205 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13196205 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 9972754 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 9972754 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 236397 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 236397 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 247778 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 247778 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 23169003 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 23169003 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 23169003 # number of overall hits -system.cpu.dcache.overall_hits::total 23169003 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 368059 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 368059 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 250147 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 250147 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 11386 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 11386 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 618206 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 618206 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 618206 # number of overall misses -system.cpu.dcache.overall_misses::total 618206 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5416606500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5416606500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 11623055265 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 11623055265 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 158362000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 158362000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 17039661765 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17039661765 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 17039661765 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17039661765 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13564307 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13564307 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10222902 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10222902 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 23168959 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 23168959 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 23168959 # number of overall hits +system.cpu.dcache.overall_hits::total 23168959 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 368088 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 368088 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 250156 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 250156 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 11382 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 11382 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 618244 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 618244 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 618244 # number of overall misses +system.cpu.dcache.overall_misses::total 618244 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5418733500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5418733500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 11526229765 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 11526229765 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 157891250 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 157891250 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 16944963265 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16944963265 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 16944963265 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16944963265 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13564293 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13564293 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10222910 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10222910 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247779 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 247779 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 247778 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 247778 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 23787209 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 23787209 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 23787209 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 23787209 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027134 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.027134 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024469 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.024469 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045952 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045952 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025989 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025989 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.025989 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.025989 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14716.679934 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14716.679934 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46464.899699 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 46464.899699 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13908.484103 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13908.484103 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 27563.080535 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 27563.080535 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 27563.080535 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 27563.080535 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 23787203 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 23787203 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 23787203 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 23787203 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027137 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.027137 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024470 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.024470 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045936 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045936 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.025991 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025991 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.025991 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.025991 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14721.298983 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14721.298983 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46076.167531 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 46076.167531 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13872.012827 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13872.012827 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 27408.213044 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 27408.213044 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 27408.213044 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 27408.213044 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1366,54 +990,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 595238 # number of writebacks -system.cpu.dcache.writebacks::total 595238 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368059 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 368059 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250147 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 250147 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11386 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 11386 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 618206 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 618206 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 618206 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 618206 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4678192500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4678192500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11070820735 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11070820735 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 135536000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 135536000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15749013235 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 15749013235 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15749013235 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 15749013235 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182058328250 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182058328250 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26237936841 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26237936841 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208296265091 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 208296265091 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027134 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027134 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024469 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024469 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.045952 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.045952 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025989 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025989 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025989 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025989 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12710.441804 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12710.441804 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44257.259671 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44257.259671 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11903.741437 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11903.741437 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25475.348403 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25475.348403 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25475.348403 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 25475.348403 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 595273 # number of writebacks +system.cpu.dcache.writebacks::total 595273 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368088 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 368088 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250156 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 250156 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11382 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 11382 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 618244 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 618244 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 618244 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 618244 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4680319500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4680319500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10976351235 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10976351235 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 135073750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 135073750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15656670735 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15656670735 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15656670735 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15656670735 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182058625250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182058625250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26242395404 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26242395404 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208301020654 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 208301020654 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027137 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027137 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024470 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024470 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.045936 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.045936 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025991 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025991 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025991 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025991 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12715.218915 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12715.218915 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43878.025052 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43878.025052 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11867.312423 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11867.312423 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25324.420027 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25324.420027 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25324.420027 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25324.420027 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1421,37 +1045,37 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 52965248 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2454635 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2454635 # Transaction distribution +system.cpu.toL2Bus.throughput 52967752 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2454681 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2454681 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 763385 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 763385 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 595238 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2934 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2934 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 247213 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 247213 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1725170 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5749474 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12460 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27430 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7514534 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54755228 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 83615814 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14136 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 34840 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 138420018 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 138420018 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 166312 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3008633500 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::Writeback 595273 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2931 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2931 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 247225 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 247225 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1725204 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5749577 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12461 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27438 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7514680 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54756316 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 83620422 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14140 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 34856 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 138425734 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 138425734 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 166308 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3008713250 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1295454000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1295332250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2534439174 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2533285861 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer2.occupancy 8926000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 18720500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 18724250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use @@ -1469,10 +1093,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1538398399250 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1538398399250 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1538398399250 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1538398399250 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1763840630000 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1763840630000 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1763840630000 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1763840630000 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency |