diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-03 07:42:59 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-03 07:42:59 -0400 |
| commit | a217eba078b17c51f6a74c9237584f066ef78bf1 (patch) | |
| tree | e566cbeb3520341dbdf6ecb0d3932a31d4e156fe /tests/quick/fs/10.linux-boot/ref/arm | |
| parent | db430698bfd4d77a49e11031bb65444552891f37 (diff) | |
| download | gem5-a217eba078b17c51f6a74c9237584f066ef78bf1.tar.xz | |
stats: Update stats for CPU and cache changes
This patch updates the stats to reflect the fixes and changes to the
CPU (mainly the o3), and the caches.
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm')
5 files changed, 3429 insertions, 3318 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index 547f88656..df149be6e 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -1,73 +1,69 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.912098 # Number of seconds simulated -sim_ticks 912098398000 # Number of ticks simulated -final_tick 912098398000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.900855 # Number of seconds simulated +sim_ticks 900854787500 # Number of ticks simulated +final_tick 900854787500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1024713 # Simulator instruction rate (inst/s) -host_op_rate 1319299 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 15163617701 # Simulator tick rate (ticks/s) -host_mem_usage 465872 # Number of bytes of host memory used -host_seconds 60.15 # Real time elapsed on the host -sim_insts 61636937 # Number of instructions simulated -sim_ops 79356422 # Number of ops (including micro ops) simulated +host_inst_rate 875862 # Simulator instruction rate (inst/s) +host_op_rate 1055198 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 12821864647 # Simulator tick rate (ticks/s) +host_mem_usage 433912 # Number of bytes of host memory used +host_seconds 70.26 # Real time elapsed on the host +sim_insts 61537412 # Number of instructions simulated +sim_ops 74137396 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 502220 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 6235260 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 214596 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 3364600 # Number of bytes read from this memory -system.physmem.bytes_read::total 49638724 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 502220 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 214596 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 716816 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4195904 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 3010088 # Number of bytes written to this memory -system.physmem.bytes_written::total 7222992 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 460108 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 6580092 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 258564 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2992120 # Number of bytes read from this memory +system.physmem.bytes_read::total 49612932 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 460108 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 258564 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 718672 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4174784 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 3027048 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory +system.physmem.bytes_written::total 7201872 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 4915200 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 14075 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 97500 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 3444 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 52600 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5082826 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 65561 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 752522 # Number of write requests responded to by this memory -system.physmem.num_writes::total 822333 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43111138 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 70 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 211 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 550620 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 6836170 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 211 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 235277 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 3688856 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 54422554 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 550620 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 235277 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 785898 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4600276 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 18638 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 3300179 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 7919093 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4600276 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43111138 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 70 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 211 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 550620 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 6854809 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 211 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 235277 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 6989035 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 62341647 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu0.inst 13417 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 102873 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 4131 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 46770 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5082398 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 65231 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 756762 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory +system.physmem.num_writes::total 822003 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43649210 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 284 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 213 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 510746 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 7304276 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 287021 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 3321423 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 55073173 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 510746 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 287021 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 797767 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4634247 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 3360195 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 44 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 7994487 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4634247 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43649210 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 284 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 213 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 510746 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 10664471 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 287021 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 3321468 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 63067661 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -86,188 +82,180 @@ system.realview.nvmem.bw_inst_read::total 75 # I system.realview.nvmem.bw_total::cpu0.inst 22 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 53 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 75 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 64987015 # Throughput (bytes/s) -system.membus.data_through_bus 59274552 # Total data (bytes) +system.membus.throughput 65740815 # Throughput (bytes/s) +system.membus.data_through_bus 59222928 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 70660 # number of replacements -system.l2c.tags.tagsinuse 51560.418077 # Cycle average of tags in use -system.l2c.tags.total_refs 1623334 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 135812 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 11.952802 # Average number of references to valid blocks. +system.l2c.tags.replacements 70256 # number of replacements +system.l2c.tags.tagsinuse 51491.506872 # Cycle average of tags in use +system.l2c.tags.total_refs 1633923 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 135467 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 12.061410 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 39278.982234 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000049 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001109 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4358.948754 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2482.442784 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.678936 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2126.447479 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3310.916734 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.599350 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 39155.338647 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.673377 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001056 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4830.605577 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 5154.208952 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1696.649192 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 652.030072 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.597463 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000041 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.066512 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.037879 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000041 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.032447 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.050521 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.786750 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.073709 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.078647 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.025889 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.009949 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.785698 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65148 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65207 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3771 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 12549 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 48575 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 259 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3953 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 12685 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 48286 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.994080 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 16908072 # Number of tag accesses -system.l2c.tags.data_accesses 16908072 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 3874 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 1919 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 421038 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 175187 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 5331 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1734 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 430511 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 169510 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1209104 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 567806 # number of Writeback hits -system.l2c.Writeback_hits::total 567806 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 611 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 663 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1274 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 137 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 31 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 168 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 58145 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 50213 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 108358 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 3874 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 1919 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 421038 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 233332 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 5331 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 1734 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 430511 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 219723 # number of demand (read+write) hits -system.l2c.demand_hits::total 1317462 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 3874 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 1919 # number of overall hits -system.l2c.overall_hits::cpu0.inst 421038 # number of overall hits -system.l2c.overall_hits::cpu0.data 233332 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 5331 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 1734 # number of overall hits -system.l2c.overall_hits::cpu1.inst 430511 # number of overall hits -system.l2c.overall_hits::cpu1.data 219723 # number of overall hits -system.l2c.overall_hits::total 1317462 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses +system.l2c.tags.occ_task_id_percent::1024 0.994980 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 16963603 # Number of tag accesses +system.l2c.tags.data_accesses 16963603 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 4298 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 1596 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 413244 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 202837 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 4578 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 1943 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 438543 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 146503 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1213542 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 571726 # number of Writeback hits +system.l2c.Writeback_hits::total 571726 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 1266 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 397 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1663 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 238 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 38 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 276 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 51499 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 57148 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 108647 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 4298 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 1596 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 413244 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 254336 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 4578 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 1943 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 438543 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 203651 # number of demand (read+write) hits +system.l2c.demand_hits::total 1322189 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 4298 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 1596 # number of overall hits +system.l2c.overall_hits::cpu0.inst 413244 # number of overall hits +system.l2c.overall_hits::cpu0.data 254336 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 4578 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 1943 # number of overall hits +system.l2c.overall_hits::cpu1.inst 438543 # number of overall hits +system.l2c.overall_hits::cpu1.data 203651 # number of overall hits +system.l2c.overall_hits::total 1322189 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 4 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 7432 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6392 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 3 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 3347 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 5276 # number of ReadReq misses -system.l2c.ReadReq_misses::total 22454 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 4941 # 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miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.016128 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.045635 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.009115 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.012324 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.018078 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.696548 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.926888 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.826807 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.634969 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.945714 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.795858 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.646118 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.448730 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.564003 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000930 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.001876 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.016128 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.289687 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.009115 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.191851 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.109683 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000930 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.001876 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.016128 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.289687 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.009115 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.191851 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.109683 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -276,8 +264,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 65561 # number of writebacks -system.l2c.writebacks::total 65561 # number of writebacks +system.l2c.writebacks::writebacks 65231 # number of writebacks +system.l2c.writebacks::total 65231 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -285,11 +273,11 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 154019817 # Throughput (bytes/s) -system.toL2Bus.data_through_bus 140481228 # Total data (bytes) +system.toL2Bus.throughput 156214740 # Throughput (bytes/s) +system.toL2Bus.data_through_bus 140726796 # Total data (bytes) system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.iobus.throughput 45731035 # Throughput (bytes/s) -system.iobus.data_through_bus 41711204 # Total data (bytes) +system.iobus.throughput 46301771 # Throughput (bytes/s) +system.iobus.data_through_bus 41711172 # Total data (bytes) system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -313,25 +301,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7977762 # DTB read hits -system.cpu0.dtb.read_misses 3611 # DTB read misses -system.cpu0.dtb.write_hits 5967140 # DTB write hits -system.cpu0.dtb.write_misses 672 # DTB write misses +system.cpu0.dtb.read_hits 7391669 # DTB read hits +system.cpu0.dtb.read_misses 1915 # DTB read misses +system.cpu0.dtb.write_hits 6659638 # DTB write hits +system.cpu0.dtb.write_misses 1130 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1905 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 1223 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 135 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 84 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7981373 # DTB read accesses -system.cpu0.dtb.write_accesses 5967812 # DTB write accesses +system.cpu0.dtb.perms_faults 185 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 7393584 # DTB read accesses +system.cpu0.dtb.write_accesses 6660768 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 13944902 # DTB hits -system.cpu0.dtb.misses 4283 # DTB misses -system.cpu0.dtb.accesses 13949185 # DTB accesses +system.cpu0.dtb.hits 14051307 # DTB hits +system.cpu0.dtb.misses 3045 # DTB misses +system.cpu0.dtb.accesses 14054352 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -353,8 +341,8 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 30248608 # ITB inst hits -system.cpu0.itb.inst_misses 2175 # ITB inst misses +system.cpu0.itb.inst_hits 37936012 # ITB inst hits +system.cpu0.itb.inst_misses 1207 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -363,116 +351,118 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1280 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 848 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 30250783 # ITB inst accesses -system.cpu0.itb.hits 30248608 # DTB hits -system.cpu0.itb.misses 2175 # DTB misses -system.cpu0.itb.accesses 30250783 # DTB accesses -system.cpu0.numCycles 1823674676 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 37937219 # ITB inst accesses +system.cpu0.itb.hits 37936012 # DTB hits +system.cpu0.itb.misses 1207 # DTB misses +system.cpu0.itb.accesses 37937219 # DTB accesses +system.cpu0.numCycles 1801227301 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 29759626 # Number of instructions committed -system.cpu0.committedOps 39141026 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 34755088 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5449 # Number of float alu accesses -system.cpu0.num_func_calls 1242746 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4045769 # number of instructions that are conditional controls -system.cpu0.num_int_insts 34755088 # number of integer instructions -system.cpu0.num_fp_insts 5449 # number of float instructions -system.cpu0.num_int_register_reads 179913159 # number of times the integer registers were read -system.cpu0.num_int_register_writes 36837171 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 4535 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 916 # number of times the floating registers were written -system.cpu0.num_mem_refs 14629859 # number of memory refs -system.cpu0.num_load_insts 8359235 # Number of load instructions -system.cpu0.num_store_insts 6270624 # Number of store instructions -system.cpu0.num_idle_cycles 1783997876.499954 # Number of idle cycles -system.cpu0.num_busy_cycles 39676799.500046 # Number of busy cycles -system.cpu0.not_idle_fraction 0.021757 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.978243 # Percentage of idle cycles -system.cpu0.Branches 5492144 # Number of branches fetched -system.cpu0.op_class::No_OpClass 16326 0.04% 0.04% # Class of executed instruction -system.cpu0.op_class::IntAlu 24520115 62.53% 62.57% # Class of executed instruction -system.cpu0.op_class::IntMult 45259 0.12% 62.69% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 62.69% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 62.69% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 62.69% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 62.69% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 62.69% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 62.69% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 62.69% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 62.69% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 62.69% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 62.69% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 62.69% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 62.69% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 62.69% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 62.69% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 62.69% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 62.69% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 62.69% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 62.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 62.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 62.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 62.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 62.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 62.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 1421 0.00% 62.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 62.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 62.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 62.69% # Class of executed instruction -system.cpu0.op_class::MemRead 8359235 21.32% 84.01% # Class of executed instruction -system.cpu0.op_class::MemWrite 6270624 15.99% 100.00% # Class of executed instruction +system.cpu0.committedInsts 37698803 # Number of instructions committed +system.cpu0.committedOps 44946380 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 39863943 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 4171 # Number of float alu accesses +system.cpu0.num_func_calls 1205467 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4697957 # number of instructions that are conditional controls +system.cpu0.num_int_insts 39863943 # number of integer instructions +system.cpu0.num_fp_insts 4171 # number of float instructions +system.cpu0.num_int_register_reads 70363299 # number of times the integer registers were read +system.cpu0.num_int_register_writes 26108579 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3915 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 256 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 134797325 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 18388517 # number of times the CC registers were written +system.cpu0.num_mem_refs 14597479 # number of memory refs +system.cpu0.num_load_insts 7571296 # Number of load instructions +system.cpu0.num_store_insts 7026183 # Number of store instructions +system.cpu0.num_idle_cycles 1756006001.161348 # Number of idle cycles +system.cpu0.num_busy_cycles 45221299.838652 # Number of busy cycles +system.cpu0.not_idle_fraction 0.025106 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.974894 # Percentage of idle cycles +system.cpu0.Branches 6054325 # Number of branches fetched +system.cpu0.op_class::No_OpClass 13280 0.03% 0.03% # Class of executed instruction +system.cpu0.op_class::IntAlu 30338974 67.42% 67.45% # Class of executed instruction +system.cpu0.op_class::IntMult 51765 0.12% 67.56% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 67.56% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 67.56% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 67.56% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 67.56% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 67.56% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 67.56% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 67.56% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 67.56% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 67.56% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 67.56% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 67.56% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 67.56% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 67.56% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 67.56% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 67.56% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 67.56% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.56% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 67.56% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.56% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.56% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.56% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.56% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.56% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 639 0.00% 67.56% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 67.56% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.56% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.56% # Class of executed instruction +system.cpu0.op_class::MemRead 7571296 16.82% 84.39% # Class of executed instruction +system.cpu0.op_class::MemWrite 7026183 15.61% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 39212980 # Class of executed instruction +system.cpu0.op_class::total 45002137 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 50449 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 428546 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.014878 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 29820919 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 429058 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 69.503235 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 64538774500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.014878 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998076 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998076 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 42773 # number of quiesce instructions executed +system.cpu0.icache.tags.replacements 419775 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.035896 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 37516680 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 420287 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 89.264431 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 64363581500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.035896 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998117 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998117 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 508 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 30679037 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 30679037 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 29820919 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 29820919 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 29820919 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 29820919 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 29820919 # number of overall hits -system.cpu0.icache.overall_hits::total 29820919 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 429059 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 429059 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 429059 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 429059 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 429059 # number of overall misses -system.cpu0.icache.overall_misses::total 429059 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 30249978 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 30249978 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 30249978 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 30249978 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 30249978 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 30249978 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014184 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014184 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014184 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014184 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014184 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014184 # miss rate for overall accesses +system.cpu0.icache.tags.tag_accesses 38357256 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 38357256 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 37516680 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 37516680 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 37516680 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 37516680 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 37516680 # number of overall hits +system.cpu0.icache.overall_hits::total 37516680 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 420288 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 420288 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 420288 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 420288 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 420288 # number of overall misses +system.cpu0.icache.overall_misses::total 420288 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 37936968 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 37936968 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 37936968 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 37936968 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 37936968 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 37936968 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011079 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.011079 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011079 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.011079 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011079 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.011079 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -482,68 +472,76 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 323608 # number of replacements -system.cpu0.dcache.tags.tagsinuse 494.763142 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 12469968 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 323980 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 38.489931 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 22120000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.763142 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966334 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.966334 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 372 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 372 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.726562 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 51685336 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 51685336 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6513975 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6513975 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5631422 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5631422 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 151763 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 151763 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 153180 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 153180 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 12145397 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12145397 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 12145397 # number of overall hits -system.cpu0.dcache.overall_hits::total 12145397 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 197167 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 197167 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 167350 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 167350 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9208 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 9208 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7466 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7466 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 364517 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 364517 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 364517 # number of overall misses -system.cpu0.dcache.overall_misses::total 364517 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6711142 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6711142 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5798772 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5798772 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 160971 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 160971 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 160646 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 160646 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12509914 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12509914 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12509914 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12509914 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029379 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.029379 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.028860 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.028860 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.057203 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.057203 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.046475 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.046475 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029138 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.029138 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029138 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.029138 # miss rate for overall accesses +system.cpu0.dcache.tags.replacements 348431 # number of replacements +system.cpu0.dcache.tags.tagsinuse 471.119339 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 12834011 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 348738 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 36.801298 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 22109000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 471.119339 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.920155 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.920155 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 307 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 307 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.599609 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 53249455 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 53249455 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6868875 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6868875 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5598061 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5598061 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 78744 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 78744 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 135195 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 135195 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 136387 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 136387 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 12466936 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12466936 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 12545680 # number of overall hits +system.cpu0.dcache.overall_hits::total 12545680 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 173318 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 173318 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 159147 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 159147 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 50343 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 50343 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9388 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 9388 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7646 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7646 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 332465 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 332465 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 382808 # number of overall misses +system.cpu0.dcache.overall_misses::total 382808 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7042193 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7042193 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5757208 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5757208 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 129087 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 129087 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 144583 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 144583 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144033 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 144033 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12799401 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12799401 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12928488 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12928488 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.024611 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.024611 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027643 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.027643 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.389993 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.389993 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064932 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064932 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053085 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053085 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025975 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.025975 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029610 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.029610 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -552,8 +550,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 300957 # number of writebacks -system.cpu0.dcache.writebacks::total 300957 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 321785 # number of writebacks +system.cpu0.dcache.writebacks::total 321785 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -578,25 +576,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 7365100 # DTB read hits -system.cpu1.dtb.read_misses 3705 # DTB read misses -system.cpu1.dtb.write_hits 5489754 # DTB write hits -system.cpu1.dtb.write_misses 1595 # DTB write misses +system.cpu1.dtb.read_hits 6028686 # DTB read hits +system.cpu1.dtb.read_misses 5403 # DTB read misses +system.cpu1.dtb.write_hits 4781604 # DTB write hits +system.cpu1.dtb.write_misses 1104 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1696 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 2367 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 145 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 185 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 7368805 # DTB read accesses -system.cpu1.dtb.write_accesses 5491349 # DTB write accesses +system.cpu1.dtb.perms_faults 267 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 6034089 # DTB read accesses +system.cpu1.dtb.write_accesses 4782708 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 12854854 # DTB hits -system.cpu1.dtb.misses 5300 # DTB misses -system.cpu1.dtb.accesses 12860154 # DTB accesses +system.cpu1.dtb.hits 10810290 # DTB hits +system.cpu1.dtb.misses 6507 # DTB misses +system.cpu1.dtb.accesses 10816797 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -618,8 +616,8 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 32413691 # ITB inst hits -system.cpu1.itb.inst_misses 2200 # ITB inst misses +system.cpu1.itb.inst_hits 24626141 # ITB inst hits +system.cpu1.itb.inst_misses 3166 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -628,118 +626,120 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1176 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1581 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 32415891 # ITB inst accesses -system.cpu1.itb.hits 32413691 # DTB hits -system.cpu1.itb.misses 2200 # DTB misses -system.cpu1.itb.accesses 32415891 # DTB accesses -system.cpu1.numCycles 1824196797 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 24629307 # ITB inst accesses +system.cpu1.itb.hits 24626141 # DTB hits +system.cpu1.itb.misses 3166 # DTB misses +system.cpu1.itb.accesses 24629307 # DTB accesses +system.cpu1.numCycles 1801709576 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 31877311 # Number of instructions committed -system.cpu1.committedOps 40215396 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 35862250 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 4436 # Number of float alu accesses -system.cpu1.num_func_calls 955425 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 4048275 # number of instructions that are conditional controls -system.cpu1.num_int_insts 35862250 # number of integer instructions -system.cpu1.num_fp_insts 4436 # number of float instructions -system.cpu1.num_int_register_reads 183631460 # number of times the integer registers were read -system.cpu1.num_int_register_writes 39072446 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 3022 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1416 # number of times the floating registers were written -system.cpu1.num_mem_refs 13371151 # number of memory refs -system.cpu1.num_load_insts 7642991 # Number of load instructions -system.cpu1.num_store_insts 5728160 # Number of store instructions -system.cpu1.num_idle_cycles 1783402877.755682 # Number of idle cycles -system.cpu1.num_busy_cycles 40793919.244318 # Number of busy cycles -system.cpu1.not_idle_fraction 0.022363 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.977637 # Percentage of idle cycles -system.cpu1.Branches 5037975 # Number of branches fetched -system.cpu1.op_class::No_OpClass 12508 0.03% 0.03% # Class of executed instruction -system.cpu1.op_class::IntAlu 26844895 66.65% 66.68% # Class of executed instruction -system.cpu1.op_class::IntMult 49628 0.12% 66.80% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 66.80% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 66.80% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 66.80% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 66.80% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 66.80% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 66.80% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 66.80% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 66.80% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 66.80% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 66.80% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 66.80% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 66.80% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 66.80% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 66.80% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 66.80% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 66.80% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 66.80% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 66.80% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 66.80% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 66.80% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 66.80% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 66.80% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 66.80% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 737 0.00% 66.80% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 66.80% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 66.80% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 66.80% # Class of executed instruction -system.cpu1.op_class::MemRead 7642991 18.98% 85.78% # Class of executed instruction -system.cpu1.op_class::MemWrite 5728160 14.22% 100.00% # Class of executed instruction +system.cpu1.committedInsts 23838609 # Number of instructions committed +system.cpu1.committedOps 29191016 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 25547086 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 5650 # Number of float alu accesses +system.cpu1.num_func_calls 987842 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 2987341 # number of instructions that are conditional controls +system.cpu1.num_int_insts 25547086 # number of integer instructions +system.cpu1.num_fp_insts 5650 # number of float instructions +system.cpu1.num_int_register_reads 48277330 # number of times the integer registers were read +system.cpu1.num_int_register_writes 17495174 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 3706 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1948 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 86963152 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 11050350 # number of times the CC registers were written +system.cpu1.num_mem_refs 11165955 # number of memory refs +system.cpu1.num_load_insts 6206289 # Number of load instructions +system.cpu1.num_store_insts 4959666 # Number of store instructions +system.cpu1.num_idle_cycles 1771680344.893366 # Number of idle cycles +system.cpu1.num_busy_cycles 30029231.106634 # Number of busy cycles +system.cpu1.not_idle_fraction 0.016667 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.983333 # Percentage of idle cycles +system.cpu1.Branches 4459555 # Number of branches fetched +system.cpu1.op_class::No_OpClass 15552 0.05% 0.05% # Class of executed instruction +system.cpu1.op_class::IntAlu 18046643 61.66% 61.71% # Class of executed instruction +system.cpu1.op_class::IntMult 40424 0.14% 61.85% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 61.85% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 61.85% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 61.85% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 61.85% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 61.85% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 61.85% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 61.85% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 61.85% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 61.85% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 61.85% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 61.85% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 61.85% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 61.85% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 61.85% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 61.85% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 61.85% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 61.85% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 61.85% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 61.85% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 61.85% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 61.85% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 61.85% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 61.85% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 1539 0.01% 61.85% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 61.85% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 61.85% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 61.85% # Class of executed instruction +system.cpu1.op_class::MemRead 6206289 21.20% 83.06% # Class of executed instruction +system.cpu1.op_class::MemWrite 4959666 16.94% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 40278919 # Class of executed instruction +system.cpu1.op_class::total 29270113 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 40450 # number of quiesce instructions executed -system.cpu1.icache.tags.replacements 433942 # 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Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 443505 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 54.529985 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 254679414000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 472.644505 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.923134 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.923134 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 261 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 20 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 50 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 257 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 32849418 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 32849418 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 31980510 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 31980510 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 31980510 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 31980510 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 31980510 # number of overall hits -system.cpu1.icache.overall_hits::total 31980510 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 434454 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 434454 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 434454 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 434454 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 434454 # number of overall misses -system.cpu1.icache.overall_misses::total 434454 # number of overall misses -system.cpu1.icache.ReadReq_accesses::cpu1.inst 32414964 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 32414964 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 32414964 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 32414964 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 32414964 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 32414964 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013403 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.013403 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013403 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.013403 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013403 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.013403 # miss rate for overall accesses +system.cpu1.icache.tags.tag_accesses 25071331 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 25071331 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 24184321 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 24184321 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 24184321 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 24184321 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 24184321 # number of overall hits +system.cpu1.icache.overall_hits::total 24184321 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 443505 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 443505 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 443505 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 443505 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 443505 # number of overall misses +system.cpu1.icache.overall_misses::total 443505 # number of overall misses +system.cpu1.icache.ReadReq_accesses::cpu1.inst 24627826 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 24627826 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 24627826 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 24627826 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 24627826 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 24627826 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.018008 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.018008 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.018008 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.018008 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.018008 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.018008 # miss rate for overall accesses system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -749,71 +749,79 @@ system.cpu1.icache.avg_blocked_cycles::no_targets nan system.cpu1.icache.fast_writes 0 # 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number of replacements +system.cpu1.dcache.tags.tagsinuse 468.122166 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 9407683 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 274568 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 34.263581 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 94419429000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 468.122166 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.914301 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.914301 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 267 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 226 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 322 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 48419346 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 48419346 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 7002504 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 7002504 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4520263 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4520263 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 77967 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 77967 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 79030 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 79030 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 11522767 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 11522767 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 11522767 # number of overall hits -system.cpu1.dcache.overall_hits::total 11522767 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 198274 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 198274 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 126068 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 126068 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11260 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 11260 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10133 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10133 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 324342 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 324342 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 324342 # number of overall misses -system.cpu1.dcache.overall_misses::total 324342 # number of overall misses -system.cpu1.dcache.ReadReq_accesses::cpu1.data 7200778 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 7200778 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 4646331 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 4646331 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 89227 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 89227 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 89163 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 89163 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 11847109 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 11847109 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 11847109 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 11847109 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.027535 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.027535 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027133 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.027133 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.126195 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.126195 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.113646 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.113646 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027377 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.027377 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.027377 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.027377 # miss rate for overall accesses +system.cpu1.dcache.tags.tag_accesses 39106907 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 39106907 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 4611957 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 4611957 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4543395 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4543395 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 35603 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 35603 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 94939 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 94939 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 95657 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 95657 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 9155352 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 9155352 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 9190955 # number of overall hits +system.cpu1.dcache.overall_hits::total 9190955 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 143554 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 143554 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 130048 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 130048 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 27770 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 27770 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 10527 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 10527 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 9468 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 9468 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 273602 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 273602 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 301372 # number of overall misses +system.cpu1.dcache.overall_misses::total 301372 # number of overall misses +system.cpu1.dcache.ReadReq_accesses::cpu1.data 4755511 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 4755511 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 4673443 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 4673443 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 63373 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 63373 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 105466 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 105466 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105125 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 105125 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 9428954 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 9428954 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 9492327 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 9492327 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.030187 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.030187 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027827 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.027827 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.438199 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.438199 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.099814 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.099814 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.090064 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.090064 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029017 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.029017 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.031749 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.031749 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -822,8 +830,8 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 266849 # number of writebacks -system.cpu1.dcache.writebacks::total 266849 # number of writebacks +system.cpu1.dcache.writebacks::writebacks 249941 # number of writebacks +system.cpu1.dcache.writebacks::total 249941 # number of writebacks system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index 04261a831..511b86cf1 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -1,18 +1,56 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.332812 # Number of seconds simulated -sim_ticks 2332811899500 # Number of ticks simulated -final_tick 2332811899500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.321351 # Number of seconds simulated +sim_ticks 2321351025500 # Number of ticks simulated +final_tick 2321351025500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 975328 # Simulator instruction rate (inst/s) -host_op_rate 1254205 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 37662621026 # Simulator tick rate (ticks/s) -host_mem_usage 462792 # Number of bytes of host memory used -host_seconds 61.94 # Real time elapsed on the host -sim_insts 60411489 # Number of instructions simulated -sim_ops 77685090 # Number of ops (including micro ops) simulated +host_inst_rate 818788 # Simulator instruction rate (inst/s) +host_op_rate 985991 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 31464875718 # Simulator tick rate (ticks/s) +host_mem_usage 430844 # Number of bytes of host memory used +host_seconds 73.78 # Real time elapsed on the host +sim_insts 60406834 # Number of instructions simulated +sim_ops 72742429 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::realview.clcd 110100480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 705416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9071832 # Number of bytes read from this memory +system.physmem.bytes_read::total 119878240 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 705416 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 705416 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3703872 # Number of bytes written to this memory +system.physmem.bytes_written::cpu.data 3015816 # Number of bytes written to this memory +system.physmem.bytes_written::total 6719688 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 13762560 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 17234 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141773 # Number of read requests responded to by this memory +system.physmem.num_reads::total 13921575 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57873 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu.data 753954 # Number of write requests responded to by this memory +system.physmem.num_writes::total 811827 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47429483 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 138 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 83 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 303882 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3907997 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51641582 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 303882 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 303882 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1595567 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1299164 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2894732 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1595567 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47429483 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 138 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 83 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 303882 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5207161 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54536314 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -25,46 +63,8 @@ system.realview.nvmem.bw_inst_read::cpu.inst 9 system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 9 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 705160 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9071768 # Number of bytes read from this memory -system.physmem.bytes_read::total 121450784 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 705160 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 705160 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3703424 # Number of bytes written to this memory -system.physmem.bytes_written::cpu.data 3015816 # Number of bytes written to this memory -system.physmem.bytes_written::total 6719240 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 13959168 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 17230 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141782 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14118188 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57866 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu.data 753954 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811820 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47870702 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 137 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 82 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 302279 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3888770 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52061970 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 302279 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 302279 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1587536 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1292781 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2880318 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1587536 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47870702 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 137 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 82 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 302279 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5181551 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54942288 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 55969769 # Throughput (bytes/s) -system.membus.data_through_bus 130566943 # Total data (bytes) +system.membus.throughput 55568847 # Throughput (bytes/s) +system.membus.data_through_bus 128994799 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -72,8 +72,8 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 48895283 # Throughput (bytes/s) -system.iobus.data_through_bus 114063499 # Total data (bytes) +system.iobus.throughput 48459111 # Throughput (bytes/s) +system.iobus.data_through_bus 112490607 # Total data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -98,25 +98,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 14971763 # DTB read hits -system.cpu.dtb.read_misses 7294 # DTB read misses -system.cpu.dtb.write_hits 11217184 # DTB write hits +system.cpu.dtb.read_hits 13142244 # DTB read hits +system.cpu.dtb.read_misses 7297 # DTB read misses +system.cpu.dtb.write_hits 11216207 # DTB write hits system.cpu.dtb.write_misses 2181 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3403 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 3399 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.prefetch_faults 174 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 14979057 # DTB read accesses -system.cpu.dtb.write_accesses 11219365 # DTB write accesses +system.cpu.dtb.read_accesses 13149541 # DTB read accesses +system.cpu.dtb.write_accesses 11218388 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 26188947 # DTB hits -system.cpu.dtb.misses 9475 # DTB misses -system.cpu.dtb.accesses 26198422 # DTB accesses +system.cpu.dtb.hits 24358451 # DTB hits +system.cpu.dtb.misses 9478 # DTB misses +system.cpu.dtb.accesses 24367929 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -138,7 +138,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 61434680 # ITB inst hits +system.cpu.itb.inst_hits 61430007 # ITB inst hits system.cpu.itb.inst_misses 4471 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -155,105 +155,107 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 61439151 # ITB inst accesses -system.cpu.itb.hits 61434680 # DTB hits +system.cpu.itb.inst_accesses 61434478 # ITB inst accesses +system.cpu.itb.hits 61430007 # DTB hits system.cpu.itb.misses 4471 # DTB misses -system.cpu.itb.accesses 61439151 # DTB accesses -system.cpu.numCycles 4665623800 # number of cpu cycles simulated +system.cpu.itb.accesses 61434478 # DTB accesses +system.cpu.numCycles 4642702052 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60411489 # Number of instructions committed -system.cpu.committedOps 77685090 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 69133554 # Number of integer alu accesses +system.cpu.committedInsts 60406834 # Number of instructions committed +system.cpu.committedOps 72742429 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 64191430 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses -system.cpu.num_func_calls 2136078 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7942566 # number of instructions that are conditional controls -system.cpu.num_int_insts 69133554 # number of integer instructions +system.cpu.num_func_calls 2135762 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7544984 # number of instructions that are conditional controls +system.cpu.num_int_insts 64191430 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions -system.cpu.num_int_register_reads 355910547 # number of times the integer registers were read -system.cpu.num_int_register_writes 74442273 # number of times the integer registers were written +system.cpu.num_int_register_reads 116427347 # number of times the integer registers were read +system.cpu.num_int_register_writes 42818107 # number of times the integer registers were written system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written -system.cpu.num_mem_refs 27362421 # number of memory refs -system.cpu.num_load_insts 15640088 # Number of load instructions -system.cpu.num_store_insts 11722333 # Number of store instructions -system.cpu.num_idle_cycles 4586822073.007144 # Number of idle cycles -system.cpu.num_busy_cycles 78801726.992856 # Number of busy cycles -system.cpu.not_idle_fraction 0.016890 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.983110 # Percentage of idle cycles -system.cpu.Branches 10299261 # Number of branches fetched +system.cpu.num_cc_register_reads 217570004 # number of times the CC registers were read +system.cpu.num_cc_register_writes 28977741 # number of times the CC registers were written +system.cpu.num_mem_refs 25221274 # number of memory refs +system.cpu.num_load_insts 13499937 # Number of load instructions +system.cpu.num_store_insts 11721337 # Number of store instructions +system.cpu.num_idle_cycles 4568843017.980124 # Number of idle cycles +system.cpu.num_busy_cycles 73859034.019877 # Number of busy cycles +system.cpu.not_idle_fraction 0.015909 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.984091 # Percentage of idle cycles +system.cpu.Branches 10298517 # Number of branches fetched system.cpu.op_class::No_OpClass 28518 0.04% 0.04% # Class of executed instruction -system.cpu.op_class::IntAlu 50337551 64.69% 64.72% # Class of executed instruction -system.cpu.op_class::IntMult 87780 0.11% 64.84% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 64.84% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 64.84% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 64.84% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 64.84% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 64.84% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 64.84% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 64.84% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 64.84% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 64.84% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 64.84% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 64.84% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 64.84% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 64.84% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 64.84% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 64.84% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 64.84% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 64.84% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 64.84% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 64.84% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 64.84% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 64.84% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 64.84% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 64.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 2117 0.00% 64.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 64.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.84% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.84% # Class of executed instruction -system.cpu.op_class::MemRead 15640088 20.10% 84.94% # Class of executed instruction -system.cpu.op_class::MemWrite 11722333 15.06% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 47536032 65.23% 65.27% # Class of executed instruction +system.cpu.op_class::IntMult 87771 0.12% 65.39% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 2113 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::MemRead 13499937 18.52% 83.92% # Class of executed instruction +system.cpu.op_class::MemWrite 11721337 16.08% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 77818387 # Class of executed instruction +system.cpu.op_class::total 72875708 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 82795 # number of quiesce instructions executed -system.cpu.icache.tags.replacements 850590 # number of replacements -system.cpu.icache.tags.tagsinuse 511.678462 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 60586338 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 851102 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 71.185754 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 5711018500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.678462 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999372 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999372 # Average percentage of cache occupancy +system.cpu.kern.inst.quiesce 82781 # number of quiesce instructions executed +system.cpu.icache.tags.replacements 850515 # number of replacements +system.cpu.icache.tags.tagsinuse 511.689593 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 60581740 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 851027 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 71.186625 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 5455017500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.689593 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999394 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999394 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 177 # 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number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1483942 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7546 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 3154 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 849401 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 623841 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1483942 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000663 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000951 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012489 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026207 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.016565 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991165 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991165 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.539987 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.539987 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000663 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000951 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012489 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.229778 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.103751 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000663 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000951 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012489 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.229778 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.103751 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -386,69 +388,77 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 57866 # number of writebacks -system.cpu.l2cache.writebacks::total 57866 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 57873 # number of writebacks +system.cpu.l2cache.writebacks::total 57873 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 623343 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.997030 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 23629012 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 623855 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37.875808 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 21768000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.997030 # Average occupied blocks per requestor +system.cpu.dcache.tags.replacements 623329 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.997018 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 21798545 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 623841 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 34.942469 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 21757000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.997018 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 278 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 291 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 197 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 97635323 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 97635323 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 13180574 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13180574 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 9962233 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 9962233 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 236039 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 236039 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247221 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247221 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 23142807 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 23142807 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 23142807 # number of overall hits -system.cpu.dcache.overall_hits::total 23142807 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 365463 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 365463 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 250154 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 250154 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 11183 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 11183 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 615617 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 615617 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 615617 # number of overall misses -system.cpu.dcache.overall_misses::total 615617 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 13546037 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13546037 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10212387 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10212387 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247222 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 247222 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 247221 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 247221 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 23758424 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 23758424 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 23758424 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 23758424 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026979 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.026979 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024495 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.024495 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045235 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045235 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025912 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025912 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.025912 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.025912 # miss rate for overall accesses +system.cpu.dcache.tags.tag_accesses 90313385 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 90313385 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 11240226 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11240226 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 9961316 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 9961316 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 110856 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 110856 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 236008 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 236008 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247196 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247196 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21201542 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21201542 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21312398 # number of overall hits +system.cpu.dcache.overall_hits::total 21312398 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 292030 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 292030 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 250123 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 250123 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 73442 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 73442 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 11189 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 11189 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 542153 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 542153 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 615595 # number of overall misses +system.cpu.dcache.overall_misses::total 615595 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 11532256 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 11532256 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10211439 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10211439 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 184298 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 184298 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247197 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 247197 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247196 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247196 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21743695 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21743695 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21927993 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21927993 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025323 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.025323 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024494 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.024494 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.398496 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.398496 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045263 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045263 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.024934 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.024934 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.028073 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.028073 # miss rate for overall accesses system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -457,11 +467,11 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 592648 # number of writebacks -system.cpu.dcache.writebacks::total 592648 # number of writebacks +system.cpu.dcache.writebacks::writebacks 592642 # number of writebacks +system.cpu.dcache.writebacks::total 592642 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 59102995 # Throughput (bytes/s) -system.cpu.toL2Bus.data_through_bus 137876171 # Total data (bytes) +system.cpu.toL2Bus.throughput 59392167 # Throughput (bytes/s) +system.cpu.toL2Bus.data_through_bus 137870067 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 8e4b444a3..051c13810 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,156 +1,156 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.195945 # Number of seconds simulated -sim_ticks 1195945260000 # Number of ticks simulated -final_tick 1195945260000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.194312 # Number of seconds simulated +sim_ticks 1194312178000 # Number of ticks simulated +final_tick 1194312178000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 424891 # Simulator instruction rate (inst/s) -host_op_rate 541366 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8267957779 # Simulator tick rate (ticks/s) -host_mem_usage 468940 # Number of bytes of host memory used -host_seconds 144.65 # Real time elapsed on the host -sim_insts 61459750 # Number of instructions simulated -sim_ops 78307634 # Number of ops (including micro ops) simulated +host_inst_rate 475403 # Simulator instruction rate (inst/s) +host_op_rate 567868 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9241250441 # Simulator tick rate (ticks/s) +host_mem_usage 438040 # Number of bytes of host memory used +host_seconds 129.24 # Real time elapsed on the host +sim_insts 61439698 # Number of instructions simulated +sim_ops 73389630 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 393612 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4714684 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 393932 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4710012 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 324676 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4804472 # Number of bytes read from this memory -system.physmem.bytes_read::total 62142468 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 393612 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 324676 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 718288 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4110592 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 323460 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4796088 # Number of bytes read from this memory +system.physmem.bytes_read::total 62128516 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 393932 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 323460 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 717392 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4097216 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7137936 # Number of bytes written to this memory +system.physmem.bytes_written::total 7124560 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 12378 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 73741 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 12383 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 73653 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 5164 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 75098 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6654453 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 64228 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.inst 5145 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 74957 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6654210 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 64019 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 821064 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43400408 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 820855 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43459753 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 54 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 107 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 329122 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3942224 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 329840 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3943703 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 214 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 54 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 271481 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4017301 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51960963 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 329122 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 271481 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 600603 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3437107 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 14215 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2517125 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 5968447 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3437107 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43400408 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 270834 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4015774 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52020332 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 329840 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 270834 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 600674 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3430607 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 14234 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2520567 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 5965408 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3430607 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43459753 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 54 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 107 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 329122 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3956439 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 329840 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3957937 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 214 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 54 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 271481 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 6534426 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 57929411 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6654453 # Number of read requests accepted -system.physmem.writeReqs 821064 # Number of write requests accepted -system.physmem.readBursts 6654453 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 821064 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 425841472 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 43520 # Total number of bytes read from write queue -system.physmem.bytesWritten 7149184 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 62142468 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7137936 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 680 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 709327 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 12098 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 415328 # Per bank write bursts -system.physmem.perBankRdBursts::1 415212 # Per bank write bursts -system.physmem.perBankRdBursts::2 415403 # Per bank write bursts -system.physmem.perBankRdBursts::3 415611 # Per bank write bursts -system.physmem.perBankRdBursts::4 422397 # Per bank write bursts -system.physmem.perBankRdBursts::5 415577 # Per bank write bursts -system.physmem.perBankRdBursts::6 415747 # Per bank write bursts -system.physmem.perBankRdBursts::7 415496 # Per bank write bursts -system.physmem.perBankRdBursts::8 416027 # Per bank write bursts -system.physmem.perBankRdBursts::9 415632 # Per bank write bursts -system.physmem.perBankRdBursts::10 415426 # Per bank write bursts -system.physmem.perBankRdBursts::11 414842 # Per bank write bursts -system.physmem.perBankRdBursts::12 414820 # Per bank write bursts -system.physmem.perBankRdBursts::13 415557 # Per bank write bursts -system.physmem.perBankRdBursts::14 415554 # Per bank write bursts -system.physmem.perBankRdBursts::15 415144 # Per bank write bursts -system.physmem.perBankWrBursts::0 6840 # Per bank write bursts -system.physmem.perBankWrBursts::1 6732 # Per bank write bursts -system.physmem.perBankWrBursts::2 6969 # Per bank write bursts -system.physmem.perBankWrBursts::3 7025 # Per bank write bursts -system.physmem.perBankWrBursts::4 7326 # Per bank write bursts -system.physmem.perBankWrBursts::5 7107 # Per bank write bursts -system.physmem.perBankWrBursts::6 7317 # Per bank write bursts -system.physmem.perBankWrBursts::7 7078 # Per bank write bursts -system.physmem.perBankWrBursts::8 7464 # Per bank write bursts -system.physmem.perBankWrBursts::9 7155 # Per bank write bursts -system.physmem.perBankWrBursts::10 7023 # Per bank write bursts -system.physmem.perBankWrBursts::11 6543 # Per bank write bursts -system.physmem.perBankWrBursts::12 6616 # Per bank write bursts -system.physmem.perBankWrBursts::13 6901 # Per bank write bursts -system.physmem.perBankWrBursts::14 6977 # Per bank write bursts -system.physmem.perBankWrBursts::15 6633 # Per bank write bursts +system.physmem.bw_total::cpu1.inst 270834 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 6536341 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 57985740 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 6654210 # Number of read requests accepted +system.physmem.writeReqs 820855 # Number of write requests accepted +system.physmem.readBursts 6654210 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 820855 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 425838464 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 30976 # Total number of bytes read from write queue +system.physmem.bytesWritten 7136448 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 62128516 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7124560 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 484 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 709321 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 12079 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 415236 # Per bank write bursts +system.physmem.perBankRdBursts::1 415218 # Per bank write bursts +system.physmem.perBankRdBursts::2 415240 # Per bank write bursts +system.physmem.perBankRdBursts::3 415658 # Per bank write bursts +system.physmem.perBankRdBursts::4 422402 # Per bank write bursts +system.physmem.perBankRdBursts::5 415506 # Per bank write bursts +system.physmem.perBankRdBursts::6 415779 # Per bank write bursts +system.physmem.perBankRdBursts::7 415682 # Per bank write bursts +system.physmem.perBankRdBursts::8 416047 # Per bank write bursts +system.physmem.perBankRdBursts::9 415577 # Per bank write bursts +system.physmem.perBankRdBursts::10 415398 # Per bank write bursts +system.physmem.perBankRdBursts::11 414862 # Per bank write bursts +system.physmem.perBankRdBursts::12 415007 # Per bank write bursts +system.physmem.perBankRdBursts::13 415552 # Per bank write bursts +system.physmem.perBankRdBursts::14 415496 # Per bank write bursts +system.physmem.perBankRdBursts::15 415066 # Per bank write bursts +system.physmem.perBankWrBursts::0 6763 # Per bank write bursts +system.physmem.perBankWrBursts::1 6728 # Per bank write bursts +system.physmem.perBankWrBursts::2 6819 # Per bank write bursts +system.physmem.perBankWrBursts::3 7055 # Per bank write bursts +system.physmem.perBankWrBursts::4 7301 # Per bank write bursts +system.physmem.perBankWrBursts::5 7028 # Per bank write bursts +system.physmem.perBankWrBursts::6 7316 # Per bank write bursts +system.physmem.perBankWrBursts::7 7231 # Per bank write bursts +system.physmem.perBankWrBursts::8 7485 # Per bank write bursts +system.physmem.perBankWrBursts::9 7107 # Per bank write bursts +system.physmem.perBankWrBursts::10 7000 # Per bank write bursts +system.physmem.perBankWrBursts::11 6549 # Per bank write bursts +system.physmem.perBankWrBursts::12 6696 # Per bank write bursts +system.physmem.perBankWrBursts::13 6902 # Per bank write bursts +system.physmem.perBankWrBursts::14 6960 # Per bank write bursts +system.physmem.perBankWrBursts::15 6567 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1195940759000 # Total gap between requests +system.physmem.totGap 1194307723500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 6849 # Read request sizes (log2) -system.physmem.readPktSize::3 6488064 # Read request sizes (log2) +system.physmem.readPktSize::2 6799 # Read request sizes (log2) +system.physmem.readPktSize::3 6488089 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 159540 # Read request sizes (log2) +system.physmem.readPktSize::6 159322 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 756836 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 64228 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 572493 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 410656 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 412880 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 461685 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 417933 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 446395 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1149366 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1113988 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1438120 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 64577 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 50343 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 45843 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 44044 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 8771 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 8319 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 8183 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 162 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 15 # What read queue length does an incoming req see +system.physmem.writePktSize::6 64019 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 572550 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 410650 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 412558 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 460055 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 417389 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 445707 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1151151 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1116358 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1442650 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 62467 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 48974 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 44870 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 43130 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 8689 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 8270 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 8147 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 108 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -180,24 +180,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3947 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4027 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3883 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3903 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 6452 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6482 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6480 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 6485 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6483 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6487 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6486 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6490 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6486 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6486 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6484 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6500 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6486 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6488 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6485 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6491 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6485 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6483 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6485 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6483 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6495 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6488 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6484 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 6486 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6485 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6482 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6484 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6481 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -229,66 +229,67 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 473596 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 914.261641 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 784.047795 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 289.306705 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 25239 5.33% 5.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 21585 4.56% 9.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5945 1.26% 11.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2453 0.52% 11.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2290 0.48% 12.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1636 0.35% 12.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4075 0.86% 13.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 899 0.19% 13.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 409474 86.46% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 473596 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6482 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 1026.497532 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 34346.134147 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-131071 6476 99.91% 99.91% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::131072-262143 3 0.05% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::524288-655359 1 0.02% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::786432-917503 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2.49037e+06-2.62144e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6482 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6482 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.233261 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.205432 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.970583 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2453 37.84% 37.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 80 1.23% 39.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 3936 60.72% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 11 0.17% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6482 # Writes before turning the bus around for reads -system.physmem.totQLat 171035006500 # Total ticks spent queuing -system.physmem.totMemAccLat 295793250250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 33268865000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25704.97 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 473292 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 914.815615 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 785.169464 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 288.643252 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 25022 5.29% 5.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 21566 4.56% 9.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5869 1.24% 11.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2391 0.51% 11.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2344 0.50% 12.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1629 0.34% 12.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4093 0.86% 13.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 899 0.19% 13.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 409479 86.52% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 473292 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6481 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 1026.648974 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 26505.494009 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-65535 6473 99.88% 99.88% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::65536-131071 1 0.02% 99.89% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::196608-262143 3 0.05% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::589824-655359 1 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::786432-851967 1 0.02% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::983040-1.04858e+06 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1.50733e+06-1.57286e+06 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6481 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6481 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.205215 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.176618 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.984217 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2581 39.82% 39.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 15 0.23% 40.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 3862 59.59% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 20 0.31% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 3 0.05% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6481 # Writes before turning the bus around for reads +system.physmem.totQLat 170730095750 # Total ticks spent queuing +system.physmem.totMemAccLat 295487458250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 33268630000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25659.32 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44454.97 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 356.07 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 44409.32 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 356.56 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 5.98 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 51.96 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 52.02 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 5.97 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.83 # Data bus utilization in percentage -system.physmem.busUtilRead 2.78 # Data bus utilization in percentage for reads +system.physmem.busUtilRead 2.79 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 4.89 # Average read queue length when enqueuing -system.physmem.avgWrQLen 27.45 # Average write queue length when enqueuing -system.physmem.readRowHits 6199461 # Number of row buffer hits during reads -system.physmem.writeRowHits 92422 # Number of row buffer hits during writes +system.physmem.avgRdQLen 4.36 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.98 # Average write queue length when enqueuing +system.physmem.readRowHits 6199598 # Number of row buffer hits during reads +system.physmem.writeRowHits 92343 # Number of row buffer hits during writes system.physmem.readRowHitRate 93.17 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 82.71 # Row buffer hit rate for writes -system.physmem.avgGap 159981.01 # Average gap between requests +system.physmem.writeRowHitRate 82.79 # Row buffer hit rate for writes +system.physmem.avgGap 159772.22 # Average gap between requests system.physmem.pageHitRate 93.00 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 947634468500 # Time in different power states -system.physmem.memoryStateTime::REF 39935220000 # Time in different power states +system.physmem.memoryStateTime::IDLE 945808643750 # Time in different power states +system.physmem.memoryStateTime::REF 39880620000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 208375212750 # Time in different power states +system.physmem.memoryStateTime::ACT 208620525000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory @@ -308,314 +309,314 @@ system.realview.nvmem.bw_inst_read::total 57 # I system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 59946686 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 7703403 # Transaction distribution -system.membus.trans_dist::ReadResp 7703403 # Transaction distribution -system.membus.trans_dist::WriteReq 767582 # Transaction distribution -system.membus.trans_dist::WriteResp 767582 # Transaction distribution -system.membus.trans_dist::Writeback 64228 # Transaction distribution -system.membus.trans_dist::UpgradeReq 31700 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 17261 # Transaction distribution -system.membus.trans_dist::UpgradeResp 12098 # Transaction distribution -system.membus.trans_dist::ReadExReq 137709 # Transaction distribution -system.membus.trans_dist::ReadExResp 137266 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382666 # Packet count per connected master and slave (bytes) +system.membus.throughput 60005732 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 7703348 # Transaction distribution +system.membus.trans_dist::ReadResp 7703348 # Transaction distribution +system.membus.trans_dist::WriteReq 767581 # Transaction distribution +system.membus.trans_dist::WriteResp 767581 # Transaction distribution +system.membus.trans_dist::Writeback 64019 # Transaction distribution +system.membus.trans_dist::UpgradeReq 31325 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 17234 # Transaction distribution +system.membus.trans_dist::UpgradeResp 12079 # Transaction distribution +system.membus.trans_dist::ReadExReq 137481 # Transaction distribution +system.membus.trans_dist::ReadExResp 137066 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382642 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 10310 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 10312 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 910 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1972180 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4366104 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 906 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1971036 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4364934 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12976128 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 12976128 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 17342232 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390035 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 17341062 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389989 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 20620 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 20624 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1820 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17375892 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 19788443 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1812 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17348564 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 19761065 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 51904512 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 51904512 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 71692955 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 71692955 # Total data (bytes) +system.membus.tot_pkt_size::total 71665577 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 71665577 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1224801000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1224785500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 18000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 9242500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 9231500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 784500 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 778500 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 9211274000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 9212282000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 5078680829 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 5079172023 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.respLayer2.occupancy 16046108250 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 16050388750 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 69421 # number of replacements -system.l2c.tags.tagsinuse 53012.823108 # Cycle average of tags in use -system.l2c.tags.total_refs 1672128 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 134609 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 12.422111 # Average number of references to valid blocks. +system.l2c.tags.replacements 69203 # number of replacements +system.l2c.tags.tagsinuse 52959.316379 # Cycle average of tags in use +system.l2c.tags.total_refs 1672724 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 134375 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 12.448179 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 40185.217534 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000410 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 40136.915421 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000411 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001544 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3710.755623 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4242.358437 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.742287 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.001689 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2808.724549 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2063.021033 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.613178 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.inst 3716.167205 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4233.542603 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.741623 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.001622 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2809.362324 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2060.583626 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.612441 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.056622 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.064733 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.056704 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.064599 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.042858 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.031479 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.808911 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.042867 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.031442 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.808095 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65183 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65167 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1920 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 8039 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55163 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1911 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 8176 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 55031 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.994614 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 17207703 # Number of tag accesses -system.l2c.tags.data_accesses 17207703 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 3810 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 1739 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 419090 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 205762 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 5504 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1909 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 464812 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 143326 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1245952 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 570869 # number of Writeback hits -system.l2c.Writeback_hits::total 570869 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1175 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 561 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1736 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 218 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 106 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 324 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 56320 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 52713 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 109033 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 3810 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 1739 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 419090 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 262082 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 5504 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 1909 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 464812 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 196039 # number of demand (read+write) hits -system.l2c.demand_hits::total 1354985 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 3810 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 1739 # number of overall hits -system.l2c.overall_hits::cpu0.inst 419090 # number of overall hits -system.l2c.overall_hits::cpu0.data 262082 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 5504 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 1909 # number of overall hits -system.l2c.overall_hits::cpu1.inst 464812 # number of overall hits -system.l2c.overall_hits::cpu1.data 196039 # number of overall hits -system.l2c.overall_hits::total 1354985 # number of overall hits +system.l2c.tags.occ_task_id_percent::1024 0.994370 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 17204185 # Number of tag accesses +system.l2c.tags.data_accesses 17204185 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 3944 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 1786 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 419390 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 205855 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 5333 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 1846 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 464270 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 143434 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1245858 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 570720 # number of Writeback hits +system.l2c.Writeback_hits::total 570720 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 1291 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 523 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1814 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 214 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 97 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 311 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 56339 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 52717 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 109056 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 3944 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 1786 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 419390 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 262194 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 5333 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 1846 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 464270 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 196151 # number of demand (read+write) hits +system.l2c.demand_hits::total 1354914 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 3944 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 1786 # number of overall hits +system.l2c.overall_hits::cpu0.inst 419390 # number of overall hits +system.l2c.overall_hits::cpu0.data 262194 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 5333 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 1846 # number of overall hits +system.l2c.overall_hits::cpu1.inst 464270 # number of overall hits +system.l2c.overall_hits::cpu1.data 196151 # number of overall hits +system.l2c.overall_hits::total 1354914 # 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average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 54565.083729 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 67500 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58768.354056 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59868.024895 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 57443.266676 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58734.350238 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59619.458537 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 57194.817495 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -809,64 +810,64 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 119513329 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2535217 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2535217 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 767582 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 767582 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 570869 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 30989 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 17585 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 48574 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 260651 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 260651 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 863496 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1226215 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 6137 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 12691 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 940498 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4601530 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 6236 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 15421 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7672224 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 27215456 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 41348685 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 6964 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 15244 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 30072692 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 39622266 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 7640 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 22032 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 138310979 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 138310979 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 4620420 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4758868690 # Layer occupancy (ticks) +system.toL2Bus.throughput 119643708 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2534658 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2534658 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 767581 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 767581 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 570720 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 30701 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 17545 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 48246 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 260694 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 260694 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 864108 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1226294 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 6184 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 12819 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 939372 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4600756 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 6173 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 15243 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7670949 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 27234976 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 41362613 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 7152 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 15780 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 30036788 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 39599456 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 7388 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 21348 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 138285501 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 138285501 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 4606436 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4757764712 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1923485226 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1924888432 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1752589322 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1752701680 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 4396000 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 4396499 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 8880000 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 8876994 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 2117887474 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.occupancy 2115350205 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 2927028338 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 2925844707 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 0.2 # Layer utilization (%) system.toL2Bus.respLayer8.occupancy 4326000 # Layer occupancy (ticks) system.toL2Bus.respLayer8.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer9.occupancy 9913999 # Layer occupancy (ticks) +system.toL2Bus.respLayer9.occupancy 9906999 # Layer occupancy (ticks) system.toL2Bus.respLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 45398856 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 7671434 # Transaction distribution -system.iobus.trans_dist::ReadResp 7671434 # Transaction distribution -system.iobus.trans_dist::WriteReq 7963 # Transaction distribution -system.iobus.trans_dist::WriteResp 7963 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30550 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8060 # Packet count per connected master and slave (bytes) +system.iobus.throughput 45460895 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7671423 # Transaction distribution +system.iobus.trans_dist::ReadResp 7671423 # Transaction distribution +system.iobus.trans_dist::WriteReq 7962 # Transaction distribution +system.iobus.trans_dist::WriteResp 7962 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30548 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8040 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 742 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 740 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 496 # Packet count per connected master and slave (bytes) @@ -886,14 +887,14 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382666 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382642 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12976128 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 12976128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 15358794 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40319 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 15358770 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40317 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16080 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1484 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1480 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 272 # Cumulative packet size per connected master and slave (bytes) @@ -913,18 +914,18 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390035 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2389989 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 51904512 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 51904512 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 54294547 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 54294547 # Total data (bytes) -system.iobus.reqLayer0.occupancy 21418000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::total 54294501 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 54294501 # Total data (bytes) +system.iobus.reqLayer0.occupancy 21416000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 4036000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 4026000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 377000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 376000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -966,9 +967,9 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 6488064000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374703000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374680000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.2 # Layer utilization (%) -system.iobus.respLayer1.occupancy 16368811750 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 16364250250 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.4 # Layer utilization (%) system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -993,25 +994,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7064335 # DTB read hits -system.cpu0.dtb.read_misses 3758 # DTB read misses -system.cpu0.dtb.write_hits 5649339 # DTB write hits -system.cpu0.dtb.write_misses 802 # DTB write misses +system.cpu0.dtb.read_hits 6063582 # DTB read hits +system.cpu0.dtb.read_misses 3748 # DTB read misses +system.cpu0.dtb.write_hits 5648980 # DTB write hits +system.cpu0.dtb.write_misses 807 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1711 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 1709 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 143 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 140 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7068093 # DTB read accesses -system.cpu0.dtb.write_accesses 5650141 # DTB write accesses +system.cpu0.dtb.read_accesses 6067330 # DTB read accesses +system.cpu0.dtb.write_accesses 5649787 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12713674 # DTB hits -system.cpu0.dtb.misses 4560 # DTB misses -system.cpu0.dtb.accesses 12718234 # DTB accesses +system.cpu0.dtb.hits 11712562 # DTB hits +system.cpu0.dtb.misses 4555 # DTB misses +system.cpu0.dtb.accesses 11717117 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1033,7 +1034,7 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 29562995 # ITB inst hits +system.cpu0.itb.inst_hits 29557926 # ITB inst hits system.cpu0.itb.inst_misses 2205 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -1050,123 +1051,125 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 29565200 # ITB inst accesses -system.cpu0.itb.hits 29562995 # DTB hits +system.cpu0.itb.inst_accesses 29560131 # ITB inst accesses +system.cpu0.itb.hits 29557926 # DTB hits system.cpu0.itb.misses 2205 # DTB misses -system.cpu0.itb.accesses 29565200 # DTB accesses -system.cpu0.numCycles 2391890520 # number of cpu cycles simulated +system.cpu0.itb.accesses 29560131 # DTB accesses +system.cpu0.numCycles 2388624356 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 28864889 # Number of instructions committed -system.cpu0.committedOps 37190899 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 33115613 # Number of integer alu accesses +system.cpu0.committedInsts 28859743 # Number of instructions committed +system.cpu0.committedOps 34624628 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 30439288 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses -system.cpu0.num_func_calls 1241798 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4372441 # number of instructions that are conditional controls -system.cpu0.num_int_insts 33115613 # number of integer instructions +system.cpu0.num_func_calls 1241573 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4174263 # number of instructions that are conditional controls +system.cpu0.num_int_insts 30439288 # number of integer instructions system.cpu0.num_fp_insts 3860 # number of float instructions -system.cpu0.num_int_register_reads 192173380 # number of times the integer registers were read -system.cpu0.num_int_register_writes 36248506 # number of times the integer registers were written +system.cpu0.num_int_register_reads 53589242 # number of times the integer registers were read +system.cpu0.num_int_register_writes 19764786 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written -system.cpu0.num_mem_refs 13380838 # number of memory refs -system.cpu0.num_load_insts 7401595 # Number of load instructions -system.cpu0.num_store_insts 5979243 # Number of store instructions -system.cpu0.num_idle_cycles 2246179687.500122 # Number of idle cycles -system.cpu0.num_busy_cycles 145710832.499878 # Number of busy cycles -system.cpu0.not_idle_fraction 0.060919 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.939081 # Percentage of idle cycles -system.cpu0.Branches 5600259 # Number of branches fetched -system.cpu0.op_class::No_OpClass 14567 0.04% 0.04% # Class of executed instruction -system.cpu0.op_class::IntAlu 24478507 64.56% 64.59% # Class of executed instruction -system.cpu0.op_class::IntMult 43773 0.12% 64.71% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 64.71% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 64.71% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 64.71% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 64.71% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 64.71% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 64.71% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 64.71% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 64.71% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 64.71% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 64.71% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 64.71% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 64.71% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 64.71% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 64.71% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 64.71% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 64.71% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 64.71% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 64.71% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 64.71% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 64.71% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 64.71% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 64.71% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 64.71% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 694 0.00% 64.71% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 64.71% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 64.71% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 64.71% # Class of executed instruction -system.cpu0.op_class::MemRead 7401595 19.52% 84.23% # Class of executed instruction -system.cpu0.op_class::MemWrite 5979243 15.77% 100.00% # Class of executed instruction +system.cpu0.num_cc_register_reads 123695766 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 15045730 # number of times the CC registers were written +system.cpu0.num_mem_refs 12225186 # number of memory refs +system.cpu0.num_load_insts 6245915 # Number of load instructions +system.cpu0.num_store_insts 5979271 # Number of store instructions +system.cpu0.num_idle_cycles 2246427873.598119 # Number of idle cycles +system.cpu0.num_busy_cycles 142196482.401881 # Number of busy cycles +system.cpu0.not_idle_fraction 0.059531 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.940469 # Percentage of idle cycles +system.cpu0.Branches 5599312 # Number of branches fetched +system.cpu0.op_class::No_OpClass 14563 0.04% 0.04% # Class of executed instruction +system.cpu0.op_class::IntAlu 22957352 65.14% 65.18% # Class of executed instruction +system.cpu0.op_class::IntMult 43755 0.12% 65.31% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 65.31% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 65.31% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 65.31% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 65.31% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 65.31% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 65.31% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 65.31% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 65.31% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 65.31% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 65.31% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 65.31% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 65.31% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 65.31% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 65.31% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 65.31% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 65.31% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 65.31% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 65.31% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 65.31% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 65.31% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 65.31% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 65.31% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 65.31% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 692 0.00% 65.31% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 65.31% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 65.31% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 65.31% # Class of executed instruction +system.cpu0.op_class::MemRead 6245915 17.72% 83.03% # Class of executed instruction +system.cpu0.op_class::MemWrite 5979271 16.97% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 37918379 # Class of executed instruction +system.cpu0.op_class::total 35241548 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 46956 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 424861 # number of replacements -system.cpu0.icache.tags.tagsinuse 509.353809 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 29137604 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 425373 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 68.498950 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 76246574000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.353809 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994832 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.994832 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 47055 # number of quiesce instructions executed +system.cpu0.icache.tags.replacements 425168 # number of replacements +system.cpu0.icache.tags.tagsinuse 509.375466 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 29132228 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 425680 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 68.436920 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 75988011000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.375466 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994874 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.994874 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 229 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 188 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 269 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 29988352 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 29988352 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 29137604 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 29137604 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 29137604 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 29137604 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 29137604 # number of overall hits -system.cpu0.icache.overall_hits::total 29137604 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 425374 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 425374 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 425374 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 425374 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 425374 # number of overall misses -system.cpu0.icache.overall_misses::total 425374 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5893447476 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5893447476 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5893447476 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5893447476 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5893447476 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5893447476 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 29562978 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 29562978 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 29562978 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 29562978 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 29562978 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 29562978 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014389 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014389 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014389 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014389 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014389 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014389 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13854.743064 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13854.743064 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13854.743064 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13854.743064 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13854.743064 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13854.743064 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 29983590 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 29983590 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 29132228 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 29132228 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 29132228 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 29132228 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 29132228 # number of overall hits +system.cpu0.icache.overall_hits::total 29132228 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 425681 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 425681 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 425681 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 425681 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 425681 # number of overall misses +system.cpu0.icache.overall_misses::total 425681 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5899766682 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5899766682 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5899766682 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5899766682 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5899766682 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5899766682 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 29557909 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 29557909 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 29557909 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 29557909 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 29557909 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 29557909 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014402 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014402 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014402 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014402 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014402 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014402 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13859.595993 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13859.595993 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13859.595993 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13859.595993 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13859.595993 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13859.595993 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1175,128 +1178,136 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 425374 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 425374 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 425374 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 425374 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 425374 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 425374 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5040497524 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 5040497524 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5040497524 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 5040497524 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5040497524 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 5040497524 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 442131250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 442131250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 442131250 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 442131250 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014389 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014389 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014389 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014389 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014389 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014389 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11849.566556 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11849.566556 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11849.566556 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11849.566556 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11849.566556 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11849.566556 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 425681 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 425681 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 425681 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 425681 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 425681 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 425681 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5046160318 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 5046160318 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5046160318 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 5046160318 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5046160318 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 5046160318 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 442165750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 442165750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 442165750 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 442165750 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014402 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014402 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014402 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014402 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014402 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014402 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11854.323585 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11854.323585 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11854.323585 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11854.323585 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11854.323585 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11854.323585 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 329701 # number of replacements -system.cpu0.dcache.tags.tagsinuse 455.940244 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 12258862 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 330213 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 37.124105 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 671876250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 455.940244 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.890508 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.890508 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 329792 # number of replacements +system.cpu0.dcache.tags.tagsinuse 452.041842 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 11239100 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 330304 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 34.026533 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 671364250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 452.041842 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.882894 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.882894 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 340 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 98 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 342 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 94 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 50852546 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 50852546 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6594319 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6594319 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5344510 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5344510 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 148000 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 148000 # 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miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059469 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047841 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047841 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029978 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.029978 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029978 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.029978 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14490.096577 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14490.096577 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39956.000247 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 39956.000247 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9918.171618 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9918.171618 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5921.519888 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5921.519888 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24250.844941 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 24250.844941 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 24250.844941 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 24250.844941 # average overall miss latency +system.cpu0.dcache.tags.tag_accesses 46848154 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 46848154 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 5514035 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5514035 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5340154 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5340154 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 64966 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 64966 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 148024 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 148024 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149636 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 149636 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10854189 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10854189 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10919155 # number of overall hits +system.cpu0.dcache.overall_hits::total 10919155 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 179189 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 179189 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 145422 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 145422 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 62829 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 62829 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9439 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 9439 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7485 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7485 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 324611 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 324611 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 387440 # number of overall misses +system.cpu0.dcache.overall_misses::total 387440 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2350643732 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 2350643732 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5817567140 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 5817567140 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 94706749 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 94706749 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44450567 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 44450567 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 8168210872 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 8168210872 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 8168210872 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 8168210872 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 5693224 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 5693224 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5485576 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5485576 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 127795 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 127795 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157463 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 157463 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157121 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 157121 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 11178800 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 11178800 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 11306595 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 11306595 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.031474 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.031474 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.026510 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.026510 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.491639 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.491639 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059944 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059944 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047638 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047638 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029038 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.029038 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.034267 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.034267 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13118.236789 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13118.236789 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40004.725145 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 40004.725145 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10033.557474 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10033.557474 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5938.619506 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5938.619506 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25163.074794 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 25163.074794 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 21082.518253 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 21082.518253 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1305,62 +1316,78 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 305583 # number of writebacks -system.cpu0.dcache.writebacks::total 305583 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 227548 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 227548 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141421 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 141421 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9358 # 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mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047828 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047828 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029978 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029978 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029978 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.029978 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12481.522597 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12481.522597 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37747.961682 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37747.961682 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7912.668305 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7912.668305 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3922.945442 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3922.945442 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22165.818790 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22165.818790 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22165.818790 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22165.818790 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 305747 # number of writebacks +system.cpu0.dcache.writebacks::total 305747 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 276 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 276 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 4042 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 4042 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 4318 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 4318 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 4318 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 4318 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 178913 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 178913 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141380 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 141380 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 48508 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 48508 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9439 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9439 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7483 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7483 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 320293 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 320293 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 368801 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 368801 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 1988652518 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 1988652518 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5320324110 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5320324110 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 853626758 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 853626758 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 75777251 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 75777251 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 29483433 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29483433 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7308976628 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 7308976628 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8162603386 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 8162603386 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13564535750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13564535750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1170801000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1170801000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14735336750 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14735336750 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.031426 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.031426 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025773 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025773 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.379577 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.379577 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059944 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059944 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047626 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047626 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028652 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.028652 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032618 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.032618 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11115.192960 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11115.192960 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37631.377210 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37631.377210 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 17597.649006 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17597.649006 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8028.101600 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8028.101600 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3940.055192 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3940.055192 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22819.657713 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22819.657713 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22132.812509 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22132.812509 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1391,25 +1418,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 8317790 # DTB read hits -system.cpu1.dtb.read_misses 3645 # DTB read misses -system.cpu1.dtb.write_hits 5833574 # DTB write hits -system.cpu1.dtb.write_misses 1433 # DTB write misses +system.cpu1.dtb.read_hits 7408792 # DTB read hits +system.cpu1.dtb.read_misses 3640 # DTB read misses +system.cpu1.dtb.write_hits 5825509 # DTB write hits +system.cpu1.dtb.write_misses 1435 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1863 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1866 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 144 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 141 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 8321435 # DTB read accesses -system.cpu1.dtb.write_accesses 5835007 # DTB write accesses +system.cpu1.dtb.read_accesses 7412432 # DTB read accesses +system.cpu1.dtb.write_accesses 5826944 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 14151364 # DTB hits -system.cpu1.dtb.misses 5078 # DTB misses -system.cpu1.dtb.accesses 14156442 # DTB accesses +system.cpu1.dtb.hits 13234301 # DTB hits +system.cpu1.dtb.misses 5075 # DTB misses +system.cpu1.dtb.accesses 13239376 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1431,7 +1458,7 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 33205963 # ITB inst hits +system.cpu1.itb.inst_hits 33190882 # ITB inst hits system.cpu1.itb.inst_misses 2171 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -1448,122 +1475,123 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 33208134 # ITB inst accesses -system.cpu1.itb.hits 33205963 # DTB hits +system.cpu1.itb.inst_accesses 33193053 # ITB inst accesses +system.cpu1.itb.hits 33190882 # DTB hits system.cpu1.itb.misses 2171 # DTB misses -system.cpu1.itb.accesses 33208134 # DTB accesses -system.cpu1.numCycles 2390414629 # number of cpu cycles simulated +system.cpu1.itb.accesses 33193053 # DTB accesses +system.cpu1.numCycles 2387219429 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 32594861 # Number of instructions committed -system.cpu1.committedOps 41116735 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 37639270 # Number of integer alu accesses +system.cpu1.committedInsts 32579955 # Number of instructions committed +system.cpu1.committedOps 38765002 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 35167643 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses -system.cpu1.num_func_calls 962738 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3734786 # number of instructions that are conditional controls -system.cpu1.num_int_insts 37639270 # number of integer instructions +system.cpu1.num_func_calls 962341 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3529676 # number of instructions that are conditional controls +system.cpu1.num_int_insts 35167643 # number of integer instructions system.cpu1.num_fp_insts 6793 # number of float instructions -system.cpu1.num_int_register_reads 218315433 # number of times the integer registers were read -system.cpu1.num_int_register_writes 39777331 # number of times the integer registers were written +system.cpu1.num_int_register_reads 64976079 # number of times the integer registers were read +system.cpu1.num_int_register_writes 23977665 # number of times the integer registers were written system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written -system.cpu1.num_mem_refs 14690124 # number of memory refs -system.cpu1.num_load_insts 8639728 # Number of load instructions -system.cpu1.num_store_insts 6050396 # Number of store instructions -system.cpu1.num_idle_cycles 1874297798.309079 # Number of idle cycles -system.cpu1.num_busy_cycles 516116830.690921 # Number of busy cycles -system.cpu1.not_idle_fraction 0.215911 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.784089 # Percentage of idle cycles -system.cpu1.Branches 4947313 # Number of branches fetched -system.cpu1.op_class::No_OpClass 14267 0.03% 0.03% # Class of executed instruction -system.cpu1.op_class::IntAlu 26968126 64.63% 64.67% # Class of executed instruction -system.cpu1.op_class::IntMult 50231 0.12% 64.79% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 1470 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::MemRead 8639728 20.71% 85.50% # Class of executed instruction -system.cpu1.op_class::MemWrite 6050396 14.50% 100.00% # Class of executed instruction +system.cpu1.num_cc_register_reads 139669414 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 14465628 # number of times the CC registers were written +system.cpu1.num_mem_refs 13620676 # number of memory refs +system.cpu1.num_load_insts 7578910 # Number of load instructions +system.cpu1.num_store_insts 6041766 # Number of store instructions +system.cpu1.num_idle_cycles 1873842319.884373 # Number of idle cycles +system.cpu1.num_busy_cycles 513377109.115627 # Number of busy cycles +system.cpu1.not_idle_fraction 0.215052 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.784948 # Percentage of idle cycles +system.cpu1.Branches 4944984 # Number of branches fetched +system.cpu1.op_class::No_OpClass 14265 0.04% 0.04% # Class of executed instruction +system.cpu1.op_class::IntAlu 25564023 65.13% 65.17% # Class of executed instruction +system.cpu1.op_class::IntMult 50133 0.13% 65.29% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 65.29% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 65.29% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 65.29% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 65.29% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 65.29% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 65.29% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 65.29% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 65.29% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 65.29% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 65.29% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 65.29% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 65.29% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 65.29% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 65.29% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 65.29% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 65.29% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 65.29% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 65.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 65.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 65.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 65.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 65.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 65.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 1482 0.00% 65.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 65.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 65.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 65.30% # Class of executed instruction +system.cpu1.op_class::MemRead 7578910 19.31% 84.61% # Class of executed instruction +system.cpu1.op_class::MemWrite 6041766 15.39% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 41724218 # Class of executed instruction +system.cpu1.op_class::total 39250579 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 44363 # number of quiesce instructions executed -system.cpu1.icache.tags.replacements 469889 # number of replacements -system.cpu1.icache.tags.tagsinuse 478.549875 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 32735558 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 470401 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 69.590749 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 93998064500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 478.549875 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.934668 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.934668 # Average percentage of cache occupancy +system.cpu1.kern.inst.quiesce 44258 # number of quiesce instructions executed +system.cpu1.icache.tags.replacements 469324 # number of replacements +system.cpu1.icache.tags.tagsinuse 478.642267 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 32721042 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 469836 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 69.643539 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 93149552500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 478.642267 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.934848 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.934848 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 448 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 63 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 456 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 56 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 33676360 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 33676360 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 32735558 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 32735558 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 32735558 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 32735558 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 32735558 # number of overall hits -system.cpu1.icache.overall_hits::total 32735558 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 470401 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 470401 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 470401 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 470401 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 470401 # number of overall misses -system.cpu1.icache.overall_misses::total 470401 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6443025224 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 6443025224 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 6443025224 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 6443025224 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 6443025224 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 6443025224 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 33205959 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 33205959 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 33205959 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 33205959 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 33205959 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 33205959 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014166 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.014166 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014166 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.014166 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014166 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.014166 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13696.878246 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13696.878246 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13696.878246 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13696.878246 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13696.878246 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13696.878246 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 33660714 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 33660714 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 32721042 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 32721042 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 32721042 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 32721042 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 32721042 # 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number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 6435695955 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 33190878 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 33190878 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 33190878 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 33190878 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 33190878 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 33190878 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014156 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.014156 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014156 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.014156 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014156 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.014156 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13697.749757 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13697.749757 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13697.749757 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13697.749757 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13697.749757 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13697.749757 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # 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number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5500320776 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5500320776 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5500320776 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5500320776 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7094750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 7094750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 7094750 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 7094750 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014166 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014166 # 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Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 333 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 15 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.679688 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 49486795 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 49486795 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 6952689 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 6952689 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4832965 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4832965 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 82012 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 82012 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 82761 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 82761 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 11785654 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 11785654 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 11785654 # number of overall hits -system.cpu1.dcache.overall_hits::total 11785654 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 170655 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 170655 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 150219 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 150219 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11301 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 11301 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10073 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10073 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 320874 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 320874 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 320874 # number of overall misses -system.cpu1.dcache.overall_misses::total 320874 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2212742497 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2212742497 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 6365695527 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 6365695527 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 97206750 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 97206750 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 52182477 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 52182477 # 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average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8601.606053 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5180.430557 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5180.430557 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 26734.599949 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 26734.599949 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 26734.599949 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 26734.599949 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.tags.replacements 292234 # number of replacements +system.cpu1.dcache.tags.tagsinuse 471.923930 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 11040887 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 292603 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 37.733335 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 84705826250 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 471.923930 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.921726 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.921726 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 369 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 356 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.720703 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 45818347 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 45818347 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 6006097 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 6006097 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4823101 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4823101 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 22483 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 22483 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 81936 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 81936 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 82707 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 82707 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 10829198 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 10829198 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 10851681 # number of overall hits +system.cpu1.dcache.overall_hits::total 10851681 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 144053 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 144053 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 152082 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 152082 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 41875 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 41875 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11222 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 11222 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10064 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10064 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 296135 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 296135 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 338010 # number of overall misses +system.cpu1.dcache.overall_misses::total 338010 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1718496498 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1718496498 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 6437170330 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 6437170330 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 96291249 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 96291249 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 52005971 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 52005971 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 8155666828 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 8155666828 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 8155666828 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 8155666828 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 6150150 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 6150150 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 4975183 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 4975183 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 64358 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 64358 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 93158 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 93158 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92771 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 92771 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 11125333 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 11125333 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 11189691 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 11189691 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023423 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.023423 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030568 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.030568 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.650657 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.650657 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.120462 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.120462 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108482 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108482 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026618 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.026618 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.030207 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.030207 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 11929.612698 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 11929.612698 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 42326.970516 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 42326.970516 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8580.578239 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8580.578239 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5167.524940 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5167.524940 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 27540.367832 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 27540.367832 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24128.477939 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 24128.477939 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 57 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 57 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 265286 # number of writebacks -system.cpu1.dcache.writebacks::total 265286 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170655 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 170655 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 150219 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 150219 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11301 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11301 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10070 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10070 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 320874 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 320874 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 320874 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 320874 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1870737503 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1870737503 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 6042583473 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 6042583473 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 74594250 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 74594250 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32041523 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32041523 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7913320976 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 7913320976 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7913320976 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 7913320976 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168608523750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168608523750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25187494163 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25187494163 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 193796017913 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 193796017913 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023957 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023957 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030145 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030145 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.121109 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.121109 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108473 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108473 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026504 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026504 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026504 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026504 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10962.101919 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10962.101919 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 40225.161085 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 40225.161085 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6600.676931 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6600.676931 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3181.879146 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3181.879146 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 24661.770589 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 24661.770589 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 24661.770589 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 24661.770589 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 264973 # number of writebacks +system.cpu1.dcache.writebacks::total 264973 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 379 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 379 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 2067 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 2067 # number of WriteReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 2446 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 2446 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 2446 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 2446 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 143674 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 143674 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 150015 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 150015 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 26855 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 26855 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11222 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11222 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10062 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10062 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 293689 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 293689 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 320544 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 320544 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1427169251 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1427169251 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 6022199670 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 6022199670 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 445093004 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 445093004 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 73834751 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 73834751 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31881029 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31881029 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7449368921 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 7449368921 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7894461925 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 7894461925 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168604609000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168604609000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25187299088 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25187299088 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 193791908088 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 193791908088 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023361 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023361 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030153 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030153 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.417275 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.417275 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.120462 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.120462 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108461 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108461 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026398 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026398 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.028646 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.028646 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 9933.385658 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 9933.385658 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 40143.983402 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 40143.983402 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16573.934239 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16573.934239 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6579.464534 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6579.464534 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3168.458458 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3168.458458 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 25364.821022 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 25364.821022 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 24628.325363 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 24628.325363 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1779,10 +1831,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 745373562750 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 745373562750 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 745373562750 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 745373562750 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 745112259250 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 745112259250 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 745112259250 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 745112259250 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 41f066b07..563f1978d 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,146 +1,134 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.616230 # Number of seconds simulated -sim_ticks 2616229847000 # Number of ticks simulated -final_tick 2616229847000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.614581 # Number of seconds simulated +sim_ticks 2614581252500 # Number of ticks simulated +final_tick 2614581252500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 375445 # Simulator instruction rate (inst/s) -host_op_rate 477768 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 16316419265 # Simulator tick rate (ticks/s) -host_mem_usage 464828 # Number of bytes of host memory used -host_seconds 160.34 # Real time elapsed on the host -sim_insts 60200042 # Number of instructions simulated -sim_ops 76606857 # Number of ops (including micro ops) simulated +host_inst_rate 331710 # Simulator instruction rate (inst/s) +host_op_rate 396174 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 14409825510 # Simulator tick rate (ticks/s) +host_mem_usage 433940 # Number of bytes of host memory used +host_seconds 181.44 # Real time elapsed on the host +sim_insts 60186875 # Number of instructions simulated +sim_ops 71883476 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 703560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9089944 # Number of bytes read from this memory -system.physmem.bytes_read::total 132477344 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 703560 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 703560 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3706304 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 704520 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9109080 # Number of bytes read from this memory +system.physmem.bytes_read::total 132497440 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 704520 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 704520 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3720512 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6722376 # Number of bytes written to this memory +system.physmem.bytes_written::total 6736584 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 17205 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142066 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15494702 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57911 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 17220 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142355 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15495006 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58133 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811929 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 46893201 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 812151 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46922769 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 122 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 268921 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3474444 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50636737 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 268921 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 268921 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1416658 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1152831 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2569490 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1416658 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 46893201 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 269458 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3483954 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50676352 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 269458 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 269458 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1422986 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1153558 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2576544 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1422986 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46922769 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 122 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 268921 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4627275 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53206227 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15494702 # Number of read requests accepted -system.physmem.writeReqs 811929 # Number of write requests accepted -system.physmem.readBursts 15494702 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 811929 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 991533248 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 127680 # Total number of bytes read from write queue -system.physmem.bytesWritten 6729728 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 132477344 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6722376 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1995 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 706751 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4516 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 967982 # Per bank write bursts -system.physmem.perBankRdBursts::1 967715 # Per bank write bursts -system.physmem.perBankRdBursts::2 967669 # Per bank write bursts -system.physmem.perBankRdBursts::3 967754 # Per bank write bursts -system.physmem.perBankRdBursts::4 974564 # Per bank write bursts -system.physmem.perBankRdBursts::5 968184 # Per bank write bursts -system.physmem.perBankRdBursts::6 967779 # Per bank write bursts -system.physmem.perBankRdBursts::7 967692 # Per bank write bursts -system.physmem.perBankRdBursts::8 968544 # Per bank write bursts -system.physmem.perBankRdBursts::9 968137 # Per bank write bursts -system.physmem.perBankRdBursts::10 967949 # Per bank write bursts -system.physmem.perBankRdBursts::11 967746 # Per bank write bursts -system.physmem.perBankRdBursts::12 967851 # Per bank write bursts -system.physmem.perBankRdBursts::13 967741 # Per bank write bursts -system.physmem.perBankRdBursts::14 967800 # Per bank write bursts -system.physmem.perBankRdBursts::15 967600 # Per bank write bursts -system.physmem.perBankWrBursts::0 6503 # Per bank write bursts -system.physmem.perBankWrBursts::1 6305 # Per bank write bursts -system.physmem.perBankWrBursts::2 6309 # Per bank write bursts -system.physmem.perBankWrBursts::3 6231 # Per bank write bursts -system.physmem.perBankWrBursts::4 6800 # Per bank write bursts -system.physmem.perBankWrBursts::5 6982 # Per bank write bursts -system.physmem.perBankWrBursts::6 6786 # Per bank write bursts -system.physmem.perBankWrBursts::7 6777 # Per bank write bursts -system.physmem.perBankWrBursts::8 7080 # Per bank write bursts -system.physmem.perBankWrBursts::9 6733 # Per bank write bursts -system.physmem.perBankWrBursts::10 6548 # Per bank write bursts -system.physmem.perBankWrBursts::11 6441 # Per bank write bursts -system.physmem.perBankWrBursts::12 6486 # Per bank write bursts -system.physmem.perBankWrBursts::13 6281 # Per bank write bursts -system.physmem.perBankWrBursts::14 6425 # Per bank write bursts -system.physmem.perBankWrBursts::15 6465 # Per bank write bursts +system.physmem.bw_total::cpu.inst 269458 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4637512 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53252896 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15495006 # Number of read requests accepted +system.physmem.writeReqs 812151 # Number of write requests accepted +system.physmem.readBursts 15495006 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 812151 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 991553920 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 126464 # Total number of bytes read from write queue +system.physmem.bytesWritten 6744512 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 132497440 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6736584 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1976 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 706747 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4511 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 968147 # Per bank write bursts +system.physmem.perBankRdBursts::1 967810 # Per bank write bursts +system.physmem.perBankRdBursts::2 967673 # Per bank write bursts +system.physmem.perBankRdBursts::3 967915 # Per bank write bursts +system.physmem.perBankRdBursts::4 974375 # Per bank write bursts +system.physmem.perBankRdBursts::5 968054 # Per bank write bursts +system.physmem.perBankRdBursts::6 967653 # Per bank write bursts +system.physmem.perBankRdBursts::7 967480 # Per bank write bursts +system.physmem.perBankRdBursts::8 968459 # Per bank write bursts +system.physmem.perBankRdBursts::9 968209 # Per bank write bursts +system.physmem.perBankRdBursts::10 967967 # Per bank write bursts +system.physmem.perBankRdBursts::11 967960 # Per bank write bursts +system.physmem.perBankRdBursts::12 967929 # Per bank write bursts +system.physmem.perBankRdBursts::13 967878 # Per bank write bursts +system.physmem.perBankRdBursts::14 967953 # Per bank write bursts +system.physmem.perBankRdBursts::15 967568 # Per bank write bursts +system.physmem.perBankWrBursts::0 6652 # Per bank write bursts +system.physmem.perBankWrBursts::1 6388 # Per bank write bursts +system.physmem.perBankWrBursts::2 6319 # Per bank write bursts +system.physmem.perBankWrBursts::3 6364 # Per bank write bursts +system.physmem.perBankWrBursts::4 6622 # Per bank write bursts +system.physmem.perBankWrBursts::5 6858 # Per bank write bursts +system.physmem.perBankWrBursts::6 6646 # Per bank write bursts +system.physmem.perBankWrBursts::7 6573 # Per bank write bursts +system.physmem.perBankWrBursts::8 7007 # Per bank write bursts +system.physmem.perBankWrBursts::9 6769 # Per bank write bursts +system.physmem.perBankWrBursts::10 6571 # Per bank write bursts +system.physmem.perBankWrBursts::11 6647 # Per bank write bursts +system.physmem.perBankWrBursts::12 6565 # Per bank write bursts +system.physmem.perBankWrBursts::13 6381 # Per bank write bursts +system.physmem.perBankWrBursts::14 6555 # Per bank write bursts +system.physmem.perBankWrBursts::15 6466 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2616225486000 # Total gap between requests +system.physmem.totGap 2614576987500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 6664 # Read request sizes (log2) -system.physmem.readPktSize::3 15335424 # Read request sizes (log2) +system.physmem.readPktSize::2 6644 # Read request sizes (log2) +system.physmem.readPktSize::3 15335434 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 152614 # Read request sizes (log2) +system.physmem.readPktSize::6 152928 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754018 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 57911 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1126567 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 970563 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 976518 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1090618 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 986596 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1051326 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2724005 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2632042 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3421723 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 136210 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 113171 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 104737 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 101252 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 19730 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 18895 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 18668 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 86 # What read queue length does an incoming req see +system.physmem.writePktSize::6 58133 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1126497 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 970808 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 976433 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1092616 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 986699 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1053397 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2722203 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2628336 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3415970 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 138177 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 115073 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 106569 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 103082 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 19658 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 18818 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 18605 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 89 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -171,24 +159,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3804 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3835 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6081 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6095 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6099 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6095 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6098 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6095 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6095 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6095 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6095 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6094 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6095 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6094 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6121 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -220,124 +208,136 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1027354 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 971.683544 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 905.447521 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 204.224200 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22943 2.23% 2.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 22460 2.19% 4.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8461 0.82% 5.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2563 0.25% 5.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2504 0.24% 5.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1783 0.17% 5.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8706 0.85% 6.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 969 0.09% 6.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 956965 93.15% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1027354 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6094 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2542.286675 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 118884.715097 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-524287 6090 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.03% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2.09715e+06-2.62144e+06 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1027240 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 971.825895 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 905.842120 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 203.903622 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22776 2.22% 2.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 22448 2.19% 4.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8450 0.82% 5.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2555 0.25% 5.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2575 0.25% 5.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1819 0.18% 5.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8664 0.84% 6.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 942 0.09% 6.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 957011 93.16% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1027240 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6120 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2531.539869 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 116318.280129 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-524287 6115 99.92% 99.92% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::524288-1.04858e+06 3 0.05% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1.04858e+06-1.57286e+06 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6094 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6094 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.255005 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.227328 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.967528 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2261 37.10% 37.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 29 0.48% 37.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 3794 62.26% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 9 0.15% 99.98% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 6120 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6120 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.219444 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.191199 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.977796 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2386 38.99% 38.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 19 0.31% 39.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 3702 60.49% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 12 0.20% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::20 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6094 # Writes before turning the bus around for reads -system.physmem.totQLat 400062590250 # Total ticks spent queuing -system.physmem.totMemAccLat 690550846500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 77463535000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25822.64 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 6120 # Writes before turning the bus around for reads +system.physmem.totQLat 400457727500 # Total ticks spent queuing +system.physmem.totMemAccLat 690952040000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 77465150000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25847.61 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44572.64 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 378.99 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.57 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 50.64 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.57 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 44597.61 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 379.24 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.58 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 50.68 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.58 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.98 # Data bus utilization in percentage system.physmem.busUtilRead 2.96 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 6.59 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.10 # Average write queue length when enqueuing -system.physmem.readRowHits 14482119 # Number of row buffer hits during reads -system.physmem.writeRowHits 88386 # Number of row buffer hits during writes +system.physmem.avgRdQLen 6.67 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.38 # Average write queue length when enqueuing +system.physmem.readRowHits 14482583 # Number of row buffer hits during reads +system.physmem.writeRowHits 88590 # Number of row buffer hits during writes system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 84.03 # Row buffer hit rate for writes -system.physmem.avgGap 160439.36 # Average gap between requests +system.physmem.writeRowHitRate 84.05 # Row buffer hit rate for writes +system.physmem.avgGap 160333.10 # Average gap between requests system.physmem.pageHitRate 93.41 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2245273695250 # Time in different power states -system.physmem.memoryStateTime::REF 87361560000 # Time in different power states +system.physmem.memoryStateTime::IDLE 2239817846000 # Time in different power states +system.physmem.memoryStateTime::REF 87306440000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 283591722250 # Time in different power states +system.physmem.memoryStateTime::ACT 287452006500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 54122917 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16546592 # Transaction distribution -system.membus.trans_dist::ReadResp 16546592 # Transaction distribution -system.membus.trans_dist::WriteReq 763385 # Transaction distribution -system.membus.trans_dist::WriteResp 763385 # Transaction distribution -system.membus.trans_dist::Writeback 57911 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4516 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4516 # Transaction distribution -system.membus.trans_dist::ReadExReq 132219 # Transaction distribution -system.membus.trans_dist::ReadExResp 132219 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383090 # Packet count per connected master and slave (bytes) +system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 54170150 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16546653 # Transaction distribution +system.membus.trans_dist::ReadResp 16546653 # Transaction distribution +system.membus.trans_dist::WriteReq 763381 # Transaction distribution +system.membus.trans_dist::WriteResp 763381 # Transaction distribution +system.membus.trans_dist::Writeback 58133 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4511 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4511 # Transaction distribution +system.membus.trans_dist::ReadExReq 132457 # Transaction distribution +system.membus.trans_dist::ReadExResp 132457 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383082 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3850 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3840 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1893535 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4280487 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1894355 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4281289 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30670848 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30670848 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34951335 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390546 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 34952137 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390530 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7700 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7680 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16516328 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 18914598 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16550632 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 18948866 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 122683392 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 122683392 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 141597990 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 141597990 # Total data (bytes) +system.membus.tot_pkt_size::total 141632258 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 141632258 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1206224000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1207280500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3616500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3534000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17911182500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17916889500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4951111812 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4952195664 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 37928474750 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 1.4 # Layer utilization (%) +system.membus.respLayer2.occupancy 37921268500 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 1.5 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 47806938 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16518786 # Transaction distribution -system.iobus.trans_dist::ReadResp 16518786 # Transaction distribution -system.iobus.trans_dist::WriteReq 8183 # Transaction distribution -system.iobus.trans_dist::WriteResp 8183 # Transaction distribution +system.iobus.throughput 47837076 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16518783 # Transaction distribution +system.iobus.trans_dist::ReadResp 16518783 # Transaction distribution +system.iobus.trans_dist::WriteReq 8182 # Transaction distribution +system.iobus.trans_dist::WriteResp 8182 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7946 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 534 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7942 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 532 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1040 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) @@ -357,14 +357,14 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2383090 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2383082 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 30670848 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 33053938 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 33053930 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15892 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1068 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15884 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1064 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2080 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) @@ -384,18 +384,18 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390546 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390530 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 122683392 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 125073938 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 125073938 # Total data (bytes) +system.iobus.tot_pkt_size::total 125073922 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 125073922 # Total data (bytes) system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3978000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3976000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 534000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 532000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 527000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 526000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -437,9 +437,9 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 15335424000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374907000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374900000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 38686102250 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 38692913500 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits @@ -465,25 +465,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 14996190 # DTB read hits -system.cpu.dtb.read_misses 7339 # DTB read misses -system.cpu.dtb.write_hits 11230344 # DTB write hits -system.cpu.dtb.write_misses 2214 # DTB write misses +system.cpu.dtb.read_hits 13160128 # DTB read hits +system.cpu.dtb.read_misses 7329 # DTB read misses +system.cpu.dtb.write_hits 11227968 # DTB write hits +system.cpu.dtb.write_misses 2212 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3405 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 3401 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 192 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 189 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 15003529 # DTB read accesses -system.cpu.dtb.write_accesses 11232558 # DTB write accesses +system.cpu.dtb.read_accesses 13167457 # DTB read accesses +system.cpu.dtb.write_accesses 11230180 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 26226534 # DTB hits -system.cpu.dtb.misses 9553 # DTB misses -system.cpu.dtb.accesses 26236087 # DTB accesses +system.cpu.dtb.hits 24388096 # DTB hits +system.cpu.dtb.misses 9541 # DTB misses +system.cpu.dtb.accesses 24397637 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -505,7 +505,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 61493913 # ITB inst hits +system.cpu.itb.inst_hits 61480692 # ITB inst hits system.cpu.itb.inst_misses 4471 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -522,123 +522,125 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 61498384 # ITB inst accesses -system.cpu.itb.hits 61493913 # DTB hits +system.cpu.itb.inst_accesses 61485163 # ITB inst accesses +system.cpu.itb.hits 61480692 # DTB hits system.cpu.itb.misses 4471 # DTB misses -system.cpu.itb.accesses 61498384 # DTB accesses -system.cpu.numCycles 5232459694 # number of cpu cycles simulated +system.cpu.itb.accesses 61485163 # DTB accesses +system.cpu.numCycles 5229162505 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60200042 # Number of instructions committed -system.cpu.committedOps 76606857 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 69208585 # Number of integer alu accesses +system.cpu.committedInsts 60186875 # Number of instructions committed +system.cpu.committedOps 71883476 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 64248071 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses -system.cpu.num_func_calls 2140468 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7948679 # number of instructions that are conditional controls -system.cpu.num_int_insts 69208585 # number of integer instructions +system.cpu.num_func_calls 2139776 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7549008 # number of instructions that are conditional controls +system.cpu.num_int_insts 64248071 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions -system.cpu.num_int_register_reads 401368270 # number of times the integer registers were read -system.cpu.num_int_register_writes 74518872 # number of times the integer registers were written +system.cpu.num_int_register_reads 116109819 # number of times the integer registers were read +system.cpu.num_int_register_writes 42862791 # number of times the integer registers were written system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written -system.cpu.num_mem_refs 27394017 # number of memory refs -system.cpu.num_load_insts 15660224 # Number of load instructions -system.cpu.num_store_insts 11733793 # Number of store instructions -system.cpu.num_idle_cycles 4581582300.610249 # Number of idle cycles -system.cpu.num_busy_cycles 650877393.389751 # Number of busy cycles -system.cpu.not_idle_fraction 0.124392 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.875608 # Percentage of idle cycles -system.cpu.Branches 10308802 # Number of branches fetched +system.cpu.num_cc_register_reads 257767219 # number of times the CC registers were read +system.cpu.num_cc_register_writes 28995131 # number of times the CC registers were written +system.cpu.num_mem_refs 25244051 # number of memory refs +system.cpu.num_load_insts 13512687 # Number of load instructions +system.cpu.num_store_insts 11731364 # Number of store instructions +system.cpu.num_idle_cycles 4584182254.578246 # Number of idle cycles +system.cpu.num_busy_cycles 644980250.421753 # Number of busy cycles +system.cpu.not_idle_fraction 0.123343 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.876657 # Percentage of idle cycles +system.cpu.Branches 10306559 # Number of branches fetched system.cpu.op_class::No_OpClass 28518 0.04% 0.04% # Class of executed instruction -system.cpu.op_class::IntAlu 50389316 64.68% 64.72% # Class of executed instruction -system.cpu.op_class::IntMult 87585 0.11% 64.83% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 64.83% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 64.83% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 64.83% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 64.83% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 64.83% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 64.83% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 64.83% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 64.83% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 64.83% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 64.83% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 64.83% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 64.83% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 64.83% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 64.83% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 64.83% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 64.83% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 64.83% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 64.83% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 64.83% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 64.83% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 64.83% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 64.83% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 64.83% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 2109 0.00% 64.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 64.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.84% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.84% # Class of executed instruction -system.cpu.op_class::MemRead 15660224 20.10% 84.94% # Class of executed instruction -system.cpu.op_class::MemWrite 11733793 15.06% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 47576706 65.23% 65.27% # Class of executed instruction +system.cpu.op_class::IntMult 87551 0.12% 65.39% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 2109 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.39% # Class of executed instruction +system.cpu.op_class::MemRead 13512687 18.53% 83.92% # Class of executed instruction +system.cpu.op_class::MemWrite 11731364 16.08% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 77901545 # Class of executed instruction +system.cpu.op_class::total 72938935 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83017 # number of quiesce instructions executed -system.cpu.icache.tags.replacements 856351 # number of replacements -system.cpu.icache.tags.tagsinuse 510.866135 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 60637050 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 856863 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 70.766330 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 20005377250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.866135 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997785 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997785 # Average percentage of cache occupancy +system.cpu.kern.inst.quiesce 83001 # number of quiesce instructions executed +system.cpu.icache.tags.replacements 855859 # number of replacements +system.cpu.icache.tags.tagsinuse 510.877209 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 60624321 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 856371 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 70.792123 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 19627747250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.877209 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997807 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997807 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 193 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 269 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 194 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 266 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 62350776 # Number of tag accesses -system.cpu.icache.tags.data_accesses 62350776 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 60637050 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 60637050 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 60637050 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 60637050 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 60637050 # number of overall hits -system.cpu.icache.overall_hits::total 60637050 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 856863 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 856863 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 856863 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 856863 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 856863 # number of overall misses -system.cpu.icache.overall_misses::total 856863 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11766560750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11766560750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11766560750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11766560750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11766560750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11766560750 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 61493913 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 61493913 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 61493913 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 61493913 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 61493913 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 61493913 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013934 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.013934 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.013934 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.013934 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.013934 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.013934 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13732.137751 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13732.137751 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13732.137751 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13732.137751 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13732.137751 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13732.137751 # average overall miss latency +system.cpu.icache.tags.tag_accesses 62337063 # Number of tag accesses +system.cpu.icache.tags.data_accesses 62337063 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 60624321 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 60624321 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 60624321 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 60624321 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 60624321 # number of overall hits +system.cpu.icache.overall_hits::total 60624321 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 856371 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 856371 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 856371 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 856371 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 856371 # number of overall misses +system.cpu.icache.overall_misses::total 856371 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11763954000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11763954000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11763954000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11763954000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11763954000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11763954000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 61480692 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 61480692 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 61480692 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 61480692 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 61480692 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 61480692 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013929 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.013929 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.013929 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.013929 # 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number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 183370513825 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 183720021575 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000663 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000642 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012394 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026055 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016453 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991102 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991102 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541620 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541620 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000663 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000642 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012394 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229809 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.103597 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000663 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000642 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012394 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229809 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.103597 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57789.039607 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61852.533388 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59741.578818 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.033770 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.033770 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56765.043853 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56765.043853 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58038.465169 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62306.914894 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60094.597235 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.381215 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.381215 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56954.786346 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56954.786346 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57789.039607 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57112.457457 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57158.658700 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58038.465169 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57321.777973 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57370.690455 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57789.039607 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57112.457457 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57158.658700 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58038.465169 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57321.777973 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57370.690455 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -930,143 +932,166 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 626320 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.875633 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 23655948 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 626832 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37.738897 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 669376250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.875633 # Average occupied blocks per requestor +system.cpu.dcache.tags.replacements 625842 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.875658 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 21786000 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 626354 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 34.782248 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 668864250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.875658 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999757 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999757 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 333 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 105 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 319 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 116 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 97757952 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 97757952 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 13196101 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13196101 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 9972757 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 9972757 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 236378 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 236378 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247784 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247784 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 23168858 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 23168858 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 23168858 # number of overall hits -system.cpu.dcache.overall_hits::total 23168858 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 368196 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 368196 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 250157 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 250157 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 11407 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 11407 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 618353 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 618353 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 618353 # number of overall misses -system.cpu.dcache.overall_misses::total 618353 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5410361250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5410361250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 11271639016 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 11271639016 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 158326750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 158326750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 16682000266 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 16682000266 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 16682000266 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 16682000266 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13564297 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13564297 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10222914 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10222914 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247785 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 247785 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 247784 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 247784 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 23787211 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 23787211 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 23787211 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 23787211 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027144 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.027144 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024470 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.024470 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046036 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046036 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025995 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025995 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.025995 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.025995 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14694.242333 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14694.242333 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45058.259477 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 45058.259477 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13879.788726 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13879.788726 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 26978.118107 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 26978.118107 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 26978.118107 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 26978.118107 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.tags.tag_accesses 90403758 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 90403758 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 11249339 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11249339 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 9965366 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 9965366 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 84253 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 84253 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 236457 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 236457 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247663 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247663 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21214705 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21214705 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21298958 # number of overall hits +system.cpu.dcache.overall_hits::total 21298958 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 294663 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 294663 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 255297 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 255297 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 100106 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 100106 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 11207 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 11207 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 549960 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 549960 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 650066 # number of overall misses +system.cpu.dcache.overall_misses::total 650066 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4040384999 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4040384999 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 11533122261 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 11533122261 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 155182000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 155182000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 15573507260 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 15573507260 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 15573507260 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 15573507260 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 11544002 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 11544002 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10220663 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10220663 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 184359 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 184359 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247664 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 247664 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247663 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247663 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21764665 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21764665 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21949024 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21949024 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025525 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.025525 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024979 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.024979 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.542995 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.542995 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045251 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045251 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.025268 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025268 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.029617 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.029617 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13711.884421 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13711.884421 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45175.314481 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 45175.314481 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13846.881413 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13846.881413 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 28317.527202 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 28317.527202 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23956.809401 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23956.809401 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 58 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 58 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 595396 # number of writebacks -system.cpu.dcache.writebacks::total 595396 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368196 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 368196 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250157 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 250157 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11407 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 11407 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 618353 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 618353 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 618353 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 618353 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4671668750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4671668750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10721268984 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10721268984 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 135458250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 135458250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15392937734 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 15392937734 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15392937734 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 15392937734 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182058578250 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182058578250 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26242925328 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26242925328 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208301503578 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 208301503578 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027144 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027144 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024470 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024470 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046036 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046036 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025995 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025995 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025995 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025995 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12687.994302 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12687.994302 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42858.161011 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42858.161011 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11875.010958 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11875.010958 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24893.447164 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24893.447164 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24893.447164 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24893.447164 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 594981 # number of writebacks +system.cpu.dcache.writebacks::total 594981 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 534 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 534 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 4836 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 4836 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 5370 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 5370 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 5370 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 5370 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 294129 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 294129 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250461 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 250461 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 73479 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 73479 # number of SoftPFReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11207 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 11207 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 544590 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 544590 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 618069 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 618069 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3445567250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3445567250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10763005489 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10763005489 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1228271500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1228271500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 132710000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 132710000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14208572739 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 14208572739 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15436844239 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15436844239 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182058544250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182058544250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26242551425 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26242551425 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208301095675 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 208301095675 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025479 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.025479 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024505 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024505 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.398565 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.398565 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.045251 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.045251 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025022 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025022 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028159 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.028159 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11714.476471 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11714.476471 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42972.780149 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42972.780149 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16715.952857 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16715.952857 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11841.706077 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11841.706077 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26090.403311 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26090.403311 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24975.923787 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24975.923787 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1074,37 +1099,37 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 52982138 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2454896 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2454896 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 763385 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 763385 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 595396 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2928 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2928 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 247229 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 247229 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1725354 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5749970 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12465 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27449 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7515238 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54761180 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 83637066 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14156 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 34872 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 138447274 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 138447274 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 166176 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3009006000 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 52981595 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2453579 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2453579 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 763381 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 763381 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 594981 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2922 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2922 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 247539 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 247539 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1724389 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5748549 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12041 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 26252 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7511231 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54730908 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 83579878 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12460 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 30172 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 138353418 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 138353418 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 171268 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3007873000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1295477750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1294746250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2533767938 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2533153086 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer2.occupancy 8926000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 18731500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 18709500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use @@ -1122,10 +1147,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1759698189250 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1759698189250 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1759698189250 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1759698189250 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1760059764500 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1760059764500 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1760059764500 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1760059764500 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt index 203fb6e65..a9cd1b1ac 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt @@ -1,18 +1,69 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.332812 # Number of seconds simulated -sim_ticks 2332811899500 # Number of ticks simulated -final_tick 2332811899500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.321351 # Number of seconds simulated +sim_ticks 2321351025500 # Number of ticks simulated +final_tick 2321351025500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 860450 # Simulator instruction rate (inst/s) -host_op_rate 1106481 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 33226597982 # Simulator tick rate (ticks/s) -host_mem_usage 465868 # Number of bytes of host memory used -host_seconds 70.21 # Real time elapsed on the host -sim_insts 60411489 # Number of instructions simulated -sim_ops 77685090 # Number of ops (including micro ops) simulated +host_inst_rate 709541 # Simulator instruction rate (inst/s) +host_op_rate 854435 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 27266672116 # Simulator tick rate (ticks/s) +host_mem_usage 431868 # Number of bytes of host memory used +host_seconds 85.14 # Real time elapsed on the host +sim_insts 60406834 # Number of instructions simulated +sim_ops 72742429 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::realview.clcd 110100480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 508168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5844952 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 197248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 3227072 # Number of bytes read from this memory +system.physmem.bytes_read::total 119878240 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 508168 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 197248 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 705416 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3703808 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1462736 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1553080 # Number of bytes written to this memory +system.physmem.bytes_written::total 6719624 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 13762560 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 14152 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 91353 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 3082 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 50423 # Number of read requests responded to by this memory +system.physmem.num_reads::total 13921575 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57872 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 365684 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 388270 # Number of write requests responded to by this memory +system.physmem.num_writes::total 811826 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47429483 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 55 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 83 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 218910 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 2517910 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 84971 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1390170 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51641582 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 218910 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 84971 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 303882 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1595540 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 630123 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 669041 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2894704 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1595540 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47429483 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 55 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 83 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 218910 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3148032 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 84971 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2059211 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54536286 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory @@ -25,218 +76,167 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 9 system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 9 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 492808 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 6490264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 212352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2581696 # Number of bytes read from this memory -system.physmem.bytes_read::total 121450784 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 492808 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 212352 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 705160 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3703360 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1405780 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1610036 # Number of bytes written to this memory -system.physmem.bytes_written::total 6719176 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 13959168 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 13912 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 101446 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 3318 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 40339 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14118188 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57865 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 351445 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 402509 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811819 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47870702 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 55 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 82 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 211251 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 2782163 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 91028 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1106688 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52061970 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 211251 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 91028 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 302279 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1587509 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 602612 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 690170 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2880291 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1587509 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47870702 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 55 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 82 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 211251 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3384775 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 91028 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1796858 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54942261 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 55969742 # Throughput (bytes/s) -system.membus.data_through_bus 130566879 # Total data (bytes) +system.membus.throughput 55568819 # Throughput (bytes/s) +system.membus.data_through_bus 128994735 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 62245 # number of replacements -system.l2c.tags.tagsinuse 50006.493098 # Cycle average of tags in use -system.l2c.tags.total_refs 1678467 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 127630 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.151038 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2316903124500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36901.760029 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.993822 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.993931 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4918.263908 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3148.560878 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2096.452041 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2939.468488 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.563076 # Average percentage of cache occupancy +system.l2c.tags.replacements 62250 # number of replacements +system.l2c.tags.tagsinuse 50005.872632 # Cycle average of tags in use +system.l2c.tags.total_refs 1678480 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 127635 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.150625 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2306278064000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 36900.828862 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.993863 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.993971 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4874.093087 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3539.587837 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2140.383073 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2548.991939 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.563062 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000015 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.075047 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.048043 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.031989 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.044853 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.763039 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.074373 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.054010 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.032660 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.038895 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.763029 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1023 2 # Occupied blocks per task id system.l2c.tags.occ_task_id_blocks::1024 65383 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3589 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 9187 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 52391 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3672 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 9281 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 52128 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.000031 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1024 0.997665 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 17104618 # Number of tag accesses -system.l2c.tags.data_accesses 17104618 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 9008 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3279 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 473060 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 196974 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 4855 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 2031 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 365811 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 169798 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1224816 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 592692 # number of Writeback hits -system.l2c.Writeback_hits::total 592692 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 12 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 14 # number of UpgradeReq hits +system.l2c.tags.tag_accesses 17104797 # Number of tag accesses +system.l2c.tags.data_accesses 17104797 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 8775 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 3263 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 451755 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 188951 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 5151 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 2105 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 387038 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 177833 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1224871 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 592686 # number of Writeback hits +system.l2c.Writeback_hits::total 592686 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 16 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 10 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 63344 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 50394 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 113738 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 9008 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3279 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 473060 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 260318 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 4855 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 2031 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 365811 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 220192 # number of demand (read+write) hits -system.l2c.demand_hits::total 1338554 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 9008 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3279 # number of overall hits -system.l2c.overall_hits::cpu0.inst 473060 # number of overall hits -system.l2c.overall_hits::cpu0.data 260318 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 4855 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 2031 # number of overall hits -system.l2c.overall_hits::cpu1.inst 365811 # number of overall hits -system.l2c.overall_hits::cpu1.data 220192 # number of overall hits -system.l2c.overall_hits::total 1338554 # number of overall hits +system.l2c.ReadExReq_hits::cpu0.data 62028 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 51680 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 113708 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 8775 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 3263 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 451755 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 250979 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 5151 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 2105 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 387038 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 229513 # number of demand (read+write) hits +system.l2c.demand_hits::total 1338579 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 8775 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 3263 # number of overall hits +system.l2c.overall_hits::cpu0.inst 451755 # number of overall hits +system.l2c.overall_hits::cpu0.data 250979 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 5151 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 2105 # number of overall hits +system.l2c.overall_hits::cpu1.inst 387038 # number of overall hits +system.l2c.overall_hits::cpu1.data 229513 # number of overall hits +system.l2c.overall_hits::total 1338579 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 2 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 7286 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 5803 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 3318 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 4068 # number of ReadReq misses -system.l2c.ReadReq_misses::total 20480 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1525 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1394 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2919 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 96422 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 37052 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133474 # number of ReadExReq misses +system.l2c.ReadReq_misses::cpu0.inst 7526 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6094 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 3082 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 3778 # number of ReadReq misses +system.l2c.ReadReq_misses::total 20485 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1505 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1412 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2917 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 86064 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 47413 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 133477 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 2 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 7286 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 102225 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 3318 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 41120 # number of demand (read+write) misses -system.l2c.demand_misses::total 153954 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 7526 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 92158 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 3082 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 51191 # number of demand (read+write) misses +system.l2c.demand_misses::total 153962 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 2 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses -system.l2c.overall_misses::cpu0.inst 7286 # number of overall misses -system.l2c.overall_misses::cpu0.data 102225 # number of overall misses -system.l2c.overall_misses::cpu1.inst 3318 # number of overall misses -system.l2c.overall_misses::cpu1.data 41120 # number of overall misses -system.l2c.overall_misses::total 153954 # number of overall misses -system.l2c.ReadReq_accesses::cpu0.dtb.walker 9010 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 3282 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 480346 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 202777 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 4855 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 2031 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 369129 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 173866 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1245296 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 592692 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 592692 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1537 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1408 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2945 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 159766 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 87446 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 247212 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 9010 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 3282 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 480346 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 362543 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 4855 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 2031 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 369129 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 261312 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1492508 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 9010 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 3282 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 480346 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 362543 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 4855 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 2031 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 369129 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 261312 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1492508 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000222 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000914 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.015168 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.028618 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.008989 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.023397 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.016446 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.992193 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.990057 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.991171 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.603520 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.423713 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.539917 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000222 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000914 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.015168 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.281967 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.008989 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.157360 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.103151 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000222 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000914 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.015168 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.281967 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.008989 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.157360 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.103151 # miss rate for overall accesses +system.l2c.overall_misses::cpu0.inst 7526 # number of overall misses +system.l2c.overall_misses::cpu0.data 92158 # number of overall misses +system.l2c.overall_misses::cpu1.inst 3082 # number of overall misses +system.l2c.overall_misses::cpu1.data 51191 # number of overall misses +system.l2c.overall_misses::total 153962 # number of overall misses +system.l2c.ReadReq_accesses::cpu0.dtb.walker 8777 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 3266 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 459281 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 195045 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 5151 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 2105 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 390120 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 181611 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1245356 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 592686 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 592686 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 1521 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1422 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2943 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 148092 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 99093 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 247185 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 8777 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 3266 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 459281 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 343137 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 5151 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 2105 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 390120 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 280704 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1492541 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 8777 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 3266 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 459281 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 343137 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 5151 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 2105 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 390120 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 280704 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1492541 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000228 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000919 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.016386 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.031244 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.007900 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.020803 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.016449 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.989481 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.992968 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.991165 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.581152 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.478470 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.539988 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000228 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000919 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.016386 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.268575 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.007900 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.182366 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.103154 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000228 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000919 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.016386 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.268575 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.007900 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.182366 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.103154 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -245,8 +245,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 57865 # number of writebacks -system.l2c.writebacks::total 57865 # number of writebacks +system.l2c.writebacks::writebacks 57872 # number of writebacks +system.l2c.writebacks::total 57872 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -254,11 +254,11 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 59119724 # Throughput (bytes/s) -system.toL2Bus.data_through_bus 137915195 # Total data (bytes) +system.toL2Bus.throughput 59409488 # Throughput (bytes/s) +system.toL2Bus.data_through_bus 137910275 # Total data (bytes) system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.iobus.throughput 48895283 # Throughput (bytes/s) -system.iobus.data_through_bus 114063499 # Total data (bytes) +system.iobus.throughput 48459111 # Throughput (bytes/s) +system.iobus.data_through_bus 112490607 # Total data (bytes) system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -282,25 +282,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7929658 # DTB read hits -system.cpu0.dtb.read_misses 6455 # DTB read misses -system.cpu0.dtb.write_hits 6435419 # DTB write hits -system.cpu0.dtb.write_misses 1929 # DTB write misses -system.cpu0.dtb.flush_tlb 2334 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 6811742 # DTB read hits +system.cpu0.dtb.read_misses 6183 # DTB read misses +system.cpu0.dtb.write_hits 6269363 # DTB write hits +system.cpu0.dtb.write_misses 2047 # DTB write misses +system.cpu0.dtb.flush_tlb 2324 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 753 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5575 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 763 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 5527 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 137 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 117 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 240 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7936113 # DTB read accesses -system.cpu0.dtb.write_accesses 6437348 # DTB write accesses +system.cpu0.dtb.perms_faults 235 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 6817925 # DTB read accesses +system.cpu0.dtb.write_accesses 6271410 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14365077 # DTB hits -system.cpu0.dtb.misses 8384 # DTB misses -system.cpu0.dtb.accesses 14373461 # DTB accesses +system.cpu0.dtb.hits 13081105 # DTB hits +system.cpu0.dtb.misses 8230 # DTB misses +system.cpu0.dtb.accesses 13089335 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -322,141 +322,143 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 32541992 # ITB inst hits -system.cpu0.itb.inst_misses 3717 # ITB inst misses +system.cpu0.itb.inst_hits 32133466 # ITB inst hits +system.cpu0.itb.inst_misses 3581 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 2334 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 2324 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 753 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2674 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 763 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 2662 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 32545709 # ITB inst accesses -system.cpu0.itb.hits 32541992 # DTB hits -system.cpu0.itb.misses 3717 # DTB misses -system.cpu0.itb.accesses 32545709 # DTB accesses -system.cpu0.numCycles 4625561989 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 32137047 # ITB inst accesses +system.cpu0.itb.hits 32133466 # DTB hits +system.cpu0.itb.misses 3581 # DTB misses +system.cpu0.itb.accesses 32137047 # DTB accesses +system.cpu0.numCycles 4608021079 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 31996828 # Number of instructions committed -system.cpu0.committedOps 41898003 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 37241416 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5364 # Number of float alu accesses -system.cpu0.num_func_calls 1207166 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4285035 # number of instructions that are conditional controls -system.cpu0.num_int_insts 37241416 # number of integer instructions -system.cpu0.num_fp_insts 5364 # number of float instructions -system.cpu0.num_int_register_reads 192512823 # number of times the integer registers were read -system.cpu0.num_int_register_writes 39713188 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3938 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1428 # number of times the floating registers were written -system.cpu0.num_mem_refs 15011832 # number of memory refs -system.cpu0.num_load_insts 8305325 # Number of load instructions -system.cpu0.num_store_insts 6706507 # Number of store instructions -system.cpu0.num_idle_cycles 4549718927.235470 # Number of idle cycles -system.cpu0.num_busy_cycles 75843061.764530 # Number of busy cycles -system.cpu0.not_idle_fraction 0.016397 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.983603 # Percentage of idle cycles -system.cpu0.Branches 5613326 # Number of branches fetched -system.cpu0.op_class::No_OpClass 16463 0.04% 0.04% # Class of executed instruction -system.cpu0.op_class::IntAlu 26898614 64.08% 64.12% # Class of executed instruction -system.cpu0.op_class::IntMult 45874 0.11% 64.23% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 64.23% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 64.23% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 64.23% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 64.23% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 64.23% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 64.23% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 64.23% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 64.23% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 64.23% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 64.23% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 64.23% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 64.23% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 64.23% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 64.23% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 64.23% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 64.23% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 64.23% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 64.23% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 64.23% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 64.23% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 64.23% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 64.23% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 64.23% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 1340 0.00% 64.24% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 64.24% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 64.24% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 64.24% # Class of executed instruction -system.cpu0.op_class::MemRead 8305325 19.79% 84.02% # Class of executed instruction -system.cpu0.op_class::MemWrite 6706507 15.98% 100.00% # Class of executed instruction +system.cpu0.committedInsts 31639227 # Number of instructions committed +system.cpu0.committedOps 38587883 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 34004805 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5482 # Number of float alu accesses +system.cpu0.num_func_calls 1192523 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4010781 # number of instructions that are conditional controls +system.cpu0.num_int_insts 34004805 # number of integer instructions +system.cpu0.num_fp_insts 5482 # number of float instructions +system.cpu0.num_int_register_reads 62290177 # number of times the integer registers were read +system.cpu0.num_int_register_writes 22551825 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3925 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1558 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 115496065 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 15262729 # number of times the CC registers were written +system.cpu0.num_mem_refs 13528824 # number of memory refs +system.cpu0.num_load_insts 6988108 # Number of load instructions +system.cpu0.num_store_insts 6540716 # Number of store instructions +system.cpu0.num_idle_cycles 4534732444.570566 # Number of idle cycles +system.cpu0.num_busy_cycles 73288634.429434 # Number of busy cycles +system.cpu0.not_idle_fraction 0.015905 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.984095 # Percentage of idle cycles +system.cpu0.Branches 5541899 # Number of branches fetched +system.cpu0.op_class::No_OpClass 16090 0.04% 0.04% # Class of executed instruction +system.cpu0.op_class::IntAlu 25070156 64.84% 64.89% # Class of executed instruction +system.cpu0.op_class::IntMult 45827 0.12% 65.00% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 65.00% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 65.00% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 65.00% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 65.00% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 65.00% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 65.00% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 65.00% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 65.00% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 65.00% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 65.00% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 65.00% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 65.00% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 65.00% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 65.00% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 65.00% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 65.00% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 65.00% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 65.00% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 65.00% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 65.00% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 65.00% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 65.00% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 65.00% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 1368 0.00% 65.01% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 65.01% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 65.01% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 65.01% # Class of executed instruction +system.cpu0.op_class::MemRead 6988108 18.07% 83.08% # Class of executed instruction +system.cpu0.op_class::MemWrite 6540716 16.92% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 41974123 # Class of executed instruction +system.cpu0.op_class::total 38662265 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 82795 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 850590 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.678462 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 60586338 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 851102 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 71.185754 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 5711018500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 444.500524 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 67.177938 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.868165 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.131207 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999372 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 82781 # number of quiesce instructions executed +system.cpu0.icache.tags.replacements 850515 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.689593 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 60581740 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 851027 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 71.186625 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 5455017500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 446.344221 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 65.345372 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.871766 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.127628 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999394 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 78 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 255 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 200 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 62 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 249 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 62288542 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 62288542 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 32063555 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 28522783 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 60586338 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 32063555 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 28522783 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 60586338 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 32063555 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 28522783 # number of overall hits -system.cpu0.icache.overall_hits::total 60586338 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 481227 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 369875 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 851102 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 481227 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 369875 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 851102 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 481227 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 369875 # number of overall misses -system.cpu0.icache.overall_misses::total 851102 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 32544782 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 28892658 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 61437440 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 32544782 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 28892658 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 61437440 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 32544782 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 28892658 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 61437440 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014787 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.012802 # miss rate for ReadReq accesses +system.cpu0.icache.tags.tag_accesses 62283794 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 62283794 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 31676072 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 28905668 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 60581740 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 31676072 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 28905668 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 60581740 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 31676072 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 28905668 # number of overall hits +system.cpu0.icache.overall_hits::total 60581740 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 460107 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 390920 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 851027 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 460107 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 390920 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 851027 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 460107 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 390920 # number of overall misses +system.cpu0.icache.overall_misses::total 851027 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 32136179 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 29296588 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 61432767 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 32136179 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 29296588 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 61432767 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 32136179 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 29296588 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 61432767 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014317 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.013344 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::total 0.013853 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014787 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.012802 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014317 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.013344 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total 0.013853 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014787 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.012802 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014317 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.013344 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.013853 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -467,90 +469,102 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 623343 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.997030 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 23628961 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 623855 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 37.875726 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 21768000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 451.291422 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 60.705608 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.881429 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.118566 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 623329 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.997018 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 21798515 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 623841 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 34.942421 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 21757000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 453.974436 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 58.022582 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.886669 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.113325 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 278 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 291 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 197 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 97635119 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 97635119 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6996051 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 6184476 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13180527 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5775160 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 4187070 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 9962230 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139339 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 96699 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 236038 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 145986 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 101235 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 247221 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 12771211 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 10371546 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 23142757 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 12771211 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 10371546 # number of overall hits -system.cpu0.dcache.overall_hits::total 23142757 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 196129 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 169330 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 365459 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 161303 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 88854 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 250157 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6648 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 4536 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 11184 # number of LoadLockedReq misses -system.cpu0.dcache.demand_misses::cpu0.data 357432 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 258184 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 615616 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 357432 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 258184 # number of overall misses -system.cpu0.dcache.overall_misses::total 615616 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7192180 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 6353806 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 13545986 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5936463 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 4275924 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10212387 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 145987 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 101235 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 247222 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 145986 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 101235 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 247221 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13128643 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 10629730 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 23758373 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13128643 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 10629730 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 23758373 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.027270 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.026650 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.026979 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027172 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.020780 # miss rate for WriteReq accesses +system.cpu0.dcache.tags.tag_accesses 90313265 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 90313265 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 5835707 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 5404504 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 11240211 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5610278 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 4351033 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 9961311 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 52098 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 58749 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 110847 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 136238 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 99769 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 236007 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 142767 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 104429 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 247196 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 11445985 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 9755537 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 21201522 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11498083 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 9814286 # number of overall hits +system.cpu0.dcache.overall_hits::total 21312369 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 155593 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 136452 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 292045 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 149613 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 100515 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 250128 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 32922 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 40499 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 73421 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6530 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 4660 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 11190 # number of LoadLockedReq misses +system.cpu0.dcache.demand_misses::cpu0.data 305206 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 236967 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 542173 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 338128 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 277466 # number of overall misses +system.cpu0.dcache.overall_misses::total 615594 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 5991300 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 5540956 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 11532256 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5759891 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 4451548 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 10211439 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 85020 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 99248 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 184268 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 142768 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 104429 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 247197 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 142767 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 104429 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 247196 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 11751191 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 9992504 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 21743695 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 11836211 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 10091752 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 21927963 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.025970 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.024626 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.025324 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025975 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.022580 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::total 0.024495 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.045538 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.044807 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.045239 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027225 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.024289 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.025912 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.027225 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.024289 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.025912 # miss rate for overall accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.387227 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.408059 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.398447 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.045739 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.044624 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.045268 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025972 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.023714 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.024935 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.028567 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.027494 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.028073 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -559,8 +573,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 592692 # number of writebacks -system.cpu0.dcache.writebacks::total 592692 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 592686 # number of writebacks +system.cpu0.dcache.writebacks::total 592686 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -585,25 +599,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 7038699 # DTB read hits -system.cpu1.dtb.read_misses 4194 # DTB read misses -system.cpu1.dtb.write_hits 4780763 # DTB write hits -system.cpu1.dtb.write_misses 1254 # DTB write misses -system.cpu1.dtb.flush_tlb 2332 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 6327054 # DTB read hits +system.cpu1.dtb.read_misses 4532 # DTB read misses +system.cpu1.dtb.write_hits 4945852 # DTB write hits +system.cpu1.dtb.write_misses 1126 # DTB write misses +system.cpu1.dtb.flush_tlb 2320 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 686 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2928 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 676 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 3028 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 88 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 87 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 212 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 7042893 # DTB read accesses -system.cpu1.dtb.write_accesses 4782017 # DTB write accesses +system.cpu1.dtb.perms_faults 217 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 6331586 # DTB read accesses +system.cpu1.dtb.write_accesses 4946978 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 11819462 # DTB hits -system.cpu1.dtb.misses 5448 # DTB misses -system.cpu1.dtb.accesses 11824910 # DTB accesses +system.cpu1.dtb.hits 11272906 # DTB hits +system.cpu1.dtb.misses 5658 # DTB misses +system.cpu1.dtb.accesses 11278564 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -625,85 +639,87 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 28890998 # ITB inst hits -system.cpu1.itb.inst_misses 2444 # ITB inst misses +system.cpu1.itb.inst_hits 29294834 # ITB inst hits +system.cpu1.itb.inst_misses 2597 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 2332 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 2320 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 686 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1642 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 676 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 1660 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 28893442 # ITB inst accesses -system.cpu1.itb.hits 28890998 # DTB hits -system.cpu1.itb.misses 2444 # DTB misses -system.cpu1.itb.accesses 28893442 # DTB accesses -system.cpu1.numCycles 4282034895 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 29297431 # ITB inst accesses +system.cpu1.itb.hits 29294834 # DTB hits +system.cpu1.itb.misses 2597 # DTB misses +system.cpu1.itb.accesses 29297431 # DTB accesses +system.cpu1.numCycles 141054432 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 28414661 # Number of instructions committed -system.cpu1.committedOps 35787087 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 31892138 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 4905 # Number of float alu accesses -system.cpu1.num_func_calls 928912 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3657531 # number of instructions that are conditional controls -system.cpu1.num_int_insts 31892138 # number of integer instructions -system.cpu1.num_fp_insts 4905 # number of float instructions -system.cpu1.num_int_register_reads 163397724 # number of times the integer registers were read -system.cpu1.num_int_register_writes 34729085 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 3555 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1352 # number of times the floating registers were written -system.cpu1.num_mem_refs 12350589 # number of memory refs -system.cpu1.num_load_insts 7334763 # Number of load instructions -system.cpu1.num_store_insts 5015826 # Number of store instructions -system.cpu1.num_idle_cycles 4212351630.069436 # Number of idle cycles -system.cpu1.num_busy_cycles 69683264.930565 # Number of busy cycles -system.cpu1.not_idle_fraction 0.016273 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.983727 # Percentage of idle cycles -system.cpu1.Branches 4685935 # Number of branches fetched -system.cpu1.op_class::No_OpClass 12055 0.03% 0.03% # Class of executed instruction -system.cpu1.op_class::IntAlu 23438937 65.39% 65.42% # Class of executed instruction -system.cpu1.op_class::IntMult 41906 0.12% 65.54% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 65.54% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 65.54% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 65.54% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 65.54% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 65.54% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 65.54% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 65.54% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 65.54% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 65.54% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 65.54% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 65.54% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 65.54% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 65.54% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 65.54% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 65.54% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 65.54% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 65.54% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 65.54% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 65.54% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 65.54% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 65.54% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 65.54% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 65.54% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 777 0.00% 65.54% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 65.54% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 65.54% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 65.54% # Class of executed instruction -system.cpu1.op_class::MemRead 7334763 20.46% 86.01% # Class of executed instruction -system.cpu1.op_class::MemWrite 5015826 13.99% 100.00% # Class of executed instruction +system.cpu1.committedInsts 28767607 # Number of instructions committed +system.cpu1.committedOps 34154546 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 30186625 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 4787 # Number of float alu accesses +system.cpu1.num_func_calls 943239 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3534203 # number of instructions that are conditional controls +system.cpu1.num_int_insts 30186625 # number of integer instructions +system.cpu1.num_fp_insts 4787 # number of float instructions +system.cpu1.num_int_register_reads 54137170 # number of times the integer registers were read +system.cpu1.num_int_register_writes 20266282 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 3568 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1222 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 102073939 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 13715012 # number of times the CC registers were written +system.cpu1.num_mem_refs 11692450 # number of memory refs +system.cpu1.num_load_insts 6511829 # Number of load instructions +system.cpu1.num_store_insts 5180621 # Number of store instructions +system.cpu1.num_idle_cycles 138966556.858503 # Number of idle cycles +system.cpu1.num_busy_cycles 2087875.141497 # Number of busy cycles +system.cpu1.not_idle_fraction 0.014802 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.985198 # Percentage of idle cycles +system.cpu1.Branches 4756618 # Number of branches fetched +system.cpu1.op_class::No_OpClass 12428 0.04% 0.04% # Class of executed instruction +system.cpu1.op_class::IntAlu 22465876 65.66% 65.70% # Class of executed instruction +system.cpu1.op_class::IntMult 41944 0.12% 65.82% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 65.82% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 65.82% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 65.82% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 65.82% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 65.82% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 65.82% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 65.82% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 65.82% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 65.82% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 65.82% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 65.82% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 65.82% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 65.82% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 65.82% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 65.82% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 65.82% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 65.82% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 65.82% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 65.82% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 65.82% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 65.82% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 65.82% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 65.82% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 745 0.00% 65.82% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 65.82% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 65.82% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 65.82% # Class of executed instruction +system.cpu1.op_class::MemRead 6511829 19.03% 84.86% # Class of executed instruction +system.cpu1.op_class::MemWrite 5180621 15.14% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 35844264 # Class of executed instruction +system.cpu1.op_class::total 34213443 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.iocache.tags.replacements 0 # number of replacements |