diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-11-06 03:26:50 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-11-06 03:26:50 -0500 |
| commit | 324bc9771d1f3129aee87ccb73bcf23ea4c3b60e (patch) | |
| tree | e5ca02cc181b18d2806e30b99da07d6072724988 /tests/quick/fs/10.linux-boot/ref/arm | |
| parent | 337774e192cb9268244d05e828b395060ba1cefb (diff) | |
| download | gem5-324bc9771d1f3129aee87ccb73bcf23ea4c3b60e.tar.xz | |
stats: Update stats to match cache changes
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/arm')
7 files changed, 5261 insertions, 5209 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt index 14fab3b83..7875c5c7b 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.783867 # Nu sim_ticks 2783867052000 # Number of ticks simulated final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1159279 # Simulator instruction rate (inst/s) -host_op_rate 1411237 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 22604281025 # Simulator tick rate (ticks/s) -host_mem_usage 628452 # Number of bytes of host memory used -host_seconds 123.16 # Real time elapsed on the host +host_inst_rate 1280554 # Simulator instruction rate (inst/s) +host_op_rate 1558869 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 24968967598 # Simulator tick rate (ticks/s) +host_mem_usage 628580 # Number of bytes of host memory used +host_seconds 111.49 # Real time elapsed on the host sim_insts 142772879 # Number of instructions simulated sim_ops 173803124 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -209,6 +209,8 @@ system.cpu.itb.accesses 147044108 # DT system.cpu.numCycles 5567737188 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.kern.inst.arm 0 # number of arm instructions executed +system.cpu.kern.inst.quiesce 3083 # number of quiesce instructions executed system.cpu.committedInsts 142772879 # Number of instructions committed system.cpu.committedOps 173803124 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 153162683 # Number of integer alu accesses @@ -266,8 +268,6 @@ system.cpu.op_class::MemWrite 24083392 13.59% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 177219912 # Class of executed instruction -system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 3083 # number of quiesce instructions executed system.cpu.dcache.tags.replacements 819402 # number of replacements system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 53784483 # Total number of references to valid blocks. @@ -400,6 +400,8 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 1699214 # number of writebacks +system.cpu.icache.writebacks::total 1699214 # number of writebacks system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 109913 # number of replacements system.cpu.l2cache.tags.tagsinuse 65155.309141 # Cycle average of tags in use @@ -433,8 +435,10 @@ system.cpu.l2cache.tags.data_accesses 40582495 # Nu system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7601 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 11222 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 682040 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 682040 # number of Writeback hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 682040 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 682040 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 1667206 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 1667206 # number of WritebackClean hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits system.cpu.l2cache.ReadExReq_hits::cpu.data 151146 # number of ReadExReq hits @@ -479,8 +483,10 @@ system.cpu.l2cache.overall_misses::total 181651 # nu system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7608 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3623 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 11231 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 682040 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 682040 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::writebacks 682040 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 682040 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 1667206 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 1667206 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2756 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) @@ -545,8 +551,9 @@ system.cpu.toL2Bus.trans_dist::ReadReq 67802 # Tr system.cpu.toL2Bus.trans_dist::ReadResp 2288542 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 682040 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1797302 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 682040 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1667206 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 130096 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution @@ -559,11 +566,11 @@ system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_ system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 37000 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 7714878 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108818936 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 215520120 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96308833 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 74000 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 205238629 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 311939813 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 182974 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 5319191 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.018482 # Request fanout histogram @@ -683,7 +690,7 @@ system.membus.trans_dist::ReadReq 40087 # Tr system.membus.trans_dist::ReadResp 74202 # Transaction distribution system.membus.trans_dist::WriteReq 27546 # Transaction distribution system.membus.trans_dist::WriteResp 27546 # Transaction distribution -system.membus.trans_dist::Writeback 138139 # Transaction distribution +system.membus.trans_dist::WritebackDirty 138139 # Transaction distribution system.membus.trans_dist::CleanEvict 7977 # Transaction distribution system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index 6c9ee9f79..4554ab525 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -4,70 +4,66 @@ sim_seconds 2.802895 # Nu sim_ticks 2802894699500 # Number of ticks simulated final_tick 2802894699500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1151168 # Simulator instruction rate (inst/s) -host_op_rate 1402682 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 21975358508 # Simulator tick rate (ticks/s) -host_mem_usage 637292 # Number of bytes of host memory used -host_seconds 127.55 # Real time elapsed on the host +host_inst_rate 1249421 # Simulator instruction rate (inst/s) +host_op_rate 1522401 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 23850961642 # Simulator tick rate (ticks/s) +host_mem_usage 637428 # Number of bytes of host memory used +host_seconds 117.52 # Real time elapsed on the host sim_insts 146828240 # Number of instructions simulated sim_ops 178908039 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 512 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1095972 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 9418276 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 148052 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1084052 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1108644 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 9410404 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 153876 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1082576 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11747952 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1095972 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 148052 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1244024 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8467328 # Number of bytes written to this memory +system.physmem.bytes_read::total 11757100 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1108644 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 153876 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1262520 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8452288 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8484892 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8469852 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 8 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 25578 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 147680 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2468 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 16959 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 25776 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 147557 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2559 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 16935 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 192710 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 132302 # Number of write requests responded to by this memory +system.physmem.num_reads::total 192852 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 132067 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 136693 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 160 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 136458 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 183 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 46 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 391014 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3360196 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 52821 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 386762 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 395535 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3357388 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 54899 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 386235 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 343 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4191364 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 391014 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 52821 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 443835 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3020923 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4194628 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 395535 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 54899 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 450434 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3015557 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6252 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3027189 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3020923 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3021823 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3015557 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 183 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 391014 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3366448 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 52821 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 386776 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 395535 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3363640 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 54899 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 386249 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 343 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7218553 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7216451 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -232,6 +228,8 @@ system.cpu0.itb.accesses 97442689 # DT system.cpu0.numCycles 5605791368 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu0.kern.inst.arm 0 # number of arm instructions executed +system.cpu0.kern.inst.quiesce 1968 # number of quiesce instructions executed system.cpu0.committedInsts 95426926 # Number of instructions committed system.cpu0.committedOps 115560427 # Number of ops (including micro ops) committed system.cpu0.num_int_alu_accesses 100762696 # Number of integer alu accesses @@ -289,8 +287,6 @@ system.cpu0.op_class::MemWrite 17276500 14.78% 100.00% # Cl system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::total 116882065 # Class of executed instruction -system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1968 # number of quiesce instructions executed system.cpu0.dcache.tags.replacements 693486 # number of replacements system.cpu0.dcache.tags.tagsinuse 494.853665 # Cycle average of tags in use system.cpu0.dcache.tags.total_refs 35932410 # Total number of references to valid blocks. @@ -309,32 +305,32 @@ system.cpu0.dcache.tags.tag_accesses 74113887 # Nu system.cpu0.dcache.tags.data_accesses 74113887 # Number of data accesses system.cpu0.dcache.ReadReq_hits::cpu0.data 19108541 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 19108541 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 15690436 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 15690436 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 15690389 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 15690389 # number of WriteReq hits system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346093 # number of SoftPFReq hits system.cpu0.dcache.SoftPFReq_hits::total 346093 # number of SoftPFReq hits system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379629 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 379629 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363043 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 363043 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 34798977 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 34798977 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 35145070 # number of overall hits -system.cpu0.dcache.overall_hits::total 35145070 # number of overall hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363050 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 363050 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 34798930 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 34798930 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 35145023 # number of overall hits +system.cpu0.dcache.overall_hits::total 35145023 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 373103 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 373103 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 295749 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 295749 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 295796 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 295796 # number of WriteReq misses system.cpu0.dcache.SoftPFReq_misses::cpu0.data 100321 # number of SoftPFReq misses system.cpu0.dcache.SoftPFReq_misses::total 100321 # number of SoftPFReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6742 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 6742 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18442 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 18442 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 668852 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 668852 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 769173 # number of overall misses -system.cpu0.dcache.overall_misses::total 769173 # number of overall misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18435 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 18435 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 668899 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 668899 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 769220 # number of overall misses +system.cpu0.dcache.overall_misses::total 769220 # number of overall misses system.cpu0.dcache.ReadReq_accesses::cpu0.data 19481644 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 19481644 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 15986185 # number of WriteReq accesses(hits+misses) @@ -351,18 +347,18 @@ system.cpu0.dcache.overall_accesses::cpu0.data 35914243 system.cpu0.dcache.overall_accesses::total 35914243 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019152 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.019152 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018500 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.018500 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018503 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.018503 # miss rate for WriteReq accesses system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224726 # miss rate for SoftPFReq accesses system.cpu0.dcache.SoftPFReq_miss_rate::total 0.224726 # miss rate for SoftPFReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017450 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017450 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048343 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048343 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.018858 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.018858 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021417 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.021417 # miss rate for overall accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048324 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048324 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.018859 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.018859 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021418 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.021418 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -371,8 +367,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 511149 # number of writebacks -system.cpu0.dcache.writebacks::total 511149 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 693486 # number of writebacks +system.cpu0.dcache.writebacks::total 693486 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 1109735 # number of replacements system.cpu0.icache.tags.tagsinuse 511.809992 # Cycle average of tags in use @@ -422,6 +418,8 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.writebacks::writebacks 1109735 # number of writebacks +system.cpu0.icache.writebacks::total 1109735 # number of writebacks system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified @@ -429,131 +427,128 @@ system.cpu0.l2cache.prefetcher.pfBufferHit 0 # system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 252605 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16140.025703 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 3066089 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 268799 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 11.406624 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 1764261500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 8106.193746 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 0.314062 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.090207 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4734.889291 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3298.538396 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.494763 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000019 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000006 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.288995 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.201327 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.985109 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 16181 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 8 # Occupied blocks per task id +system.cpu0.l2cache.tags.replacements 249527 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16129.991654 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 2731505 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 265646 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 10.282500 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 1471234000 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 16127.358870 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 2.556147 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.076637 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.984336 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000156 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000005 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.984497 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 16112 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 298 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5523 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7582 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2694 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000793 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.987610 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 59674327 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 59674327 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7815 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3333 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 11148 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 511149 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 511149 # number of Writeback hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 16 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 16 # number of UpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94430 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 94430 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1065344 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 1065344 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 351762 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 351762 # number of ReadSharedReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 7815 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3333 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1065344 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 446192 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 1522684 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 7815 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3333 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1065344 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 446192 # number of overall hits -system.cpu0.l2cache.overall_hits::total 1522684 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 232 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 124 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 356 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26210 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 26210 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18442 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 18442 # number of SCUpgradeReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 175093 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 175093 # number of ReadExReq misses -system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 44912 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadCleanReq_misses::total 44912 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 128404 # number of ReadSharedReq misses -system.cpu0.l2cache.ReadSharedReq_misses::total 128404 # number of ReadSharedReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 232 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 124 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 44912 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 303497 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 348765 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 232 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 124 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 44912 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 303497 # number of overall misses -system.cpu0.l2cache.overall_misses::total 348765 # number of overall misses -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 8047 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3457 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 11504 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 511149 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 511149 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26226 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 26226 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18442 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 18442 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 147 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 339 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5452 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7536 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2638 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000427 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.983398 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 59699237 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 59699237 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 10182 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4496 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 14678 # number of ReadReq hits +system.cpu0.l2cache.WritebackDirty_hits::writebacks 510201 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackDirty_hits::total 510201 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackClean_hits::writebacks 1265145 # number of WritebackClean hits +system.cpu0.l2cache.WritebackClean_hits::total 1265145 # number of WritebackClean hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94344 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 94344 # number of ReadExReq hits +system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1068613 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadCleanReq_hits::total 1068613 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 352244 # number of ReadSharedReq hits +system.cpu0.l2cache.ReadSharedReq_hits::total 352244 # number of ReadSharedReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 10182 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4496 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 1068613 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 446588 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 1529879 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 10182 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4496 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 1068613 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 446588 # number of overall hits +system.cpu0.l2cache.overall_hits::total 1529879 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 214 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 130 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 344 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26273 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 26273 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18435 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 18435 # number of SCUpgradeReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 175179 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 175179 # number of ReadExReq misses +system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 41643 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadCleanReq_misses::total 41643 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 127922 # number of ReadSharedReq misses +system.cpu0.l2cache.ReadSharedReq_misses::total 127922 # number of ReadSharedReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 214 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 130 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 41643 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 303101 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 345088 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 214 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 130 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 41643 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 303101 # number of overall misses +system.cpu0.l2cache.overall_misses::total 345088 # number of overall misses +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 10396 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4626 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 15022 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::writebacks 510201 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::total 510201 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::writebacks 1265145 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::total 1265145 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26273 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 26273 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18435 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 18435 # number of SCUpgradeReq accesses(hits+misses) system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269523 # number of ReadExReq accesses(hits+misses) system.cpu0.l2cache.ReadExReq_accesses::total 269523 # number of ReadExReq accesses(hits+misses) system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1110256 # number of ReadCleanReq accesses(hits+misses) system.cpu0.l2cache.ReadCleanReq_accesses::total 1110256 # number of ReadCleanReq accesses(hits+misses) system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 480166 # number of ReadSharedReq accesses(hits+misses) system.cpu0.l2cache.ReadSharedReq_accesses::total 480166 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 8047 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3457 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 10396 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4626 # number of demand (read+write) accesses system.cpu0.l2cache.demand_accesses::cpu0.inst 1110256 # number of demand (read+write) accesses system.cpu0.l2cache.demand_accesses::cpu0.data 749689 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 1871449 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 8047 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3457 # number of overall (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 1874967 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 10396 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4626 # number of overall (read+write) accesses system.cpu0.l2cache.overall_accesses::cpu0.inst 1110256 # number of overall (read+write) accesses system.cpu0.l2cache.overall_accesses::cpu0.data 749689 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 1871449 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.028831 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.035869 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.030946 # miss rate for ReadReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999390 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999390 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.overall_accesses::total 1874967 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.020585 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.028102 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.022900 # miss rate for ReadReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.649640 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.649640 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.040452 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.040452 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.267416 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.267416 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.028831 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.035869 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040452 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404831 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.186361 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.028831 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.035869 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040452 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404831 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.186361 # miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.649959 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.649959 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.037508 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.037508 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.266412 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.266412 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.020585 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.028102 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.037508 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404302 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.184050 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.020585 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.028102 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.037508 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404302 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.184050 # miss rate for overall accesses system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -562,50 +557,50 @@ system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 192992 # number of writebacks -system.cpu0.l2cache.writebacks::total 192992 # number of writebacks +system.cpu0.l2cache.writebacks::writebacks 192911 # number of writebacks +system.cpu0.l2cache.writebacks::total 192911 # number of writebacks system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.snoop_filter.tot_requests 3720205 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1860284 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_requests 3720245 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1860324 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27875 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 118049 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 117943 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 106 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 218142 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 215248 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 2894 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu0.toL2Bus.trans_dist::ReadReq 61416 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadResp 1651838 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteReq 28341 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteResp 28341 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 511149 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 1264197 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 26226 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18442 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 44668 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 510201 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 1265145 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 26273 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18435 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 44708 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadExReq 269523 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadExResp 269523 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1110256 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadSharedReq 480166 # Transaction distribution system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3327246 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2395204 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2395284 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12828 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 28808 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 5764086 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 71092472 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80884164 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 5764166 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 140768632 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 92116612 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 25656 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 57616 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 152059908 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 522626 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 4217611 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.044172 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.205599 # Request fanout histogram +system.cpu0.toL2Bus.pkt_size::total 232968516 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 623122 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 4318148 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.066969 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.252635 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 4031417 95.59% 95.59% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 186088 4.41% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 106 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 4031861 93.37% 93.37% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 283393 6.56% 99.93% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 2894 0.07% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 4217611 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 4318148 # Request fanout histogram system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -745,6 +740,8 @@ system.cpu1.itb.accesses 53673309 # DT system.cpu1.numCycles 5605320274 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu1.kern.inst.arm 0 # number of arm instructions executed +system.cpu1.kern.inst.quiesce 2739 # number of quiesce instructions executed system.cpu1.committedInsts 51401314 # Number of instructions committed system.cpu1.committedOps 63347612 # Number of ops (including micro ops) committed system.cpu1.num_int_alu_accesses 56984241 # Number of integer alu accesses @@ -802,8 +799,6 @@ system.cpu1.op_class::MemWrite 7736844 11.82% 100.00% # Cl system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::total 65459464 # Class of executed instruction -system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2739 # number of quiesce instructions executed system.cpu1.dcache.tags.replacements 191938 # number of replacements system.cpu1.dcache.tags.tagsinuse 472.735415 # Cycle average of tags in use system.cpu1.dcache.tags.total_refs 19503509 # Total number of references to valid blocks. @@ -821,32 +816,32 @@ system.cpu1.dcache.tags.tag_accesses 39751979 # Nu system.cpu1.dcache.tags.data_accesses 39751979 # Number of data accesses system.cpu1.dcache.ReadReq_hits::cpu1.data 11858694 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 11858694 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 7397498 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 7397498 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 7397500 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 7397500 # number of WriteReq hits system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50099 # number of SoftPFReq hits system.cpu1.dcache.SoftPFReq_hits::total 50099 # number of SoftPFReq hits system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91447 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_hits::total 91447 # number of LoadLockedReq hits system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72436 # number of StoreCondReq hits system.cpu1.dcache.StoreCondReq_hits::total 72436 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 19256192 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 19256192 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 19306291 # number of overall hits -system.cpu1.dcache.overall_hits::total 19306291 # number of overall hits +system.cpu1.dcache.demand_hits::cpu1.data 19256194 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 19256194 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 19306293 # number of overall hits +system.cpu1.dcache.overall_hits::total 19306293 # number of overall hits system.cpu1.dcache.ReadReq_misses::cpu1.data 136630 # number of ReadReq misses system.cpu1.dcache.ReadReq_misses::total 136630 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 92464 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 92464 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 92462 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 92462 # number of WriteReq misses system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30719 # number of SoftPFReq misses system.cpu1.dcache.SoftPFReq_misses::total 30719 # number of SoftPFReq misses system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5318 # number of LoadLockedReq misses system.cpu1.dcache.LoadLockedReq_misses::total 5318 # number of LoadLockedReq misses system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22543 # number of StoreCondReq misses system.cpu1.dcache.StoreCondReq_misses::total 22543 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 229094 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 229094 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 259813 # number of overall misses -system.cpu1.dcache.overall_misses::total 259813 # number of overall misses +system.cpu1.dcache.demand_misses::cpu1.data 229092 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 229092 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 259811 # number of overall misses +system.cpu1.dcache.overall_misses::total 259811 # number of overall misses system.cpu1.dcache.ReadReq_accesses::cpu1.data 11995324 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_accesses::total 11995324 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::cpu1.data 7489962 # number of WriteReq accesses(hits+misses) @@ -883,8 +878,8 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 120812 # number of writebacks -system.cpu1.dcache.writebacks::total 120812 # number of writebacks +system.cpu1.dcache.writebacks::writebacks 191938 # number of writebacks +system.cpu1.dcache.writebacks::total 191938 # number of writebacks system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.tags.replacements 523373 # number of replacements system.cpu1.icache.tags.tagsinuse 499.711129 # Cycle average of tags in use @@ -933,6 +928,8 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed +system.cpu1.icache.writebacks::writebacks 523373 # number of writebacks +system.cpu1.icache.writebacks::total 523373 # number of writebacks system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified @@ -940,88 +937,86 @@ system.cpu1.l2cache.prefetcher.pfBufferHit 0 # system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 48465 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15315.522353 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1296358 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 63323 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 20.472151 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.replacements 47555 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15235.297156 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 1184961 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 62593 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 18.931206 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 8309.782152 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.119682 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.019591 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3270.237857 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3730.363071 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.507189 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000190 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_blocks::writebacks 15230.950549 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 2.335617 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.010990 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.929623 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000143 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000123 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.199599 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.227683 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.934785 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.929889 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_task_id_blocks::1023 19 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14839 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15019 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 554 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9338 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4947 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 530 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9526 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4963 # Occupied blocks per task id system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001160 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.905701 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 24545002 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 24545002 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3108 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1684 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 4792 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 120812 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 120812 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 8 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 8 # number of UpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19803 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 19803 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 510140 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 510140 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 99386 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 99386 # number of ReadSharedReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3108 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1684 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 510140 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 119189 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 634121 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3108 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1684 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 510140 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 119189 # number of overall hits -system.cpu1.l2cache.overall_hits::total 634121 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 340 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 270 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 610 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28840 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 28840 # number of UpgradeReq misses +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.916687 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 24500378 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 24500378 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3621 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1913 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 5534 # number of ReadReq hits +system.cpu1.l2cache.WritebackDirty_hits::writebacks 121109 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackDirty_hits::total 121109 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackClean_hits::writebacks 583044 # number of WritebackClean hits +system.cpu1.l2cache.WritebackClean_hits::total 583044 # number of WritebackClean hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19763 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 19763 # number of ReadExReq hits +system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 510346 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadCleanReq_hits::total 510346 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 99093 # number of ReadSharedReq hits +system.cpu1.l2cache.ReadSharedReq_hits::total 99093 # number of ReadSharedReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3621 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1913 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 510346 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 118856 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 634736 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3621 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1913 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 510346 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 118856 # number of overall hits +system.cpu1.l2cache.overall_hits::total 634736 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 336 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 271 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 607 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28846 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 28846 # number of UpgradeReq misses system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22543 # number of SCUpgradeReq misses system.cpu1.l2cache.SCUpgradeReq_misses::total 22543 # number of SCUpgradeReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43813 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 43813 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 13745 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 13745 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 73281 # number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 73281 # number of ReadSharedReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 340 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 270 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 13745 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 117094 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 131449 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 340 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 270 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 13745 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 117094 # number of overall misses -system.cpu1.l2cache.overall_misses::total 131449 # number of overall misses -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3448 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 1954 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 5402 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 120812 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 120812 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28848 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 28848 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43853 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 43853 # number of ReadExReq misses +system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 13539 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadCleanReq_misses::total 13539 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 73574 # number of ReadSharedReq misses +system.cpu1.l2cache.ReadSharedReq_misses::total 73574 # number of ReadSharedReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 336 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 271 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 13539 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 117427 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 131573 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 336 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 271 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 13539 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 117427 # number of overall misses +system.cpu1.l2cache.overall_misses::total 131573 # number of overall misses +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3957 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2184 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 6141 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::writebacks 121109 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::total 121109 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::writebacks 583044 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::total 583044 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28846 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 28846 # number of UpgradeReq accesses(hits+misses) system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22543 # number of SCUpgradeReq accesses(hits+misses) system.cpu1.l2cache.SCUpgradeReq_accesses::total 22543 # number of SCUpgradeReq accesses(hits+misses) system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63616 # number of ReadExReq accesses(hits+misses) @@ -1030,39 +1025,39 @@ system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 523885 system.cpu1.l2cache.ReadCleanReq_accesses::total 523885 # number of ReadCleanReq accesses(hits+misses) system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 172667 # number of ReadSharedReq accesses(hits+misses) system.cpu1.l2cache.ReadSharedReq_accesses::total 172667 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3448 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 1954 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3957 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2184 # number of demand (read+write) accesses system.cpu1.l2cache.demand_accesses::cpu1.inst 523885 # number of demand (read+write) accesses system.cpu1.l2cache.demand_accesses::cpu1.data 236283 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 765570 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3448 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 1954 # number of overall (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 766309 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3957 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2184 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.inst 523885 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.data 236283 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 765570 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.098608 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.138178 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.112921 # miss rate for ReadReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.999723 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.999723 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.overall_accesses::total 766309 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.084913 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.124084 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.098844 # miss rate for ReadReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.688710 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.688710 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.026237 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.026237 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.424407 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.424407 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.098608 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.138178 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026237 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.495567 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.171701 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.098608 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.138178 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026237 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.495567 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.171701 # miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.689339 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.689339 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.025843 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.025843 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.426103 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.426103 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.084913 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.124084 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.025843 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.496976 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.171697 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.084913 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.124084 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.025843 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.496976 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.171697 # miss rate for overall accesses system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1071,50 +1066,50 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 32915 # number of writebacks -system.cpu1.l2cache.writebacks::total 32915 # number of writebacks +system.cpu1.l2cache.writebacks::writebacks 32818 # number of writebacks +system.cpu1.l2cache.writebacks::total 32818 # number of writebacks system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.snoop_filter.tot_requests 1533423 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 773258 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_requests 1533421 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 773256 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11158 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 88765 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 88649 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 116 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 165978 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 164041 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1937 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu1.toL2Bus.trans_dist::ReadReq 12749 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadResp 709301 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteReq 2505 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteResp 2505 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 120812 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 583341 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 28848 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 121109 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 583044 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 28846 # Transaction distribution system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22543 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 51391 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 51389 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadExReq 63616 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadExResp 63616 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadCleanReq 523885 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadSharedReq 172667 # Transaction distribution system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1562572 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 776513 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 776509 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6616 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 12078 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2357779 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 33529348 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 22873262 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2357775 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 66454020 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 27282414 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13232 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24156 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 56439998 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 273409 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1745865 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.067447 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.251059 # Request fanout histogram +system.cpu1.toL2Bus.pkt_size::total 93773822 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 347349 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1819817 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.108136 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.313960 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 1628228 93.26% 93.26% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 117521 6.73% 99.99% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 116 0.01% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 1624967 89.29% 89.29% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 192913 10.60% 99.89% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 1937 0.11% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1745865 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 1819817 # Request fanout histogram system.iobus.trans_dist::ReadReq 30995 # Transaction distribution system.iobus.trans_dist::ReadResp 30995 # Transaction distribution system.iobus.trans_dist::WriteReq 59419 # Transaction distribution @@ -1218,183 +1213,175 @@ system.iocache.cache_copies 0 # nu system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 106968 # number of replacements -system.l2c.tags.tagsinuse 62096.352232 # Cycle average of tags in use -system.l2c.tags.total_refs 248810 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 167499 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 1.485442 # Average number of references to valid blocks. +system.l2c.tags.replacements 107037 # number of replacements +system.l2c.tags.tagsinuse 62176.956554 # Cycle average of tags in use +system.l2c.tags.total_refs 241620 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 167464 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 1.442818 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 47767.595021 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.035923 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030795 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 7914.071704 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4068.609194 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.861600 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1612.456889 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 728.691105 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.728876 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000062 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 47954.224141 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.010653 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030815 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 7778.474758 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4056.241083 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1664.556464 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 718.418639 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.731723 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000076 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.120759 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.062082 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000013 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.024604 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.011119 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.947515 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 60524 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1892 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 13030 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 45506 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000107 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.923523 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 5237373 # Number of tag accesses -system.l2c.tags.data_accesses 5237373 # Number of data accesses -system.l2c.Writeback_hits::writebacks 225907 # number of Writeback hits -system.l2c.Writeback_hits::total 225907 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 289 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 71 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 360 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 59 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 8 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 67 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 14099 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 3087 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 17186 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 93 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 64 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 28346 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 76399 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 42 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 35 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 11438 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 11382 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 127799 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 93 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 64 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 28346 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 90498 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 42 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 35 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 11438 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 14469 # number of demand (read+write) hits -system.l2c.demand_hits::total 144985 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 93 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 64 # number of overall hits -system.l2c.overall_hits::cpu0.inst 28346 # number of overall hits -system.l2c.overall_hits::cpu0.data 90498 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 42 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 35 # number of overall hits -system.l2c.overall_hits::cpu1.inst 11438 # number of overall hits -system.l2c.overall_hits::cpu1.data 14469 # number of overall hits -system.l2c.overall_hits::total 144985 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 9985 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 3298 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 13283 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 759 # number of SCUpgradeReq misses +system.l2c.tags.occ_percent::cpu0.inst 0.118690 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.061893 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.025399 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.010962 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.948745 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 60421 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 59 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1839 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 13234 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 45269 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.921951 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 5183068 # Number of tag accesses +system.l2c.tags.data_accesses 5183068 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 225729 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 225729 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0.data 511 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 64 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 575 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 65 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 7 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 72 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 13894 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 3132 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 17026 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 74 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 68 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 24882 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 76059 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 36 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.itb.walker 27 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.inst 11145 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 11759 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 124050 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 74 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 68 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 24882 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 89953 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 36 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 27 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 11145 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 14891 # number of demand (read+write) hits +system.l2c.demand_hits::total 141076 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 74 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 68 # number of overall hits +system.l2c.overall_hits::cpu0.inst 24882 # number of overall hits +system.l2c.overall_hits::cpu0.data 89953 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 36 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 27 # number of overall hits +system.l2c.overall_hits::cpu1.inst 11145 # number of overall hits +system.l2c.overall_hits::cpu1.data 14891 # number of overall hits +system.l2c.overall_hits::total 141076 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 10043 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 3295 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 13338 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 754 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 1178 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1937 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 136565 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 15836 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 152401 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 7 # number of ReadSharedReq misses +system.l2c.SCUpgradeReq_misses::total 1932 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 136525 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 15837 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 152362 # number of ReadExReq misses +system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 8 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 16563 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 11232 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 2303 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 1139 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 31247 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.dtb.walker 7 # number of demand (read+write) misses +system.l2c.ReadSharedReq_misses::cpu0.inst 16761 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 11173 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.inst 2394 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 1126 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 31464 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0.dtb.walker 8 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 16563 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 147797 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 2303 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 16975 # number of demand (read+write) misses -system.l2c.demand_misses::total 183648 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 7 # number of overall misses +system.l2c.demand_misses::cpu0.inst 16761 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 147698 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 2394 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 16963 # number of demand (read+write) misses +system.l2c.demand_misses::total 183826 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 8 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 16563 # number of overall misses -system.l2c.overall_misses::cpu0.data 147797 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 2303 # number of overall misses -system.l2c.overall_misses::cpu1.data 16975 # number of overall misses -system.l2c.overall_misses::total 183648 # number of overall misses -system.l2c.Writeback_accesses::writebacks 225907 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 225907 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 10274 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 3369 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 13643 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 818 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 1186 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.overall_misses::cpu0.inst 16761 # number of overall misses +system.l2c.overall_misses::cpu0.data 147698 # number of overall misses +system.l2c.overall_misses::cpu1.inst 2394 # number of overall misses +system.l2c.overall_misses::cpu1.data 16963 # number of overall misses +system.l2c.overall_misses::total 183826 # number of overall misses +system.l2c.WritebackDirty_accesses::writebacks 225729 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 225729 # number of WritebackDirty accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 10554 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 3359 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 13913 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 819 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 1185 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 2004 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 150664 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 18923 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 169587 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 100 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 66 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.inst 44909 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 87631 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 43 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 35 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.inst 13741 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 12521 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 159046 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 100 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 66 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 44909 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 238295 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 43 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 35 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 13741 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 31444 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 328633 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 100 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 66 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 44909 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 238295 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 43 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 35 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 13741 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 31444 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 328633 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.971871 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.978925 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.973613 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.927873 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.993255 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.966567 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.906421 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.836865 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.898660 # miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.070000 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.030303 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.368812 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.128174 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.023256 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.167601 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.090967 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.196465 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.070000 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.030303 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.368812 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.620227 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.023256 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.167601 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.539849 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.558824 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.070000 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.030303 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.368812 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.620227 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.023256 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.167601 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.539849 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.558824 # miss rate for overall accesses +system.l2c.ReadExReq_accesses::cpu0.data 150419 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 18969 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 169388 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 82 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 70 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.inst 41643 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 87232 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 36 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 27 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.inst 13539 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 12885 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 155514 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 82 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 70 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 41643 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 237651 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 36 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 27 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 13539 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 31854 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 324902 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 82 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 70 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 41643 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 237651 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 36 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 27 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 13539 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 31854 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 324902 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.951582 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.980947 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.958672 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.920635 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.994093 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.964072 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.907631 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.834889 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.899485 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.097561 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.028571 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.402493 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.128084 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.176823 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.087388 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.202323 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.097561 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.028571 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.402493 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.621491 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.176823 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.532523 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.565789 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.097561 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.028571 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.402493 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.621491 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.176823 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.532523 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.565789 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1403,51 +1390,51 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 96112 # number of writebacks -system.l2c.writebacks::total 96112 # number of writebacks +system.l2c.writebacks::writebacks 95877 # number of writebacks +system.l2c.writebacks::total 95877 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 43997 # Transaction distribution -system.membus.trans_dist::ReadResp 75496 # Transaction distribution +system.membus.trans_dist::ReadReq 43996 # Transaction distribution +system.membus.trans_dist::ReadResp 75712 # Transaction distribution system.membus.trans_dist::WriteReq 30846 # Transaction distribution system.membus.trans_dist::WriteResp 30846 # Transaction distribution -system.membus.trans_dist::Writeback 132302 # Transaction distribution -system.membus.trans_dist::CleanEvict 8413 # Transaction distribution -system.membus.trans_dist::UpgradeReq 60363 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 40918 # Transaction distribution -system.membus.trans_dist::UpgradeResp 15656 # Transaction distribution -system.membus.trans_dist::ReadExReq 196047 # Transaction distribution -system.membus.trans_dist::ReadExResp 151965 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 31499 # Transaction distribution +system.membus.trans_dist::WritebackDirty 132067 # Transaction distribution +system.membus.trans_dist::CleanEvict 8465 # Transaction distribution +system.membus.trans_dist::UpgradeReq 60519 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40906 # Transaction distribution +system.membus.trans_dist::UpgradeResp 15741 # Transaction distribution +system.membus.trans_dist::ReadExReq 196031 # Transaction distribution +system.membus.trans_dist::ReadExResp 151891 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 31716 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107876 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13474 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 660257 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 781641 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 660645 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 782029 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109155 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 109155 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 890796 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 891184 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162766 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26948 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17933452 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18123234 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17927560 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18117342 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2332288 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2332288 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20455522 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20449630 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 580848 # Request fanout histogram +system.membus.snoop_fanout::samples 581009 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 580848 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 581009 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 580848 # Request fanout histogram +system.membus.snoop_fanout::total 581009 # Request fanout histogram system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1489,41 +1476,41 @@ system.realview.realview_io.osc_peripheral.clock 41667 system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 874927 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 450220 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 131568 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 9077 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 8809 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 268 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_requests 863003 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 444472 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 128485 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 9552 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 9071 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 481 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.trans_dist::ReadReq 44000 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 305308 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 301629 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 30846 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 30846 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 225907 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 41761 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 60287 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 40985 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 101272 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 213669 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 213669 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 261308 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1153838 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 416020 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1569858 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34685372 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10417714 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 45103086 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 180140 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 1129657 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.285654 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.452250 # Request fanout histogram +system.toL2Bus.trans_dist::WritebackDirty 225729 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 38612 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 60623 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 40978 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 101601 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 213528 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 213528 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 257629 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1143706 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 415843 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1559549 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34428348 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10418866 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 44847214 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 180208 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 1117804 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.282168 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.451010 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 807234 71.46% 71.46% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 322155 28.52% 99.98% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 268 0.02% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 802876 71.83% 71.83% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 314447 28.13% 99.96% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 481 0.04% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 1129657 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 1117804 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index 8e10ef807..deec780f5 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.783867 # Nu sim_ticks 2783867052000 # Number of ticks simulated final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1171566 # Simulator instruction rate (inst/s) -host_op_rate 1426194 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 22843865684 # Simulator tick rate (ticks/s) -host_mem_usage 624228 # Number of bytes of host memory used -host_seconds 121.87 # Real time elapsed on the host +host_inst_rate 1269873 # Simulator instruction rate (inst/s) +host_op_rate 1545867 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 24760705808 # Simulator tick rate (ticks/s) +host_mem_usage 624348 # Number of bytes of host memory used +host_seconds 112.43 # Real time elapsed on the host sim_insts 142772879 # Number of instructions simulated sim_ops 173803124 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -209,6 +209,8 @@ system.cpu.itb.accesses 147044108 # DT system.cpu.numCycles 5567737188 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.kern.inst.arm 0 # number of arm instructions executed +system.cpu.kern.inst.quiesce 3083 # number of quiesce instructions executed system.cpu.committedInsts 142772879 # Number of instructions committed system.cpu.committedOps 173803124 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 153162683 # Number of integer alu accesses @@ -266,8 +268,6 @@ system.cpu.op_class::MemWrite 24083392 13.59% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 177219912 # Class of executed instruction -system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 3083 # number of quiesce instructions executed system.cpu.dcache.tags.replacements 819402 # number of replacements system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 53784483 # Total number of references to valid blocks. @@ -400,6 +400,8 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 1699214 # number of writebacks +system.cpu.icache.writebacks::total 1699214 # number of writebacks system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 109913 # number of replacements system.cpu.l2cache.tags.tagsinuse 65155.309141 # Cycle average of tags in use @@ -433,8 +435,10 @@ system.cpu.l2cache.tags.data_accesses 40582495 # Nu system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7601 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 11222 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 682040 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 682040 # number of Writeback hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 682040 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 682040 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 1667206 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 1667206 # number of WritebackClean hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits system.cpu.l2cache.ReadExReq_hits::cpu.data 151146 # number of ReadExReq hits @@ -479,8 +483,10 @@ system.cpu.l2cache.overall_misses::total 181651 # nu system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7608 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3623 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 11231 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 682040 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 682040 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::writebacks 682040 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 682040 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 1667206 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 1667206 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2756 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) @@ -545,8 +551,9 @@ system.cpu.toL2Bus.trans_dist::ReadReq 67802 # Tr system.cpu.toL2Bus.trans_dist::ReadResp 2288542 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 682040 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1797302 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 682040 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1667206 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 130096 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution @@ -559,11 +566,11 @@ system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_ system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 37000 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 7714878 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108818936 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 215520120 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96308833 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 74000 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 205238629 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 311939813 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 182974 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 5319191 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.018482 # Request fanout histogram @@ -683,7 +690,7 @@ system.membus.trans_dist::ReadReq 40087 # Tr system.membus.trans_dist::ReadResp 74202 # Transaction distribution system.membus.trans_dist::WriteReq 27546 # Transaction distribution system.membus.trans_dist::WriteResp 27546 # Transaction distribution -system.membus.trans_dist::Writeback 138139 # Transaction distribution +system.membus.trans_dist::WritebackDirty 138139 # Transaction distribution system.membus.trans_dist::CleanEvict 7977 # Transaction distribution system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 719058a40..29fa724c5 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,156 +1,160 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.871120 # Number of seconds simulated -sim_ticks 2871119862000 # Number of ticks simulated -final_tick 2871119862000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.871820 # Number of seconds simulated +sim_ticks 2871819744000 # Number of ticks simulated +final_tick 2871819744000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 654504 # Simulator instruction rate (inst/s) -host_op_rate 791691 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 14285860596 # Simulator tick rate (ticks/s) -host_mem_usage 653456 # Number of bytes of host memory used -host_seconds 200.98 # Real time elapsed on the host -sim_insts 131539806 # Number of instructions simulated -sim_ops 159111212 # Number of ops (including micro ops) simulated +host_inst_rate 897166 # Simulator instruction rate (inst/s) +host_op_rate 1085198 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 19602639675 # Simulator tick rate (ticks/s) +host_mem_usage 617092 # Number of bytes of host memory used +host_seconds 146.50 # Real time elapsed on the host +sim_insts 131436334 # Number of instructions simulated +sim_ops 158983282 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1136484 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1250788 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8185344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 157844 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 581136 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 673536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1155428 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1268388 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8606976 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 151764 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 551380 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 345088 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11986604 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1136484 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 157844 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1294328 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8637696 # Number of bytes written to this memory +system.physmem.bytes_read::total 12080624 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1155428 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 151764 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1307192 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8516928 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8655260 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 6 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8534492 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 26211 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 20063 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 127896 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2621 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 9100 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 10524 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 26507 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 20338 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 134484 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2526 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 8636 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 5392 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 196438 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 134964 # Number of write requests responded to by this memory +system.physmem.num_reads::total 197908 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 133077 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 139355 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 134 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 137468 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 156 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 395833 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 435645 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 2850924 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 54976 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 202407 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 234590 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 402333 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 441667 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 2997046 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 22 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 52846 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 191997 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 120164 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 334 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4174888 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 395833 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 54976 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 450809 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3008476 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6104 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4206609 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 402333 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 52846 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 455179 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2965690 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6102 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3014594 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3008476 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 134 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2971806 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2965690 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 156 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 395833 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 441748 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 2850924 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 54976 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 202421 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 234590 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 402333 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 447769 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 2997046 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 22 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 52846 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 192011 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 120164 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 334 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7189482 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 196438 # Number of read requests accepted -system.physmem.writeReqs 139355 # Number of write requests accepted -system.physmem.readBursts 196438 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 139355 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12561984 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 10048 # Total number of bytes read from write queue -system.physmem.bytesWritten 8668288 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 11986604 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8655260 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 157 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 49183 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11406 # Per bank write bursts -system.physmem.perBankRdBursts::1 11655 # Per bank write bursts -system.physmem.perBankRdBursts::2 11752 # Per bank write bursts -system.physmem.perBankRdBursts::3 11575 # Per bank write bursts -system.physmem.perBankRdBursts::4 20585 # Per bank write bursts -system.physmem.perBankRdBursts::5 12467 # Per bank write bursts -system.physmem.perBankRdBursts::6 12095 # Per bank write bursts -system.physmem.perBankRdBursts::7 12222 # Per bank write bursts -system.physmem.perBankRdBursts::8 12044 # Per bank write bursts -system.physmem.perBankRdBursts::9 12120 # Per bank write bursts -system.physmem.perBankRdBursts::10 11627 # Per bank write bursts -system.physmem.perBankRdBursts::11 11103 # Per bank write bursts -system.physmem.perBankRdBursts::12 11588 # Per bank write bursts -system.physmem.perBankRdBursts::13 11719 # Per bank write bursts -system.physmem.perBankRdBursts::14 10853 # Per bank write bursts -system.physmem.perBankRdBursts::15 11470 # Per bank write bursts -system.physmem.perBankWrBursts::0 8250 # Per bank write bursts -system.physmem.perBankWrBursts::1 8603 # Per bank write bursts -system.physmem.perBankWrBursts::2 8782 # Per bank write bursts -system.physmem.perBankWrBursts::3 8359 # Per bank write bursts -system.physmem.perBankWrBursts::4 8401 # Per bank write bursts -system.physmem.perBankWrBursts::5 9093 # Per bank write bursts -system.physmem.perBankWrBursts::6 8866 # Per bank write bursts -system.physmem.perBankWrBursts::7 8828 # Per bank write bursts -system.physmem.perBankWrBursts::8 8708 # Per bank write bursts -system.physmem.perBankWrBursts::9 8716 # Per bank write bursts -system.physmem.perBankWrBursts::10 8411 # Per bank write bursts -system.physmem.perBankWrBursts::11 8212 # Per bank write bursts -system.physmem.perBankWrBursts::12 8400 # Per bank write bursts -system.physmem.perBankWrBursts::13 8108 # Per bank write bursts -system.physmem.perBankWrBursts::14 7766 # Per bank write bursts -system.physmem.perBankWrBursts::15 7939 # Per bank write bursts +system.physmem.bw_total::total 7178416 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 197908 # Number of read requests accepted +system.physmem.writeReqs 137468 # Number of write requests accepted +system.physmem.readBursts 197908 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 137468 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12655744 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 10368 # Total number of bytes read from write queue +system.physmem.bytesWritten 8547392 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12080624 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8534492 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 162 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 3895 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 64406 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11744 # Per bank write bursts +system.physmem.perBankRdBursts::1 11857 # Per bank write bursts +system.physmem.perBankRdBursts::2 11924 # Per bank write bursts +system.physmem.perBankRdBursts::3 11590 # Per bank write bursts +system.physmem.perBankRdBursts::4 20227 # Per bank write bursts +system.physmem.perBankRdBursts::5 11881 # Per bank write bursts +system.physmem.perBankRdBursts::6 12481 # Per bank write bursts +system.physmem.perBankRdBursts::7 12857 # Per bank write bursts +system.physmem.perBankRdBursts::8 12335 # Per bank write bursts +system.physmem.perBankRdBursts::9 12711 # Per bank write bursts +system.physmem.perBankRdBursts::10 11891 # Per bank write bursts +system.physmem.perBankRdBursts::11 11251 # Per bank write bursts +system.physmem.perBankRdBursts::12 11484 # Per bank write bursts +system.physmem.perBankRdBursts::13 11698 # Per bank write bursts +system.physmem.perBankRdBursts::14 10879 # Per bank write bursts +system.physmem.perBankRdBursts::15 10936 # Per bank write bursts +system.physmem.perBankWrBursts::0 8367 # Per bank write bursts +system.physmem.perBankWrBursts::1 8665 # Per bank write bursts +system.physmem.perBankWrBursts::2 8799 # Per bank write bursts +system.physmem.perBankWrBursts::3 8189 # Per bank write bursts +system.physmem.perBankWrBursts::4 7964 # Per bank write bursts +system.physmem.perBankWrBursts::5 8309 # Per bank write bursts +system.physmem.perBankWrBursts::6 8959 # Per bank write bursts +system.physmem.perBankWrBursts::7 8936 # Per bank write bursts +system.physmem.perBankWrBursts::8 8719 # Per bank write bursts +system.physmem.perBankWrBursts::9 9048 # Per bank write bursts +system.physmem.perBankWrBursts::10 8437 # Per bank write bursts +system.physmem.perBankWrBursts::11 8181 # Per bank write bursts +system.physmem.perBankWrBursts::12 8223 # Per bank write bursts +system.physmem.perBankWrBursts::13 7876 # Per bank write bursts +system.physmem.perBankWrBursts::14 7572 # Per bank write bursts +system.physmem.perBankWrBursts::15 7309 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 25 # Number of times write queue was full causing retry -system.physmem.totGap 2871119474000 # Total gap between requests +system.physmem.numWrRetry 22 # Number of times write queue was full causing retry +system.physmem.totGap 2871819304000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 9731 # Read request sizes (log2) +system.physmem.readPktSize::2 9732 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 186679 # Read request sizes (log2) +system.physmem.readPktSize::6 188148 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 134964 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 137894 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 15510 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 10092 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 8580 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6925 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5397 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 4544 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 3804 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3324 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 83 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 55 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 37 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 17 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 133077 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 139055 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 15611 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 10231 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8666 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6945 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5399 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4517 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 3779 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3330 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 87 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 68 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 39 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -180,161 +184,163 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2816 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3322 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4567 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5041 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6254 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6921 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7905 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7932 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8891 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 9048 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10505 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8560 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8477 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9734 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 381 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 270 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2831 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4365 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5073 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6821 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8728 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8917 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8948 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10581 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8534 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8466 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9640 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8066 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6906 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 375 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 119 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 63 # What write queue length does an incoming req see system.physmem.wrQLenPdf::53 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 68 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 87652 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 242.210195 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 137.335340 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 303.154059 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 46068 52.56% 52.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17715 20.21% 72.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6262 7.14% 79.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3427 3.91% 83.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2480 2.83% 86.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1647 1.88% 88.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 825 0.94% 89.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 930 1.06% 90.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8298 9.47% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 87652 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6626 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 29.622698 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 552.814463 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6624 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::54 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 33 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 79 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 87485 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 242.362371 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 136.946957 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 304.393854 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 46305 52.93% 52.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17523 20.03% 72.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6069 6.94% 79.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3389 3.87% 83.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2483 2.84% 86.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1521 1.74% 88.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 858 0.98% 89.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 952 1.09% 90.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8385 9.58% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 87485 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6517 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 30.342949 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 586.244331 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6515 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6626 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6626 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.440990 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.878741 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.359150 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5426 81.89% 81.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 462 6.97% 88.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 72 1.09% 89.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 157 2.37% 92.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 32 0.48% 92.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 137 2.07% 94.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 41 0.62% 95.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 17 0.26% 95.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 26 0.39% 96.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 21 0.32% 96.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 8 0.12% 96.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 4 0.06% 96.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 152 2.29% 98.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 5 0.08% 99.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 3 0.05% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 25 0.38% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 4 0.06% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.02% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.02% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.02% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 4 0.06% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 3 0.05% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.02% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.02% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 13 0.20% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.03% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 2 0.03% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.03% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6626 # Writes before turning the bus around for reads -system.physmem.totQLat 4505900396 # Total ticks spent queuing -system.physmem.totMemAccLat 8186169146 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 981405000 # Total ticks spent in databus transfers -system.physmem.avgQLat 22956.38 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::47104-49151 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6517 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6517 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.493018 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.920871 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.293044 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5326 81.72% 81.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 466 7.15% 88.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 68 1.04% 89.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 161 2.47% 92.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 25 0.38% 92.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 129 1.98% 94.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 31 0.48% 95.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 20 0.31% 95.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 32 0.49% 96.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 18 0.28% 96.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 9 0.14% 96.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 7 0.11% 96.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 150 2.30% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 6 0.09% 98.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 7 0.11% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 24 0.37% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 5 0.08% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 4 0.06% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 3 0.05% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.02% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 3 0.05% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.02% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 3 0.05% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.02% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 9 0.14% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6517 # Writes before turning the bus around for reads +system.physmem.totQLat 4471540489 # Total ticks spent queuing +system.physmem.totMemAccLat 8179277989 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 988730000 # Total ticks spent in databus transfers +system.physmem.avgQLat 22612.55 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 41706.38 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.38 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.02 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.17 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.01 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 41362.55 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.41 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.98 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.21 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.97 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.18 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.23 # Average write queue length when enqueuing -system.physmem.readRowHits 163849 # Number of row buffer hits during reads -system.physmem.writeRowHits 80221 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.48 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 59.22 # Row buffer hit rate for writes -system.physmem.avgGap 8550266.01 # Average gap between requests -system.physmem.pageHitRate 73.57 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 338884560 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 184907250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 809296800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 448299360 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 187527431520 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 85706052435 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1647489846750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1922504718675 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.601510 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2740606830696 # Time in different power states -system.physmem_0.memoryStateTime::REF 95872920000 # Time in different power states +system.physmem.avgRdQLen 1.13 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.95 # Average write queue length when enqueuing +system.physmem.readRowHits 164996 # Number of row buffer hits during reads +system.physmem.writeRowHits 78817 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.44 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 59.01 # Row buffer hit rate for writes +system.physmem.avgGap 8562983.95 # Average gap between requests +system.physmem.pageHitRate 73.59 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 341636400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 186408750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 815575800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 441858240 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 187573201920 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 85932696690 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1647711485250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1923002863050 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.611581 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2740967841659 # Time in different power states +system.physmem_0.memoryStateTime::REF 95896320000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 34639965804 # Time in different power states +system.physmem_0.memoryStateTime::ACT 34954258341 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 323764560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 176657250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 721687200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 429364800 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 187527431520 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 84711391605 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1648362356250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1922252653185 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.513716 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2742063716846 # Time in different power states -system.physmem_1.memoryStateTime::REF 95872920000 # Time in different power states +system.physmem_1.actEnergy 319750200 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 174466875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 726835200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 423565200 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 187573201920 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 85000293540 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1648529382750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1922747495685 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.522659 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2742335596201 # Time in different power states +system.physmem_1.memoryStateTime::REF 95896320000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 33181034404 # Time in different power states +system.physmem_1.memoryStateTime::ACT 33587665799 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory @@ -390,56 +396,57 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 5019 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 5019 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1041 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 3978 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 5019 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 5019 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 5019 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 4056 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 10869.452663 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 9826.177645 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 7625.006320 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-32767 4042 99.65% 99.65% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-65535 10 0.25% 99.90% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-163839 3 0.07% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::294912-327679 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 4056 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walks 8797 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 8797 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1607 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 7190 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 8797 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 8797 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 8797 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 7279 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 12032.971562 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 11059.534367 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 6527.254746 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-32767 7242 99.49% 99.49% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-65535 32 0.44% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-163839 3 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::163840-196607 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 7279 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walksPending::samples 1809726500 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 1809726500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 1809726500 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 3032 74.75% 74.75% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1024 25.25% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 4056 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 5019 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 5719 78.57% 78.57% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1560 21.43% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 7279 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 8797 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 5019 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4056 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 8797 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7279 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4056 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 9075 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7279 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 16076 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 23515104 # DTB read hits -system.cpu0.dtb.read_misses 4346 # DTB read misses -system.cpu0.dtb.write_hits 17278792 # DTB write hits -system.cpu0.dtb.write_misses 673 # DTB write misses +system.cpu0.dtb.read_hits 25745693 # DTB read hits +system.cpu0.dtb.read_misses 7581 # DTB read misses +system.cpu0.dtb.write_hits 19246585 # DTB write hits +system.cpu0.dtb.write_misses 1216 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2434 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 3751 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1554 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 1856 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 187 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 23519450 # DTB read accesses -system.cpu0.dtb.write_accesses 17279465 # DTB write accesses +system.cpu0.dtb.perms_faults 321 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 25753274 # DTB read accesses +system.cpu0.dtb.write_accesses 19247801 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 40793896 # DTB hits -system.cpu0.dtb.misses 5019 # DTB misses -system.cpu0.dtb.accesses 40798915 # DTB accesses +system.cpu0.dtb.hits 44992278 # DTB hits +system.cpu0.dtb.misses 8797 # DTB misses +system.cpu0.dtb.accesses 45001075 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -469,38 +476,39 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 2305 # Table walker walks requested -system.cpu0.itb.walker.walksShort 2305 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 237 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 2068 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 2305 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 2305 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 2305 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 1509 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 10774.022531 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 9696.406116 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 7256.111559 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-16383 1436 95.16% 95.16% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-32767 61 4.04% 99.20% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-49151 10 0.66% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.07% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::163840-180223 1 0.07% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 1509 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 3674 # Table walker walks requested +system.cpu0.itb.walker.walksShort 3674 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 320 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3354 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 3674 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 3674 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 3674 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2576 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 12417.119565 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 11509.653289 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 6255.531301 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-16383 2268 88.04% 88.04% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-32767 277 10.75% 98.80% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-49151 28 1.09% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::49152-65535 1 0.04% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::163840-180223 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2576 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples 1809154500 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 1809154500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 1809154500 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 1272 84.29% 84.29% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 237 15.71% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 1509 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 2256 87.58% 87.58% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 320 12.42% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2576 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2305 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2305 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3674 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3674 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 1509 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 1509 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 3814 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 111711640 # ITB inst hits -system.cpu0.itb.inst_misses 2305 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2576 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2576 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 6250 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 121573780 # ITB inst hits +system.cpu0.itb.inst_misses 3674 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -509,178 +517,179 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1402 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2371 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 111713945 # ITB inst accesses -system.cpu0.itb.hits 111711640 # DTB hits -system.cpu0.itb.misses 2305 # DTB misses -system.cpu0.itb.accesses 111713945 # DTB accesses -system.cpu0.numCycles 5741309822 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 121577454 # ITB inst accesses +system.cpu0.itb.hits 121573780 # DTB hits +system.cpu0.itb.misses 3674 # DTB misses +system.cpu0.itb.accesses 121577454 # DTB accesses +system.cpu0.numCycles 5743639488 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 108455216 # Number of instructions committed -system.cpu0.committedOps 130919966 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 115934267 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 4495 # Number of float alu accesses -system.cpu0.num_func_calls 12371356 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 14793634 # number of instructions that are conditional controls -system.cpu0.num_int_insts 115934267 # number of integer instructions -system.cpu0.num_fp_insts 4495 # number of float instructions -system.cpu0.num_int_register_reads 213655151 # number of times the integer registers were read -system.cpu0.num_int_register_writes 80737315 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3581 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 916 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 474775860 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 48809609 # number of times the CC registers were written -system.cpu0.num_mem_refs 41877995 # number of memory refs -system.cpu0.num_load_insts 23749275 # Number of load instructions -system.cpu0.num_store_insts 18128720 # Number of store instructions -system.cpu0.num_idle_cycles 5480212444.901863 # Number of idle cycles -system.cpu0.num_busy_cycles 261097377.098137 # Number of busy cycles -system.cpu0.not_idle_fraction 0.045477 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.954523 # Percentage of idle cycles -system.cpu0.Branches 27818534 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2172 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 92606456 68.80% 68.80% # Class of executed instruction -system.cpu0.op_class::IntMult 105045 0.08% 68.88% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 7793 0.01% 68.89% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 68.89% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.89% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.89% # Class of executed instruction -system.cpu0.op_class::MemRead 23749275 17.64% 86.53% # Class of executed instruction -system.cpu0.op_class::MemWrite 18128720 13.47% 100.00% # Class of executed instruction +system.cpu0.kern.inst.arm 0 # number of arm instructions executed +system.cpu0.kern.inst.quiesce 1907 # number of quiesce instructions executed +system.cpu0.committedInsts 117757184 # Number of instructions committed +system.cpu0.committedOps 142314769 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 125928094 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 11483 # Number of float alu accesses +system.cpu0.num_func_calls 12772213 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 16007583 # number of instructions that are conditional controls +system.cpu0.num_int_insts 125928094 # number of integer instructions +system.cpu0.num_fp_insts 11483 # number of float instructions +system.cpu0.num_int_register_reads 231704258 # number of times the integer registers were read +system.cpu0.num_int_register_writes 87445622 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 8771 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 2716 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 515435615 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 53492348 # number of times the CC registers were written +system.cpu0.num_mem_refs 46148278 # number of memory refs +system.cpu0.num_load_insts 26004695 # Number of load instructions +system.cpu0.num_store_insts 20143583 # Number of store instructions +system.cpu0.num_idle_cycles 5456012961.442100 # Number of idle cycles +system.cpu0.num_busy_cycles 287626526.557900 # Number of busy cycles +system.cpu0.not_idle_fraction 0.050077 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.949923 # Percentage of idle cycles +system.cpu0.Branches 29545337 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2315 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 99836654 68.33% 68.33% # Class of executed instruction +system.cpu0.op_class::IntMult 112117 0.08% 68.41% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 8321 0.01% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::MemRead 26004695 17.80% 86.21% # Class of executed instruction +system.cpu0.op_class::MemWrite 20143583 13.79% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 134599461 # Class of executed instruction -system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1796 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 588364 # number of replacements -system.cpu0.dcache.tags.tagsinuse 493.639030 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 40011095 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 588715 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 67.963437 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 1836356000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 493.639030 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.964139 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.964139 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 351 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 314 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 37 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.685547 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 82121594 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 82121594 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 22367728 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 22367728 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 16608644 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 16608644 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 300494 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 300494 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 340955 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 340955 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 337105 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 337105 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 38976372 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 38976372 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 39276866 # number of overall hits -system.cpu0.dcache.overall_hits::total 39276866 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 340778 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 340778 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 289444 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 289444 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 113643 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 113643 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20322 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 20322 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19364 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 19364 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 630222 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 630222 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 743865 # number of overall misses -system.cpu0.dcache.overall_misses::total 743865 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4892226500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 4892226500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5708519500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 5708519500 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 329935000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 329935000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 454112500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 454112500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1575000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1575000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 10600746000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 10600746000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 10600746000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 10600746000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 22708506 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 22708506 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 16898088 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 16898088 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 414137 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 414137 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 361277 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 361277 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 356469 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 356469 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 39606594 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 39606594 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 40020731 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 40020731 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.015007 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.015007 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017129 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.017129 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.274409 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.274409 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056250 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056250 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.054322 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.054322 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.015912 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.015912 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.018587 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.018587 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14356.051447 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14356.051447 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19722.362530 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 19722.362530 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16235.360693 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16235.360693 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23451.378847 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23451.378847 # average StoreCondReq miss latency +system.cpu0.op_class::total 146107685 # Class of executed instruction +system.cpu0.dcache.tags.replacements 732170 # number of replacements +system.cpu0.dcache.tags.tagsinuse 488.694805 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 44080957 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 732682 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 60.163832 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 1836359000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 488.694805 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.954482 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.954482 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 306 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 99 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 90660887 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 90660887 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 24440244 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 24440244 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 18493380 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 18493380 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 326498 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 326498 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 374202 # 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average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15491.461442 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25463.876895 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25463.876895 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16820.653674 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 16820.653674 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14250.900365 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 14250.900365 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16692.038886 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 16692.038886 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14190.440523 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 14190.440523 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -689,149 +698,149 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 443107 # number of writebacks -system.cpu0.dcache.writebacks::total 443107 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25234 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 25234 # number of ReadReq MSHR hits +system.cpu0.dcache.writebacks::writebacks 732170 # number of writebacks +system.cpu0.dcache.writebacks::total 732170 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25278 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 25278 # number of ReadReq MSHR hits system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1 # number of WriteReq MSHR hits system.cpu0.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14124 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14124 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 25235 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 25235 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 25235 # 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average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 17896.649814 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17896.649814 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 16374.314295 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16374.314295 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22453.857674 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22453.857674 # average StoreCondReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15552 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15552 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 25279 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 25279 # 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number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4839458000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4839458000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6609064500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6609064500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1736821000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1736821000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 104360500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 104360500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 487321500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 487321500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1579000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1579000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11448522500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 11448522500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13185343500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13185343500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6629856000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6629856000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5400865000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5400865000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12030721000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12030721000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015801 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015801 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017910 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017910 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.230832 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.230832 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016900 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016900 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.050877 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.050877 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016710 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.016710 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018940 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.018940 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12320.569254 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12320.569254 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19596.348514 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19596.348514 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16369.197855 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16369.197855 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15576.194030 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15576.194030 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24466.387187 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24466.387187 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15814.890237 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15814.890237 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16076.174659 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16076.174659 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197703.777806 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 197703.777806 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 179135.579192 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 179135.579192 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 188936.139429 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 188936.139429 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15681.726034 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15681.726034 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15768.961727 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15768.961727 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208361.544989 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208361.544989 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189510.684585 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189510.684585 # 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Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 103 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::4 9 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 223 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 224410836 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 224410836 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 110724084 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 110724084 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 110724084 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 110724084 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 110724084 # 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number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 10780435500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 111711640 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 111711640 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 111711640 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 111711640 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 111711640 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 111711640 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.008840 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.008840 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.008840 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.008840 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.008840 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.008840 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10916.277659 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10916.277659 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10916.277659 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10916.277659 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10916.277659 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10916.277659 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 244294980 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 244294980 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 120426360 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 120426360 # 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miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.009438 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009438 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.009438 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009438 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.009438 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10682.992278 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10682.992278 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10682.992278 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10682.992278 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10682.992278 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10682.992278 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -840,236 +849,238 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 987556 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 987556 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 987556 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 987556 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 987556 # 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number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10286657500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 10286657500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10286657500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 10286657500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10286657500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 10286657500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11684169000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 11684169000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11684169000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11684169000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11684169000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11684169000 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1253876500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1253876500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1253876500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 1253876500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.008840 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.008840 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.008840 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.008840 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.008840 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.008840 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10416.277659 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10416.277659 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10416.277659 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 10416.277659 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10416.277659 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 10416.277659 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009438 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009438 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009438 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.009438 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009438 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.009438 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10182.992278 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10182.992278 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10182.992278 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 10182.992278 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10182.992278 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 10182.992278 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138979.882509 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138979.882509 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138979.882509 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138979.882509 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1606259 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1606313 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 46 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1935560 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1935650 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 78 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 209215 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 245604 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16082.851224 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 2813687 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 260278 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 10.810314 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 245750 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 273082 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16075.027062 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 3061877 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 289178 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 10.588209 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 7782.048512 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 0.435939 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.142248 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4563.552019 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1967.112212 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1769.560295 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.474979 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000027 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000009 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.278537 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.120063 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.108005 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.981619 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1320 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 19 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 13335 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 46 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 1270 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 259 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 1410 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 11666 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.080566 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.001160 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.813904 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 52809362 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 52809362 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 5209 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 2366 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 7575 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 443106 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 443106 # number of Writeback hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28064 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 28064 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1524 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 1524 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 197142 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 197142 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 946461 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 946461 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 317431 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 317431 # number of ReadSharedReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 5209 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 2366 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 946461 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 514573 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 1468609 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 5209 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 2366 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 946461 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 514573 # number of overall hits -system.cpu0.l2cache.overall_hits::total 1468609 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 313 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 217 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 530 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 25366 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 25366 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 17838 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 17838 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 2 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 38871 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 38871 # number of ReadExReq misses -system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 41095 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadCleanReq_misses::total 41095 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 91142 # number of ReadSharedReq misses -system.cpu0.l2cache.ReadSharedReq_misses::total 91142 # number of ReadSharedReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 313 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 217 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 41095 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 130013 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 171638 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 313 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 217 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 41095 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 130013 # number of overall misses -system.cpu0.l2cache.overall_misses::total 171638 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 7197500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 4644500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 11842000 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 564638000 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 564638000 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 375101000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 375101000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1455000 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1455000 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2573340000 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 2573340000 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 3117324500 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::total 3117324500 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3123622500 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3123622500 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 7197500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 4644500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3117324500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 5696962500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 8826129000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 7197500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 4644500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3117324500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 5696962500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 8826129000 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 5522 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 2583 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 8105 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 443106 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 443106 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 53430 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 53430 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 19362 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 19362 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 2 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 236013 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 236013 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 987556 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::total 987556 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 408573 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::total 408573 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 5522 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 2583 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 987556 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 644586 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 1640247 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 5522 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 2583 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 987556 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 644586 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 1640247 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.056682 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.084011 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.065392 # miss rate for ReadReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.474752 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.474752 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.921289 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.921289 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.tags.occ_blocks::writebacks 14584.410184 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 2.385544 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.137322 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1488.094013 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.890162 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000146 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000008 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.090826 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.981142 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1066 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15022 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 17 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 271 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 320 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 458 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 219 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3316 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7592 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3838 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.065063 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000488 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.916870 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 62794753 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 62794753 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 10867 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4767 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 15634 # number of ReadReq hits +system.cpu0.l2cache.WritebackDirty_hits::writebacks 501313 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackDirty_hits::total 501313 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackClean_hits::writebacks 1348863 # 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mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.084011 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.041613 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.199216 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.148427 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.148427 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.040844 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040844 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.186417 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.186417 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.016027 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.015693 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.040844 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.172811 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.093922 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.016027 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.015693 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.040844 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.172811 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.244353 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 16995.207668 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15403.225806 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 16343.396226 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 83027.252039 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 83027.252039 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 31352.992194 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31352.992194 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16210.561722 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16210.561722 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 583500 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 583500 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 58928.736033 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 58928.736033 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 69856.539725 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69856.539725 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28234.315480 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28234.315480 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 16995.207668 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15403.225806 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 69856.539725 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 37154.705168 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 44993.304398 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 16995.207668 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15403.225806 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 69856.539725 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37154.705168 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 83027.252039 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 66891.537242 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.229818 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 21663.841808 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 20907.894737 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 21436.758893 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 76826.616510 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 76826.616510 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 25907.101794 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 25907.101794 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16991.636108 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16991.636108 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 109090.181818 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 109090.181818 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 56425.478817 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 56425.478817 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 64594.281447 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64594.281447 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28280.131987 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28280.131987 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 21663.841808 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 20907.894737 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 64594.281447 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 36937.980254 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 43989.729541 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 21663.841808 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 20907.894737 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 64594.281447 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 36937.980254 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 76826.616510 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 63406.833032 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 131479.882509 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 189703.746298 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 176816.216879 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 171635.579192 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 171635.579192 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200348.549609 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 185135.084841 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182006.421278 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 182006.421278 # average WriteReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 131479.882509 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 181172.215662 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 174689.138577 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 191682.275606 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 183849.192385 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.snoop_filter.tot_requests 3288140 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1656034 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 25235 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 165607 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 165490 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 117 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.trans_dist::ReadReq 54153 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1498300 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 28393 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 28393 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 629767 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 1193646 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 275537 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 87023 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42073 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 110674 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 51 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 97 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 255600 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 251928 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 987556 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 494836 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 3354 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2960662 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2239612 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 6956 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 14519 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 5221749 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 63239672 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 73903156 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10332 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 22088 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 137175248 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 821565 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 4077224 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.054943 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.227994 # Request fanout histogram +system.cpu0.toL2Bus.snoop_filter.tot_requests 3903345 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1968246 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 28892 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 321222 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 317069 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4153 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.trans_dist::ReadReq 63874 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1765403 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 28499 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 28499 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 733576 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 1348863 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 190188 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 312390 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 85764 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42077 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 112758 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 45 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 84 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 301102 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 297729 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1147420 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 574776 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 3316 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3438002 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2673168 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11871 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 27031 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 6150072 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 145478520 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 101119646 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 19372 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 44176 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 246661714 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 988213 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 2981714 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.123543 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.333265 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 3853328 94.51% 94.51% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 223779 5.49% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 117 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 2617497 87.78% 87.78% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 360064 12.08% 99.86% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 4153 0.14% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 4077224 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 2138731998 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 2981714 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 3884130992 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 115020156 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 115184885 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1490356000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 1730152000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1049276975 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1265237983 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 4373000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 7028000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 8998497 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 15993487 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1315,64 +1323,57 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 6206 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 6206 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 1170 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 5036 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 6206 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 6206 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 6206 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 5005 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 10147.252747 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 9159.943965 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 4842.286315 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-4095 42 0.84% 0.84% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::4096-8191 2213 44.22% 45.05% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-12287 1504 30.05% 75.10% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::12288-16383 1077 21.52% 96.62% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-20479 52 1.04% 97.66% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::20480-24575 27 0.54% 98.20% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-28671 32 0.64% 98.84% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::28672-32767 42 0.84% 99.68% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-36863 5 0.10% 99.78% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::36864-40959 7 0.14% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::40960-45055 3 0.06% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::57344-61439 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 5005 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples -1704519828 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -1704519828 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -1704519828 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 3865 77.22% 77.22% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 1140 22.78% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 5005 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 6206 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 2355 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 2355 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 481 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1874 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 2355 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 2355 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 2355 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 1709 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 11678.466940 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 11002.721261 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 5695.537695 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-16383 1565 91.57% 91.57% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-32767 135 7.90% 99.47% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-49151 5 0.29% 99.77% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::49152-65535 3 0.18% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::147456-163839 1 0.06% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 1709 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -1207257828 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -1207257828 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -1207257828 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 1228 71.85% 71.85% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 481 28.15% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 1709 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 2355 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 6206 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5005 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 2355 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1709 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5005 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 11211 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1709 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 4064 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 5575996 # DTB read hits -system.cpu1.dtb.read_misses 5233 # DTB read misses -system.cpu1.dtb.write_hits 4889133 # DTB write hits -system.cpu1.dtb.write_misses 973 # DTB write misses +system.cpu1.dtb.read_hits 3323284 # DTB read hits +system.cpu1.dtb.read_misses 1962 # DTB read misses +system.cpu1.dtb.write_hits 2909831 # DTB write hits +system.cpu1.dtb.write_misses 393 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 3067 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1652 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 530 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 231 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 258 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 5581229 # DTB read accesses -system.cpu1.dtb.write_accesses 4890106 # DTB write accesses +system.cpu1.dtb.perms_faults 124 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 3325246 # DTB read accesses +system.cpu1.dtb.write_accesses 2910224 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 10465129 # DTB hits -system.cpu1.dtb.misses 6206 # DTB misses -system.cpu1.dtb.accesses 10471335 # DTB accesses +system.cpu1.dtb.hits 6233115 # DTB hits +system.cpu1.dtb.misses 2355 # DTB misses +system.cpu1.dtb.accesses 6235470 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1402,46 +1403,44 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 2787 # Table walker walks requested -system.cpu1.itb.walker.walksShort 2787 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 249 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2538 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 2787 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 2787 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 2787 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 1928 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 11234.439834 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 9816.231267 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 6428.442620 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 752 39.00% 39.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-12287 479 24.84% 63.85% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 554 28.73% 92.58% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-20479 71 3.68% 96.27% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-24575 2 0.10% 96.37% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 15 0.78% 97.15% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 17 0.88% 98.03% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-36863 5 0.26% 98.29% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::36864-40959 26 1.35% 99.64% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-45055 3 0.16% 99.79% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.05% 99.84% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::53248-57343 2 0.10% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::57344-61439 1 0.05% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 1928 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples -1705600828 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -1705600828 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total -1705600828 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 1679 87.09% 87.09% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 249 12.91% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 1928 # Table walker page sizes translated +system.cpu1.itb.walker.walks 1376 # Table walker walks requested +system.cpu1.itb.walker.walksShort 1376 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 134 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1242 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 1376 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 1376 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 1376 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 819 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 11895.604396 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 11259.508648 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 5169.477869 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 116 14.16% 14.16% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-12287 583 71.18% 85.35% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 72 8.79% 94.14% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 8 0.98% 95.12% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-24575 1 0.12% 95.24% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 22 2.69% 97.92% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 7 0.85% 98.78% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-36863 1 0.12% 98.90% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::36864-40959 5 0.61% 99.51% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-45055 1 0.12% 99.63% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::49152-53247 3 0.37% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 819 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -1208095828 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -1208095828 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -1208095828 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 685 83.64% 83.64% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 134 16.36% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 819 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2787 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2787 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1376 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1376 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1928 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1928 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 4715 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 23850368 # ITB inst hits -system.cpu1.itb.inst_misses 2787 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 819 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 819 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 2195 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 13877832 # ITB inst hits +system.cpu1.itb.inst_misses 1376 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1450,179 +1449,178 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1894 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 883 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 23853155 # ITB inst accesses -system.cpu1.itb.hits 23850368 # DTB hits -system.cpu1.itb.misses 2787 # DTB misses -system.cpu1.itb.accesses 23853155 # DTB accesses -system.cpu1.numCycles 5742239724 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 13879208 # ITB inst accesses +system.cpu1.itb.hits 13877832 # DTB hits +system.cpu1.itb.misses 1376 # DTB misses +system.cpu1.itb.accesses 13879208 # DTB accesses +system.cpu1.numCycles 5742698802 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 23084590 # Number of instructions committed -system.cpu1.committedOps 28191246 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 25227117 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 6988 # Number of float alu accesses -system.cpu1.num_func_calls 1341368 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 2715447 # number of instructions that are conditional controls -system.cpu1.num_int_insts 25227117 # number of integer instructions -system.cpu1.num_fp_insts 6988 # number of float instructions -system.cpu1.num_int_register_reads 45751310 # number of times the integer registers were read -system.cpu1.num_int_register_writes 17465196 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 5190 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1800 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 102291851 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 9890204 # number of times the CC registers were written -system.cpu1.num_mem_refs 10752307 # number of memory refs -system.cpu1.num_load_insts 5706058 # Number of load instructions -system.cpu1.num_store_insts 5046249 # Number of store instructions -system.cpu1.num_idle_cycles 5671495056.418025 # Number of idle cycles -system.cpu1.num_busy_cycles 70744667.581975 # Number of busy cycles -system.cpu1.not_idle_fraction 0.012320 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.987680 # Percentage of idle cycles -system.cpu1.Branches 4219564 # Number of branches fetched -system.cpu1.op_class::No_OpClass 167 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 17843088 62.32% 62.32% # Class of executed instruction -system.cpu1.op_class::IntMult 31349 0.11% 62.43% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 3702 0.01% 62.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 62.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.44% # Class of executed instruction -system.cpu1.op_class::MemRead 5706058 19.93% 82.37% # Class of executed instruction -system.cpu1.op_class::MemWrite 5046249 17.63% 100.00% # Class of executed instruction +system.cpu1.kern.inst.arm 0 # number of arm instructions executed +system.cpu1.kern.inst.quiesce 2717 # number of quiesce instructions executed +system.cpu1.committedInsts 13679150 # Number of instructions committed +system.cpu1.committedOps 16668513 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 15113644 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu1.num_func_calls 913162 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1492467 # number of instructions that are conditional controls +system.cpu1.num_int_insts 15113644 # number of integer instructions +system.cpu1.num_fp_insts 0 # number of float instructions +system.cpu1.num_int_register_reads 27463830 # number of times the integer registers were read +system.cpu1.num_int_register_writes 10666857 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 61159895 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 5174219 # number of times the CC registers were written +system.cpu1.num_mem_refs 6447631 # number of memory refs +system.cpu1.num_load_insts 3428751 # Number of load instructions +system.cpu1.num_store_insts 3018880 # Number of store instructions +system.cpu1.num_idle_cycles 5696160545.959164 # Number of idle cycles +system.cpu1.num_busy_cycles 46538256.040836 # Number of busy cycles +system.cpu1.not_idle_fraction 0.008104 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.991896 # Percentage of idle cycles +system.cpu1.Branches 2456488 # Number of branches fetched +system.cpu1.op_class::No_OpClass 24 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 10511910 61.88% 61.88% # Class of executed instruction +system.cpu1.op_class::IntMult 24272 0.14% 62.03% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 3188 0.02% 62.04% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 62.04% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.04% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.04% # Class of executed instruction +system.cpu1.op_class::MemRead 3428751 20.18% 82.23% # Class of executed instruction +system.cpu1.op_class::MemWrite 3018880 17.77% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 28630613 # Class of executed instruction -system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2852 # number of quiesce instructions executed -system.cpu1.dcache.tags.replacements 292035 # number of replacements -system.cpu1.dcache.tags.tagsinuse 469.567308 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 10109505 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 292547 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 34.556858 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 105794397000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 469.567308 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.917124 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.917124 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 302 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 100 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 21253597 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 21253597 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 5149175 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 5149175 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4639914 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4639914 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 67630 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 67630 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 103001 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 103001 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 95778 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 95778 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 9789089 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 9789089 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 9856719 # number of overall hits -system.cpu1.dcache.overall_hits::total 9856719 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 190277 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 190277 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 126690 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 126690 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 44121 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 44121 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18673 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 18673 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23929 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23929 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 316967 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 316967 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 361088 # number of overall misses -system.cpu1.dcache.overall_misses::total 361088 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2557291000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2557291000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3433917500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 3433917500 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 339355000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 339355000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 630190000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 630190000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 5470500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 5470500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 5991208500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 5991208500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 5991208500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 5991208500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 5339452 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 5339452 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 4766604 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 4766604 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 111751 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 111751 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 121674 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 121674 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 119707 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 119707 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 10106056 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 10106056 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 10217807 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 10217807 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035636 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.035636 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.026579 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.026579 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.394815 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.394815 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.153467 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.153467 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.199896 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.199896 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031364 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.031364 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035339 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.035339 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13439.832455 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 13439.832455 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 27104.881995 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 27104.881995 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18173.566111 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18173.566111 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 26335.826821 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 26335.826821 # average StoreCondReq miss latency +system.cpu1.op_class::total 16987025 # Class of executed instruction +system.cpu1.dcache.tags.replacements 147592 # number of replacements +system.cpu1.dcache.tags.tagsinuse 468.392474 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 6004450 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 147942 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 40.586514 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 106294932000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 468.392474 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.914829 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.914829 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 350 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 318 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 32 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.683594 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 12646180 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 12646180 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 3055213 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 3055213 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 2743263 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 2743263 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 41902 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 41902 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 69872 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 69872 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 61606 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 61606 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 5798476 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 5798476 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 5840378 # number of overall hits +system.cpu1.dcache.overall_hits::total 5840378 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 112221 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 112221 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 79294 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 79294 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 24421 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 24421 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16601 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 16601 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23085 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23085 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 191515 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 191515 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 215936 # number of overall misses +system.cpu1.dcache.overall_misses::total 215936 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1751790500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1751790500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2724343500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 2724343500 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 320772500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 320772500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 629240500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 629240500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3762500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3762500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 4476134000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 4476134000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 4476134000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 4476134000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 3167434 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 3167434 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 2822557 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 2822557 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 66323 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 66323 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 86473 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 86473 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 84691 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 84691 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 5989991 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 5989991 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 6056314 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 6056314 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035430 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.035430 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.028093 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.028093 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.368213 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.368213 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.191979 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.191979 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.272579 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.272579 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031973 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.031973 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035655 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.035655 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15610.184368 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15610.184368 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34357.498676 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 34357.498676 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19322.480573 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19322.480573 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27257.548191 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27257.548191 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18901.679039 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 18901.679039 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16592.100818 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 16592.100818 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23372.237162 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 23372.237162 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20728.984514 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 20728.984514 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1631,147 +1629,147 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 180790 # number of writebacks -system.cpu1.dcache.writebacks::total 180790 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 404 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 404 # number of ReadReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13063 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13063 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 404 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 404 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 404 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 404 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 189873 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 189873 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 126690 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 126690 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 43074 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 43074 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5610 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5610 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23929 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23929 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 316563 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 316563 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 359637 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 359637 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3143 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3143 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2520 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2520 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5663 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5663 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2352437000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2352437000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 3307227500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 3307227500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 648806500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 648806500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 97651500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 97651500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 606310000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 606310000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 5421500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 5421500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5659664500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 5659664500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6308471000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 6308471000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 420340500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 420340500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 296300500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 296300500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 716641000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 716641000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035560 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035560 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.026579 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.026579 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.385446 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.385446 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.046107 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.046107 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.199896 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.199896 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031324 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.031324 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035197 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.035197 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12389.528790 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12389.528790 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26104.881995 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26104.881995 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15062.601569 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15062.601569 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17406.684492 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17406.684492 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 25337.874546 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 25337.874546 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 147592 # number of writebacks +system.cpu1.dcache.writebacks::total 147592 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 221 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 221 # number of ReadReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 11676 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 11676 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 221 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 221 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 221 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 221 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 112000 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 112000 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 79294 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 79294 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 23950 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 23950 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4925 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4925 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23085 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23085 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 191294 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 191294 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 215244 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 215244 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3081 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3081 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2423 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2423 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5504 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5504 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1626671000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1626671000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2645049500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2645049500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 437326000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 437326000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 90573500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 90573500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 606189500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 606189500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3728500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3728500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4271720500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4271720500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4709046500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4709046500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 439448500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 439448500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 303112500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 303112500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 742561000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 742561000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035360 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035360 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028093 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028093 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.361112 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.361112 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.056954 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.056954 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.272579 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.272579 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031936 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.031936 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035540 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.035540 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14523.848214 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14523.848214 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33357.498676 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33357.498676 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18259.958246 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 18259.958246 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18390.558376 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18390.558376 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26259.021009 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26259.021009 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17878.477586 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17878.477586 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17541.217950 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17541.217950 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 133738.625517 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 133738.625517 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117579.563492 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 117579.563492 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 126547.942787 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 126547.942787 # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22330.655954 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22330.655954 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21877.713200 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21877.713200 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 142631.775398 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 142631.775398 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 125098.018985 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 125098.018985 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 134912.972384 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 134912.972384 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 622414 # number of replacements -system.cpu1.icache.tags.tagsinuse 498.397194 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 23227437 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 622926 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 37.287634 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 105696892000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.397194 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973432 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.973432 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 463636 # number of replacements +system.cpu1.icache.tags.tagsinuse 498.311121 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 13413679 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 464148 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 28.899573 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 106195496500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.311121 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973264 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.973264 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 209 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 220 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 387 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 118 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::4 7 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 48323652 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 48323652 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 23227437 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 23227437 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 23227437 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 23227437 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 23227437 # number of overall hits -system.cpu1.icache.overall_hits::total 23227437 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 622926 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 622926 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 622926 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 622926 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 622926 # number of overall misses -system.cpu1.icache.overall_misses::total 622926 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5716886500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 5716886500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 5716886500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 5716886500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 5716886500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 5716886500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 23850363 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 23850363 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 23850363 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 23850363 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 23850363 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 23850363 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.026118 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.026118 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.026118 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.026118 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.026118 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.026118 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9177.472926 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 9177.472926 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9177.472926 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 9177.472926 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9177.472926 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 9177.472926 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 28219802 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 28219802 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 13413679 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 13413679 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 13413679 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 13413679 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 13413679 # number of overall hits +system.cpu1.icache.overall_hits::total 13413679 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 464148 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 464148 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 464148 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 464148 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 464148 # number of overall misses +system.cpu1.icache.overall_misses::total 464148 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4215419500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4215419500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4215419500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4215419500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4215419500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4215419500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 13877827 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 13877827 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 13877827 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 13877827 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 13877827 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 13877827 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.033445 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.033445 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.033445 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.033445 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.033445 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.033445 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9082.058955 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 9082.058955 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9082.058955 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 9082.058955 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9082.058955 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 9082.058955 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1780,240 +1778,234 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 622926 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 622926 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 622926 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 622926 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 622926 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 622926 # number of overall MSHR misses +system.cpu1.icache.writebacks::writebacks 463636 # number of writebacks +system.cpu1.icache.writebacks::total 463636 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 464148 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 464148 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 464148 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 464148 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 464148 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 464148 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 177 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 177 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5405423500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5405423500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5405423500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5405423500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5405423500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5405423500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 23975000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 23975000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 23975000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 23975000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.026118 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.026118 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.026118 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.026118 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.026118 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.026118 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8677.472926 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8677.472926 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8677.472926 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 8677.472926 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8677.472926 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 8677.472926 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 135451.977401 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 135451.977401 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 135451.977401 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 135451.977401 # average overall mshr uncacheable latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3983345500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3983345500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3983345500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3983345500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3983345500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3983345500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 23546500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 23546500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 23546500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 23546500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.033445 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.033445 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.033445 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.033445 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.033445 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.033445 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8582.058955 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8582.058955 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8582.058955 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8582.058955 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8582.058955 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8582.058955 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 133031.073446 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 133031.073446 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 133031.073446 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 133031.073446 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 437692 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 437708 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 14 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 118070 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 118078 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 7 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 85932 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 65711 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15078.335139 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1680940 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 81927 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 20.517534 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 50218 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 30957 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 14956.632857 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 1041724 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 46098 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 22.598030 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 8770.071442 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.089565 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.088469 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3192.092107 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2103.725355 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1007.268201 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.535283 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000189 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_blocks::writebacks 14500.509333 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 1.321768 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.084166 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 452.717591 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.885041 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000081 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000127 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.194830 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.128401 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.061479 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.920309 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1082 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15126 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 11 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 297 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 350 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 424 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 49 # 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number of overall MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 22647500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 395196500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 417844000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 277400500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 277400500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 22647500 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 672597000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 695244500 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.034056 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.057895 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.041953 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5504 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5681 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 4965000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 4158500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 9123500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 915724625 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 915724625 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 582445000 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 582445000 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 432971000 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 432971000 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 3473500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 3473500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1449025500 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1449025500 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 476167000 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 476167000 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1055047000 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1055047000 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 4965000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 4158500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 476167000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2504072500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 2989363000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 4965000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4158500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 476167000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2504072500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 915724625 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 3905087625 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 22219000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 414452000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 436671000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 284931500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 284931500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 22219000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 699383500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 721602500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.123214 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.168081 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.140574 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.942414 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.942414 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.954027 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.954027 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.386863 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.386863 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.030944 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.030944 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.296596 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.296596 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.034056 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.057895 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.030944 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.322615 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.132116 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.034056 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.057895 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.030944 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.322615 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.638940 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.638940 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.018679 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.018679 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.452905 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.452905 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.123214 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.168081 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.018679 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.501862 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.159511 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.123214 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.168081 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.018679 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.501862 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.168343 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15119.617225 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 16051.136364 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15545.454545 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 57126.740283 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 57126.740283 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 22278.461810 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 22278.461810 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18691.023788 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18691.023788 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 2527000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 2527000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 44219.940604 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 44219.940604 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 37728.548454 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 37728.548454 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17293.844958 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17293.844958 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15119.617225 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 16051.136364 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 37728.548454 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 26600.979368 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 28246.142169 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15119.617225 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 16051.136364 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 37728.548454 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 26600.979368 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 57126.740283 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 34461.268734 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 127951.977401 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 125738.625517 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 125856.626506 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 110079.563492 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 110079.563492 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 127951.977401 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 118770.439696 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 119048.715753 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.191087 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14391.304348 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14001.683502 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14211.059190 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43947.047320 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 43947.047320 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20097.477658 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20097.477658 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18756.324727 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18756.324727 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 3473500 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 3473500 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 45074.983669 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 45074.983669 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 54921.222607 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 54921.222607 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16536.009279 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16536.009279 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14391.304348 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14001.683502 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 54921.222607 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 26097.681084 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 28399.260892 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14391.304348 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14001.683502 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 54921.222607 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 26097.681084 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43947.047320 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 30968.426593 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 125531.073446 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 134518.662772 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 134030.386740 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117594.510937 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 117594.510937 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 125531.073446 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 127068.223110 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 127020.330928 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.snoop_filter.tot_requests 1936586 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 978536 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 13921 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 103851 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 103732 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 119 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.trans_dist::ReadReq 19887 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 919525 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 2520 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 2520 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 223940 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 770866 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 41722 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 69543 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41698 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 86819 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 50 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 97 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 103431 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 101180 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 622926 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 309787 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 46 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1858177 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 1153867 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8365 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 17379 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 3037788 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 39867972 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 35780458 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 12160 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24548 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 75685138 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 354401 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 2220337 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.063895 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.244785 # Request fanout histogram +system.cpu1.toL2Bus.snoop_filter.tot_requests 1323663 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 668360 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 10107 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 169443 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 166760 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 2683 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.trans_dist::ReadReq 10105 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 652363 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 2423 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 2423 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 118404 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 509576 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 86260 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 25020 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 70278 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 40907 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 84739 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 51 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 84 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 57602 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 55059 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 464148 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 215012 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 32 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1383984 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 718041 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 4385 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 7029 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2113439 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 58847556 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24276952 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7068 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 11200 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 83142776 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 355785 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 998697 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.187513 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.397146 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 2078588 93.62% 93.62% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 141630 6.38% 99.99% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 119 0.01% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 814111 81.52% 81.52% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 181903 18.21% 99.73% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 2683 0.27% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 2220337 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 1156529000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 998697 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 1278018500 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 80617594 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 79432929 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 934566000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 696399000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 534214495 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 317143500 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 5325000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 2618000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 11246990 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 4229000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 31011 # Transaction distribution -system.iobus.trans_dist::ReadResp 31011 # Transaction distribution -system.iobus.trans_dist::WriteReq 59422 # Transaction distribution -system.iobus.trans_dist::WriteResp 59422 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56596 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 31021 # Transaction distribution +system.iobus.trans_dist::ReadResp 31021 # Transaction distribution +system.iobus.trans_dist::WriteReq 59425 # Transaction distribution +system.iobus.trans_dist::WriteResp 59425 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56620 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) @@ -2253,11 +2242,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107910 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72956 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72956 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180866 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71540 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107934 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 180892 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71564 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) @@ -2278,96 +2267,96 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162790 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321264 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321264 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2484054 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 40088000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 162814 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2484086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 48741500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 106500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 32500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 16000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 93000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 609500 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 23500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 48500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer21.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6155500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 165000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 32044000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 119500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 186504974 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 186329030 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.occupancy 37500 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 84712000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 84733000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36780000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36782000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36460 # number of replacements -system.iocache.tags.tagsinuse 14.383048 # Cycle average of tags in use +system.iocache.tags.replacements 36461 # number of replacements +system.iocache.tags.tagsinuse 14.380003 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36476 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36477 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 290140338000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.383048 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.898940 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.898940 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 290757542000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.380003 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.898750 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.898750 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328302 # Number of tag accesses -system.iocache.tags.data_accesses 328302 # Number of data accesses -system.iocache.ReadReq_misses::realview.ide 254 # number of ReadReq misses -system.iocache.ReadReq_misses::total 254 # number of ReadReq misses +system.iocache.tags.tag_accesses 328311 # Number of tag accesses +system.iocache.tags.data_accesses 328311 # Number of data accesses +system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses +system.iocache.ReadReq_misses::total 255 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 254 # number of demand (read+write) misses -system.iocache.demand_misses::total 254 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 254 # number of overall misses -system.iocache.overall_misses::total 254 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 33010877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 33010877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4717790097 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4717790097 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 33010877 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 33010877 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 33010877 # number of overall miss cycles -system.iocache.overall_miss_latency::total 33010877 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 254 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 254 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::realview.ide 255 # number of demand (read+write) misses +system.iocache.demand_misses::total 255 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 255 # number of overall misses +system.iocache.overall_misses::total 255 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 32882376 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 32882376 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4738851654 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4738851654 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 32882376 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 32882376 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 32882376 # number of overall miss cycles +system.iocache.overall_miss_latency::total 32882376 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 254 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 254 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 254 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 254 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 255 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 255 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 255 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 255 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses @@ -2376,40 +2365,40 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 129964.082677 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 129964.082677 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130239.346759 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 130239.346759 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 129964.082677 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 129964.082677 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 129964.082677 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 129964.082677 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 25 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 128950.494118 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 128950.494118 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130820.772250 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130820.772250 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 128950.494118 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 128950.494118 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 128950.494118 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 128950.494118 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 818 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 99 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 3.571429 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.262626 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 36206 # number of writebacks system.iocache.writebacks::total 36206 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 254 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 254 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 255 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 254 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 254 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 254 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 254 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 20310877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 20310877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2906590097 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2906590097 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 20310877 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 20310877 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 20310877 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 20310877 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::realview.ide 255 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 255 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 255 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 255 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 20132376 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 20132376 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2927651654 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2927651654 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 20132376 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 20132376 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 20132376 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 20132376 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -2418,289 +2407,304 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79964.082677 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 79964.082677 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80239.346759 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80239.346759 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 79964.082677 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 79964.082677 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 79964.082677 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 79964.082677 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 78950.494118 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 78950.494118 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80820.772250 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80820.772250 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 78950.494118 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 78950.494118 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 78950.494118 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 78950.494118 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 127982 # number of replacements -system.l2c.tags.tagsinuse 63841.400540 # Cycle average of tags in use -system.l2c.tags.total_refs 386797 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 192628 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.008000 # Average number of references to valid blocks. +system.l2c.tags.replacements 123906 # number of replacements +system.l2c.tags.tagsinuse 62994.829806 # Cycle average of tags in use +system.l2c.tags.total_refs 421817 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 187980 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.243946 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 12055.995118 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.049810 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.047185 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 7486.510812 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2815.662270 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37403.783442 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1406.932882 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 489.801266 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2179.617757 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.183960 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000047 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 13459.681359 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.946988 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.042686 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 7381.464495 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2783.395152 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 35774.545550 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.954481 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1451.828957 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 405.858901 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1734.111238 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.205378 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000045 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.114235 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.042964 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.570736 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.021468 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.007474 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.033258 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.974142 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 31928 # Occupied blocks per task id +system.l2c.tags.occ_percent::cpu0.inst 0.112632 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.042471 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.545876 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.022153 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.006193 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.026460 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.961225 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 31889 # Occupied blocks per task id system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 32714 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 74 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 4325 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 27529 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 32181 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::1 4 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 315 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 5132 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 26438 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 288 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 2359 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 30054 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.487183 # Percentage of cache occupancy per task id +system.l2c.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 384 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 2392 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 29385 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.486588 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.499176 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 5261289 # Number of tag accesses -system.l2c.tags.data_accesses 5261289 # Number of data accesses -system.l2c.Writeback_hits::writebacks 224862 # number of Writeback hits -system.l2c.Writeback_hits::total 224862 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1507 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 1131 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2638 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 135 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 177 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 312 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 3596 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 1989 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 5585 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 55 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 33 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 23888 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 41259 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 41598 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 52 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 64 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 16804 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 11932 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 9486 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 145171 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 55 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 33 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 23888 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 44855 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 41598 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 52 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 64 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 16804 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 13921 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 9486 # number of demand (read+write) hits -system.l2c.demand_hits::total 150756 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 55 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 33 # number of overall hits -system.l2c.overall_hits::cpu0.inst 23888 # number of overall hits -system.l2c.overall_hits::cpu0.data 44855 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 41598 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 52 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 64 # number of overall hits -system.l2c.overall_hits::cpu1.inst 16804 # number of overall hits -system.l2c.overall_hits::cpu1.data 13921 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 9486 # number of overall hits -system.l2c.overall_hits::total 150756 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 6940 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 4223 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 11163 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 425 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1268 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1693 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 11072 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 8126 # 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mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.098361 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.057143 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.418506 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.305392 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.754803 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.127432 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.396445 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.525937 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.553759 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 76013.832853 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 73964.006630 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 75238.376780 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 77363.529412 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76840.694006 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76971.943296 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 135438.267702 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121123.554024 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 129379.232212 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 125000 # average ReadSharedReq mshr miss latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.225495 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.536387 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.253953 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.216624 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.590930 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.382377 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.733622 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.855459 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.779344 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.066667 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.027397 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.373242 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.158446 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.738913 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.043478 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.272318 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.136403 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.614893 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.549795 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.066667 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.027397 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.373242 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.281832 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.738913 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.043478 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.272318 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.577358 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.614893 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.566633 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.066667 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.027397 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.373242 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.281832 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.738913 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.043478 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.272318 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.577358 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.614893 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.566633 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 75375.839642 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 75068.282918 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 75316.375677 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 77319.185059 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76712.999217 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76904.340836 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 135426.566550 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 120947.932619 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 129462.492772 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 125500 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 126000 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 121391.922540 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 126557.694531 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133872.756124 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 123518.322476 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 128658.644401 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 162601.038578 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 133834.881063 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 125000 # average overall mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 121472.130117 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 126214.027354 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135091.616172 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 122500 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124281.872088 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 138253.172589 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 145695.106639 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 133423.918387 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 125500 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 126000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121391.922540 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 131543.532275 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133872.756124 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 123518.322476 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121962.434383 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 162601.038578 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 133377.699704 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 125000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121472.130117 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 131358.315863 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135091.616172 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 122500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124281.872088 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 122529.162801 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 145695.106639 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 133024.254633 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 125500 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 126000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121391.922540 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 131543.532275 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133872.756124 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 123518.322476 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121962.434383 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 162601.038578 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 133377.699704 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121472.130117 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 131358.315863 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135091.616172 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 122500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124281.872088 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 122529.162801 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 145695.106639 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 133024.254633 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113479.827089 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 171703.525742 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 109951.977401 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 107879.738770 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 154992.229331 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 154635.508752 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 93079.365079 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 149617.507198 # average WriteReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182348.062478 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 107528.248588 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 116633.690708 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 163370.351052 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165006.070388 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 100577.177053 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159957.522153 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113479.827089 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 163644.251717 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 109951.977401 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 101289.008659 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 152776.587233 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 174154.332040 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 107528.248588 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 109561.352481 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 161963.602069 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 44076 # Transaction distribution -system.membus.trans_dist::ReadResp 212234 # Transaction distribution -system.membus.trans_dist::WriteReq 30913 # Transaction distribution -system.membus.trans_dist::WriteResp 30913 # Transaction distribution -system.membus.trans_dist::Writeback 134964 # Transaction distribution -system.membus.trans_dist::CleanEvict 15319 # Transaction distribution -system.membus.trans_dist::UpgradeReq 74839 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 40260 # Transaction distribution -system.membus.trans_dist::UpgradeResp 12961 # Transaction distribution -system.membus.trans_dist::ReadExReq 39815 # Transaction distribution -system.membus.trans_dist::ReadExResp 19093 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 168158 # Transaction distribution +system.membus.trans_dist::ReadReq 44096 # Transaction distribution +system.membus.trans_dist::ReadResp 213882 # Transaction distribution +system.membus.trans_dist::WriteReq 30922 # Transaction distribution +system.membus.trans_dist::WriteResp 30922 # Transaction distribution +system.membus.trans_dist::WritebackDirty 133077 # Transaction distribution +system.membus.trans_dist::CleanEvict 14603 # Transaction distribution +system.membus.trans_dist::UpgradeReq 73616 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 39905 # Transaction distribution +system.membus.trans_dist::UpgradeResp 13581 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 8 # Transaction distribution +system.membus.trans_dist::ReadExReq 39514 # Transaction distribution +system.membus.trans_dist::ReadExResp 18935 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 169786 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107910 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107934 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13734 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 664805 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 786483 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108936 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108936 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 895419 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162790 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13766 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 664049 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 785783 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108937 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108937 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 894720 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162814 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27468 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18323720 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18514046 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27532 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18296972 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18487386 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20832190 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 123434 # Total snoops (count) -system.membus.snoop_fanout::samples 584834 # Request fanout histogram +system.membus.pkt_size::total 20805530 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 121102 # Total snoops (count) +system.membus.snoop_fanout::samples 582015 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 584834 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 582015 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 584834 # Request fanout histogram -system.membus.reqLayer0.occupancy 88258000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 582015 # Request fanout histogram +system.membus.reqLayer0.occupancy 88274000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 19000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11355499 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11368000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 974246641 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 966740692 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1126274005 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1134075509 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 64655929 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 64085297 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -3003,52 +3020,52 @@ system.realview.realview_io.osc_peripheral.clock 41667 system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 910965 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 460102 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 151032 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 21991 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 21404 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 587 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 44080 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 476819 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 30913 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 30913 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 359850 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 80476 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 77372 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 40572 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 117944 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 97 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 97 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 51046 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 51046 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 432754 # Transaction distribution +system.toL2Bus.snoop_filter.tot_requests 961177 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 518872 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 139554 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 20662 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 19793 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 869 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 44099 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 468456 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30922 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30922 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 390602 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 84323 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 107685 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 42919 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 150604 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 84 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 84 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 50476 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 50476 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 424372 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1048506 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 332828 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1381334 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 29760096 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6517470 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 36277566 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 449108 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 1186895 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.300945 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.459746 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1224412 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 249093 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1473505 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34296330 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 3743120 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 38039450 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 438983 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 897187 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.337621 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.474943 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 830292 69.95% 69.95% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 356016 30.00% 99.95% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 587 0.05% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 595147 66.33% 66.33% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 301171 33.57% 99.90% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 869 0.10% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 1186895 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 806375018 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 897187 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 864296758 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 359119 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 360622 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 593704114 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 647366860 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 252660411 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 201908331 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 79e3a7b0a..05fb1382f 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.909343 # Number of seconds simulated -sim_ticks 2909343316500 # Number of ticks simulated -final_tick 2909343316500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.909604 # Number of seconds simulated +sim_ticks 2909603958500 # Number of ticks simulated +final_tick 2909603958500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 666869 # Simulator instruction rate (inst/s) -host_op_rate 804035 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 17251437084 # Simulator tick rate (ticks/s) -host_mem_usage 624248 # Number of bytes of host memory used -host_seconds 168.64 # Real time elapsed on the host -sim_insts 112463069 # Number of instructions simulated -sim_ops 135595282 # Number of ops (including micro ops) simulated +host_inst_rate 894735 # Simulator instruction rate (inst/s) +host_op_rate 1078768 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 23149732072 # Simulator tick rate (ticks/s) +host_mem_usage 579968 # Number of bytes of host memory used +host_seconds 125.69 # Real time elapsed on the host +sim_insts 112455934 # Number of instructions simulated +sim_ops 135586369 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1184996 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8901092 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1186596 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8901732 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10087624 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1184996 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1184996 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7517376 # Number of bytes written to this memory +system.physmem.bytes_read::total 10089864 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1186596 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1186596 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7512000 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 7534900 # Number of bytes written to this memory +system.physmem.bytes_written::total 7529524 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 26969 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 139599 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 26994 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 139609 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166592 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117459 # Number of write requests responded to by this memory +system.physmem.num_reads::total 166627 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117375 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 121840 # Number of write requests responded to by this memory +system.physmem.num_writes::total 121756 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 154 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 44 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 407307 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3059485 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 407820 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3059431 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 330 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3467320 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 407307 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 407307 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2583874 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3467779 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 407820 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 407820 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2581795 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6023 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2589897 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2583874 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2587817 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2581795 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 44 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 407307 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3065508 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 407820 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3065454 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 330 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6057217 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166592 # Number of read requests accepted -system.physmem.writeReqs 121840 # Number of write requests accepted -system.physmem.readBursts 166592 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 121840 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10654272 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7616 # Total number of bytes read from write queue -system.physmem.bytesWritten 7547776 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10087624 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7534900 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 119 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 6055597 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166627 # Number of read requests accepted +system.physmem.writeReqs 121756 # Number of write requests accepted +system.physmem.readBursts 166627 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 121756 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10656896 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7232 # Total number of bytes read from write queue +system.physmem.bytesWritten 7542080 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10089864 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7529524 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 113 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 40724 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10226 # Per bank write bursts -system.physmem.perBankRdBursts::1 9700 # Per bank write bursts -system.physmem.perBankRdBursts::2 10356 # Per bank write bursts -system.physmem.perBankRdBursts::3 10496 # Per bank write bursts -system.physmem.perBankRdBursts::4 18505 # Per bank write bursts -system.physmem.perBankRdBursts::5 10022 # Per bank write bursts -system.physmem.perBankRdBursts::6 10179 # Per bank write bursts -system.physmem.perBankRdBursts::7 10614 # Per bank write bursts -system.physmem.perBankRdBursts::8 9478 # Per bank write bursts -system.physmem.perBankRdBursts::9 10041 # Per bank write bursts -system.physmem.perBankRdBursts::10 9320 # Per bank write bursts -system.physmem.perBankRdBursts::11 9342 # Per bank write bursts -system.physmem.perBankRdBursts::12 9424 # Per bank write bursts -system.physmem.perBankRdBursts::13 10229 # Per bank write bursts -system.physmem.perBankRdBursts::14 9340 # Per bank write bursts -system.physmem.perBankRdBursts::15 9201 # Per bank write bursts -system.physmem.perBankWrBursts::0 7577 # Per bank write bursts -system.physmem.perBankWrBursts::1 7036 # Per bank write bursts -system.physmem.perBankWrBursts::2 7887 # Per bank write bursts -system.physmem.perBankWrBursts::3 8049 # Per bank write bursts -system.physmem.perBankWrBursts::4 7151 # Per bank write bursts -system.physmem.perBankWrBursts::5 7579 # Per bank write bursts -system.physmem.perBankWrBursts::6 7566 # Per bank write bursts -system.physmem.perBankWrBursts::7 7770 # Per bank write bursts -system.physmem.perBankWrBursts::8 7275 # Per bank write bursts -system.physmem.perBankWrBursts::9 7619 # Per bank write bursts -system.physmem.perBankWrBursts::10 6810 # Per bank write bursts -system.physmem.perBankWrBursts::11 7097 # Per bank write bursts -system.physmem.perBankWrBursts::12 7200 # Per bank write bursts -system.physmem.perBankWrBursts::13 7753 # Per bank write bursts -system.physmem.perBankWrBursts::14 6925 # Per bank write bursts -system.physmem.perBankWrBursts::15 6640 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 47113 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10077 # Per bank write bursts +system.physmem.perBankRdBursts::1 9979 # Per bank write bursts +system.physmem.perBankRdBursts::2 10695 # Per bank write bursts +system.physmem.perBankRdBursts::3 10661 # Per bank write bursts +system.physmem.perBankRdBursts::4 18797 # Per bank write bursts +system.physmem.perBankRdBursts::5 9659 # Per bank write bursts +system.physmem.perBankRdBursts::6 9665 # Per bank write bursts +system.physmem.perBankRdBursts::7 10488 # Per bank write bursts +system.physmem.perBankRdBursts::8 9276 # Per bank write bursts +system.physmem.perBankRdBursts::9 9973 # Per bank write bursts +system.physmem.perBankRdBursts::10 9230 # Per bank write bursts +system.physmem.perBankRdBursts::11 8679 # Per bank write bursts +system.physmem.perBankRdBursts::12 9820 # Per bank write bursts +system.physmem.perBankRdBursts::13 10379 # Per bank write bursts +system.physmem.perBankRdBursts::14 9723 # Per bank write bursts +system.physmem.perBankRdBursts::15 9413 # Per bank write bursts +system.physmem.perBankWrBursts::0 7393 # Per bank write bursts +system.physmem.perBankWrBursts::1 7263 # Per bank write bursts +system.physmem.perBankWrBursts::2 8282 # Per bank write bursts +system.physmem.perBankWrBursts::3 8171 # Per bank write bursts +system.physmem.perBankWrBursts::4 7489 # Per bank write bursts +system.physmem.perBankWrBursts::5 7265 # Per bank write bursts +system.physmem.perBankWrBursts::6 7108 # Per bank write bursts +system.physmem.perBankWrBursts::7 7662 # Per bank write bursts +system.physmem.perBankWrBursts::8 7080 # Per bank write bursts +system.physmem.perBankWrBursts::9 7523 # Per bank write bursts +system.physmem.perBankWrBursts::10 6693 # Per bank write bursts +system.physmem.perBankWrBursts::11 6470 # Per bank write bursts +system.physmem.perBankWrBursts::12 7534 # Per bank write bursts +system.physmem.perBankWrBursts::13 7859 # Per bank write bursts +system.physmem.perBankWrBursts::14 7265 # Per bank write bursts +system.physmem.perBankWrBursts::15 6788 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 3 # Number of times write queue was full causing retry -system.physmem.totGap 2909342872000 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 2909603601500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9558 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 157020 # Read request sizes (log2) +system.physmem.readPktSize::6 157055 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 117459 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 165675 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 528 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 258 # What read queue length does an incoming req see +system.physmem.writePktSize::6 117375 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 165631 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 614 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 257 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -159,109 +159,116 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2393 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6014 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5882 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6380 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7267 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6822 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7809 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7989 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9329 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6661 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6301 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6059 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5924 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2472 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5973 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5912 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6422 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7824 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7975 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7837 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6630 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6710 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6026 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5995 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 12 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 7 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 58587 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 310.682984 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 183.521208 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 329.535953 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 21321 36.39% 36.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14587 24.90% 61.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6073 10.37% 71.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3205 5.47% 77.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2612 4.46% 81.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1486 2.54% 84.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1112 1.90% 86.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1062 1.81% 87.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7129 12.17% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 58587 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5766 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.870621 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 589.954659 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 5765 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::62 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 58748 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 309.779261 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 182.856223 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.388013 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 21447 36.51% 36.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14643 24.93% 61.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6082 10.35% 71.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3222 5.48% 77.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2599 4.42% 81.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1493 2.54% 84.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1038 1.77% 86.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1067 1.82% 87.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7157 12.18% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 58748 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5762 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.896737 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 590.107660 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 5761 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5766 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5766 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.453347 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.695263 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 13.074003 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4962 86.06% 86.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 90 1.56% 87.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 33 0.57% 88.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 174 3.02% 91.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 30 0.52% 91.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 151 2.62% 94.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 46 0.80% 95.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 5 0.09% 95.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 17 0.29% 95.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 15 0.26% 95.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 7 0.12% 95.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 2 0.03% 95.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 166 2.88% 98.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 5 0.09% 98.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 8 0.14% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 26 0.45% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 2 0.03% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.02% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.03% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 17 0.29% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 4 0.07% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5766 # Writes before turning the bus around for reads -system.physmem.totQLat 1636363750 # Total ticks spent queuing -system.physmem.totMemAccLat 4757732500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 832365000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9829.60 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5762 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5762 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.452100 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.700018 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.100411 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4964 86.15% 86.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 94 1.63% 87.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 35 0.61% 88.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 168 2.92% 91.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 22 0.38% 91.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 152 2.64% 94.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 51 0.89% 95.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 7 0.12% 95.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 11 0.19% 95.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 15 0.26% 95.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 3 0.05% 95.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 4 0.07% 95.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 174 3.02% 98.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 7 0.12% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 3 0.05% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 18 0.31% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 4 0.07% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.02% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 2 0.03% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.02% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.02% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 15 0.26% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.02% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.02% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.03% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 2 0.03% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5762 # Writes before turning the bus around for reads +system.physmem.totQLat 1626690000 # Total ticks spent queuing +system.physmem.totMemAccLat 4748827500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 832570000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9769.09 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28579.60 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 28519.09 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.66 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.59 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.47 # Average system read bandwidth in MiByte/s @@ -271,40 +278,40 @@ system.physmem.busUtil 0.05 # Da system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.26 # Average write queue length when enqueuing -system.physmem.readRowHits 136200 # Number of row buffer hits during reads -system.physmem.writeRowHits 89619 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.82 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.98 # Row buffer hit rate for writes -system.physmem.avgGap 10086754.84 # Average gap between requests -system.physmem.pageHitRate 79.39 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 229098240 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 125004000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 702764400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 392785200 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 190023952560 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 90217297485 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1666466226750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1948157128635 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.621597 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2772138232000 # Time in different power states -system.physmem_0.memoryStateTime::REF 97149260000 # Time in different power states +system.physmem.avgWrQLen 26.01 # Average write queue length when enqueuing +system.physmem.readRowHits 136108 # Number of row buffer hits during reads +system.physmem.writeRowHits 89502 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.74 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.93 # Row buffer hit rate for writes +system.physmem.avgGap 10089372.82 # Average gap between requests +system.physmem.pageHitRate 79.33 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 230496840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 125767125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 702163800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 392901840 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 190040735040 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 90194010705 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1666640821500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1948326896850 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.620811 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2772423900000 # Time in different power states +system.physmem_0.memoryStateTime::REF 97157840000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 40052866750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 40015565000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 213819480 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 116667375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 595717200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 371427120 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 190023952560 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 88066202985 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1668353151750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1947740938470 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.478544 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2775299661000 # Time in different power states -system.physmem_1.memoryStateTime::REF 97149260000 # Time in different power states +system.physmem_1.actEnergy 213638040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 116568375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 596637600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 370733760 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 190040735040 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 88104913965 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1668473362500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1947916589280 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.479792 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2775503002250 # Time in different power states +system.physmem_1.memoryStateTime::REF 97157840000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 36894247500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 36942968250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory @@ -354,55 +361,56 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 9555 # Table walker walks requested -system.cpu.dtb.walker.walksShort 9555 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1270 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8285 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walkWaitTime::samples 9555 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 9555 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 9555 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 7391 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 12962.724936 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 10716.855962 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 8397.253568 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-32767 7386 99.93% 99.93% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-163839 4 0.05% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 7391 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walks 9546 # Table walker walks requested +system.cpu.dtb.walker.walksShort 9546 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1255 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8291 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 9546 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 9546 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 9546 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 7382 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 13188.702249 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 10926.693941 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 9189.684239 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-32767 7377 99.93% 99.93% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-163839 3 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-360447 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 7382 # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walksPending::samples 1638910500 # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::0 1638910500 100.00% 100.00% # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::total 1638910500 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6168 83.45% 83.45% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1223 16.55% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7391 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9555 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkPageSizes::4K 6174 83.64% 83.64% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1208 16.36% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7382 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9546 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9555 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7391 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9546 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7382 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7391 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 16946 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7382 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 16928 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 24521784 # DTB read hits -system.cpu.dtb.read_misses 8135 # DTB read misses -system.cpu.dtb.write_hits 19607400 # DTB write hits -system.cpu.dtb.write_misses 1420 # DTB write misses +system.cpu.dtb.read_hits 24520223 # DTB read hits +system.cpu.dtb.read_misses 8124 # DTB read misses +system.cpu.dtb.write_hits 19606444 # DTB write hits +system.cpu.dtb.write_misses 1422 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_entries 4272 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 1651 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 1650 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 24529919 # DTB read accesses -system.cpu.dtb.write_accesses 19608820 # DTB write accesses +system.cpu.dtb.read_accesses 24528347 # DTB read accesses +system.cpu.dtb.write_accesses 19607866 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 44129184 # DTB hits -system.cpu.dtb.misses 9555 # DTB misses -system.cpu.dtb.accesses 44138739 # DTB accesses +system.cpu.dtb.hits 44126667 # DTB hits +system.cpu.dtb.misses 9546 # DTB misses +system.cpu.dtb.accesses 44136213 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -440,11 +448,11 @@ system.cpu.itb.walker.walkWaitTime::samples 4763 # system.cpu.itb.walker.walkWaitTime::0 4763 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::total 4763 # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkCompletionTime::samples 3108 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 12663.288288 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 10495.066195 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 7808.701731 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-16383 2418 77.80% 77.80% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::16384-32767 688 22.14% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 12722.007722 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 10527.196882 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 7865.701982 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-16383 2410 77.54% 77.54% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-32767 696 22.39% 99.94% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::131072-147455 2 0.06% 100.00% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::total 3108 # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walksPending::samples 1638383000 # Table walker pending requests distribution @@ -460,7 +468,7 @@ system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3108 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::total 3108 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin::total 7871 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 115560644 # ITB inst hits +system.cpu.itb.inst_hits 115553087 # ITB inst hits system.cpu.itb.inst_misses 4763 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -477,38 +485,40 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 115565407 # ITB inst accesses -system.cpu.itb.hits 115560644 # DTB hits +system.cpu.itb.inst_accesses 115557850 # ITB inst accesses +system.cpu.itb.hits 115553087 # DTB hits system.cpu.itb.misses 4763 # DTB misses -system.cpu.itb.accesses 115565407 # DTB accesses -system.cpu.numCycles 5818686633 # number of cpu cycles simulated +system.cpu.itb.accesses 115557850 # DTB accesses +system.cpu.numCycles 5819207917 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 112463069 # Number of instructions committed -system.cpu.committedOps 135595282 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 119900050 # Number of integer alu accesses +system.cpu.kern.inst.arm 0 # number of arm instructions executed +system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed +system.cpu.committedInsts 112455934 # Number of instructions committed +system.cpu.committedOps 135586369 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 119891885 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 11161 # Number of float alu accesses -system.cpu.num_func_calls 9893453 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 15231190 # number of instructions that are conditional controls -system.cpu.num_int_insts 119900050 # number of integer instructions +system.cpu.num_func_calls 9891908 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 15230427 # number of instructions that are conditional controls +system.cpu.num_int_insts 119891885 # number of integer instructions system.cpu.num_fp_insts 11161 # number of float instructions -system.cpu.num_int_register_reads 218076436 # number of times the integer registers were read -system.cpu.num_int_register_writes 82650791 # number of times the integer registers were written +system.cpu.num_int_register_reads 218060317 # number of times the integer registers were read +system.cpu.num_int_register_writes 82644878 # number of times the integer registers were written system.cpu.num_fp_register_reads 8449 # number of times the floating registers were read system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written -system.cpu.num_cc_register_reads 489768723 # number of times the CC registers were read -system.cpu.num_cc_register_writes 51897400 # number of times the CC registers were written -system.cpu.num_mem_refs 45409486 # number of memory refs -system.cpu.num_load_insts 24844046 # Number of load instructions -system.cpu.num_store_insts 20565440 # Number of store instructions -system.cpu.num_idle_cycles 5379802959.980151 # Number of idle cycles -system.cpu.num_busy_cycles 438883673.019849 # Number of busy cycles -system.cpu.not_idle_fraction 0.075427 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.924573 # Percentage of idle cycles -system.cpu.Branches 25918657 # Number of branches fetched +system.cpu.num_cc_register_reads 489736143 # number of times the CC registers were read +system.cpu.num_cc_register_writes 51894204 # number of times the CC registers were written +system.cpu.num_mem_refs 45406948 # number of memory refs +system.cpu.num_load_insts 24842511 # Number of load instructions +system.cpu.num_store_insts 20564437 # Number of store instructions +system.cpu.num_idle_cycles 5379072532.100152 # Number of idle cycles +system.cpu.num_busy_cycles 440135384.899849 # Number of busy cycles +system.cpu.not_idle_fraction 0.075635 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.924365 # Percentage of idle cycles +system.cpu.Branches 25916368 # Number of branches fetched system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 93180998 67.17% 67.18% # Class of executed instruction -system.cpu.op_class::IntMult 114440 0.08% 67.26% # Class of executed instruction +system.cpu.op_class::IntAlu 93174225 67.17% 67.18% # Class of executed instruction +system.cpu.op_class::IntMult 114427 0.08% 67.26% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 67.26% # Class of executed instruction @@ -536,256 +546,254 @@ system.cpu.op_class::SimdFloatMisc 8455 0.01% 67.26% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::MemRead 24844046 17.91% 85.17% # Class of executed instruction -system.cpu.op_class::MemWrite 20565440 14.83% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 24842511 17.91% 85.17% # Class of executed instruction +system.cpu.op_class::MemWrite 20564437 14.83% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 138715716 # Class of executed instruction -system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed -system.cpu.dcache.tags.replacements 821347 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.702129 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 43235829 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 821859 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 52.607356 # Average number of references to valid blocks. +system.cpu.op_class::total 138706392 # Class of executed instruction +system.cpu.dcache.tags.replacements 819093 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.702336 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 43235572 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 819605 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 52.751718 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 1736147500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.702129 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999418 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999418 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 511.702336 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999419 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999419 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 344 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 105 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 107 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 177121649 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 177121649 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23112263 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23112263 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18824569 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18824569 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 392807 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 392807 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 443229 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 443229 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460200 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460200 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41936832 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41936832 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42329639 # number of overall hits -system.cpu.dcache.overall_hits::total 42329639 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 401818 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 401818 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 298972 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 298972 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 118323 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 118323 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 22757 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22757 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 177109325 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 177109325 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23112645 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23112645 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18823942 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18823942 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 392782 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 392782 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 443235 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 443235 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460203 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460203 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 41936587 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41936587 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42329369 # number of overall hits +system.cpu.dcache.overall_hits::total 42329369 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 399856 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 399856 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 298641 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 298641 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 118367 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 118367 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22751 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22751 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 700790 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 700790 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 819113 # number of overall misses -system.cpu.dcache.overall_misses::total 819113 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6512815000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6512815000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19103648000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19103648000 # 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number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 511130 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 511130 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 25600196000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 25600196000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 25600196000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 25600196000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23512501 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23512501 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19122583 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19122583 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 511149 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 511149 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465986 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 465986 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 460202 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 460202 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42637622 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42637622 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 43148752 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 43148752 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017088 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.017088 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015634 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.015634 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.231493 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.231493 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048836 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048836 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_accesses::cpu.data 460205 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 460205 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 42635084 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42635084 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 43146233 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 43146233 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017006 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.017006 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015617 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.015617 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.231570 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.231570 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048823 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048823 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # 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miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.016383 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.018932 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.018932 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16215.965247 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16215.965247 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64010.450675 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64010.450675 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12922.794602 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12922.794602 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82000 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 36553.693689 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 36553.693689 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31273.417709 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31273.417709 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 76 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 36650.402221 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 36650.402221 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31339.606103 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31339.606103 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 100 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 19 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 20 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 685107 # number of writebacks -system.cpu.dcache.writebacks::total 685107 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 939 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 939 # number of ReadReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14240 # 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number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 58727 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6080968000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6080968000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 18804676000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 18804676000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1617499500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1617499500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 115437000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 115437000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6055510500 # 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number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017048 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017048 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015634 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015634 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227496 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227496 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018277 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018277 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24873014500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 24873014500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26490149500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26490149500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6279074500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6279074500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5089978000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5089978000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11369052500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 11369052500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016967 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016967 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015617 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015617 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227546 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227546 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018260 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018260 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016414 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016414 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018914 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.018914 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15169.085934 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15169.085934 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62897.783070 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62897.783070 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13910.384417 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13910.384417 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13553.716097 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13553.716097 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016361 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016361 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018863 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.018863 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15179.304994 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15179.304994 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63010.450675 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63010.450675 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13903.662626 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13903.662626 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13548.007992 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13548.007992 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81000 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35558.488878 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 35558.488878 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32474.129153 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 32474.129153 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 190659.595992 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190659.595992 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173673.039980 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173673.039980 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 182679.585199 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 182679.585199 # average overall mshr uncacheable latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35656.504050 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 35656.504050 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32547.859459 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 32547.859459 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201653.108742 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201653.108742 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184493.022581 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184493.022581 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193591.576277 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193591.576277 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 1696276 # number of replacements -system.cpu.icache.tags.tagsinuse 510.440576 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 113863850 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1696788 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 67.105525 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 28967481500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.440576 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996954 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996954 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1695571 # number of replacements +system.cpu.icache.tags.tagsinuse 510.436867 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 113856998 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1696083 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 67.129379 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 29070355500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.436867 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996947 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996947 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 262 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 117257438 # Number of tag accesses -system.cpu.icache.tags.data_accesses 117257438 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 113863850 # 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number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 24262817500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 24262817500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 24262817500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 24262817500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 115560644 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 115560644 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 115560644 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 115560644 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 115560644 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 115560644 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014683 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.014683 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.014683 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.014683 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.014683 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.014683 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14299.212220 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14299.212220 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14299.212220 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14299.212220 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14299.212220 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14299.212220 # average overall miss latency +system.cpu.icache.tags.tag_accesses 117249176 # Number of tag accesses +system.cpu.icache.tags.data_accesses 117249176 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 113856998 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 113856998 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 113856998 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 113856998 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 113856998 # number of overall hits +system.cpu.icache.overall_hits::total 113856998 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1696089 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1696089 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1696089 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1696089 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1696089 # 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number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 115553087 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 115553087 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014678 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.014678 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.014678 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.014678 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.014678 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.014678 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14309.218443 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14309.218443 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14309.218443 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14309.218443 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14309.218443 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14309.218443 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -794,212 +802,218 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1696794 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1696794 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1696794 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1696794 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1696794 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1696794 # number of overall MSHR misses +system.cpu.icache.writebacks::writebacks 1695571 # number of writebacks +system.cpu.icache.writebacks::total 1695571 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1696089 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1696089 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1696089 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1696089 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1696089 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1696089 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 9022 # number of ReadReq MSHR uncacheable system.cpu.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 9022 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22566023500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22566023500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22566023500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22566023500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22566023500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22566023500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22573619000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22573619000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22573619000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22573619000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22573619000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22573619000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 1142541000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1142541000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 1142541000 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 1142541000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014683 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014683 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014683 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.014683 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014683 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.014683 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13299.212220 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13299.212220 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13299.212220 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13299.212220 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13299.212220 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13299.212220 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014678 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014678 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014678 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.014678 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014678 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.014678 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13309.218443 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13309.218443 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13309.218443 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13309.218443 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13309.218443 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13309.218443 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126639.436932 # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126639.436932 # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126639.436932 # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126639.436932 # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 87598 # 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Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.012642 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 9659.374197 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 5012.219980 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.765845 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 50197.653066 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.799333 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.012653 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 9701.739092 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 4962.023293 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.765955 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000058 # 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mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.435700 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010600 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010600 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.023240 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.023240 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000895 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000495 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010600 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172134 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.062936 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000895 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000495 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010600 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172134 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.062936 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 153928.571429 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 123000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 122777.777778 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70800.548446 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70800.548446 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 147055.555556 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70804.014599 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70804.014599 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69500 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117148.641724 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117148.641724 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121367.271917 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121367.271917 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122269.562739 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122269.562739 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 122714.285714 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117148.281025 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117148.281025 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120754.797263 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120754.797263 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122558.535984 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122558.535984 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 153928.571429 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 123000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121367.271917 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 117594.404752 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118020.597685 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 122714.285714 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120754.797263 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 117615.043307 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 117971.572979 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 153928.571429 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 123000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121367.271917 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 117594.404752 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118020.597685 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120754.797263 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 117615.043307 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 117971.572979 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 114139.436932 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 178159.563877 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 163777.353088 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 162173.039980 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 162173.039980 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189149.238872 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 172298.182271 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172988.310559 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172988.310559 # average WriteReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 114139.436932 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 170649.352087 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 163124.038731 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181557.094692 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 172579.218881 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 5058225 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2539566 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 38059 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 583 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 583 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 5052300 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2536604 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 38129 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 581 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 581 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadReq 67216 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2289899 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 67213 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2287266 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27589 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27589 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 802569 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1801014 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2759 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 801101 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1664804 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 134612 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2763 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2761 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 296213 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 296213 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1696794 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 525904 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2765 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 295878 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 295878 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1696089 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 523979 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5077168 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2580972 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 13250 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 25621 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7697011 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108629432 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96644509 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 16136 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 31124 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 205321201 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 175948 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5294343 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.018110 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.133351 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5074993 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2574186 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 13257 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 25655 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7688091 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 215131128 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96411485 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 16164 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 31272 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 311590049 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 175874 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2773719 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.020869 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.142946 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 5198460 98.19% 98.19% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 95883 1.81% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2715834 97.91% 97.91% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 57885 2.09% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5294343 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3265837500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.snoop_fanout::total 2773719 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4957066000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 380377 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2554213000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2553155500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1279146500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1275758999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer2.occupancy 9216000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 17840000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 17837000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 30177 # Transaction distribution system.iobus.trans_dist::ReadResp 30177 # Transaction distribution @@ -1235,63 +1250,63 @@ system.iobus.pkt_size_system.bridge.master::total 159125 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321056 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321056 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480181 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 38469000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 46338000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 97000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 16000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 94500 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 644500 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 21000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 52500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer21.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6288500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 174000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 36469500 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 127000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 186318027 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 186222546 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.occupancy 37000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36728000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36418 # number of replacements -system.iocache.tags.tagsinuse 1.083918 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.084136 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36434 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 313622510000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.083918 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.067745 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.067745 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 313818895000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.084136 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.067758 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.067758 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1305,14 +1320,14 @@ system.iocache.demand_misses::realview.ide 228 # system.iocache.demand_misses::total 228 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 228 # number of overall misses system.iocache.overall_misses::total 228 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 28366877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 28366877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4697294150 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4697294150 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 28366877 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 28366877 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 28366877 # number of overall miss cycles -system.iocache.overall_miss_latency::total 28366877 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 28180377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 28180377 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4715427169 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4715427169 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 28180377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 28180377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 28180377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 28180377 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 228 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 228 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -1329,19 +1344,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 124416.127193 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 124416.127193 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129673.535501 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 129673.535501 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 124416.127193 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 124416.127193 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 124416.127193 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 124416.127193 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 123598.144737 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 123598.144737 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130174.115752 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130174.115752 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 123598.144737 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 123598.144737 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 123598.144737 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 123598.144737 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 753 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 81 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.296296 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1355,14 +1370,14 @@ system.iocache.demand_mshr_misses::realview.ide 228 system.iocache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 228 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 228 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 16966877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 16966877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2886094150 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2886094150 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 16966877 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 16966877 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 16966877 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 16966877 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 16780377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 16780377 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2904227169 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2904227169 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 16780377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 16780377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 16780377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 16780377 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1371,68 +1386,68 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74416.127193 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 74416.127193 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79673.535501 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79673.535501 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 74416.127193 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 74416.127193 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 74416.127193 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 74416.127193 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73598.144737 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 73598.144737 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80174.115752 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80174.115752 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 73598.144737 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 73598.144737 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 73598.144737 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 73598.144737 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 40160 # Transaction distribution -system.membus.trans_dist::ReadResp 70632 # Transaction distribution +system.membus.trans_dist::ReadResp 70548 # Transaction distribution system.membus.trans_dist::WriteReq 27589 # Transaction distribution system.membus.trans_dist::WriteResp 27589 # Transaction distribution -system.membus.trans_dist::Writeback 117459 # Transaction distribution -system.membus.trans_dist::CleanEvict 6342 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4500 # Transaction distribution +system.membus.trans_dist::WritebackDirty 117375 # Transaction distribution +system.membus.trans_dist::CleanEvict 6392 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4497 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4502 # Transaction distribution -system.membus.trans_dist::ReadExReq 127038 # Transaction distribution -system.membus.trans_dist::ReadExResp 127038 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 30472 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4499 # Transaction distribution +system.membus.trans_dist::ReadExReq 127157 # Transaction distribution +system.membus.trans_dist::ReadExResp 127157 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 30388 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 438793 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 546385 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 438823 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 546415 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108894 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 108894 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 655279 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 655309 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15305404 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15468757 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15302268 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15465621 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17785877 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17782741 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 492 # Total snoops (count) -system.membus.snoop_fanout::samples 390004 # Request fanout histogram +system.membus.snoop_fanout::samples 389999 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 390004 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 389999 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 390004 # Request fanout histogram -system.membus.reqLayer0.occupancy 90504500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 389999 # Request fanout histogram +system.membus.reqLayer0.occupancy 90471000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1698500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1726000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 821932659 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 823075656 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 952275997 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 952261248 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 64458066 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 64129261 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt index 83f940052..037583e12 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.783867 # Nu sim_ticks 2783867052000 # Number of ticks simulated final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1174884 # Simulator instruction rate (inst/s) -host_op_rate 1430233 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 22908545755 # Simulator tick rate (ticks/s) -host_mem_usage 623708 # Number of bytes of host memory used -host_seconds 121.52 # Real time elapsed on the host +host_inst_rate 1268879 # Simulator instruction rate (inst/s) +host_op_rate 1544656 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 24741311872 # Simulator tick rate (ticks/s) +host_mem_usage 623824 # Number of bytes of host memory used +host_seconds 112.52 # Real time elapsed on the host sim_insts 142772879 # Number of instructions simulated sim_ops 173803124 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -226,6 +226,8 @@ system.cpu0.itb.accesses 74781709 # DT system.cpu0.numCycles 5536444792 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu0.kern.inst.arm 0 # number of arm instructions executed +system.cpu0.kern.inst.quiesce 3083 # number of quiesce instructions executed system.cpu0.committedInsts 72626333 # Number of instructions committed system.cpu0.committedOps 87972335 # Number of ops (including micro ops) committed system.cpu0.num_int_alu_accesses 77485858 # Number of integer alu accesses @@ -283,8 +285,6 @@ system.cpu0.op_class::MemWrite 11749540 13.09% 100.00% # Cl system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::total 89742700 # Class of executed instruction -system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 3083 # number of quiesce instructions executed system.cpu0.dcache.tags.replacements 819402 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use system.cpu0.dcache.tags.total_refs 53784414 # Total number of references to valid blocks. @@ -459,6 +459,8 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.writebacks::writebacks 1699214 # number of writebacks +system.cpu0.icache.writebacks::total 1699214 # number of writebacks system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -599,6 +601,8 @@ system.cpu1.itb.accesses 72262399 # DT system.cpu1.numCycles 88040649 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu1.kern.inst.arm 0 # number of arm instructions executed +system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.committedInsts 70146546 # Number of instructions committed system.cpu1.committedOps 85830789 # Number of ops (including micro ops) committed system.cpu1.num_int_alu_accesses 75676825 # Number of integer alu accesses @@ -656,8 +660,6 @@ system.cpu1.op_class::MemWrite 12333852 14.10% 100.00% # Cl system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::total 87477212 # Class of executed instruction -system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.iobus.trans_dist::ReadReq 30164 # Transaction distribution system.iobus.trans_dist::ReadResp 30164 # Transaction distribution system.iobus.trans_dist::WriteReq 59002 # Transaction distribution @@ -801,8 +803,10 @@ system.l2c.ReadReq_hits::cpu0.itb.walker 2287 # nu system.l2c.ReadReq_hits::cpu1.dtb.walker 5001 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.itb.walker 2453 # number of ReadReq hits system.l2c.ReadReq_hits::total 14441 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 682264 # number of Writeback hits -system.l2c.Writeback_hits::total 682264 # number of Writeback hits +system.l2c.WritebackDirty_hits::writebacks 682264 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 682264 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 1667206 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 1667206 # number of WritebackClean hits system.l2c.UpgradeReq_hits::cpu0.data 13 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 15 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 28 # number of UpgradeReq hits @@ -872,8 +876,10 @@ system.l2c.ReadReq_accesses::cpu0.itb.walker 2288 system.l2c.ReadReq_accesses::cpu1.dtb.walker 5003 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.itb.walker 2453 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 14449 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 682264 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 682264 # number of Writeback accesses(hits+misses) +system.l2c.WritebackDirty_accesses::writebacks 682264 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 682264 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackClean_accesses::writebacks 1667206 # number of WritebackClean accesses(hits+misses) +system.l2c.WritebackClean_accesses::total 1667206 # number of WritebackClean accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 1262 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 1494 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses) @@ -955,7 +961,7 @@ system.membus.trans_dist::ReadReq 40087 # Tr system.membus.trans_dist::ReadResp 74196 # Transaction distribution system.membus.trans_dist::WriteReq 27546 # Transaction distribution system.membus.trans_dist::WriteResp 27546 # Transaction distribution -system.membus.trans_dist::Writeback 138133 # Transaction distribution +system.membus.trans_dist::WritebackDirty 138133 # Transaction distribution system.membus.trans_dist::CleanEvict 7977 # Transaction distribution system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution @@ -1044,8 +1050,9 @@ system.toL2Bus.trans_dist::ReadReq 71244 # Tr system.toL2Bus.trans_dist::ReadResp 2291984 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 682264 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1797078 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 682264 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1667206 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 129872 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution @@ -1058,11 +1065,11 @@ system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2 system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20804 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 41510 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count::total 7721762 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108818936 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 215520120 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96323169 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 41608 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 83020 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 205266733 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 311967917 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 182968 # Total snoops (count) system.toL2Bus.snoop_fanout::samples 5322627 # Request fanout histogram system.toL2Bus.snoop_fanout::mean 0.018535 # Request fanout histogram diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt index a4264e923..6e04c32d2 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -1,136 +1,136 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.909388 # Number of seconds simulated -sim_ticks 2909387991500 # Number of ticks simulated -final_tick 2909387991500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.909654 # Number of seconds simulated +sim_ticks 2909653700500 # Number of ticks simulated +final_tick 2909653700500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 670421 # Simulator instruction rate (inst/s) -host_op_rate 808321 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 17345176485 # Simulator tick rate (ticks/s) -host_mem_usage 625252 # Number of bytes of host memory used -host_seconds 167.73 # Real time elapsed on the host -sim_insts 112452815 # Number of instructions simulated -sim_ops 135583410 # Number of ops (including micro ops) simulated +host_inst_rate 811232 # Simulator instruction rate (inst/s) +host_op_rate 978087 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 20990567196 # Simulator tick rate (ticks/s) +host_mem_usage 580224 # Number of bytes of host memory used +host_seconds 138.62 # Real time elapsed on the host +sim_insts 112450652 # Number of instructions simulated +sim_ops 135579653 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 538144 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4761988 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 521248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4656256 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 646852 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4138720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 665348 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4245540 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10087176 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 538144 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 646852 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1184996 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7517248 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 8860 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 8664 # Number of bytes written to this memory -system.physmem.bytes_written::total 7534772 # Number of bytes written to this memory +system.physmem.bytes_read::total 10089864 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 521248 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 665348 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1186596 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7511936 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 8852 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 8672 # Number of bytes written to this memory +system.physmem.bytes_written::total 7529460 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 13696 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 74910 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 13432 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 73257 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 13273 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 64683 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 13562 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 66353 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166585 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117457 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 2215 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 2166 # Number of write requests responded to by this memory -system.physmem.num_writes::total 121838 # Number of write requests responded to by this memory +system.physmem.num_reads::total 166627 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117374 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 2213 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 2168 # Number of write requests responded to by this memory +system.physmem.num_writes::total 121755 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 88 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 184968 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1636766 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 179144 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1600278 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 66 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 222333 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1422540 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 228669 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1459122 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 330 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3467113 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 184968 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 222333 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 407301 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2583790 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 3045 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2978 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2589813 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2583790 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 3467720 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 179144 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 228669 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 407813 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2581729 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 3042 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2980 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2587751 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2581729 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 88 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 184968 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1639812 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 179144 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1603321 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 66 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 222333 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1425518 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 228669 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1462103 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 330 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6056926 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166585 # Number of read requests accepted -system.physmem.writeReqs 121838 # Number of write requests accepted -system.physmem.readBursts 166585 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 121838 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10654272 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7168 # Total number of bytes read from write queue -system.physmem.bytesWritten 7548800 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10087176 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7534772 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 112 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 6055471 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166627 # Number of read requests accepted +system.physmem.writeReqs 121755 # Number of write requests accepted +system.physmem.readBursts 166627 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 121755 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10658432 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 5696 # Total number of bytes read from write queue +system.physmem.bytesWritten 7541440 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10089864 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7529460 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 89 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 40727 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10228 # Per bank write bursts -system.physmem.perBankRdBursts::1 9700 # Per bank write bursts -system.physmem.perBankRdBursts::2 10356 # Per bank write bursts -system.physmem.perBankRdBursts::3 10495 # Per bank write bursts -system.physmem.perBankRdBursts::4 18506 # Per bank write bursts -system.physmem.perBankRdBursts::5 10022 # Per bank write bursts -system.physmem.perBankRdBursts::6 10178 # Per bank write bursts -system.physmem.perBankRdBursts::7 10614 # Per bank write bursts -system.physmem.perBankRdBursts::8 9477 # Per bank write bursts -system.physmem.perBankRdBursts::9 10047 # Per bank write bursts -system.physmem.perBankRdBursts::10 9317 # Per bank write bursts -system.physmem.perBankRdBursts::11 9342 # Per bank write bursts -system.physmem.perBankRdBursts::12 9423 # Per bank write bursts -system.physmem.perBankRdBursts::13 10228 # Per bank write bursts -system.physmem.perBankRdBursts::14 9339 # Per bank write bursts -system.physmem.perBankRdBursts::15 9201 # Per bank write bursts -system.physmem.perBankWrBursts::0 7595 # Per bank write bursts -system.physmem.perBankWrBursts::1 7036 # Per bank write bursts -system.physmem.perBankWrBursts::2 7887 # Per bank write bursts -system.physmem.perBankWrBursts::3 8047 # Per bank write bursts -system.physmem.perBankWrBursts::4 7152 # Per bank write bursts -system.physmem.perBankWrBursts::5 7580 # Per bank write bursts -system.physmem.perBankWrBursts::6 7566 # Per bank write bursts -system.physmem.perBankWrBursts::7 7770 # Per bank write bursts -system.physmem.perBankWrBursts::8 7275 # Per bank write bursts -system.physmem.perBankWrBursts::9 7619 # Per bank write bursts -system.physmem.perBankWrBursts::10 6806 # Per bank write bursts -system.physmem.perBankWrBursts::11 7096 # Per bank write bursts -system.physmem.perBankWrBursts::12 7204 # Per bank write bursts -system.physmem.perBankWrBursts::13 7753 # Per bank write bursts -system.physmem.perBankWrBursts::14 6924 # Per bank write bursts -system.physmem.perBankWrBursts::15 6640 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 47114 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10080 # Per bank write bursts +system.physmem.perBankRdBursts::1 9979 # Per bank write bursts +system.physmem.perBankRdBursts::2 10697 # Per bank write bursts +system.physmem.perBankRdBursts::3 10658 # Per bank write bursts +system.physmem.perBankRdBursts::4 18793 # Per bank write bursts +system.physmem.perBankRdBursts::5 9660 # Per bank write bursts +system.physmem.perBankRdBursts::6 9676 # Per bank write bursts +system.physmem.perBankRdBursts::7 10492 # Per bank write bursts +system.physmem.perBankRdBursts::8 9276 # Per bank write bursts +system.physmem.perBankRdBursts::9 9982 # Per bank write bursts +system.physmem.perBankRdBursts::10 9231 # Per bank write bursts +system.physmem.perBankRdBursts::11 8678 # Per bank write bursts +system.physmem.perBankRdBursts::12 9823 # Per bank write bursts +system.physmem.perBankRdBursts::13 10380 # Per bank write bursts +system.physmem.perBankRdBursts::14 9720 # Per bank write bursts +system.physmem.perBankRdBursts::15 9413 # Per bank write bursts +system.physmem.perBankWrBursts::0 7393 # Per bank write bursts +system.physmem.perBankWrBursts::1 7263 # Per bank write bursts +system.physmem.perBankWrBursts::2 8284 # Per bank write bursts +system.physmem.perBankWrBursts::3 8168 # Per bank write bursts +system.physmem.perBankWrBursts::4 7485 # Per bank write bursts +system.physmem.perBankWrBursts::5 7265 # Per bank write bursts +system.physmem.perBankWrBursts::6 7108 # Per bank write bursts +system.physmem.perBankWrBursts::7 7667 # Per bank write bursts +system.physmem.perBankWrBursts::8 7080 # Per bank write bursts +system.physmem.perBankWrBursts::9 7523 # Per bank write bursts +system.physmem.perBankWrBursts::10 6694 # Per bank write bursts +system.physmem.perBankWrBursts::11 6470 # Per bank write bursts +system.physmem.perBankWrBursts::12 7527 # Per bank write bursts +system.physmem.perBankWrBursts::13 7859 # Per bank write bursts +system.physmem.perBankWrBursts::14 7261 # Per bank write bursts +system.physmem.perBankWrBursts::15 6788 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2909387547000 # Total gap between requests +system.physmem.numWrRetry 3 # Number of times write queue was full causing retry +system.physmem.totGap 2909653343500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9558 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 157013 # Read request sizes (log2) +system.physmem.readPktSize::6 157055 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 117457 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 165681 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 523 # What read queue length does an incoming req see +system.physmem.writePktSize::6 117374 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 165652 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 617 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 257 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see @@ -161,132 +161,137 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 168 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 165 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2514 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5781 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5826 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6207 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6667 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7640 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7823 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6968 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6509 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5809 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5740 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2515 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5891 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5740 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6773 # 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What write queue length does an incoming req see system.physmem.wrQLenPdf::35 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 72 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 58549 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 310.902116 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 183.522866 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 330.172226 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 21290 36.36% 36.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14652 25.03% 61.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6083 10.39% 71.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3178 5.43% 77.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2491 4.25% 81.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1565 2.67% 84.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1038 1.77% 85.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1041 1.78% 87.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7211 12.32% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 58549 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5743 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.986941 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 548.492879 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 5740 99.95% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 2 0.03% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::36 173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 8 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 58556 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 310.810301 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 183.232220 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 330.272692 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 21388 36.53% 36.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14563 24.87% 61.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6001 10.25% 71.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3238 5.53% 77.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2533 4.33% 81.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1526 2.61% 84.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1009 1.72% 85.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1158 1.98% 87.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7140 12.19% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 58556 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5712 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 29.151786 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 545.492775 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 5709 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 2 0.04% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5743 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5743 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.538046 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.602147 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 13.025411 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 27 0.47% 0.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 14 0.24% 0.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 12 0.21% 0.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 14 0.24% 1.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4750 82.71% 83.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 125 2.18% 86.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 82 1.43% 87.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 205 3.57% 91.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 32 0.56% 91.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 152 2.65% 94.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 51 0.89% 95.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 6 0.10% 95.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 11 0.19% 95.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 18 0.31% 95.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 9 0.16% 95.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 1 0.02% 95.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 172 2.99% 98.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 6 0.10% 99.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 5 0.09% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 21 0.37% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 1 0.02% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.03% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 3 0.05% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.02% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.03% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.02% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 14 0.24% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 3 0.05% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5743 # Writes before turning the bus around for reads -system.physmem.totQLat 1603192250 # Total ticks spent queuing -system.physmem.totMemAccLat 4724561000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 832365000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9630.34 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5712 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5712 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.629377 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.719500 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.211627 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 18 0.32% 0.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 9 0.16% 0.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 8 0.14% 0.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 11 0.19% 0.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4765 83.42% 84.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 125 2.19% 86.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 59 1.03% 87.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 204 3.57% 91.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 32 0.56% 91.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 148 2.59% 94.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 51 0.89% 95.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 8 0.14% 95.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 9 0.16% 95.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 17 0.30% 95.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 5 0.09% 95.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 8 0.14% 95.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 167 2.92% 98.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 5 0.09% 98.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 6 0.11% 99.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 19 0.33% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 4 0.07% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 2 0.04% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.02% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 3 0.05% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.02% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.02% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.02% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.04% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.04% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 15 0.26% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 2 0.04% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5712 # Writes before turning the bus around for reads +system.physmem.totQLat 1608810750 # Total ticks spent queuing +system.physmem.totMemAccLat 4731398250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 832690000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9660.32 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28380.34 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 28410.32 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.66 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.59 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.47 # Average system read bandwidth in MiByte/s @@ -296,40 +301,40 @@ system.physmem.busUtil 0.05 # Da system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 7.27 # Average write queue length when enqueuing -system.physmem.readRowHits 136293 # Number of row buffer hits during reads -system.physmem.writeRowHits 89580 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.87 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.95 # Row buffer hit rate for writes -system.physmem.avgGap 10087224.48 # Average gap between requests -system.physmem.pageHitRate 79.41 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 229158720 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 125037000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 702772200 # Energy for read commands per rank (pJ) +system.physmem.avgWrQLen 12.25 # Average write queue length when enqueuing +system.physmem.readRowHits 136274 # Number of row buffer hits during reads +system.physmem.writeRowHits 89542 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.83 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.97 # Row buffer hit rate for writes +system.physmem.avgGap 10089580.29 # Average gap between requests +system.physmem.pageHitRate 79.40 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 230519520 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 125779500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 702273000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 392901840 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 190027003920 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 90369730305 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1666360544250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1948207148235 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.628037 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2771956641500 # Time in different power states -system.physmem_0.memoryStateTime::REF 97150820000 # Time in different power states +system.physmem_0.refreshEnergy 190044294960 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 90285662430 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1666593127500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1948374558750 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.624648 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2772342347250 # Time in different power states +system.physmem_0.memoryStateTime::REF 97159660000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 40279614750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 40149801500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 213471720 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 116477625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 595709400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 371414160 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 190027003920 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 88357601520 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1668125569500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1947807247845 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.490585 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2774916457500 # Time in different power states -system.physmem_1.memoryStateTime::REF 97150820000 # Time in different power states +system.physmem_1.actEnergy 212163840 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 115764000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 596715600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 370668960 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 190044294960 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 88503009660 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1668156858000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1947999475020 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.495738 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2774969217000 # Time in different power states +system.physmem_1.memoryStateTime::REF 97159660000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 37320566000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 37524675500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory @@ -379,58 +384,58 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 6929 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 6929 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 2193 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 4735 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 1 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 6928 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 6928 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 6928 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 5821 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 12939.357499 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 11196.384549 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 7211.949482 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 4588 78.82% 78.82% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1229 21.11% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-147455 4 0.07% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 5821 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 1237488496 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean -0.616549 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 2000461000 161.65% 161.65% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 -762972504 -61.65% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 1237488496 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 3649 62.70% 62.70% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 2171 37.30% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 5820 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 6929 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 6385 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 6385 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1824 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 4559 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 2 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 6383 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 6383 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 6383 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 5318 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 13413.689357 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 11614.000174 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 7416.349168 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 3990 75.03% 75.03% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1324 24.90% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-147455 4 0.08% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 5318 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 1993677436 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean -0.003389 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 2000434000 100.34% 100.34% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 -6756564 -0.34% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 1993677436 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 3519 66.20% 66.20% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1797 33.80% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 5316 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 6385 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 6929 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5820 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 6385 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5316 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5820 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 12749 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5316 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 11701 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 12044488 # DTB read hits -system.cpu0.dtb.read_misses 5975 # DTB read misses -system.cpu0.dtb.write_hits 9654865 # DTB write hits -system.cpu0.dtb.write_misses 954 # DTB write misses +system.cpu0.dtb.read_hits 12043498 # DTB read hits +system.cpu0.dtb.read_misses 5581 # DTB read misses +system.cpu0.dtb.write_hits 9607194 # DTB write hits +system.cpu0.dtb.write_misses 804 # DTB write misses system.cpu0.dtb.flush_tlb 2940 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 481 # Number of times TLB was flushed by MVA +system.cpu0.dtb.flush_tlb_mva 441 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 4388 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 3980 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 864 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 867 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 231 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 12050463 # DTB read accesses -system.cpu0.dtb.write_accesses 9655819 # DTB write accesses +system.cpu0.dtb.perms_faults 217 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 12049079 # DTB read accesses +system.cpu0.dtb.write_accesses 9607998 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 21699353 # DTB hits -system.cpu0.dtb.misses 6929 # DTB misses -system.cpu0.dtb.accesses 21706282 # DTB accesses +system.cpu0.dtb.hits 21650692 # DTB hits +system.cpu0.dtb.misses 6385 # DTB misses +system.cpu0.dtb.accesses 21657077 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -460,256 +465,256 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 3426 # Table walker walks requested -system.cpu0.itb.walker.walksShort 3426 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 828 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 2598 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 3426 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 3426 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 3426 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2558 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 12817.630962 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 11147.269267 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 6399.295854 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::4096-6143 694 27.13% 27.13% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::10240-12287 823 32.17% 59.30% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::12288-14335 178 6.96% 66.26% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::14336-16383 343 13.41% 79.67% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-18431 1 0.04% 79.71% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::22528-24575 515 20.13% 99.84% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-26623 4 0.16% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2558 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 3199 # Table walker walks requested +system.cpu0.itb.walker.walksShort 3199 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 683 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 2516 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 3199 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 3199 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 3199 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2347 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 13274.818918 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 11551.422255 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 6527.623179 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::4096-6143 600 25.56% 25.56% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::10240-12287 656 27.95% 53.52% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::12288-14335 193 8.22% 61.74% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::14336-16383 387 16.49% 78.23% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-18431 3 0.13% 78.36% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::22528-24575 500 21.30% 99.66% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-26623 8 0.34% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2347 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples 2000380500 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 2000380500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 2000380500 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 1730 67.63% 67.63% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 828 32.37% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2558 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 1664 70.90% 70.90% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 683 29.10% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2347 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3426 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3426 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3199 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3199 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2558 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2558 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 5984 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 56823446 # ITB inst hits -system.cpu0.itb.inst_misses 3426 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2347 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2347 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 5546 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 56739503 # ITB inst hits +system.cpu0.itb.inst_misses 3199 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 2940 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 481 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb_mva 441 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2582 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2369 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 56826872 # ITB inst accesses -system.cpu0.itb.hits 56823446 # DTB hits -system.cpu0.itb.misses 3426 # DTB misses -system.cpu0.itb.accesses 56826872 # DTB accesses -system.cpu0.numCycles 2910048510 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 56742702 # ITB inst accesses +system.cpu0.itb.hits 56739503 # DTB hits +system.cpu0.itb.misses 3199 # DTB misses +system.cpu0.itb.accesses 56742702 # DTB accesses +system.cpu0.numCycles 2910044532 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 55288600 # Number of instructions committed -system.cpu0.committedOps 66713599 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 58931600 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5354 # Number of float alu accesses -system.cpu0.num_func_calls 4809440 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 7565706 # number of instructions that are conditional controls -system.cpu0.num_int_insts 58931600 # number of integer instructions -system.cpu0.num_fp_insts 5354 # number of float instructions -system.cpu0.num_int_register_reads 107138015 # number of times the integer registers were read -system.cpu0.num_int_register_writes 40582750 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 4124 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1232 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 240777875 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 25734446 # number of times the CC registers were written -system.cpu0.num_mem_refs 22316238 # number of memory refs -system.cpu0.num_load_insts 12197914 # Number of load instructions -system.cpu0.num_store_insts 10118324 # Number of store instructions -system.cpu0.num_idle_cycles 2666885275.671365 # Number of idle cycles -system.cpu0.num_busy_cycles 243163234.328635 # Number of busy cycles -system.cpu0.not_idle_fraction 0.083560 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.916440 # Percentage of idle cycles -system.cpu0.Branches 12750711 # Number of branches fetched -system.cpu0.op_class::No_OpClass 119 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 45844704 67.20% 67.20% # Class of executed instruction -system.cpu0.op_class::IntMult 57827 0.08% 67.28% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 3997 0.01% 67.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 67.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.29% # Class of executed instruction -system.cpu0.op_class::MemRead 12197914 17.88% 85.17% # Class of executed instruction -system.cpu0.op_class::MemWrite 10118324 14.83% 100.00% # Class of executed instruction -system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 68222885 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 3033 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 821400 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.702036 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 43232181 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 821912 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 52.599525 # Average number of references to valid blocks. +system.cpu0.committedInsts 55201459 # Number of instructions committed +system.cpu0.committedOps 66609946 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 58847772 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5145 # Number of float alu accesses +system.cpu0.num_func_calls 4820077 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 7555989 # number of instructions that are conditional controls +system.cpu0.num_int_insts 58847772 # number of integer instructions +system.cpu0.num_fp_insts 5145 # number of float instructions +system.cpu0.num_int_register_reads 106933475 # number of times the integer registers were read +system.cpu0.num_int_register_writes 40499308 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3730 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1418 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 240486031 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 25664833 # number of times the CC registers were written +system.cpu0.num_mem_refs 22274491 # number of memory refs +system.cpu0.num_load_insts 12198391 # Number of load instructions +system.cpu0.num_store_insts 10076100 # Number of store instructions +system.cpu0.num_idle_cycles 2694628360.005429 # Number of idle cycles +system.cpu0.num_busy_cycles 215416171.994570 # Number of busy cycles +system.cpu0.not_idle_fraction 0.074025 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.925975 # Percentage of idle cycles +system.cpu0.Branches 12743161 # Number of branches fetched +system.cpu0.op_class::No_OpClass 131 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 45792912 67.22% 67.22% # Class of executed instruction +system.cpu0.op_class::IntMult 56104 0.08% 67.30% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 3963 0.01% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::MemRead 12198391 17.91% 85.21% # Class of executed instruction +system.cpu0.op_class::MemWrite 10076100 14.79% 100.00% # Class of executed instruction +system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::total 68127601 # Class of executed instruction +system.cpu0.dcache.tags.replacements 819018 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.702192 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 43232909 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 819530 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 52.753296 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 1736913500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 174.965504 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 336.736532 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.341730 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.657689 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 43.309115 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 468.393077 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.084588 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.914830 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999418 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 344 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 105 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 107 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 177107266 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 177107266 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 11359748 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 11750430 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 23110178 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 9271451 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 9551716 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 18823167 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 190318 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 202376 # 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number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 12877448500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 26473407500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3049211500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3229832500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6279044000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2494979500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2594954500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5089934000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5544191000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5824787000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11368978000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017217 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.016725 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016966 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015946 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.015301 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015617 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.231398 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.223875 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.227541 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017079 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.019404 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.018282 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000008 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016621 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.016221 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.016417 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.019130 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.018712 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.018917 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15162.609022 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15163.629489 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15163.127298 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 65879.506811 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 59734.344194 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 62845.823620 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 14006.742043 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13774.679242 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13889.269308 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13606.183146 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13461.169191 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13526.408451 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016648 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.016085 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.016361 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.019173 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.018564 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.018863 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15507.469476 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14830.063464 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15167.905490 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 64979.244160 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 60982.963460 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 62983.285112 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 13848.966558 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13920.725989 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13885.163493 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13655.419489 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13448.515275 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13541.730250 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 81000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 37180.146542 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 33892.999089 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35530.620263 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 33904.704683 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 31006.127998 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32448.350937 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190199.669421 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 191093.892462 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190659.531762 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 173647.785478 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 173695.207154 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173672.387546 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 182462.518925 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 182882.213282 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 182679.244640 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 36731.464128 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 34548.101298 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35638.705941 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 33484.119869 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 31581.105705 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32530.606414 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 203199.486872 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 200212.775849 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201652.129231 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 186345.470162 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 182743.274648 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184491.427743 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 195252.368375 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 192034.386127 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 193590.307695 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1696133 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.440350 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 113853580 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1696645 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 67.105128 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 28968175500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 264.675620 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 245.764730 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.516945 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.480009 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.996954 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 1695285 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.436603 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 113852008 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1695797 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 67.137758 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 29075840500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 59.971705 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 450.464899 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.117132 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.879814 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.996946 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 262 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 117246882 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 117246882 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 55981187 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 57872393 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 113853580 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 55981187 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 57872393 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 113853580 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 55981187 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 57872393 # number of overall hits -system.cpu0.icache.overall_hits::total 113853580 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 842259 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 854392 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1696651 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 842259 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 854392 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1696651 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 842259 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 854392 # number of overall misses -system.cpu0.icache.overall_misses::total 1696651 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11932408500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 12314837000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 24247245500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 11932408500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 12314837000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 24247245500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 11932408500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 12314837000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 24247245500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 56823446 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 58726785 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 115550231 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 56823446 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 58726785 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 115550231 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 56823446 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 58726785 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 115550231 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014822 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014549 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014683 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014822 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014549 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014683 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014822 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014549 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014683 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14167.148704 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14413.567777 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14291.239330 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14167.148704 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14413.567777 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14291.239330 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14167.148704 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14413.567777 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14291.239330 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 117243614 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 117243614 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 55899037 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 57952971 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 113852008 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 55899037 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 57952971 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 113852008 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 55899037 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 57952971 # number of overall hits +system.cpu0.icache.overall_hits::total 113852008 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 840466 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 855337 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1695803 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 840466 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 855337 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1695803 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 840466 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 855337 # number of overall misses +system.cpu0.icache.overall_misses::total 1695803 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11890019000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 12374432000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 24264451000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 11890019000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 12374432000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 24264451000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 11890019000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 12374432000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 24264451000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 56739503 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 58808308 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 115547811 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 56739503 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 58808308 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 115547811 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 56739503 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 58808308 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 115547811 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014813 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014544 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014676 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014813 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014544 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014676 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014813 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014544 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014676 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14146.936342 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14467.317560 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14308.531710 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14146.936342 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14467.317560 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14308.531710 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14146.936342 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14467.317560 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14308.531710 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -921,54 +926,56 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 842259 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 854392 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1696651 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 842259 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 854392 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1696651 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 842259 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 854392 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1696651 # number of overall MSHR misses +system.cpu0.icache.writebacks::writebacks 1695285 # number of writebacks +system.cpu0.icache.writebacks::total 1695285 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 840466 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 855337 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1695803 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 840466 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 855337 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1695803 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 840466 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 855337 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1695803 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 5645 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst 3377 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 5645 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst 3377 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11090149500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 11460445000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 22550594500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11090149500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 11460445000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 22550594500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11090149500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 11460445000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 22550594500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11049553000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 11519095000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 22568648000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11049553000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 11519095000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 22568648000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11049553000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 11519095000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 22568648000 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 713903000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 428990000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1142893000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 713903000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 428990000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 1142893000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014822 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014549 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014683 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014822 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.014549 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014683 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014822 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014549 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014683 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13167.148704 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13413.567777 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13291.239330 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13167.148704 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13413.567777 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13291.239330 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13167.148704 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13413.567777 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13291.239330 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014813 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014544 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014676 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014813 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.014544 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014676 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014813 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014544 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014676 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13146.936342 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13467.317560 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13308.531710 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13146.936342 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13467.317560 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13308.531710 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13146.936342 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13467.317560 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13308.531710 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 126466.430469 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 127032.869411 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 126678.452671 # average ReadReq mshr uncacheable latency @@ -1005,54 +1012,54 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 6703 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 6703 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 2138 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 4565 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 6703 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 6703 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 6703 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 5647 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 13331.414911 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 11611.737502 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 7443.565061 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-32767 5646 99.98% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walks 6953 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 6953 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 2226 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 4727 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 6953 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 6953 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 6953 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 5856 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 13269.296448 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 11561.565854 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 7342.287931 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-32767 5855 99.98% 99.98% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::262144-294911 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 5647 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 5856 # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walksPending::samples 1639416500 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::0 1639416500 100.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::total 1639416500 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 3534 62.58% 62.58% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 2113 37.42% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 5647 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 6703 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkPageSizes::4K 3650 62.33% 62.33% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 2206 37.67% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 5856 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 6953 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 6703 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5647 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 6953 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5856 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5647 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 12350 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5856 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 12809 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses system.cpu1.dtb.read_hits 12475099 # DTB read hits -system.cpu1.dtb.read_misses 5811 # DTB read misses -system.cpu1.dtb.write_hits 9951122 # DTB write hits -system.cpu1.dtb.write_misses 892 # DTB write misses +system.cpu1.dtb.read_misses 5924 # DTB read misses +system.cpu1.dtb.write_hits 9998125 # DTB write hits +system.cpu1.dtb.write_misses 1029 # DTB write misses system.cpu1.dtb.flush_tlb 2942 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 436 # Number of times TLB was flushed by MVA +system.cpu1.dtb.flush_tlb_mva 476 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 4467 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 4683 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 929 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 921 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 214 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 12480910 # DTB read accesses -system.cpu1.dtb.write_accesses 9952014 # DTB write accesses +system.cpu1.dtb.perms_faults 228 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 12481023 # DTB read accesses +system.cpu1.dtb.write_accesses 9999154 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 22426221 # DTB hits -system.cpu1.dtb.misses 6703 # DTB misses -system.cpu1.dtb.accesses 22432924 # DTB accesses +system.cpu1.dtb.hits 22473224 # DTB hits +system.cpu1.dtb.misses 6953 # DTB misses +system.cpu1.dtb.accesses 22480177 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1082,117 +1089,117 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 3400 # Table walker walks requested -system.cpu1.itb.walker.walksShort 3400 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 811 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2589 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 3400 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 3400 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 3400 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 2613 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 13798.698814 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 12017.058980 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 7032.742162 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-16383 1945 74.44% 74.44% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-32767 667 25.53% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walks 3510 # Table walker walks requested +system.cpu1.itb.walker.walksShort 3510 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 846 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2664 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 3510 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 3510 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 3510 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 2707 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 13960.103436 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 12104.099399 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 7184.126564 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-16383 1964 72.55% 72.55% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-32767 742 27.41% 99.96% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::131072-147455 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 2613 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 2707 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walksPending::samples 1638889000 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 1638889000 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total 1638889000 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 1802 68.96% 68.96% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 811 31.04% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 2613 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 1861 68.75% 68.75% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 846 31.25% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 2707 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 3400 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 3400 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 3510 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 3510 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2613 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2613 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 6013 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 58726785 # ITB inst hits -system.cpu1.itb.inst_misses 3400 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2707 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2707 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 6217 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 58808308 # ITB inst hits +system.cpu1.itb.inst_misses 3510 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 2942 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 436 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb_mva 476 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2616 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2708 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 58730185 # ITB inst accesses -system.cpu1.itb.hits 58726785 # DTB hits -system.cpu1.itb.misses 3400 # DTB misses -system.cpu1.itb.accesses 58730185 # DTB accesses -system.cpu1.numCycles 2908727473 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 58811818 # ITB inst accesses +system.cpu1.itb.hits 58808308 # DTB hits +system.cpu1.itb.misses 3510 # DTB misses +system.cpu1.itb.accesses 58811818 # DTB accesses +system.cpu1.numCycles 2909262869 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 57164215 # Number of instructions committed -system.cpu1.committedOps 68869811 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 60957593 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 5807 # Number of float alu accesses -system.cpu1.num_func_calls 5082908 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 7664467 # number of instructions that are conditional controls -system.cpu1.num_int_insts 60957593 # number of integer instructions -system.cpu1.num_fp_insts 5807 # number of float instructions -system.cpu1.num_int_register_reads 110918664 # number of times the integer registers were read -system.cpu1.num_int_register_writes 42060766 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 4325 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1484 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 248948036 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 26157973 # number of times the CC registers were written -system.cpu1.num_mem_refs 23089661 # number of memory refs -system.cpu1.num_load_insts 12644031 # Number of load instructions -system.cpu1.num_store_insts 10445630 # Number of store instructions -system.cpu1.num_idle_cycles 2688977301.144567 # Number of idle cycles -system.cpu1.num_busy_cycles 219750171.855433 # Number of busy cycles -system.cpu1.not_idle_fraction 0.075549 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.924451 # Percentage of idle cycles -system.cpu1.Branches 13165858 # Number of branches fetched -system.cpu1.op_class::No_OpClass 2218 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 47327866 67.15% 67.15% # Class of executed instruction -system.cpu1.op_class::IntMult 56561 0.08% 67.23% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 4450 0.01% 67.24% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 67.24% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.24% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.24% # Class of executed instruction -system.cpu1.op_class::MemRead 12644031 17.94% 85.18% # Class of executed instruction -system.cpu1.op_class::MemWrite 10445630 14.82% 100.00% # Class of executed instruction -system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 70480756 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed +system.cpu1.committedInsts 57249193 # Number of instructions committed +system.cpu1.committedOps 68969707 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 61038090 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 5951 # Number of float alu accesses +system.cpu1.num_func_calls 5071147 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 7673896 # number of instructions that are conditional controls +system.cpu1.num_int_insts 61038090 # number of integer instructions +system.cpu1.num_fp_insts 5951 # number of float instructions +system.cpu1.num_int_register_reads 111115264 # number of times the integer registers were read +system.cpu1.num_int_register_writes 42140927 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 4654 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1298 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 249224724 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 26227815 # number of times the CC registers were written +system.cpu1.num_mem_refs 23129732 # number of memory refs +system.cpu1.num_load_insts 12642519 # Number of load instructions +system.cpu1.num_store_insts 10487213 # Number of store instructions +system.cpu1.num_idle_cycles 2689871255.481362 # Number of idle cycles +system.cpu1.num_busy_cycles 219391613.518638 # Number of busy cycles +system.cpu1.not_idle_fraction 0.075411 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.924589 # Percentage of idle cycles +system.cpu1.Branches 13171953 # Number of branches fetched +system.cpu1.op_class::No_OpClass 2206 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 47377307 67.13% 67.14% # Class of executed instruction +system.cpu1.op_class::IntMult 58319 0.08% 67.22% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 4478 0.01% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::MemRead 12642519 17.91% 85.14% # Class of executed instruction +system.cpu1.op_class::MemWrite 10487213 14.86% 100.00% # Class of executed instruction +system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::total 70572042 # Class of executed instruction system.iobus.trans_dist::ReadReq 30177 # Transaction distribution system.iobus.trans_dist::ReadResp 30177 # Transaction distribution system.iobus.trans_dist::WriteReq 59014 # Transaction distribution @@ -1247,63 +1254,63 @@ system.iobus.pkt_size_system.bridge.master::total 159125 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321056 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321056 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480181 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 38469000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 46335000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 98000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 16000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 95000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 644000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 21000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 52000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer21.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6286500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 172500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 36458500 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 126500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 186329023 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 186202055 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.occupancy 37000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36728000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36418 # number of replacements -system.iocache.tags.tagsinuse 1.084103 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.084308 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36434 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 313630728000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.084103 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.067756 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.067756 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 313834390000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.084308 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.067769 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.067769 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1317,14 +1324,14 @@ system.iocache.demand_misses::realview.ide 228 # system.iocache.demand_misses::total 228 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 228 # number of overall misses system.iocache.overall_misses::total 228 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 28361877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 28361877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4696967146 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4696967146 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 28361877 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 28361877 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 28361877 # number of overall miss cycles -system.iocache.overall_miss_latency::total 28361877 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 28182877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 28182877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4712497178 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4712497178 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 28182877 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 28182877 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 28182877 # number of overall miss cycles +system.iocache.overall_miss_latency::total 28182877 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 228 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 228 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -1341,19 +1348,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 124394.197368 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 124394.197368 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129664.508227 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 129664.508227 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 124394.197368 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 124394.197368 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 124394.197368 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 124394.197368 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 123609.109649 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 123609.109649 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130093.230400 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130093.230400 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 123609.109649 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 123609.109649 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 123609.109649 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 123609.109649 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 617 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 60 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.283333 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1367,14 +1374,14 @@ system.iocache.demand_mshr_misses::realview.ide 228 system.iocache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 228 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 228 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 16961877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 16961877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2885767146 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2885767146 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 16961877 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 16961877 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 16961877 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 16961877 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 16782877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 16782877 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2901297178 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2901297178 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 16782877 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 16782877 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 16782877 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 16782877 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1383,262 +1390,266 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74394.197368 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 74394.197368 # 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Cycle average of tags in use +system.l2c.tags.total_refs 4550112 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 152799 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 29.778415 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 50194.873681 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 1.905171 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4138.424328 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2240.226521 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.840428 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.000599 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 5521.257429 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2766.304421 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.765913 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 50199.141301 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 1.905024 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4090.389058 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2504.726247 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.838093 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.000605 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 5610.428826 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2455.776722 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.765978 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000029 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.063147 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.034183 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.062414 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.038219 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000043 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.084248 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.042210 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.989774 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.085608 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.037472 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.989764 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65165 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65231 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 40 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2128 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6804 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 56179 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 13 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2129 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6848 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 56203 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.994339 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 40610992 # Number of tag accesses -system.l2c.tags.data_accesses 40610992 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 6164 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3132 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 6231 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 3376 # number of ReadReq hits -system.l2c.ReadReq_hits::total 18903 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 685305 # number of Writeback hits -system.l2c.Writeback_hits::total 685305 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 10 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 14 # 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number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 6231 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 3376 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 844481 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 347722 # number of demand (read+write) hits -system.l2c.demand_hits::total 2378439 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 6164 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3132 # number of overall hits -system.l2c.overall_hits::cpu0.inst 834184 # number of overall hits -system.l2c.overall_hits::cpu0.data 333149 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 6231 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 3376 # number of overall hits -system.l2c.overall_hits::cpu1.inst 844481 # number of overall hits -system.l2c.overall_hits::cpu1.data 347722 # number of overall hits -system.l2c.overall_hits::total 2378439 # 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number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 23 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 80852 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 86095 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 166947 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 832656 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 845134 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 1677790 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 253841 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 257681 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 511522 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 5806 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 3022 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 832656 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 334693 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 6360 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 3498 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 845134 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 343776 # number of demand (read+write) hits +system.l2c.demand_hits::total 2374945 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 5806 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 3022 # number of overall hits +system.l2c.overall_hits::cpu0.inst 832656 # number of overall hits +system.l2c.overall_hits::cpu0.data 334693 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 6360 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 3498 # number of overall hits +system.l2c.overall_hits::cpu1.inst 845134 # number of overall hits +system.l2c.overall_hits::cpu1.data 343776 # number of overall hits +system.l2c.overall_hits::total 2374945 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 4 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 3 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses system.l2c.ReadReq_misses::total 8 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1406 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1339 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2745 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1384 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1358 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2742 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 2 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 69293 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 59501 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 128794 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 8056 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 9898 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 17954 # number of ReadCleanReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 6081 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 6196 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 12277 # number of ReadSharedReq misses +system.l2c.ReadExReq_misses::cpu0.data 67226 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 61688 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 128914 # number of ReadExReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 7792 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 10187 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 17979 # 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mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000296 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.000423 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.992938 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.989653 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.991333 # mshr miss rate for UpgradeReq accesses +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 5459722500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 11692365000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000688 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000471 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000286 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.000428 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.989986 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.993416 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.991682 # mshr miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.462058 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.406861 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.434806 # mshr miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.009565 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.011585 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::total 0.010582 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.023519 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.023191 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.023352 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000649 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.009565 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.184504 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000481 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000296 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011585 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.158911 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.062674 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000649 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.009565 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.184504 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000481 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000296 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011585 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.158911 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.062674 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 122750 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 127333.333333 # average ReadReq mshr miss latency +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.453990 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.417423 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.435725 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.009271 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.011910 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.010602 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.025203 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.021300 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.023241 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000688 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.009271 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.180642 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000471 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000286 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011910 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.163709 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.062775 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000688 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.009271 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.180642 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000471 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000286 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011910 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.163709 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.062775 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 122625 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 122833.333333 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 123000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 124500 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70817.211949 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70784.540702 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70801.275046 # average UpgradeReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 122750 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70812.861272 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70803.387334 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70808.169220 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 69500 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 116781.514727 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 117326.893666 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 117033.472056 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 120446.933962 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 120738.886644 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 120607.886822 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 122228.169709 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 121606.601033 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 121914.474220 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 122750 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 120446.933962 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 117220.938255 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 127333.333333 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 116824.829679 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 117354.534107 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 117078.304141 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 120547.099589 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 120769.755571 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 120673.257690 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 122722.763980 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 121158.612696 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 122002.054063 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 122625 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 120547.099589 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 117349.408448 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 122833.333333 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 123000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 120738.886644 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 117730.520420 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 117814.183220 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 122750 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 120446.933962 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 117220.938255 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 127333.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 120769.755571 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 117671.540656 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 117861.634983 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 122625 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 120547.099589 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 117349.408448 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 122833.333333 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 123000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 120738.886644 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 117730.520420 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 117814.183220 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 120769.755571 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 117671.540656 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 117861.634983 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113966.430469 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 177699.603306 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190696.288151 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 114532.869411 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 178593.892462 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 163786.068227 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 162147.785478 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 162195.207154 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 162172.387546 # average WriteReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 187709.397471 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 172306.635956 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 174840.241990 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 171239.049296 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172986.715720 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113966.430469 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 170429.932045 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 183219.739391 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 114532.869411 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 170854.184528 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 163128.939173 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 179998.763682 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 172583.580569 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 40160 # Transaction distribution -system.membus.trans_dist::ReadResp 70627 # Transaction distribution +system.membus.trans_dist::ReadResp 70546 # Transaction distribution system.membus.trans_dist::WriteReq 27589 # Transaction distribution system.membus.trans_dist::WriteResp 27589 # Transaction distribution -system.membus.trans_dist::Writeback 117457 # Transaction distribution -system.membus.trans_dist::CleanEvict 6338 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4503 # Transaction distribution +system.membus.trans_dist::WritebackDirty 117374 # Transaction distribution +system.membus.trans_dist::CleanEvict 6393 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4497 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4505 # Transaction distribution -system.membus.trans_dist::ReadExReq 127036 # Transaction distribution -system.membus.trans_dist::ReadExResp 127036 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 30467 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4499 # Transaction distribution +system.membus.trans_dist::ReadExReq 127159 # Transaction distribution +system.membus.trans_dist::ReadExResp 127159 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 30386 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 438779 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 546371 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 438823 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 546415 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108894 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 108894 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 655265 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 655309 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 15304828 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 15468181 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 15302204 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 15465557 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17785301 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17782677 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 492 # Total snoops (count) -system.membus.snoop_fanout::samples 389991 # Request fanout histogram +system.membus.snoop_fanout::samples 390002 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 389991 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 390002 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 389991 # Request fanout histogram -system.membus.reqLayer0.occupancy 90490000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 390002 # Request fanout histogram +system.membus.reqLayer0.occupancy 90453500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1693000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1722000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 821977659 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 823113783 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 952225245 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 952221498 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 64492032 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 64071640 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -1920,59 +1931,60 @@ system.realview.realview_io.osc_peripheral.clock 41667 system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 5059453 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2540884 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 38074 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 582 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 582 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 5052869 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2537534 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 38120 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 581 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 581 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 75104 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2297700 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 74671 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2294380 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 27589 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 27589 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 802762 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1800707 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2769 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 801219 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1664516 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 134433 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2765 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2771 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 296210 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 296210 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1696651 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 525960 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2767 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 295861 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 295861 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1695803 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 523921 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5076713 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2581153 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 18522 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 35333 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7711721 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108619704 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96660573 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 26036 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 49608 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 205355921 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 176740 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 5302052 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.018353 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.134225 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5074132 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2573976 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 18410 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 34795 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7701313 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 215094328 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96414109 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 26084 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 48692 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 311583213 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 176501 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 2780821 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.021276 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.144303 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 5204742 98.16% 98.16% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 97310 1.84% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 2721656 97.87% 97.87% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 59165 2.13% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 5302052 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 3269894500 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.snoop_fanout::total 2780821 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4960265000 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 380377 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2553998500 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2552726500 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1279231000 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1275647499 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 12013000 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 11889000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 22931000 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 22622000 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |