diff options
author | Andreas Sandberg <andreas@sandberg.pp.se> | 2013-10-02 11:03:38 +0200 |
---|---|---|
committer | Andreas Sandberg <andreas@sandberg.pp.se> | 2013-10-02 11:03:38 +0200 |
commit | 0438bf9389f8cdfa76c532e4f288c2256bdca9ff (patch) | |
tree | 97279f7a58dee3174bfbd8f36de6a5e44a1a19ad /tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt | |
parent | d3d53938c05aa2cecd47fd8b29ec36f1c71303d5 (diff) | |
download | gem5-0438bf9389f8cdfa76c532e4f288c2256bdca9ff.tar.xz |
stats: Update x86 stats after x87 fixes
The updates to the x87 caused the stats for several regressions to
change. This was mainly caused by the addition of a working 32-bit and
80-bit FP load instruction and xsave support.
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt')
-rw-r--r-- | tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt | 456 |
1 files changed, 228 insertions, 228 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index 4e0947e27..2407ce1be 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -1,51 +1,51 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.112102 # Number of seconds simulated -sim_ticks 5112102211000 # Number of ticks simulated -final_tick 5112102211000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.112126 # Number of seconds simulated +sim_ticks 5112126311000 # Number of ticks simulated +final_tick 5112126311000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 856407 # Simulator instruction rate (inst/s) -host_op_rate 1753461 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 21900233108 # Simulator tick rate (ticks/s) -host_mem_usage 584104 # Number of bytes of host memory used -host_seconds 233.43 # Real time elapsed on the host -sim_insts 199908396 # Number of instructions simulated -sim_ops 409304707 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2421056 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory +host_inst_rate 1020096 # Simulator instruction rate (inst/s) +host_op_rate 2088583 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 26083435490 # Simulator tick rate (ticks/s) +host_mem_usage 587152 # Number of bytes of host memory used +host_seconds 195.99 # Real time elapsed on the host +sim_insts 199929810 # Number of instructions simulated +sim_ops 409343980 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2421184 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 852736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10605120 # Number of bytes read from this memory -system.physmem.bytes_read::total 13879360 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10609344 # Number of bytes read from this memory +system.physmem.bytes_read::total 13883648 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 852736 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 852736 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9264512 # Number of bytes written to this memory -system.physmem.bytes_written::total 9264512 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 37829 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 2 # Number of read requests responded to by this memory +system.physmem.bytes_written::writebacks 9268672 # Number of bytes written to this memory +system.physmem.bytes_written::total 9268672 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 37831 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 13324 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 165705 # Number of read requests responded to by this memory -system.physmem.num_reads::total 216865 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 144758 # Number of write requests responded to by this memory -system.physmem.num_writes::total 144758 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 473593 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 25 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu.data 165771 # Number of read requests responded to by this memory +system.physmem.num_reads::total 216932 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 144823 # Number of write requests responded to by this memory +system.physmem.num_writes::total 144823 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 473616 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 13 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 166807 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2074513 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2715000 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2075329 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2715826 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 166807 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 166807 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1812270 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1812270 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1812270 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 473593 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 25 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 1813076 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1813076 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1813076 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 473616 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 13 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 166807 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2074513 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4527271 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2075329 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4528902 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 0 # Total number of read requests accepted by DRAM controller system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller system.physmem.readBursts 0 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts @@ -193,16 +193,16 @@ system.physmem.writeRowHits 0 # Nu system.physmem.readRowHitRate nan # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap nan # Average gap between requests -system.membus.throughput 9632725 # Throughput (bytes/s) -system.membus.data_through_bus 49243475 # Total data (bytes) +system.membus.throughput 9634332 # Throughput (bytes/s) +system.membus.data_through_bus 49251923 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.iocache.tags.replacements 47569 # number of replacements -system.iocache.tags.tagsinuse 0.042449 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.042448 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 47585 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 4994822663009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042449 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 4994846763009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042448 # Average occupied blocks per requestor system.iocache.tags.occ_percent::pc.south_bridge.ide 0.002653 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.002653 # Average percentage of cache occupancy system.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses @@ -252,59 +252,59 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.throughput 2555194 # Throughput (bytes/s) -system.iobus.data_through_bus 13062414 # Total data (bytes) -system.cpu.numCycles 10224204444 # number of cpu cycles simulated +system.iobus.throughput 2555207 # Throughput (bytes/s) +system.iobus.data_through_bus 13062542 # Total data (bytes) +system.cpu.numCycles 10224252644 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 199908396 # Number of instructions committed -system.cpu.committedOps 409304707 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 374467605 # Number of integer alu accesses +system.cpu.committedInsts 199929810 # Number of instructions committed +system.cpu.committedOps 409343980 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 374506599 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 2307395 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 39972475 # number of instructions that are conditional controls -system.cpu.num_int_insts 374467605 # number of integer instructions +system.cpu.num_func_calls 2307717 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 39976354 # number of instructions that are conditional controls +system.cpu.num_int_insts 374506599 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 915905592 # number of times the integer registers were read -system.cpu.num_int_register_writes 480549431 # number of times the integer registers were written +system.cpu.num_int_register_reads 916001165 # number of times the integer registers were read +system.cpu.num_int_register_writes 480603129 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 35655576 # number of memory refs -system.cpu.num_load_insts 27235236 # Number of load instructions -system.cpu.num_store_insts 8420340 # Number of store instructions -system.cpu.num_idle_cycles 9770516372.735863 # Number of idle cycles -system.cpu.num_busy_cycles 453688071.264138 # Number of busy cycles -system.cpu.not_idle_fraction 0.044374 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.955626 # Percentage of idle cycles +system.cpu.num_mem_refs 35660913 # number of memory refs +system.cpu.num_load_insts 27238816 # Number of load instructions +system.cpu.num_store_insts 8422097 # Number of store instructions +system.cpu.num_idle_cycles 9770516880.735765 # Number of idle cycles +system.cpu.num_busy_cycles 453735763.264236 # Number of busy cycles +system.cpu.not_idle_fraction 0.044378 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.955622 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.icache.tags.replacements 790522 # number of replacements -system.cpu.icache.tags.tagsinuse 510.666660 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 243495984 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 791034 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 307.819871 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 148824778500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.666660 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997396 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997396 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 243495984 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 243495984 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 243495984 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 243495984 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 243495984 # number of overall hits -system.cpu.icache.overall_hits::total 243495984 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 791041 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 791041 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 791041 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 791041 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 791041 # number of overall misses -system.cpu.icache.overall_misses::total 791041 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 244287025 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 244287025 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 244287025 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 244287025 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 244287025 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 244287025 # number of overall (read+write) accesses +system.cpu.icache.tags.replacements 790541 # number of replacements +system.cpu.icache.tags.tagsinuse 510.665021 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 243525798 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 791053 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 307.850167 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 148848615500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.665021 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997393 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997393 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 243525798 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 243525798 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 243525798 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 243525798 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 243525798 # number of overall hits +system.cpu.icache.overall_hits::total 243525798 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 791060 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 791060 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 791060 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 791060 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 791060 # number of overall misses +system.cpu.icache.overall_misses::total 791060 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 244316858 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 244316858 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 244316858 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 244316858 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 244316858 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 244316858 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003238 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.003238 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.003238 # miss rate for demand accesses @@ -321,14 +321,14 @@ system.cpu.icache.fast_writes 0 # nu system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.itb_walker_cache.tags.replacements 3477 # number of replacements -system.cpu.itb_walker_cache.tags.tagsinuse 3.026296 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.tagsinuse 3.026300 # Cycle average of tags in use system.cpu.itb_walker_cache.tags.total_refs 7886 # Total number of references to valid blocks. system.cpu.itb_walker_cache.tags.sampled_refs 3489 # Sample count of references to valid blocks. system.cpu.itb_walker_cache.tags.avg_refs 2.260246 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.tags.warmup_cycle 5102094222000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026296 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.189143 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_percent::total 0.189143 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.warmup_cycle 5102118322000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026300 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.189144 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_percent::total 0.189144 # Average percentage of cache occupancy system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7887 # number of ReadReq hits system.cpu.itb_walker_cache.ReadReq_hits::total 7887 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits @@ -369,38 +369,38 @@ system.cpu.itb_walker_cache.writebacks::writebacks 526 system.cpu.itb_walker_cache.writebacks::total 526 # number of writebacks system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dtb_walker_cache.tags.replacements 7632 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 5.014181 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 12948 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.tagsinuse 5.014180 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 12955 # Total number of references to valid blocks. system.cpu.dtb_walker_cache.tags.sampled_refs 7644 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.693878 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 5100438909500 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.014181 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.avg_refs 1.694793 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 5100463009500 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.014180 # Average occupied blocks per requestor system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313386 # Average percentage of cache occupancy system.cpu.dtb_walker_cache.tags.occ_percent::total 0.313386 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12956 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 12956 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12956 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 12956 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12956 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 12956 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8822 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 8822 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8822 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 8822 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8822 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 8822 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21778 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 21778 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21778 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 21778 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21778 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 21778 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.405088 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.405088 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.405088 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.405088 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.405088 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.405088 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12963 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 12963 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12963 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 12963 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12963 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 12963 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8824 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 8824 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8824 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 8824 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8824 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 8824 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21787 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 21787 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21787 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 21787 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21787 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 21787 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.405012 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.405012 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.405012 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.405012 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.405012 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.405012 # miss rate for overall accesses system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -409,50 +409,50 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 2413 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 2413 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::writebacks 2433 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 2433 # number of writebacks system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1622027 # number of replacements +system.cpu.dcache.tags.replacements 1622093 # number of replacements system.cpu.dcache.tags.tagsinuse 511.999424 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 20170040 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1622539 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.431159 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 20175183 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1622605 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.433823 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.999424 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 12074025 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 12074025 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8093747 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8093747 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 20167772 # 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miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.074558 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.074558 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.074558 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.074558 # miss rate for overall accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.074544 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.074544 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.074544 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.074544 # miss rate for overall accesses system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -461,109 +461,109 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # 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number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2422259 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6504 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 791047 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1621986 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2422345 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6505 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.itb.walker 2807 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 791028 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1621920 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2422259 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000308 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::cpu.inst 791047 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1621986 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2422345 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000154 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001781 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016845 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024657 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.021620 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989029 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989029 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.427823 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.427823 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000308 # miss rate for demand accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.021619 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989041 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989041 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.427942 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.427942 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000154 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001781 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016845 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.102741 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.074298 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000308 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.102778 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.074323 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000154 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001781 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016845 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.102741 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.074298 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.102778 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.074323 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -572,8 +572,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 98091 # number of writebacks -system.cpu.l2cache.writebacks::total 98091 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 98156 # number of writebacks +system.cpu.l2cache.writebacks::total 98156 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |