stats: update stats for icache change not allowing dirty data

1 files changed, 11 insertions, 13 deletions

diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
index 96f4e7d80..4f10e01e9 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  5.112043                       # Nu
 sim_ticks                                5112043255000                       # Number of ticks simulated
 final_tick                               5112043255000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1067695                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2186181                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            27315912254                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 409548                       # Number of bytes of host memory used
-host_seconds                                   187.15                       # Real time elapsed on the host
+host_inst_rate                                1419112                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2905734                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            36306590178                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 362152                       # Number of bytes of host memory used
+host_seconds                                   140.80                       # Real time elapsed on the host
 sim_insts                                   199813914                       # Number of instructions simulated
 sim_ops                                     409133298                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::pc.south_bridge.ide      2464768                       # Number of bytes read from this memory
@@ -48,9 +48,9 @@ system.physmem.bw_total::cpu.data             2073572                       # To
 system.physmem.bw_total::total                4540656                       # Total bandwidth to/from this memory (bytes/s)
 system.l2c.replacements                        106561                       # number of replacements
 system.l2c.tagsinuse                     64822.143261                       # Cycle average of tags in use
-system.l2c.total_refs                         3457342                       # Total number of references to valid blocks.
+system.l2c.total_refs                         3456533                       # Total number of references to valid blocks.
 system.l2c.sampled_refs                        170680                       # Sample count of references to valid blocks.
-system.l2c.avg_refs                         20.256281                       # Average number of references to valid blocks.
+system.l2c.avg_refs                         20.251541                       # Average number of references to valid blocks.
 system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
 system.l2c.occ_blocks::writebacks        51981.461987                       # Average occupied blocks per requestor
 system.l2c.occ_blocks::cpu.dtb.walker        0.004954                       # Average occupied blocks per requestor
@@ -68,8 +68,8 @@ system.l2c.ReadReq_hits::cpu.itb.walker          2700                       # nu
 system.l2c.ReadReq_hits::cpu.inst              777957                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu.data             1275395                       # number of ReadReq hits
 system.l2c.ReadReq_hits::total                2062630                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks         1538939                       # number of Writeback hits
-system.l2c.Writeback_hits::total              1538939                       # number of Writeback hits
+system.l2c.Writeback_hits::writebacks         1538130                       # number of Writeback hits
+system.l2c.Writeback_hits::total              1538130                       # number of Writeback hits
 system.l2c.UpgradeReq_hits::cpu.data               28                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::total                  28                       # number of UpgradeReq hits
 system.l2c.ReadExReq_hits::cpu.data            179208                       # number of ReadExReq hits
@@ -108,8 +108,8 @@ system.l2c.ReadReq_accesses::cpu.itb.walker         2705                       #
 system.l2c.ReadReq_accesses::cpu.inst          791299                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::cpu.data         1307579                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::total            2108163                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks      1538939                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total          1538939                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks      1538130                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total          1538130                       # number of Writeback accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::cpu.data         1824                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::total            1824                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::cpu.data        313585                       # number of ReadExReq accesses(hits+misses)
@@ -275,8 +275,6 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks          809                       # number of writebacks
-system.cpu.icache.writebacks::total               809                       # number of writebacks
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.itb_walker_cache.replacements         3335                       # number of replacements
 system.cpu.itb_walker_cache.tagsinuse        3.026444                       # Cycle average of tags in use