all: Update stats for memory per master and total fix.

2 files changed, 137 insertions, 18 deletions

diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
index 70b899ba9..d30404a01 100755
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun  3 2012 13:30:44
-gem5 started Jun  3 2012 13:30:59
-gem5 executing on burrito
+gem5 compiled Jun  4 2012 13:44:28
+gem5 started Jun  4 2012 15:05:12
+gem5 executing on zizzer
 command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing
 warning: add_child('terminal'): child 'terminal' already has parent
 Global frequency set at 1000000000000 ticks per second
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
index 92c083c66..9cc951eb3 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
@@ -4,23 +4,48 @@ sim_seconds                                  5.195470                       # Nu
 sim_ticks                                5195470393000                       # Number of ticks simulated
 final_tick                               5195470393000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 435377                       # Simulator instruction rate (inst/s)
-host_op_rate                                   835677                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            16374771456                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 374904                       # Number of bytes of host memory used
-host_seconds                                   317.29                       # Real time elapsed on the host
+host_inst_rate                                 792632                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1521406                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            29811367673                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 354100                       # Number of bytes of host memory used
+host_seconds                                   174.28                       # Real time elapsed on the host
 sim_insts                                   138138472                       # Number of instructions simulated
 sim_ops                                     265147881                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                    13764096                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                 974400                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                 10427072                       # Number of bytes written to this memory
-system.physmem.num_reads                       215064                       # Number of read requests responded to by this memory
-system.physmem.num_writes                      162923                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                        2649249                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                    187548                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                       2006954                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                       4656204                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::pc.south_bridge.ide      2876352                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker          832                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker          640                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst            974400                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9911872                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             13764096                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       974400                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          974400                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     10427072                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          10427072                       # Number of bytes written to this memory
+system.physmem.num_reads::pc.south_bridge.ide        44943                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker           13                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker           10                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              15225                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             154873                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                215064                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          162923                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               162923                       # Number of write requests responded to by this memory
+system.physmem.bw_read::pc.south_bridge.ide       553627                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker            160                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker            123                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               187548                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1907791                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2649249                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          187548                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             187548                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2006954                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2006954                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2006954                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide       553627                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker           160                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker           123                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              187548                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1907791                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                4656204                       # Total bandwidth to/from this memory (bytes/s)
 system.l2c.replacements                        136133                       # number of replacements
 system.l2c.tagsinuse                     31389.895470                       # Cycle average of tags in use
 system.l2c.total_refs                         3363370                       # Total number of references to valid blocks.
@@ -122,30 +147,40 @@ system.l2c.ReadReq_miss_rate::cpu.dtb.walker     0.001987
 system.l2c.ReadReq_miss_rate::cpu.itb.walker     0.003286                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu.inst       0.019307                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu.data       0.027160                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.024110                       # miss rate for ReadReq accesses
 system.l2c.UpgradeReq_miss_rate::cpu.data     0.810539                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.810539                       # miss rate for UpgradeReq accesses
 system.l2c.ReadExReq_miss_rate::cpu.data     0.383769                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.383769                       # miss rate for ReadExReq accesses
 system.l2c.demand_miss_rate::cpu.dtb.walker     0.001987                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu.itb.walker     0.003286                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu.inst        0.019307                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu.data        0.095954                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.070620                       # miss rate for demand accesses
 system.l2c.overall_miss_rate::cpu.dtb.walker     0.001987                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu.itb.walker     0.003286                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu.inst       0.019307                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu.data       0.095954                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.070620                       # miss rate for overall accesses
 system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker        52000                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker        52000                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu.inst 52007.618547                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu.data 52361.049436                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 52255.016722                       # average ReadReq miss latency
 system.l2c.UpgradeReq_avg_miss_latency::cpu.data 24673.484295                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 24673.484295                       # average UpgradeReq miss latency
 system.l2c.ReadExReq_avg_miss_latency::cpu.data 52004.897310                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 52004.897310                       # average ReadExReq miss latency
 system.l2c.demand_avg_miss_latency::cpu.dtb.walker        52000                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu.itb.walker        52000                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu.inst 52007.618547                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu.data 52086.260586                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 52079.246541                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu.dtb.walker        52000                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu.itb.walker        52000                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu.inst 52007.618547                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu.data 52086.260586                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 52079.246541                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -204,33 +239,46 @@ system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.001987
 system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker     0.003286                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::cpu.inst     0.019307                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::cpu.data     0.027160                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.024110                       # mshr miss rate for ReadReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::cpu.data     0.810539                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.810539                       # mshr miss rate for UpgradeReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::cpu.data     0.383769                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.383769                       # mshr miss rate for ReadExReq accesses
 system.l2c.demand_mshr_miss_rate::cpu.dtb.walker     0.001987                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu.itb.walker     0.003286                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu.inst     0.019307                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu.data     0.095954                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.070620                       # mshr miss rate for demand accesses
 system.l2c.overall_mshr_miss_rate::cpu.dtb.walker     0.001987                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu.itb.walker     0.003286                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu.inst     0.019307                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu.data     0.095954                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.070620                       # mshr miss rate for overall accesses
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker        40000                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        40000                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40006.699067                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40360.922965                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 40254.652764                       # average ReadReq mshr miss latency
 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40254.930606                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40254.930606                       # average UpgradeReq mshr miss latency
 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40004.868185                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 40004.868185                       # average ReadExReq mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker        40000                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker        40000                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40006.699067                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu.data 40086.209221                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 40079.117884                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker        40000                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker        40000                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40006.699067                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu.data 40086.209221                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 40079.117884                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.iocache.replacements                     47510                       # number of replacements
 system.iocache.tagsinuse                     0.120586                       # Cycle average of tags in use
@@ -266,13 +314,21 @@ system.iocache.demand_accesses::total           47564                       # nu
 system.iocache.overall_accesses::pc.south_bridge.ide        47564                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::total          47564                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteReq accesses
+system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
 system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
+system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
+system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
 system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 126274.800948                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 126274.800948                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 136801.779966                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 136801.779966                       # average WriteReq miss latency
 system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 136614.983853                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 136614.983853                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 136614.983853                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 136614.983853                       # average overall miss latency
 system.iocache.blocked_cycles::no_mshrs      69564644                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                11299                       # number of cycles access was blocked
@@ -300,13 +356,21 @@ system.iocache.demand_mshr_miss_latency::total   4024343976
 system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide   4024343976                       # number of overall MSHR miss cycles
 system.iocache.overall_mshr_miss_latency::total   4024343976                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteReq accesses
+system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
 system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
 system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 74249.973934                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 74249.973934                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 84796.168622                       # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 84796.168622                       # average WriteReq mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 84609.031536                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 84609.031536                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 84609.031536                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 84609.031536                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
 system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
@@ -378,11 +442,17 @@ system.cpu.icache.demand_accesses::total    159222590                       # nu
 system.cpu.icache.overall_accesses::cpu.inst    159222590                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::total    159222590                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.004953                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.004953                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.004953                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.004953                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.004953                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.004953                       # miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14812.203135                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 14812.203135                       # average ReadReq miss latency
 system.cpu.icache.demand_avg_miss_latency::cpu.inst 14812.203135                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 14812.203135                       # average overall miss latency
 system.cpu.icache.overall_avg_miss_latency::cpu.inst 14812.203135                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 14812.203135                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -406,11 +476,17 @@ system.cpu.icache.demand_mshr_miss_latency::total   9314744000
 system.cpu.icache.overall_mshr_miss_latency::cpu.inst   9314744000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_latency::total   9314744000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.004953                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.004953                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.004953                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.004953                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.004953                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.004953                       # mshr miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11810.878733                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11810.878733                       # average ReadReq mshr miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11810.878733                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 11810.878733                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11810.878733                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11810.878733                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.itb_walker_cache.replacements         3754                       # number of replacements
 system.cpu.itb_walker_cache.tagsinuse        3.070606                       # Cycle average of tags in use
@@ -450,11 +526,17 @@ system.cpu.itb_walker_cache.demand_accesses::total        12223
 system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        12223                       # number of overall (read+write) accesses
 system.cpu.itb_walker_cache.overall_accesses::total        12223                       # number of overall (read+write) accesses
 system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.376565                       # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.376565                       # miss rate for ReadReq accesses
 system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.376503                       # miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_miss_rate::total     0.376503                       # miss rate for demand accesses
 system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.376503                       # miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_miss_rate::total     0.376503                       # miss rate for overall accesses
 system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11042.372881                       # average ReadReq miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11042.372881                       # average ReadReq miss latency
 system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11042.372881                       # average overall miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11042.372881                       # average overall miss latency
 system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11042.372881                       # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11042.372881                       # average overall miss latency
 system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -478,11 +560,17 @@ system.cpu.itb_walker_cache.demand_mshr_miss_latency::total     37011000
 system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker     37011000                       # number of overall MSHR miss cycles
 system.cpu.itb_walker_cache.overall_mshr_miss_latency::total     37011000                       # number of overall MSHR miss cycles
 system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.376565                       # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.376565                       # mshr miss rate for ReadReq accesses
 system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.376503                       # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.376503                       # mshr miss rate for demand accesses
 system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.376503                       # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.376503                       # mshr miss rate for overall accesses
 system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  8042.372881                       # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total  8042.372881                       # average ReadReq mshr miss latency
 system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  8042.372881                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total  8042.372881                       # average overall mshr miss latency
 system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  8042.372881                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total  8042.372881                       # average overall mshr miss latency
 system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
 system.cpu.dtb_walker_cache.replacements         7704                       # number of replacements
 system.cpu.dtb_walker_cache.tagsinuse        5.052403                       # Cycle average of tags in use
@@ -518,11 +606,17 @@ system.cpu.dtb_walker_cache.demand_accesses::total        21947
 system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker        21947                       # number of overall (read+write) accesses
 system.cpu.dtb_walker_cache.overall_accesses::total        21947                       # number of overall (read+write) accesses
 system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.405340                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.405340                       # miss rate for ReadReq accesses
 system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.405340                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::total     0.405340                       # miss rate for demand accesses
 system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.405340                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::total     0.405340                       # miss rate for overall accesses
 system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 11678.900629                       # average ReadReq miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 11678.900629                       # average ReadReq miss latency
 system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 11678.900629                       # average overall miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 11678.900629                       # average overall miss latency
 system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 11678.900629                       # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 11678.900629                       # average overall miss latency
 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -546,11 +640,17 @@ system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total     77207000
 system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker     77207000                       # number of overall MSHR miss cycles
 system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total     77207000                       # number of overall MSHR miss cycles
 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.405340                       # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.405340                       # mshr miss rate for ReadReq accesses
 system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.405340                       # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.405340                       # mshr miss rate for demand accesses
 system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.405340                       # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.405340                       # mshr miss rate for overall accesses
 system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker  8678.844424                       # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total  8678.844424                       # average ReadReq mshr miss latency
 system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker  8678.844424                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total  8678.844424                       # average overall mshr miss latency
 system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker  8678.844424                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total  8678.844424                       # average overall mshr miss latency
 system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                1623424                       # number of replacements
 system.cpu.dcache.tagsinuse                511.997312                       # Cycle average of tags in use
@@ -594,13 +694,21 @@ system.cpu.dcache.demand_accesses::total     21635359                       # nu
 system.cpu.dcache.overall_accesses::cpu.data     21635359                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total     21635359                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.098647                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.098647                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.037778                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.037778                       # miss rate for WriteReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.075163                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.075163                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.075163                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.075163                       # miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15144.526649                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 15144.526649                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30172.881044                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 30172.881044                       # average WriteReq miss latency
 system.cpu.dcache.demand_avg_miss_latency::cpu.data 18058.802043                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 18058.802043                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::cpu.data 18058.802043                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 18058.802043                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -634,16 +742,27 @@ system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   1379728500
 system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  77305053000                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_latency::total  77305053000                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.098647                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.098647                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.037778                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.037778                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.075163                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.075163                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.075163                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.075163                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12144.494227                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12144.494227                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27172.847747                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27172.847747                       # average WriteReq mshr miss latency
 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15058.769451                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 15058.769451                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15058.769451                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 15058.769451                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------