diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-04-23 00:03:05 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-04-23 00:03:05 -0500 |
| commit | 3295e6de699d2baa8a73cc9280f1929a42314f00 (patch) | |
| tree | bb411b7de503d564a0964a36d3b30c57350490d4 /tests/quick/fs/10.linux-boot/ref/x86 | |
| parent | 25a6b1866e7c195c45c3d23f00937aa13bb2a2ff (diff) | |
| download | gem5-3295e6de699d2baa8a73cc9280f1929a42314f00.tar.xz | |
x86, stats: updates due to lret bugfix
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/x86')
4 files changed, 809 insertions, 809 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout index f095afad7..451dd9824 100755 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-si gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 28 2013 09:59:18 -gem5 started Mar 28 2013 09:59:40 +gem5 compiled Apr 18 2013 13:37:41 +gem5 started Apr 18 2013 14:20:21 gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic Global frequency set at 1000000000000 ticks per second info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5112099860500 because m5_exit instruction encountered +Exiting @ tick 5112099861500 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index 55530e4a5..c125666af 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 5.112100 # Number of seconds simulated -sim_ticks 5112099860500 # Number of ticks simulated -final_tick 5112099860500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 5112099861500 # Number of ticks simulated +final_tick 5112099861500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1028107 # Simulator instruction rate (inst/s) -host_op_rate 2105009 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 26291327617 # Simulator tick rate (ticks/s) -host_mem_usage 628192 # Number of bytes of host memory used -host_seconds 194.44 # Real time elapsed on the host +host_inst_rate 1058684 # Simulator instruction rate (inst/s) +host_op_rate 2167614 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 27073251373 # Simulator tick rate (ticks/s) +host_mem_usage 628224 # Number of bytes of host memory used +host_seconds 188.82 # Real time elapsed on the host sim_insts 199905607 # Number of instructions simulated -sim_ops 409299132 # Number of ops (including micro ops) simulated +sim_ops 409299164 # Number of ops (including micro ops) simulated system.physmem.bytes_read::pc.south_bridge.ide 2420928 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory @@ -194,7 +194,7 @@ system.iocache.tagsinuse 0.042441 # Cy system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 47584 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 4994822603059 # Cycle when the warmup percentage was hit. +system.iocache.warmup_cycle 4994822604059 # Cycle when the warmup percentage was hit. system.iocache.occ_blocks::pc.south_bridge.ide 0.042441 # Average occupied blocks per requestor system.iocache.occ_percent::pc.south_bridge.ide 0.002653 # Average percentage of cache occupancy system.iocache.occ_percent::total 0.002653 # Average percentage of cache occupancy @@ -245,57 +245,57 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 10224199744 # number of cpu cycles simulated +system.cpu.numCycles 10224199746 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 199905607 # Number of instructions committed -system.cpu.committedOps 409299132 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 374462045 # Number of integer alu accesses +system.cpu.committedOps 409299164 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 374462077 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 39972114 # number of instructions that are conditional controls -system.cpu.num_int_insts 374462045 # number of integer instructions +system.cpu.num_conditional_control_insts 39972120 # number of instructions that are conditional controls +system.cpu.num_int_insts 374462077 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 915890298 # number of times the integer registers were read -system.cpu.num_int_register_writes 480542887 # number of times the integer registers were written +system.cpu.num_int_register_reads 915890450 # number of times the integer registers were read +system.cpu.num_int_register_writes 480542967 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written system.cpu.num_mem_refs 35654170 # number of memory refs system.cpu.num_load_insts 27234345 # Number of load instructions system.cpu.num_store_insts 8419825 # Number of store instructions -system.cpu.num_idle_cycles 9770518400.401503 # Number of idle cycles -system.cpu.num_busy_cycles 453681343.598497 # Number of busy cycles +system.cpu.num_idle_cycles 9770518373.401503 # Number of idle cycles +system.cpu.num_busy_cycles 453681372.598497 # Number of busy cycles system.cpu.not_idle_fraction 0.044373 # Percentage of non-idle cycles system.cpu.idle_fraction 0.955627 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu.icache.replacements 790584 # number of replacements system.cpu.icache.tagsinuse 510.666660 # Cycle average of tags in use -system.cpu.icache.total_refs 243492014 # Total number of references to valid blocks. +system.cpu.icache.total_refs 243492011 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 791096 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 307.790728 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 148824778500 # Cycle when the warmup percentage was hit. +system.cpu.icache.avg_refs 307.790725 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 148824779500 # Cycle when the warmup percentage was hit. system.cpu.icache.occ_blocks::cpu.inst 510.666660 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.997396 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.997396 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 243492014 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 243492014 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 243492014 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 243492014 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 243492014 # number of overall hits -system.cpu.icache.overall_hits::total 243492014 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 243492011 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 243492011 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 243492011 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 243492011 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 243492011 # number of overall hits +system.cpu.icache.overall_hits::total 243492011 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 791103 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 791103 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 791103 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 791103 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 791103 # number of overall misses system.cpu.icache.overall_misses::total 791103 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 244283117 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 244283117 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 244283117 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 244283117 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 244283117 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 244283117 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 244283114 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 244283114 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 244283114 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 244283114 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 244283114 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 244283114 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003238 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.003238 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.003238 # miss rate for demand accesses @@ -316,7 +316,7 @@ system.cpu.itb_walker_cache.tagsinuse 3.026333 # Cy system.cpu.itb_walker_cache.total_refs 7886 # Total number of references to valid blocks. system.cpu.itb_walker_cache.sampled_refs 3489 # Sample count of references to valid blocks. system.cpu.itb_walker_cache.avg_refs 2.260246 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5102064745500 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.warmup_cycle 5102064746500 # Cycle when the warmup percentage was hit. system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.026333 # Average occupied blocks per requestor system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.189146 # Average percentage of cache occupancy system.cpu.itb_walker_cache.occ_percent::total 0.189146 # Average percentage of cache occupancy @@ -364,7 +364,7 @@ system.cpu.dtb_walker_cache.tagsinuse 5.014191 # Cy system.cpu.dtb_walker_cache.total_refs 12947 # Total number of references to valid blocks. system.cpu.dtb_walker_cache.sampled_refs 7641 # Sample count of references to valid blocks. system.cpu.dtb_walker_cache.avg_refs 1.694412 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5100425401500 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.warmup_cycle 5100425402500 # Cycle when the warmup percentage was hit. system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.014191 # Average occupied blocks per requestor system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.313387 # Average percentage of cache occupancy system.cpu.dtb_walker_cache.occ_percent::total 0.313387 # Average percentage of cache occupancy @@ -403,31 +403,31 @@ system.cpu.dtb_walker_cache.cache_copies 0 # nu system.cpu.dtb_walker_cache.writebacks::writebacks 2413 # number of writebacks system.cpu.dtb_walker_cache.writebacks::total 2413 # number of writebacks system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1621965 # number of replacements +system.cpu.dcache.replacements 1621960 # number of replacements system.cpu.dcache.tagsinuse 511.999425 # Cycle average of tags in use -system.cpu.dcache.total_refs 20168700 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1622477 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.430808 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.total_refs 20168705 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1622472 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12.430849 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 7550500 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 511.999425 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999999 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 12073043 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 12073043 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8093389 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8093389 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 20166432 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20166432 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20166432 # number of overall hits -system.cpu.dcache.overall_hits::total 20166432 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1308511 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1308511 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 316250 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 316250 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1624761 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1624761 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1624761 # number of overall misses -system.cpu.dcache.overall_misses::total 1624761 # number of overall misses +system.cpu.dcache.ReadReq_hits::cpu.data 12073184 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 12073184 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8093253 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8093253 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 20166437 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20166437 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20166437 # number of overall hits +system.cpu.dcache.overall_hits::total 20166437 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1308370 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1308370 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 316386 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 316386 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1624756 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1624756 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1624756 # number of overall misses +system.cpu.dcache.overall_misses::total 1624756 # number of overall misses system.cpu.dcache.ReadReq_accesses::cpu.data 13381554 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 13381554 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 8409639 # number of WriteReq accesses(hits+misses) @@ -436,10 +436,10 @@ system.cpu.dcache.demand_accesses::cpu.data 21791193 # system.cpu.dcache.demand_accesses::total 21791193 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 21791193 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 21791193 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097785 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.097785 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037606 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037606 # miss rate for WriteReq accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097774 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.097774 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037622 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037622 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.074560 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.074560 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.074560 # miss rate for overall accesses @@ -452,56 +452,56 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1535695 # number of writebacks -system.cpu.dcache.writebacks::total 1535695 # number of writebacks +system.cpu.dcache.writebacks::writebacks 1535700 # number of writebacks +system.cpu.dcache.writebacks::total 1535700 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 105930 # number of replacements -system.cpu.l2cache.tagsinuse 64821.868749 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3456653 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 64819.953894 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3456507 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 170058 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 20.326318 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 20.325460 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 51906.789291 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 51906.788142 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.dtb.walker 0.004959 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.132241 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2490.593013 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 10424.349245 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2490.593014 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 10422.435538 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.792035 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.038003 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.159063 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.989103 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.159034 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.989074 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6501 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2802 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.inst 777765 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1275631 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2062699 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1538634 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1538634 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1275492 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2062560 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1538639 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1538639 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 20 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 20 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 179586 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 179586 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 179720 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 179720 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.dtb.walker 6501 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.itb.walker 2802 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.inst 777765 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1455217 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2242285 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1455212 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2242280 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.dtb.walker 6501 # number of overall hits system.cpu.l2cache.overall_hits::cpu.itb.walker 2802 # number of overall hits system.cpu.l2cache.overall_hits::cpu.inst 777765 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1455217 # number of overall hits -system.cpu.l2cache.overall_hits::total 2242285 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1455212 # number of overall hits +system.cpu.l2cache.overall_hits::total 2242280 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 2 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.inst 13325 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 32248 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 45580 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 32246 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 45578 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 1803 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 1803 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 134391 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 134391 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 134393 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 134393 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 2 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.inst 13325 # number of demand (read+write) misses @@ -515,33 +515,33 @@ system.cpu.l2cache.overall_misses::total 179971 # nu system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6503 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2807 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.inst 791090 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1307879 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2108279 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1538634 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1538634 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1307738 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2108138 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1538639 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1538639 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1823 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 1823 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 313977 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 313977 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 314113 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 314113 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6503 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.itb.walker 2807 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.inst 791090 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1621856 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2422256 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1621851 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2422251 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6503 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.itb.walker 2807 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 791090 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1621856 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2422256 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1621851 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2422251 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000308 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001781 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016844 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024657 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024658 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.021620 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989029 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989029 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428028 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.428028 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.427849 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.427849 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000308 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001781 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016844 # miss rate for demand accesses diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout index 3bb47e888..c33799826 100755 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-si gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 28 2013 09:59:18 -gem5 started Mar 28 2013 09:59:40 +gem5 compiled Apr 18 2013 13:37:41 +gem5 started Apr 18 2013 13:43:22 gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing Global frequency set at 1000000000000 ticks per second info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5191816279000 because m5_exit instruction encountered +Exiting @ tick 5187335906000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index 00dd0b701..fe64538c7 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -1,126 +1,126 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.191816 # Number of seconds simulated -sim_ticks 5191816279000 # Number of ticks simulated -final_tick 5191816279000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.187336 # Number of seconds simulated +sim_ticks 5187335906000 # Number of ticks simulated +final_tick 5187335906000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 631596 # Simulator instruction rate (inst/s) -host_op_rate 1217489 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 25553396248 # Simulator tick rate (ticks/s) -host_mem_usage 629228 # Number of bytes of host memory used -host_seconds 203.18 # Real time elapsed on the host -sim_insts 128324646 # Number of instructions simulated -sim_ops 247363464 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2859648 # Number of bytes read from this memory +host_inst_rate 632480 # Simulator instruction rate (inst/s) +host_op_rate 1219228 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 25568906299 # Simulator tick rate (ticks/s) +host_mem_usage 629256 # Number of bytes of host memory used +host_seconds 202.88 # Real time elapsed on the host +sim_insts 128315489 # Number of instructions simulated +sim_ops 247353050 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2850304 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 823360 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9009408 # Number of bytes read from this memory -system.physmem.bytes_read::total 12692736 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 823360 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 823360 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8106432 # Number of bytes written to this memory -system.physmem.bytes_written::total 8106432 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 44682 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu.inst 824512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9026304 # Number of bytes read from this memory +system.physmem.bytes_read::total 12701440 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 824512 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 824512 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8120576 # Number of bytes written to this memory +system.physmem.bytes_written::total 8120576 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 44536 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12865 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 140772 # Number of read requests responded to by this memory -system.physmem.num_reads::total 198324 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 126663 # Number of write requests responded to by this memory -system.physmem.num_writes::total 126663 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 550799 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu.inst 12883 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141036 # Number of read requests responded to by this memory +system.physmem.num_reads::total 198460 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 126884 # Number of write requests responded to by this memory +system.physmem.num_writes::total 126884 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 549474 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 158588 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1735309 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2444758 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 158588 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 158588 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1561387 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1561387 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1561387 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 550799 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 158947 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1740065 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2448548 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 158947 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 158947 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1565462 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1565462 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1565462 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 549474 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 158588 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1735309 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4006145 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 198324 # Total number of read requests seen -system.physmem.writeReqs 126663 # Total number of write requests seen -system.physmem.cpureqs 326610 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 12692736 # Total number of bytes read from memory -system.physmem.bytesWritten 8106432 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 12692736 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 8106432 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 80 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 1618 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 12615 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 12250 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 12267 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 12575 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 12362 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 12187 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 12619 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 12562 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 12247 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 11965 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 12423 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 12610 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 12268 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 12172 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 12546 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 12576 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 8002 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7779 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7802 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 8120 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7982 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7804 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 8130 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 8156 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7749 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7475 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7958 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 8068 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7819 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7741 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7995 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 8083 # Track writes on a per bank basis +system.physmem.bw_total::cpu.inst 158947 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1740065 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4014010 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 198460 # Total number of read requests seen +system.physmem.writeReqs 126884 # Total number of write requests seen +system.physmem.cpureqs 326965 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 12701440 # Total number of bytes read from memory +system.physmem.bytesWritten 8120576 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 12701440 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 8120576 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 110 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 1615 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 12387 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 12046 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 12118 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 12449 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 12193 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 12119 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 12473 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 12536 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 12592 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 12290 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 12456 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 12641 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 12408 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 12254 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 12740 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 12648 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7793 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7533 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7699 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7988 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7862 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7739 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7964 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 8103 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 8131 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7898 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7933 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 8107 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7973 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7879 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 8152 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 8130 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 5 # Number of times wr buffer was full causing retry -system.physmem.totGap 5191816215500 # Total gap between requests +system.physmem.numWrRetry 6 # Number of times wr buffer was full causing retry +system.physmem.totGap 5187335842500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 198324 # Categorize read packet sizes +system.physmem.readPktSize::6 198460 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 126663 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 155046 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 8732 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 6675 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3414 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3394 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2806 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2216 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2153 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2094 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2013 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1298 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1183 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1113 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1034 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 959 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 975 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1125 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1097 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 541 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 344 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 32 # What read queue length does an incoming req see +system.physmem.writePktSize::6 126884 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 155340 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 8720 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 6686 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3417 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3378 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2810 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2218 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2141 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2080 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2004 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1276 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1172 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1102 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1032 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 958 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 968 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1114 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1055 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 518 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 325 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 36 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -132,92 +132,92 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4186 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4510 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 5285 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5419 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5454 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5493 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5497 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5502 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1322 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 998 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5 # What write queue length does an incoming req see -system.physmem.totQLat 4084993999 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 7884046499 # Sum of mem lat for all requests -system.physmem.totBusLat 991220000 # Total cycles spent in databus access -system.physmem.totBankLat 2807832500 # Total cycles spent in bank access -system.physmem.avgQLat 20605.89 # Average queueing delay per request -system.physmem.avgBankLat 14163.52 # Average bank access latency per request +system.physmem.wrQLenPdf::0 4200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4548 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 5338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5455 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5485 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5501 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5506 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5508 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5508 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5517 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5517 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5517 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5517 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5517 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5517 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5517 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5516 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5516 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5516 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5516 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5516 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5516 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5516 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 969 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 9 # What write queue length does an incoming req see +system.physmem.totQLat 4133329999 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 7970683749 # Sum of mem lat for all requests +system.physmem.totBusLat 991750000 # Total cycles spent in databus access +system.physmem.totBankLat 2845603750 # Total cycles spent in bank access +system.physmem.avgQLat 20838.57 # Average queueing delay per request +system.physmem.avgBankLat 14346.38 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 39769.41 # Average memory access latency -system.physmem.avgRdBW 2.44 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 2.44 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 1.56 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 40184.94 # Average memory access latency +system.physmem.avgRdBW 2.45 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 1.57 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 2.45 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 1.57 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 8.79 # Average write queue length over time -system.physmem.readRowHits 175346 # Number of row buffer hits during reads -system.physmem.writeRowHits 94626 # Number of row buffer hits during writes -system.physmem.readRowHitRate 88.45 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.71 # Row buffer hit rate for writes -system.physmem.avgGap 15975458.14 # Average gap between requests -system.iocache.replacements 47501 # number of replacements -system.iocache.tagsinuse 0.114811 # Cycle average of tags in use +system.physmem.avgWrQLen 12.90 # Average write queue length over time +system.physmem.readRowHits 174211 # Number of row buffer hits during reads +system.physmem.writeRowHits 94671 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.83 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.61 # Row buffer hit rate for writes +system.physmem.avgGap 15944157.08 # Average gap between requests +system.iocache.replacements 47504 # number of replacements +system.iocache.tagsinuse 0.157150 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47517 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47520 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 5044702860000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.114811 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.007176 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.007176 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 836 # number of ReadReq misses -system.iocache.ReadReq_misses::total 836 # number of ReadReq misses +system.iocache.warmup_cycle 5044705088000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::pc.south_bridge.ide 0.157150 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.009822 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.009822 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 837 # number of ReadReq misses +system.iocache.ReadReq_misses::total 837 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47556 # number of demand (read+write) misses -system.iocache.demand_misses::total 47556 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47556 # number of overall misses -system.iocache.overall_misses::total 47556 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 136123397 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 136123397 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10718582907 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10718582907 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 10854706304 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10854706304 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 10854706304 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10854706304 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 836 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 836 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47557 # number of demand (read+write) misses +system.iocache.demand_misses::total 47557 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47557 # number of overall misses +system.iocache.overall_misses::total 47557 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 139731143 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 139731143 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10765565415 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10765565415 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 10905296558 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10905296558 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 10905296558 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10905296558 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 837 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 837 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47556 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47556 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47556 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47556 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47557 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47557 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47557 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47557 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -226,40 +226,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 162827.029904 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 162827.029904 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 229421.723181 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 229421.723181 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 228251.036757 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 228251.036757 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 228251.036757 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 228251.036757 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 175533 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 166942.823178 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 166942.823178 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 230427.341931 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 230427.341931 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 229310.018672 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 229310.018672 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 229310.018672 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 229310.018672 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 177808 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 16256 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 16153 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.798044 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 11.007739 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 46667 # number of writebacks -system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 836 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 836 # number of ReadReq MSHR misses +system.iocache.writebacks::writebacks 46669 # number of writebacks +system.iocache.writebacks::total 46669 # number of writebacks +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 837 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 837 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47556 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47556 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47556 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47556 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 92629177 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 92629177 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8287786786 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8287786786 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8380415963 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8380415963 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8380415963 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8380415963 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47557 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47557 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47557 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47557 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 96185423 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 96185423 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8334760316 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8334760316 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8430945739 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8430945739 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8430945739 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8430945739 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -268,14 +268,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 110800.450957 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 110800.450957 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 177392.696618 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 177392.696618 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 176222.053221 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 176222.053221 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 176222.053221 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 176222.053221 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 114916.873357 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 114916.873357 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 178398.123202 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 178398.123202 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 177280.857476 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 177280.857476 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 177280.857476 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 177280.857476 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -289,75 +289,75 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 10383632558 # number of cpu cycles simulated +system.cpu.numCycles 10374671812 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 128324646 # Number of instructions committed -system.cpu.committedOps 247363464 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 232097683 # Number of integer alu accesses +system.cpu.committedInsts 128315489 # Number of instructions committed +system.cpu.committedOps 247353050 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 232087369 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 23165556 # number of instructions that are conditional controls -system.cpu.num_int_insts 232097683 # number of integer instructions +system.cpu.num_conditional_control_insts 23166071 # number of instructions that are conditional controls +system.cpu.num_int_insts 232087369 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 567280399 # number of times the integer registers were read -system.cpu.num_int_register_writes 293347970 # number of times the integer registers were written +system.cpu.num_int_register_reads 567244076 # number of times the integer registers were read +system.cpu.num_int_register_writes 293343891 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 22249385 # number of memory refs -system.cpu.num_load_insts 13880834 # Number of load instructions -system.cpu.num_store_insts 8368551 # Number of store instructions -system.cpu.num_idle_cycles 9782435662.998116 # Number of idle cycles -system.cpu.num_busy_cycles 601196895.001884 # Number of busy cycles -system.cpu.not_idle_fraction 0.057899 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.942101 # Percentage of idle cycles +system.cpu.num_mem_refs 22240299 # number of memory refs +system.cpu.num_load_insts 13876403 # Number of load instructions +system.cpu.num_store_insts 8363896 # Number of store instructions +system.cpu.num_idle_cycles 9773542516.998116 # Number of idle cycles +system.cpu.num_busy_cycles 601129295.001884 # Number of busy cycles +system.cpu.not_idle_fraction 0.057942 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.942058 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.icache.replacements 795387 # number of replacements -system.cpu.icache.tagsinuse 510.410338 # Cycle average of tags in use -system.cpu.icache.total_refs 144562130 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 795899 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 181.633763 # Average number of references to valid blocks. +system.cpu.icache.replacements 790572 # number of replacements +system.cpu.icache.tagsinuse 510.408986 # Cycle average of tags in use +system.cpu.icache.total_refs 144555062 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 791084 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 182.730357 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 160005789000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.410338 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996895 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996895 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 144562130 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 144562130 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 144562130 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 144562130 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 144562130 # number of overall hits -system.cpu.icache.overall_hits::total 144562130 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 795906 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 795906 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 795906 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 795906 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 795906 # number of overall misses -system.cpu.icache.overall_misses::total 795906 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11017856500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11017856500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11017856500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11017856500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11017856500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11017856500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 145358036 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 145358036 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 145358036 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 145358036 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 145358036 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 145358036 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005475 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.005475 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.005475 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.005475 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.005475 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.005475 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13843.163012 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13843.163012 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13843.163012 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13843.163012 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13843.163012 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13843.163012 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 510.408986 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.996893 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.996893 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 144555062 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 144555062 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 144555062 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 144555062 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 144555062 # number of overall hits +system.cpu.icache.overall_hits::total 144555062 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 791091 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 791091 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 791091 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 791091 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 791091 # number of overall misses +system.cpu.icache.overall_misses::total 791091 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 10944017000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 10944017000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 10944017000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 10944017000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 10944017000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 10944017000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 145346153 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 145346153 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 145346153 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 145346153 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 145346153 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 145346153 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005443 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.005443 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.005443 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.005443 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.005443 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.005443 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13834.081035 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13834.081035 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13834.081035 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13834.081035 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13834.081035 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13834.081035 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -366,80 +366,80 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 795906 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 795906 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 795906 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 795906 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 795906 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 795906 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9426044500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9426044500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9426044500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9426044500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9426044500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9426044500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005475 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005475 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005475 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.005475 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005475 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.005475 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11843.163012 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11843.163012 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11843.163012 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11843.163012 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11843.163012 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11843.163012 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 791091 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 791091 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 791091 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 791091 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 791091 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 791091 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9361835000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9361835000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9361835000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9361835000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9361835000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9361835000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005443 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005443 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005443 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.005443 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005443 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.005443 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11834.081035 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11834.081035 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11834.081035 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11834.081035 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11834.081035 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11834.081035 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 3694 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 3.067610 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 7642 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 3706 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 2.062062 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5165748244000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.067610 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.191726 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.191726 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7663 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 7663 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 3538 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 3.071073 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 7817 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 3549 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 2.202592 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5161021529000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.071073 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.191942 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.191942 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7819 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 7819 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7665 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 7665 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7665 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 7665 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4553 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 4553 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4553 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 4553 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4553 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 4553 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 46128000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 46128000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 46128000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 46128000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 46128000 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 46128000 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12216 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 12216 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7821 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 7821 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7821 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 7821 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4399 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 4399 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4399 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 4399 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4399 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 4399 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 43289000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 43289000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 43289000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 43289000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 43289000 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 43289000 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12218 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 12218 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12218 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 12218 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12218 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 12218 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.372708 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.372708 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.372647 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.372647 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.372647 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.372647 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10131.341972 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10131.341972 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10131.341972 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10131.341972 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10131.341972 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10131.341972 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12220 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 12220 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12220 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 12220 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.360043 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.360043 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.359984 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.359984 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.359984 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.359984 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 9840.645601 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 9840.645601 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 9840.645601 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9840.645601 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9840.645601 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9840.645601 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -448,78 +448,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 782 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 782 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4553 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4553 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4553 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 4553 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4553 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 4553 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 37022000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 37022000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 37022000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 37022000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 37022000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 37022000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.372708 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.372708 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.372647 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.372647 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.372647 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.372647 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8131.341972 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8131.341972 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8131.341972 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8131.341972 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8131.341972 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8131.341972 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 650 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 650 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4399 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4399 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4399 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 4399 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4399 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 4399 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 34491000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 34491000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 34491000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 34491000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 34491000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 34491000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.360043 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.360043 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.359984 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.359984 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.359984 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.359984 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 7840.645601 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 7840.645601 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 7840.645601 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7840.645601 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7840.645601 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7840.645601 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 8348 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 5.050573 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 12635 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 8361 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.511183 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5162441732000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.050573 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.315661 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.315661 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12638 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 12638 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12638 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 12638 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12638 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 12638 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 9544 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 9544 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 9544 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 9544 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 9544 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 9544 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 102265000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 102265000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 102265000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 102265000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 102265000 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 102265000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22182 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 22182 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22182 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 22182 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22182 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 22182 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.430259 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.430259 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.430259 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.430259 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.430259 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.430259 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10715.108969 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10715.108969 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10715.108969 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10715.108969 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10715.108969 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10715.108969 # average overall miss latency +system.cpu.dtb_walker_cache.replacements 7602 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 5.053533 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 13277 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 7616 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.743304 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5155312372000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.053533 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.315846 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.315846 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13278 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 13278 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13278 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 13278 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13278 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 13278 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8808 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 8808 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8808 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 8808 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8808 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 8808 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 93210000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 93210000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 93210000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 93210000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 93210000 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 93210000 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22086 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 22086 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22086 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 22086 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22086 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 22086 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.398805 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.398805 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.398805 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.398805 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.398805 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.398805 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10582.425068 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10582.425068 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10582.425068 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10582.425068 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10582.425068 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10582.425068 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -528,90 +528,90 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 3309 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 3309 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 9544 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 9544 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 9544 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 9544 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 9544 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 9544 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 83177000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 83177000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 83177000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 83177000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 83177000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 83177000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.430259 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.430259 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.430259 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.430259 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.430259 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.430259 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8715.108969 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8715.108969 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8715.108969 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8715.108969 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8715.108969 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8715.108969 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 2984 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 2984 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8808 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8808 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8808 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 8808 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8808 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 8808 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 75594000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 75594000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 75594000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 75594000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 75594000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 75594000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.398805 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.398805 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.398805 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.398805 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.398805 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.398805 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8582.425068 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8582.425068 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8582.425068 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8582.425068 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8582.425068 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8582.425068 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1620219 # number of replacements -system.cpu.dcache.tagsinuse 511.997551 # Cycle average of tags in use -system.cpu.dcache.total_refs 20041204 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1620731 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.365534 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1620743 # number of replacements +system.cpu.dcache.tagsinuse 511.997667 # Cycle average of tags in use +system.cpu.dcache.total_refs 20031616 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1621255 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12.355623 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 39012000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.997551 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 511.997667 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999995 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 11996661 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11996661 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8042358 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8042358 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 20039019 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20039019 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20039019 # number of overall hits -system.cpu.dcache.overall_hits::total 20039019 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1307017 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1307017 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 315944 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 315944 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1622961 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1622961 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1622961 # number of overall misses -system.cpu.dcache.overall_misses::total 1622961 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 18338475500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 18338475500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8568992000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8568992000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 26907467500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 26907467500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 26907467500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 26907467500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13303678 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13303678 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8358302 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8358302 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21661980 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21661980 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21661980 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21661980 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098245 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.098245 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037800 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037800 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.074922 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.074922 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.074922 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.074922 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14030.785751 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14030.785751 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27121.869698 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 27121.869698 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16579.244665 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16579.244665 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16579.244665 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16579.244665 # average overall miss latency +system.cpu.dcache.ReadReq_hits::cpu.data 11991279 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11991279 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8038109 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8038109 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 20029388 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20029388 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20029388 # number of overall hits +system.cpu.dcache.overall_hits::total 20029388 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1307954 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1307954 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 315546 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 315546 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1623500 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1623500 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1623500 # number of overall misses +system.cpu.dcache.overall_misses::total 1623500 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 18389416000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 18389416000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8586143000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8586143000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 26975559000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 26975559000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 26975559000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 26975559000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13299233 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13299233 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8353655 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8353655 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21652888 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21652888 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21652888 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21652888 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098348 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.098348 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037773 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037773 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.074978 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.074978 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.074978 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.074978 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14059.680998 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14059.680998 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27210.432076 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 27210.432076 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16615.681552 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16615.681552 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16615.681552 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16615.681552 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -620,46 +620,46 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1537528 # number of writebacks -system.cpu.dcache.writebacks::total 1537528 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1307017 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1307017 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315944 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 315944 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1622961 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1622961 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1622961 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1622961 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15724441500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 15724441500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7937104000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7937104000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23661545500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23661545500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23661545500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23661545500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94200592000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94200592000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2523051000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2523051000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96723643000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 96723643000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098245 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098245 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037800 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037800 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074922 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.074922 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074922 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.074922 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12030.785751 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12030.785751 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25121.869698 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25121.869698 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14579.244665 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 14579.244665 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14579.244665 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 14579.244665 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1538215 # number of writebacks +system.cpu.dcache.writebacks::total 1538215 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1307954 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1307954 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315546 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 315546 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1623500 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1623500 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1623500 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1623500 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15773508000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 15773508000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7955051000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7955051000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23728559000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23728559000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23728559000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23728559000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94200596500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94200596500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2522793500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2522793500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96723390000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 96723390000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098348 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098348 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037773 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037773 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074978 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.074978 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074978 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.074978 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12059.680998 # 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