diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-15 08:08:06 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-15 08:08:06 -0400 |
| commit | a850fc916f06f05c1c55d634cdb2b230a7c23d11 (patch) | |
| tree | 9bfdb234f3bb65ce77b5ca188aff74031ca0e01d /tests/quick/fs/10.linux-boot/ref/x86 | |
| parent | 3cf733bcc07b0a8bf069f8581b7f3902bc38f0e0 (diff) | |
| download | gem5-a850fc916f06f05c1c55d634cdb2b230a7c23d11.tar.xz | |
Stats: Update stats for use of two-level builder
This patch updates the name of the l2 stats.
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/x86')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt | 216 | ||||
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt | 416 |
2 files changed, 316 insertions, 316 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index 58cc29985..5a613cfa1 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -46,114 +46,114 @@ system.physmem.bw_total::cpu.itb.walker 63 # To system.physmem.bw_total::cpu.inst 167022 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2073572 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 4540656 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 106561 # number of replacements -system.l2c.tagsinuse 64822.143261 # Cycle average of tags in use -system.l2c.total_refs 3456533 # Total number of references to valid blocks. -system.l2c.sampled_refs 170680 # Sample count of references to valid blocks. -system.l2c.avg_refs 20.251541 # Average number of references to valid blocks. -system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 51981.461987 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 0.004954 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.itb.walker 0.132110 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 2434.983596 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 10405.560614 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.793174 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.037155 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.158776 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.989107 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 6578 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 2700 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 777957 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 1275395 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2062630 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 1538130 # number of Writeback hits -system.l2c.Writeback_hits::total 1538130 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 28 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 179208 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 179208 # number of ReadExReq hits -system.l2c.demand_hits::cpu.dtb.walker 6578 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.itb.walker 2700 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.inst 777957 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 1454603 # number of demand (read+write) hits -system.l2c.demand_hits::total 2241838 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.dtb.walker 6578 # number of overall hits -system.l2c.overall_hits::cpu.itb.walker 2700 # number of overall hits -system.l2c.overall_hits::cpu.inst 777957 # number of overall hits -system.l2c.overall_hits::cpu.data 1454603 # number of overall hits -system.l2c.overall_hits::total 2241838 # number of overall hits -system.l2c.ReadReq_misses::cpu.dtb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.inst 13342 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 32184 # number of ReadReq misses -system.l2c.ReadReq_misses::total 45533 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 1796 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1796 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 134377 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 134377 # number of ReadExReq misses -system.l2c.demand_misses::cpu.dtb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.inst 13342 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 166561 # number of demand (read+write) misses -system.l2c.demand_misses::total 179910 # number of demand (read+write) misses -system.l2c.overall_misses::cpu.dtb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu.itb.walker 5 # number of overall misses -system.l2c.overall_misses::cpu.inst 13342 # number of overall misses -system.l2c.overall_misses::cpu.data 166561 # number of overall misses -system.l2c.overall_misses::total 179910 # number of overall misses -system.l2c.ReadReq_accesses::cpu.dtb.walker 6580 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.itb.walker 2705 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.inst 791299 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 1307579 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2108163 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 1538130 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1538130 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu.data 1824 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 1824 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu.data 313585 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 313585 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu.dtb.walker 6580 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.itb.walker 2705 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.inst 791299 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 1621164 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2421748 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu.dtb.walker 6580 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.itb.walker 2705 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.inst 791299 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 1621164 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2421748 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000304 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001848 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.016861 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.024613 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.021598 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu.data 0.984649 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.984649 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.428519 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.428519 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.dtb.walker 0.000304 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.itb.walker 0.001848 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.inst 0.016861 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.102742 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.074289 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.dtb.walker 0.000304 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.itb.walker 0.001848 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.inst 0.016861 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.102742 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.074289 # miss rate for overall accesses -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 98533 # number of writebacks -system.l2c.writebacks::total 98533 # number of writebacks -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 106561 # number of replacements +system.cpu.l2cache.tagsinuse 64822.143261 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3456533 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 170680 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 20.251541 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 51981.461987 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.dtb.walker 0.004954 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.132110 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2434.983596 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 10405.560614 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.793174 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.037155 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.158776 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.989107 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6578 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2700 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 777957 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1275395 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2062630 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1538130 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1538130 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 179208 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 179208 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 6578 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 2700 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 777957 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1454603 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2241838 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 6578 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 2700 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 777957 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1454603 # number of overall hits +system.cpu.l2cache.overall_hits::total 2241838 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 2 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 13342 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 32184 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 45533 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 1796 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 1796 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 134377 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 134377 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 2 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 13342 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 166561 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 179910 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 2 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 13342 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 166561 # number of overall misses +system.cpu.l2cache.overall_misses::total 179910 # number of overall misses +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6580 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2705 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 791299 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1307579 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2108163 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1538130 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1538130 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1824 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 1824 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 313585 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 313585 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6580 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 2705 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 791299 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1621164 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2421748 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6580 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 2705 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 791299 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1621164 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2421748 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000304 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001848 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016861 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024613 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.021598 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.984649 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.984649 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428519 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.428519 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000304 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001848 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016861 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.102742 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.074289 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000304 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001848 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016861 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.102742 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.074289 # miss rate for overall accesses +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.writebacks::writebacks 98533 # number of writebacks +system.cpu.l2cache.writebacks::total 98533 # number of writebacks +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 47570 # number of replacements system.iocache.tagsinuse 0.042409 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index 1b5c0ec90..944044d4e 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -42,214 +42,214 @@ system.physmem.bw_total::cpu.itb.walker 62 # To system.physmem.bw_total::cpu.inst 158620 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 1723682 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 3992863 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 86330 # number of replacements -system.l2c.tagsinuse 64759.737076 # Cycle average of tags in use -system.l2c.total_refs 3491284 # Total number of references to valid blocks. -system.l2c.sampled_refs 151054 # Sample count of references to valid blocks. -system.l2c.avg_refs 23.112821 # Average number of references to valid blocks. -system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 50074.264340 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.itb.walker 0.140725 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 3394.913598 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 11290.418413 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.764073 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.051802 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.172278 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.988155 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 6719 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 2994 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 778172 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 1280323 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2068208 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 1543462 # number of Writeback hits -system.l2c.Writeback_hits::total 1543462 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu.data 302 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 302 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 200678 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 200678 # number of ReadExReq hits -system.l2c.demand_hits::cpu.dtb.walker 6719 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.itb.walker 2994 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.inst 778172 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 1481001 # number of demand (read+write) hits -system.l2c.demand_hits::total 2268886 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.dtb.walker 6719 # number of overall hits -system.l2c.overall_hits::cpu.itb.walker 2994 # number of overall hits -system.l2c.overall_hits::cpu.inst 778172 # number of overall hits -system.l2c.overall_hits::cpu.data 1481001 # number of overall hits -system.l2c.overall_hits::total 2268886 # number of overall hits -system.l2c.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.inst 12879 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 28353 # number of ReadReq misses -system.l2c.ReadReq_misses::total 41237 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 1338 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1338 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 112514 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 112514 # number of ReadExReq misses -system.l2c.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.inst 12879 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 140867 # number of demand (read+write) misses -system.l2c.demand_misses::total 153751 # number of demand (read+write) misses -system.l2c.overall_misses::cpu.itb.walker 5 # number of overall misses -system.l2c.overall_misses::cpu.inst 12879 # number of overall misses -system.l2c.overall_misses::cpu.data 140867 # number of overall misses -system.l2c.overall_misses::total 153751 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu.itb.walker 260000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.inst 670083000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.data 1488776500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 2159119500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu.data 33785000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 33785000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu.data 5852520000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 5852520000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu.itb.walker 260000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.inst 670083000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.data 7341296500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 8011639500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu.itb.walker 260000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.inst 670083000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.data 7341296500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 8011639500 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu.dtb.walker 6719 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.itb.walker 2999 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.inst 791051 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 1308676 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2109445 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 1543462 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1543462 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu.data 1640 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 1640 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu.data 313192 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 313192 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu.dtb.walker 6719 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.itb.walker 2999 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.inst 791051 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 1621868 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2422637 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu.dtb.walker 6719 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.itb.walker 2999 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.inst 791051 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 1621868 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2422637 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001667 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.016281 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.021665 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.019549 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu.data 0.815854 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.815854 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.359249 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.359249 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.itb.walker 0.001667 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.inst 0.016281 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.086855 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.063464 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.itb.walker 0.001667 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.inst 0.016281 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.086855 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.063464 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.inst 52029.117167 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.data 52508.605791 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52358.791862 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu.data 25250.373692 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 25250.373692 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu.data 52015.926907 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52015.926907 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.inst 52029.117167 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.data 52115.090830 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52107.885477 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.inst 52029.117167 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.data 52115.090830 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52107.885477 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 79675 # number of writebacks -system.l2c.writebacks::total 79675 # number of writebacks -system.l2c.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.inst 12879 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.data 28353 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 41237 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu.data 1338 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 1338 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu.data 112514 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 112514 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.inst 12879 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.data 140867 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 153751 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.inst 12879 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.data 140867 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 153751 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 200000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.inst 515526000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.data 1148536000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1664262000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 53936000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 53936000 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4502349000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 4502349000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.itb.walker 200000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.inst 515526000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.data 5650885000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 6166611000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.itb.walker 200000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.inst 515526000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.data 5650885000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 6166611000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 86117450000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 86117450000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 2306155000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 2306155000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu.data 88423605000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 88423605000 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001667 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.016281 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.021665 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.019549 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.815854 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.815854 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.359249 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.359249 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.001667 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.inst 0.016281 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.data 0.086855 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.063464 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.001667 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.inst 0.016281 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.data 0.086855 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.063464 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40028.418355 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40508.447078 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40358.464486 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40310.911809 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40310.911809 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40015.900244 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40015.900244 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40028.418355 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40115.037589 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40107.778161 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40028.418355 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40115.037589 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40107.778161 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 86330 # number of replacements +system.cpu.l2cache.tagsinuse 64759.737076 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3491284 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 151054 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 23.112821 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 50074.264340 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.140725 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 3394.913598 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 11290.418413 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.764073 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.051802 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.172278 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.988155 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6719 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2994 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 778172 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1280323 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2068208 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1543462 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1543462 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 302 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 302 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 200678 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 200678 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 6719 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 2994 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 778172 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1481001 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2268886 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 6719 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 2994 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 778172 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1481001 # number of overall hits +system.cpu.l2cache.overall_hits::total 2268886 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 12879 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 28353 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 41237 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 1338 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 1338 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 112514 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 112514 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 12879 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 140867 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 153751 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 12879 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 140867 # number of overall misses +system.cpu.l2cache.overall_misses::total 153751 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 260000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 670083000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1488776500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 2159119500 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 33785000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 33785000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5852520000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5852520000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 260000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 670083000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7341296500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 8011639500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 260000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 670083000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7341296500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 8011639500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6719 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2999 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 791051 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1308676 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2109445 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1543462 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1543462 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1640 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 1640 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 313192 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 313192 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6719 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 2999 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 791051 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1621868 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2422637 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6719 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 2999 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 791051 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1621868 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2422637 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001667 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016281 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021665 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.019549 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.815854 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.815854 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.359249 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.359249 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001667 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016281 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.086855 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.063464 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001667 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016281 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.086855 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.063464 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52029.117167 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52508.605791 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52358.791862 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 25250.373692 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 25250.373692 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52015.926907 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52015.926907 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52029.117167 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52115.090830 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52107.885477 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52029.117167 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52115.090830 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52107.885477 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.writebacks::writebacks 79675 # number of writebacks +system.cpu.l2cache.writebacks::total 79675 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12879 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 28353 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 41237 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1338 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 1338 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 112514 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 112514 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 12879 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 140867 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 153751 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 12879 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 140867 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 153751 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 200000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 515526000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1148536000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1664262000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 53936000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 53936000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4502349000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4502349000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 200000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 515526000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5650885000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6166611000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 200000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 515526000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5650885000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6166611000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86117450000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86117450000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2306155000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2306155000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 88423605000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 88423605000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001667 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016281 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021665 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019549 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.815854 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.815854 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.359249 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.359249 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001667 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016281 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.086855 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.063464 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001667 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016281 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.086855 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.063464 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40028.418355 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40508.447078 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40358.464486 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40310.911809 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40310.911809 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40015.900244 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40015.900244 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40028.418355 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40115.037589 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40107.778161 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40028.418355 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40115.037589 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40107.778161 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 47503 # number of replacements system.iocache.tagsinuse 0.108744 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. |