tests: Update regressions for the new kernels and various preceeding fixes.

4 files changed, 17 insertions, 19 deletions

diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
index 2bc3edd20..b395adf7f 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
@@ -20,7 +20,7 @@ eventq_index=0
 init_param=0
 intel_mp_pointer=system.intel_mp_pointer
 intel_mp_table=system.intel_mp_table
-kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
+kernel=/dist/binaries/x86_64-vmlinux-2.6.22.9
 kernel_addr_check=true
 load_addr_mask=18446744073709551615
 load_offset=0
@@ -28,7 +28,7 @@ mem_mode=timing
 mem_ranges=0:134217727
 memories=system.physmem
 num_work_ids=16
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+readfile=/work/gem5.latest/tests/halt.sh
 smbios_table=system.smbios_table
 symbolfile=
 work_begin_ckpt_count=0
@@ -1180,7 +1180,7 @@ table_size=65536
 [system.pc.south_bridge.ide.disks0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
+image_file=/dist/disks/linux-x86.img
 read_only=true
 
 [system.pc.south_bridge.ide.disks1]
@@ -1203,7 +1203,7 @@ table_size=65536
 [system.pc.south_bridge.ide.disks1.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/dist/disks/linux-bigswap2.img
 read_only=true
 
 [system.pc.south_bridge.int_lines0]
@@ -1427,6 +1427,7 @@ clk_domain=system.clk_domain
 conf_table_reported=true
 device_bus_width=8
 device_rowbuffer_size=1024
+device_size=536870912
 devices_per_rank=8
 dll=true
 eventq_index=0
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr
index bb1874a4f..f30c0bc17 100755
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr
@@ -1,3 +1,4 @@
+warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
 warn: Sockets disabled, not accepting terminal connections
 warn: Reading current count from inactive timer.
 warn: Sockets disabled, not accepting gdb connections
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
index f1feb2eac..a4565b1b8 100755
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 22 2014 17:10:34
-gem5 started Jan 22 2014 17:30:19
+gem5 compiled Oct 29 2014 09:18:07
+gem5 started Oct 29 2014 09:26:24
 gem5 executing on u200540-lin
-command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing
+command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing -re /work/gem5.latest/tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/binaries/x86_64-vmlinux-2.6.22.9
       0: rtc: Real-time clock set to Sun Jan  1 00:00:00 2012
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 5196390180000 because m5_exit instruction encountered
+Exiting @ tick 5194410635000 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
index 89c62f3e3..8675b3331 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  5.194411                       # Nu
 sim_ticks                                5194410635000                       # Number of ticks simulated
 final_tick                               5194410635000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 693425                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1336696                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            28047460404                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 637768                       # Number of bytes of host memory used
-host_seconds                                   185.20                       # Real time elapsed on the host
+host_inst_rate                                1079720                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2081347                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            43672253601                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 589096                       # Number of bytes of host memory used
+host_seconds                                   118.94                       # Real time elapsed on the host
 sim_insts                                   128422722                       # Number of instructions simulated
 sim_ops                                     247557000                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -424,8 +424,6 @@ system.iocache.fast_writes                      46720                       # nu
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          847                       # number of ReadReq MSHR misses
 system.iocache.ReadReq_mshr_misses::total          847                       # number of ReadReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::total        46720                       # number of WriteInvalidateReq MSHR misses
 system.iocache.demand_mshr_misses::pc.south_bridge.ide          847                       # number of demand (read+write) MSHR misses
 system.iocache.demand_mshr_misses::total          847                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::pc.south_bridge.ide          847                       # number of overall MSHR misses
@@ -440,16 +438,14 @@ system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide     97471186
 system.iocache.overall_mshr_miss_latency::total     97471186                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide     0.999979                       # mshr miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::total     0.999979                       # mshr miss rate for WriteInvalidateReq accesses
 system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
 system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115078.141677                       # average ReadReq mshr miss latency
 system.iocache.ReadReq_avg_mshr_miss_latency::total 115078.141677                       # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 60522.456336                       # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60522.456336                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide          inf                       # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115078.141677                       # average overall mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::total 115078.141677                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115078.141677                       # average overall mshr miss latency