diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-06-29 11:19:03 -0400 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-06-29 11:19:03 -0400 |
| commit | 3965ecc36b3d928cf8f6a66e50eed3c6de1a54c0 (patch) | |
| tree | 63ce098bc690eb5b58b3297b747794d623cface4 /tests/quick/fs/10.linux-boot/ref | |
| parent | af2b14a362281f36347728e13dcd6b2c4d3c4991 (diff) | |
| download | gem5-3965ecc36b3d928cf8f6a66e50eed3c6de1a54c0.tar.xz | |
Stats: Update stats for RAS and LRU fixes.
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref')
24 files changed, 4395 insertions, 4453 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout index 06d87b670..86d337feb 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout @@ -1,13 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 14:39:49 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:10:04 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... info: Launching CPU 1 @ 97861500 Exiting @ tick 1870335522500 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index b45122ce6..046013e55 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -4,167 +4,167 @@ sim_seconds 1.870336 # Nu sim_ticks 1870335522500 # Number of ticks simulated final_tick 1870335522500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2870976 # Simulator instruction rate (inst/s) -host_op_rate 2870973 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 85025108641 # Simulator tick rate (ticks/s) -host_mem_usage 298608 # Number of bytes of host memory used -host_seconds 22.00 # Real time elapsed on the host +host_inst_rate 4061827 # Simulator instruction rate (inst/s) +host_op_rate 4061823 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 120292600618 # Simulator tick rate (ticks/s) +host_mem_usage 301032 # Number of bytes of host memory used +host_seconds 15.55 # Real time elapsed on the host sim_insts 63154034 # Number of instructions simulated sim_ops 63154034 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 855168 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 67882688 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 761216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 66693056 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2649600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 139840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 770176 # Number of bytes read from this memory -system.physmem.bytes_read::total 72297472 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 855168 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 139840 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 995008 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 10452352 # Number of bytes written to this memory -system.physmem.bytes_written::total 10452352 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13362 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 1060667 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu1.inst 110976 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 668672 # Number of bytes read from this memory +system.physmem.bytes_read::total 70883520 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 761216 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 110976 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 872192 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7861504 # Number of bytes written to this memory +system.physmem.bytes_written::total 7861504 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 11894 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 1042079 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41400 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2185 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 12034 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1129648 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 163318 # Number of write requests responded to by this memory -system.physmem.num_writes::total 163318 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 457227 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 36294391 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu1.inst 1734 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10448 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1107555 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 122836 # Number of write requests responded to by this memory +system.physmem.num_writes::total 122836 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 406994 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 35658338 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 1416644 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 74767 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 411785 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 38654814 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 457227 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 74767 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 531994 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 5588490 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 5588490 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 5588490 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 457227 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 36294391 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 59335 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 357514 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 37898826 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 406994 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 59335 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 466329 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4203259 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4203259 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4203259 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 406994 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 35658338 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 1416644 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 74767 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 411785 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 44243304 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 1051788 # number of replacements -system.l2c.tagsinuse 34117.721410 # Cycle average of tags in use -system.l2c.total_refs 2341203 # Total number of references to valid blocks. -system.l2c.sampled_refs 1087985 # Sample count of references to valid blocks. -system.l2c.avg_refs 2.151871 # Average number of references to valid blocks. -system.l2c.warmup_cycle 990121000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 23831.931773 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 3683.485712 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 6336.188239 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 152.381317 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 113.734368 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.363646 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.056206 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.096683 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.002325 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.001735 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.520595 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 871618 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 748887 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 101445 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 35685 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1757635 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 811846 # number of Writeback hits -system.l2c.Writeback_hits::total 811846 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 134 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 39 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 173 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 15 # number of SCUpgradeReq hits +system.physmem.bw_total::cpu1.inst 59335 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 357514 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42102084 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 1000626 # number of replacements +system.l2c.tagsinuse 65381.922680 # Cycle average of tags in use +system.l2c.total_refs 2464692 # Total number of references to valid blocks. +system.l2c.sampled_refs 1065768 # Sample count of references to valid blocks. +system.l2c.avg_refs 2.312597 # Average number of references to valid blocks. +system.l2c.warmup_cycle 838081000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 56158.702580 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4894.236968 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 4134.601551 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 174.423287 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 19.958294 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.856914 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.074680 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.063089 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.002661 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.000305 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.997649 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 873086 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 763047 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 101896 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 36724 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1774753 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 816766 # number of Writeback hits +system.l2c.Writeback_hits::total 816766 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 133 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 36 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 169 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 14 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.data 9 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 24 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 164417 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 14126 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 178543 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 871618 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 913304 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 101445 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 49811 # number of demand (read+write) hits -system.l2c.demand_hits::total 1936178 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 871618 # number of overall hits -system.l2c.overall_hits::cpu0.data 913304 # number of overall hits -system.l2c.overall_hits::cpu1.inst 101445 # number of overall hits -system.l2c.overall_hits::cpu1.data 49811 # number of overall hits -system.l2c.overall_hits::total 1936178 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 13362 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 943555 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 2185 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 2326 # number of ReadReq misses -system.l2c.ReadReq_misses::total 961428 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2441 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 567 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3008 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_hits::total 23 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 166157 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 14260 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 180417 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 873086 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 929204 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 101896 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 50984 # number of demand (read+write) hits +system.l2c.demand_hits::total 1955170 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 873086 # number of overall hits +system.l2c.overall_hits::cpu0.data 929204 # number of overall hits +system.l2c.overall_hits::cpu1.inst 101896 # number of overall hits +system.l2c.overall_hits::cpu1.data 50984 # number of overall hits +system.l2c.overall_hits::total 1955170 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 11894 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 926761 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 1734 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 908 # number of ReadReq misses +system.l2c.ReadReq_misses::total 941297 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 2442 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 570 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 3012 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu0.data 65 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 101 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 166 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 117481 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 9826 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 127307 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 13362 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 1061036 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 2185 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 12152 # number of demand (read+write) misses -system.l2c.demand_misses::total 1088735 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 13362 # number of overall misses -system.l2c.overall_misses::cpu0.data 1061036 # number of overall misses -system.l2c.overall_misses::cpu1.inst 2185 # number of overall misses -system.l2c.overall_misses::cpu1.data 12152 # number of overall misses -system.l2c.overall_misses::total 1088735 # number of overall misses +system.l2c.SCUpgradeReq_misses::cpu1.data 100 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 165 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 115706 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 9662 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 125368 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.inst 11894 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 1042467 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 1734 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 10570 # number of demand (read+write) misses +system.l2c.demand_misses::total 1066665 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 11894 # number of overall misses +system.l2c.overall_misses::cpu0.data 1042467 # number of overall misses +system.l2c.overall_misses::cpu1.inst 1734 # number of overall misses +system.l2c.overall_misses::cpu1.data 10570 # number of overall misses +system.l2c.overall_misses::total 1066665 # number of overall misses system.l2c.ReadReq_accesses::cpu0.inst 884980 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 1692442 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 1689808 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.inst 103630 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 38011 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2719063 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 811846 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 811846 # number of Writeback accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 37632 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2716050 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 816766 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 816766 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 2575 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 606 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 3181 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 80 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 110 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 190 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 281898 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 23952 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 305850 # number of ReadExReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 79 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 109 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 188 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 281863 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 23922 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 305785 # number of ReadExReq accesses(hits+misses) system.l2c.demand_accesses::cpu0.inst 884980 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1974340 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1971671 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.inst 103630 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 61963 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 3024913 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 61554 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 3021835 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu0.inst 884980 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1974340 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1971671 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.inst 103630 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 61963 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 3024913 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.015099 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.557511 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.021085 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.061193 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.353588 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.947961 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.935644 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.945615 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.812500 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.918182 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.873684 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.416750 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.410237 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.416240 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.015099 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.537413 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.021085 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.196117 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.359923 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.015099 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.537413 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.021085 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.196117 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.359923 # miss rate for overall accesses +system.l2c.overall_accesses::cpu1.data 61554 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 3021835 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.013440 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.548442 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.016733 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.024128 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.346568 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.948350 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.940594 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.946872 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.822785 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.917431 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.877660 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.410504 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.403896 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.409987 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.013440 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.528723 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.016733 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.171719 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.352986 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.013440 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.528723 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.016733 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.171719 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.352986 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -173,8 +173,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 121798 # number of writebacks -system.l2c.writebacks::total 121798 # number of writebacks +system.l2c.writebacks::writebacks 81316 # number of writebacks +system.l2c.writebacks::total 81316 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41695 # number of replacements system.iocache.tagsinuse 0.435437 # Cycle average of tags in use @@ -451,39 +451,39 @@ system.cpu0.icache.cache_copies 0 # nu system.cpu0.icache.writebacks::writebacks 95 # number of writebacks system.cpu0.icache.writebacks::total 95 # number of writebacks system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1978962 # number of replacements -system.cpu0.dcache.tagsinuse 504.827058 # Cycle average of tags in use -system.cpu0.dcache.total_refs 13123502 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1979474 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 6.629793 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 1978686 # number of replacements +system.cpu0.dcache.tagsinuse 507.129778 # Cycle average of tags in use +system.cpu0.dcache.total_refs 13123753 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1979198 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 6.630844 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 504.827058 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.985990 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.985990 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 7298106 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7298106 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5462265 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5462265 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 172138 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 172138 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 186635 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 186635 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 12760371 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12760371 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 12760371 # number of overall hits -system.cpu0.dcache.overall_hits::total 12760371 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1683563 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1683563 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 285996 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 285996 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16159 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 16159 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 703 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 703 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1969559 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1969559 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1969559 # number of overall misses -system.cpu0.dcache.overall_misses::total 1969559 # number of overall misses +system.cpu0.dcache.occ_blocks::cpu0.data 507.129778 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.990488 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.990488 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 7298337 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7298337 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5462263 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5462263 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 172144 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 172144 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 186624 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 186624 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 12760600 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12760600 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 12760600 # number of overall hits +system.cpu0.dcache.overall_hits::total 12760600 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1683332 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1683332 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 285998 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 285998 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16153 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 16153 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 714 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 714 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1969330 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1969330 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1969330 # number of overall misses +system.cpu0.dcache.overall_misses::total 1969330 # number of overall misses system.cpu0.dcache.ReadReq_accesses::cpu0.data 8981669 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 8981669 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 5748261 # number of WriteReq accesses(hits+misses) @@ -496,18 +496,18 @@ system.cpu0.dcache.demand_accesses::cpu0.data 14729930 system.cpu0.dcache.demand_accesses::total 14729930 # number of demand (read+write) accesses system.cpu0.dcache.overall_accesses::cpu0.data 14729930 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 14729930 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.187444 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.187444 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049753 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.049753 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085817 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085817 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003753 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.003753 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.133711 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.133711 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.133711 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.133711 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.187419 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.187419 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049754 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.049754 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085785 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085785 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003811 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.003811 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.133696 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.133696 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.133696 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.133696 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -516,8 +516,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 771740 # number of writebacks -system.cpu0.dcache.writebacks::total 771740 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 775641 # number of writebacks +system.cpu0.dcache.writebacks::total 775641 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses @@ -687,42 +687,42 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 15 # number of writebacks -system.cpu1.icache.writebacks::total 15 # number of writebacks +system.cpu1.icache.writebacks::writebacks 18 # number of writebacks +system.cpu1.icache.writebacks::total 18 # number of writebacks system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 62338 # number of replacements -system.cpu1.dcache.tagsinuse 391.951263 # Cycle average of tags in use -system.cpu1.dcache.total_refs 1834544 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 62657 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 29.279155 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 1851267520500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 391.951263 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.765530 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.765530 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 1109315 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1109315 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 707444 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 707444 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 15129 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 15129 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 15613 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 15613 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 1816759 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 1816759 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 1816759 # number of overall hits -system.cpu1.dcache.overall_hits::total 1816759 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 41650 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 41650 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 25861 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 25861 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1289 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 1289 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 732 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 732 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 67511 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 67511 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 67511 # number of overall misses -system.cpu1.dcache.overall_misses::total 67511 # number of overall misses +system.cpu1.dcache.replacements 62044 # number of replacements +system.cpu1.dcache.tagsinuse 421.562730 # Cycle average of tags in use +system.cpu1.dcache.total_refs 1836054 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 62382 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 29.432432 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 1851115552500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 421.562730 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.823365 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.823365 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 1109521 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1109521 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 707457 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 707457 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 15133 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 15133 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 15610 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 15610 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 1816978 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 1816978 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 1816978 # number of overall hits +system.cpu1.dcache.overall_hits::total 1816978 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 41444 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 41444 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 25848 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 25848 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1285 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 1285 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 735 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 735 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 67292 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 67292 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 67292 # number of overall misses +system.cpu1.dcache.overall_misses::total 67292 # number of overall misses system.cpu1.dcache.ReadReq_accesses::cpu1.data 1150965 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_accesses::total 1150965 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::cpu1.data 733305 # number of WriteReq accesses(hits+misses) @@ -735,18 +735,18 @@ system.cpu1.dcache.demand_accesses::cpu1.data 1884270 system.cpu1.dcache.demand_accesses::total 1884270 # number of demand (read+write) accesses system.cpu1.dcache.overall_accesses::cpu1.data 1884270 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 1884270 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036187 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.036187 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.035266 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.035266 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.078511 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.078511 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.044784 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.044784 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035829 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.035829 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035829 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.035829 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036008 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.036008 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.035249 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.035249 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.078268 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.078268 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.044968 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.044968 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035713 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.035713 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035713 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.035713 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -755,8 +755,8 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 39996 # number of writebacks -system.cpu1.dcache.writebacks::total 39996 # number of writebacks +system.cpu1.dcache.writebacks::writebacks 41012 # number of writebacks +system.cpu1.dcache.writebacks::total 41012 # number of writebacks system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout index 92dc7ad3d..d842316f6 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout @@ -1,12 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 14:07:23 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:10:03 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 1829332258000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index 4492aa0b0..e2a65cb45 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -4,109 +4,109 @@ sim_seconds 1.829332 # Nu sim_ticks 1829332258000 # Number of ticks simulated final_tick 1829332258000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2878195 # Simulator instruction rate (inst/s) -host_op_rate 2878193 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 87696777763 # Simulator tick rate (ticks/s) -host_mem_usage 296144 # Number of bytes of host memory used -host_seconds 20.86 # Real time elapsed on the host +host_inst_rate 4017982 # Simulator instruction rate (inst/s) +host_op_rate 4017978 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 122425314574 # Simulator tick rate (ticks/s) +host_mem_usage 297960 # Number of bytes of host memory used +host_seconds 14.94 # Real time elapsed on the host sim_insts 60038305 # Number of instructions simulated sim_ops 60038305 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 955904 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 68042304 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2652608 # Number of bytes read from this memory -system.physmem.bytes_read::total 71650816 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 955904 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 955904 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 10156864 # Number of bytes written to this memory -system.physmem.bytes_written::total 10156864 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 14936 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1063161 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41447 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1119544 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 158701 # Number of write requests responded to by this memory -system.physmem.num_writes::total 158701 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 522543 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 37195159 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1450042 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 39167743 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 522543 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 522543 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 5552225 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 5552225 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 5552225 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 522543 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 37195159 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1450042 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 44719968 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 1045877 # number of replacements -system.l2c.tagsinuse 33807.015903 # Cycle average of tags in use -system.l2c.total_refs 2291835 # Total number of references to valid blocks. -system.l2c.sampled_refs 1077848 # Sample count of references to valid blocks. -system.l2c.avg_refs 2.126306 # Average number of references to valid blocks. -system.l2c.warmup_cycle 765422500 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 23613.410409 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 3680.391656 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 6513.213838 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.360312 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.056158 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.099384 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.515854 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.inst 905267 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 794128 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1699395 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 825291 # number of Writeback hits -system.l2c.Writeback_hits::total 825291 # number of Writeback hits +system.physmem.bytes_read::cpu.inst 857984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 66839424 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory +system.physmem.bytes_read::total 70349696 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 857984 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 857984 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7411392 # Number of bytes written to this memory +system.physmem.bytes_written::total 7411392 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13406 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1044366 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1099214 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115803 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115803 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 469015 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 36537607 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1449867 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 38456489 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 469015 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 469015 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4051419 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4051419 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4051419 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 469015 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 36537607 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1449867 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42507908 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 992301 # number of replacements +system.l2c.tagsinuse 65424.374305 # Cycle average of tags in use +system.l2c.total_refs 2433195 # Total number of references to valid blocks. +system.l2c.sampled_refs 1057464 # Sample count of references to valid blocks. +system.l2c.avg_refs 2.300972 # Average number of references to valid blocks. +system.l2c.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 56309.122439 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 4867.329747 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 4247.922119 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.859209 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.inst 0.074270 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.064818 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.998297 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.inst 906797 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 811183 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1717980 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 833599 # number of Writeback hits +system.l2c.Writeback_hits::total 833599 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 1 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 185383 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 185383 # number of ReadExReq hits -system.l2c.demand_hits::cpu.inst 905267 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 979511 # number of demand (read+write) hits -system.l2c.demand_hits::total 1884778 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.inst 905267 # number of overall hits -system.l2c.overall_hits::cpu.data 979511 # number of overall hits -system.l2c.overall_hits::total 1884778 # number of overall hits -system.l2c.ReadReq_misses::cpu.inst 14936 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 944693 # number of ReadReq misses -system.l2c.ReadReq_misses::total 959629 # number of ReadReq misses +system.l2c.ReadExReq_hits::cpu.data 187125 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 187125 # number of ReadExReq hits +system.l2c.demand_hits::cpu.inst 906797 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 998308 # number of demand (read+write) hits +system.l2c.demand_hits::total 1905105 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.inst 906797 # number of overall hits +system.l2c.overall_hits::cpu.data 998308 # number of overall hits +system.l2c.overall_hits::total 1905105 # number of overall hits +system.l2c.ReadReq_misses::cpu.inst 13406 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 927640 # number of ReadReq misses +system.l2c.ReadReq_misses::total 941046 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 12 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 118859 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 118859 # number of ReadExReq misses -system.l2c.demand_misses::cpu.inst 14936 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 1063552 # number of demand (read+write) misses -system.l2c.demand_misses::total 1078488 # number of demand (read+write) misses -system.l2c.overall_misses::cpu.inst 14936 # number of overall misses -system.l2c.overall_misses::cpu.data 1063552 # number of overall misses -system.l2c.overall_misses::total 1078488 # number of overall misses +system.l2c.ReadExReq_misses::cpu.data 117117 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 117117 # number of ReadExReq misses +system.l2c.demand_misses::cpu.inst 13406 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 1044757 # number of demand (read+write) misses +system.l2c.demand_misses::total 1058163 # number of demand (read+write) misses +system.l2c.overall_misses::cpu.inst 13406 # number of overall misses +system.l2c.overall_misses::cpu.data 1044757 # number of overall misses +system.l2c.overall_misses::total 1058163 # number of overall misses system.l2c.ReadReq_accesses::cpu.inst 920203 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 1738821 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2659024 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 825291 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 825291 # number of Writeback accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 1738823 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2659026 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 833599 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 833599 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu.data 13 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 13 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu.data 304242 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 304242 # number of ReadExReq accesses(hits+misses) system.l2c.demand_accesses::cpu.inst 920203 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 2043063 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2963266 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 2043065 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2963268 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu.inst 920203 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 2043063 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2963266 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.016231 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.543295 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.360895 # miss rate for ReadReq accesses +system.l2c.overall_accesses::cpu.data 2043065 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2963268 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu.inst 0.014569 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.533487 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.353906 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu.data 0.923077 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 0.923077 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.390673 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.390673 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.inst 0.016231 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.520567 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.363952 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.inst 0.016231 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.520567 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.363952 # miss rate for overall accesses +system.l2c.ReadExReq_miss_rate::cpu.data 0.384947 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.384947 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu.inst 0.014569 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.511367 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.357093 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.inst 0.014569 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.511367 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.357093 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -115,8 +115,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 117189 # number of writebacks -system.l2c.writebacks::total 117189 # number of writebacks +system.l2c.writebacks::writebacks 74291 # number of writebacks +system.l2c.writebacks::total 74291 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41686 # number of replacements system.iocache.tagsinuse 1.225570 # Cycle average of tags in use @@ -388,37 +388,37 @@ system.cpu.icache.cache_copies 0 # nu system.cpu.icache.writebacks::writebacks 108 # number of writebacks system.cpu.icache.writebacks::total 108 # number of writebacks system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2042700 # number of replacements +system.cpu.dcache.replacements 2042702 # number of replacements system.cpu.dcache.tagsinuse 511.997802 # Cycle average of tags in use -system.cpu.dcache.total_refs 14038433 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2043212 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 6.870767 # Average number of references to valid blocks. +system.cpu.dcache.total_refs 14038431 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2043214 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 6.870759 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 7807782 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7807782 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 7807780 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7807780 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 5848212 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 5848212 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 183141 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 183141 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 199282 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13655994 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13655994 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13655994 # number of overall hits -system.cpu.dcache.overall_hits::total 13655994 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1721705 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1721705 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 13655992 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13655992 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13655992 # number of overall hits +system.cpu.dcache.overall_hits::total 13655992 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1721707 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1721707 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 304362 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 304362 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2026067 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2026067 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2026067 # number of overall misses -system.cpu.dcache.overall_misses::total 2026067 # number of overall misses +system.cpu.dcache.demand_misses::cpu.data 2026069 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2026069 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2026069 # number of overall misses +system.cpu.dcache.overall_misses::total 2026069 # number of overall misses system.cpu.dcache.ReadReq_accesses::cpu.data 9529487 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 9529487 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6152574 # number of WriteReq accesses(hits+misses) @@ -431,16 +431,16 @@ system.cpu.dcache.demand_accesses::cpu.data 15682061 # system.cpu.dcache.demand_accesses::total 15682061 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 15682061 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 15682061 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180671 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.180671 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180672 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.180672 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049469 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.049469 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085680 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085680 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.129196 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.129196 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.129196 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.129196 # miss rate for overall accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.129197 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.129197 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.129197 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.129197 # miss rate for overall accesses system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -449,8 +449,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 825183 # number of writebacks -system.cpu.dcache.writebacks::total 825183 # number of writebacks +system.cpu.dcache.writebacks::writebacks 833491 # number of writebacks +system.cpu.dcache.writebacks::total 833491 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout index b3456c80f..4abaeca9d 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout @@ -1,13 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 13:42:45 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:10:10 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... info: Launching CPU 1 @ 562628000 -Exiting @ tick 1958647095000 because m5_exit instruction encountered +Exiting @ tick 1957577582000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index e92359043..9611b47c5 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,218 +1,218 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.958647 # Number of seconds simulated -sim_ticks 1958647095000 # Number of ticks simulated -final_tick 1958647095000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.957578 # Number of seconds simulated +sim_ticks 1957577582000 # Number of ticks simulated +final_tick 1957577582000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1245422 # Simulator instruction rate (inst/s) -host_op_rate 1245421 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 41097010927 # Simulator tick rate (ticks/s) -host_mem_usage 295412 # Number of bytes of host memory used -host_seconds 47.66 # Real time elapsed on the host -sim_insts 59355643 # Number of instructions simulated -sim_ops 59355643 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 919744 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 25960192 # Number of bytes read from this memory +host_inst_rate 1866861 # Simulator instruction rate (inst/s) +host_op_rate 1866860 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 61595044213 # Simulator tick rate (ticks/s) +host_mem_usage 296940 # Number of bytes of host memory used +host_seconds 31.78 # Real time elapsed on the host +sim_insts 59331415 # Number of instructions simulated +sim_ops 59331415 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 825984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24749824 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 51456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 468416 # Number of bytes read from this memory -system.physmem.bytes_read::total 30050624 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 919744 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 51456 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 971200 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 10333120 # Number of bytes written to this memory -system.physmem.bytes_written::total 10333120 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 14371 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 405628 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu1.inst 37440 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 398080 # Number of bytes read from this memory +system.physmem.bytes_read::total 28662144 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 825984 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 37440 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 863424 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7684736 # Number of bytes written to this memory +system.physmem.bytes_written::total 7684736 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 12906 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 386716 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41419 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 804 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 7319 # Number of read requests responded to by this memory -system.physmem.num_reads::total 469541 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 161455 # Number of write requests responded to by this memory -system.physmem.num_writes::total 161455 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 469581 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 13254145 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1353391 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 26271 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 239153 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15342541 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 469581 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 26271 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 495852 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 5275642 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 5275642 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 5275642 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 469581 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 13254145 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1353391 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 26271 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 239153 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 20618183 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 393576 # number of replacements -system.l2c.tagsinuse 34487.800710 # Cycle average of tags in use -system.l2c.total_refs 2371449 # Total number of references to valid blocks. -system.l2c.sampled_refs 427769 # Sample count of references to valid blocks. -system.l2c.avg_refs 5.543761 # Average number of references to valid blocks. -system.l2c.warmup_cycle 10882116000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 23419.887612 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 3728.336055 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 7139.593108 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 100.838318 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 99.145617 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.357359 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.056890 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.108942 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.001539 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.001513 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.526242 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 901389 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 758006 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 86187 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 33004 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1778586 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 816294 # number of Writeback hits -system.l2c.Writeback_hits::total 816294 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 172 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 53 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 225 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 18 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 19 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 37 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 170288 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 12569 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 182857 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 901389 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 928294 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 86187 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 45573 # number of demand (read+write) hits -system.l2c.demand_hits::total 1961443 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 901389 # number of overall hits -system.l2c.overall_hits::cpu0.data 928294 # number of overall hits -system.l2c.overall_hits::cpu1.inst 86187 # number of overall hits -system.l2c.overall_hits::cpu1.data 45573 # number of overall hits -system.l2c.overall_hits::total 1961443 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 14371 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 288456 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 815 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1138 # number of ReadReq misses -system.l2c.ReadReq_misses::total 304780 # number of ReadReq misses +system.physmem.num_reads::cpu1.inst 585 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 6220 # Number of read requests responded to by this memory +system.physmem.num_reads::total 447846 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 120074 # Number of write requests responded to by this memory +system.physmem.num_writes::total 120074 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 421942 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12643087 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1354131 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 19126 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 203353 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14641639 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 421942 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 19126 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 441068 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3925635 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3925635 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3925635 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 421942 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12643087 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1354131 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 19126 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 203353 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18567274 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 340832 # number of replacements +system.l2c.tagsinuse 65295.945000 # Cycle average of tags in use +system.l2c.total_refs 2492123 # Total number of references to valid blocks. +system.l2c.sampled_refs 405944 # Sample count of references to valid blocks. +system.l2c.avg_refs 6.139081 # Average number of references to valid blocks. +system.l2c.warmup_cycle 7739998000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 55466.932424 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4795.907583 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 4852.495880 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 163.850290 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 16.758824 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.846358 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.073180 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.074043 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.002500 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.000256 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.996337 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 902441 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 771400 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 86210 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 33732 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1793783 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 821051 # number of Writeback hits +system.l2c.Writeback_hits::total 821051 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 166 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 54 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 220 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 14 # 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average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40013.578027 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40007.372976 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40013.135837 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40003.254300 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40013.578027 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40007.372976 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40013.135837 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -345,14 +345,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41694 # number of replacements -system.iocache.tagsinuse 0.563721 # Cycle average of tags in use +system.iocache.tagsinuse 0.563379 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41710 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1751545158000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 0.563721 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.035233 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.035233 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1750565168000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 0.563379 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.035211 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.035211 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses system.iocache.ReadReq_misses::total 174 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -363,12 +363,12 @@ system.iocache.overall_misses::tsunami.ide 41726 # system.iocache.overall_misses::total 41726 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 20052998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 20052998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 5721783806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 5721783806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 5741836804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 5741836804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 5741836804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 5741836804 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 5719883806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 5719883806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 5739936804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 5739936804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 5739936804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 5739936804 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -387,17 +387,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115247.114943 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 115247.114943 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137701.766606 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 137701.766606 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 137608.129320 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 137608.129320 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 137608.129320 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 137608.129320 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 64596068 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137656.040768 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 137656.040768 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 137562.594162 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 137562.594162 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 137562.594162 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 137562.594162 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 64630068 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 10459 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6176.122765 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6179.373554 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -413,12 +413,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41726 system.iocache.overall_mshr_misses::total 41726 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11004998 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 11004998 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3560928000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 3560928000 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 3571932998 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 3571932998 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 3571932998 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 3571932998 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3559028000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 3559028000 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 3570032998 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 3570032998 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 3570032998 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 3570032998 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -429,12 +429,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63247.114943 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 63247.114943 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85698.113208 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 85698.113208 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85604.491157 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 85604.491157 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85604.491157 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 85604.491157 # average overall mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85652.387370 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 85652.387370 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85558.955999 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 85558.955999 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85558.955999 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 85558.955999 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -452,22 +452,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 8633623 # DTB read hits +system.cpu0.dtb.read_hits 8630502 # DTB read hits system.cpu0.dtb.read_misses 7443 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations system.cpu0.dtb.read_accesses 490673 # DTB read accesses -system.cpu0.dtb.write_hits 6044743 # DTB write hits +system.cpu0.dtb.write_hits 6043026 # DTB write hits system.cpu0.dtb.write_misses 813 # DTB write misses system.cpu0.dtb.write_acv 134 # DTB write access violations system.cpu0.dtb.write_accesses 187452 # DTB write accesses -system.cpu0.dtb.data_hits 14678366 # DTB hits +system.cpu0.dtb.data_hits 14673528 # DTB hits system.cpu0.dtb.data_misses 8256 # DTB misses system.cpu0.dtb.data_acv 344 # DTB access violations system.cpu0.dtb.data_accesses 678125 # DTB accesses -system.cpu0.itb.fetch_hits 3853057 # ITB hits +system.cpu0.itb.fetch_hits 3852973 # ITB hits system.cpu0.itb.fetch_misses 3871 # ITB misses system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 3856928 # ITB accesses +system.cpu0.itb.fetch_accesses 3856844 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -480,55 +480,55 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3916023774 # number of cpu cycles simulated +system.cpu0.numCycles 3914070794 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 54072652 # Number of instructions committed -system.cpu0.committedOps 54072652 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 50043234 # Number of integer alu accesses +system.cpu0.committedInsts 54051547 # Number of instructions committed +system.cpu0.committedOps 54051547 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 50023130 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 293967 # Number of float alu accesses -system.cpu0.num_func_calls 1426863 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 6237040 # number of instructions that are conditional controls -system.cpu0.num_int_insts 50043234 # number of integer instructions +system.cpu0.num_func_calls 1426247 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 6235141 # number of instructions that are conditional controls +system.cpu0.num_int_insts 50023130 # number of integer instructions system.cpu0.num_fp_insts 293967 # number of float instructions -system.cpu0.num_int_register_reads 68528072 # number of times the integer registers were read -system.cpu0.num_int_register_writes 37080372 # number of times the integer registers were written +system.cpu0.num_int_register_reads 68498295 # number of times the integer registers were read +system.cpu0.num_int_register_writes 37064173 # number of times the integer registers were written system.cpu0.num_fp_register_reads 143353 # number of times the floating registers were read system.cpu0.num_fp_register_writes 146452 # number of times the floating registers were written -system.cpu0.num_mem_refs 14724357 # number of memory refs -system.cpu0.num_load_insts 8664914 # Number of load instructions -system.cpu0.num_store_insts 6059443 # Number of store instructions -system.cpu0.num_idle_cycles 3680034047.555842 # Number of idle cycles -system.cpu0.num_busy_cycles 235989726.444158 # Number of busy cycles -system.cpu0.not_idle_fraction 0.060263 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.939737 # Percentage of idle cycles +system.cpu0.num_mem_refs 14719518 # number of memory refs +system.cpu0.num_load_insts 8661793 # Number of load instructions +system.cpu0.num_store_insts 6057725 # Number of store instructions +system.cpu0.num_idle_cycles 3679914036.735006 # Number of idle cycles +system.cpu0.num_busy_cycles 234156757.264994 # Number of busy cycles +system.cpu0.not_idle_fraction 0.059824 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.940176 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6380 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 202972 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 72739 40.62% 40.62% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 6362 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 202969 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 72743 40.62% 40.62% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 131 0.07% 40.70% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1975 1.10% 41.80% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1974 1.10% 41.80% # number of times we switched to this ipl system.cpu0.kern.ipl_count::30 6 0.00% 41.80% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 104211 58.20% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 179062 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 71372 49.27% 49.27% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::31 104206 58.20% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 179060 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 71376 49.27% 49.27% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 131 0.09% 49.36% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1975 1.36% 50.73% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1974 1.36% 50.73% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::30 6 0.00% 50.73% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 71366 49.27% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 144850 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1899667899000 97.02% 97.02% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 79058000 0.00% 97.02% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 565985500 0.03% 97.05% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 4729500 0.00% 97.05% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 57694185000 2.95% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1958011857000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.981207 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good::31 71370 49.27% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 144857 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1898820258500 97.03% 97.03% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 78970000 0.00% 97.03% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 565865000 0.03% 97.06% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 4687500 0.00% 97.06% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 57565586000 2.94% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1957035367000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.981208 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.684822 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.808938 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.684893 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.808986 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed @@ -567,28 +567,28 @@ system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.05% # nu system.cpu0.kern.callpal::swpctx 3894 2.07% 2.12% # number of callpals executed system.cpu0.kern.callpal::tbi 51 0.03% 2.15% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.15% # number of callpals executed -system.cpu0.kern.callpal::swpipl 172198 91.50% 93.64% # number of callpals executed -system.cpu0.kern.callpal::rdps 6678 3.55% 97.19% # number of callpals executed +system.cpu0.kern.callpal::swpipl 172198 91.50% 93.65% # number of callpals executed +system.cpu0.kern.callpal::rdps 6677 3.55% 97.19% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 97.19% # number of callpals executed system.cpu0.kern.callpal::wrusp 3 0.00% 97.20% # number of callpals executed system.cpu0.kern.callpal::rdusp 9 0.00% 97.20% # number of callpals executed system.cpu0.kern.callpal::whami 2 0.00% 97.20% # number of callpals executed -system.cpu0.kern.callpal::rti 4751 2.52% 99.73% # number of callpals executed +system.cpu0.kern.callpal::rti 4750 2.52% 99.73% # number of callpals executed system.cpu0.kern.callpal::callsys 381 0.20% 99.93% # number of callpals executed system.cpu0.kern.callpal::imb 136 0.07% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 188203 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7302 # number of protection mode switches +system.cpu0.kern.callpal::total 188201 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7301 # number of protection mode switches system.cpu0.kern.mode_switch::user 1283 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches system.cpu0.kern.mode_good::kernel 1283 system.cpu0.kern.mode_good::user 1283 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.175705 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.175729 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.298893 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1954355762000 99.83% 99.83% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3390072000 0.17% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.298928 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1953310949000 99.83% 99.83% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3370111000 0.17% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 3895 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA @@ -622,51 +622,51 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 915147 # number of replacements -system.cpu0.icache.tagsinuse 508.800486 # Cycle average of tags in use -system.cpu0.icache.total_refs 53165471 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 915659 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 58.062522 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 36696092000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 508.800486 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.993751 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.993751 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 53165471 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 53165471 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 53165471 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 53165471 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 53165471 # number of overall hits -system.cpu0.icache.overall_hits::total 53165471 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 915781 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 915781 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 915781 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 915781 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 915781 # number of overall misses -system.cpu0.icache.overall_misses::total 915781 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13429132500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 13429132500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 13429132500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 13429132500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 13429132500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 13429132500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 54081252 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 54081252 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 54081252 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 54081252 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 54081252 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 54081252 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016933 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.016933 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016933 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.016933 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016933 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.016933 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14664.130944 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14664.130944 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14664.130944 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14664.130944 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14664.130944 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14664.130944 # average overall miss latency +system.cpu0.icache.replacements 914734 # number of replacements +system.cpu0.icache.tagsinuse 508.814250 # Cycle average of tags in use +system.cpu0.icache.total_refs 53144779 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 915246 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 58.066114 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 35914239000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 508.814250 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.993778 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.993778 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 53144779 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 53144779 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 53144779 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 53144779 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 53144779 # number of overall hits +system.cpu0.icache.overall_hits::total 53144779 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 915368 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 915368 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 915368 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 915368 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 915368 # number of overall misses +system.cpu0.icache.overall_misses::total 915368 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13361799000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 13361799000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 13361799000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 13361799000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 13361799000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 13361799000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 54060147 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 54060147 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 54060147 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 54060147 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 54060147 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 54060147 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016932 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.016932 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016932 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.016932 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016932 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.016932 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14597.188235 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14597.188235 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14597.188235 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14597.188235 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14597.188235 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14597.188235 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -677,112 +677,112 @@ system.cpu0.icache.fast_writes 0 # nu system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.writebacks::writebacks 55 # number of writebacks system.cpu0.icache.writebacks::total 55 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 915781 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 915781 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 915781 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 915781 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 915781 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 915781 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10681093500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 10681093500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10681093500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 10681093500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10681093500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 10681093500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.016933 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.016933 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.016933 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.016933 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.016933 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.016933 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11663.370937 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11663.370937 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11663.370937 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11663.370937 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11663.370937 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11663.370937 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 915368 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 915368 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 915368 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 915368 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 915368 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 915368 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10614998000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 10614998000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10614998000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 10614998000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10614998000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 10614998000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.016932 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.016932 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.016932 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.016932 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.016932 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.016932 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11596.426792 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11596.426792 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11596.426792 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11596.426792 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11596.426792 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11596.426792 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1338438 # number of replacements -system.cpu0.dcache.tagsinuse 503.524900 # Cycle average of tags in use -system.cpu0.dcache.total_refs 13348404 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1338837 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 9.970149 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 1337419 # number of replacements +system.cpu0.dcache.tagsinuse 506.341163 # Cycle average of tags in use +system.cpu0.dcache.total_refs 13344261 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1337832 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 9.974542 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 83958000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 503.524900 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.983447 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.983447 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 7421006 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7421006 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5560133 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5560133 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 176505 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 176505 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 191674 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 191674 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 12981139 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12981139 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 12981139 # number of overall hits -system.cpu0.dcache.overall_hits::total 12981139 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1036101 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1036101 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 291536 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 291536 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16544 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 16544 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 410 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 410 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1327637 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1327637 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1327637 # number of overall misses -system.cpu0.dcache.overall_misses::total 1327637 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 26570279500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 26570279500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 9109954000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 9109954000 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 234949000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 234949000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 2973000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 2973000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 35680233500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 35680233500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 35680233500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 35680233500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8457107 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8457107 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5851669 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5851669 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 193049 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 193049 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 192084 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 192084 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 14308776 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 14308776 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 14308776 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 14308776 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.122512 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.122512 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049821 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.049821 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085698 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085698 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.002134 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.002134 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.092785 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.092785 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.092785 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.092785 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25644.487844 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 25644.487844 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 31248.127161 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 31248.127161 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14201.462766 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14201.462766 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7251.219512 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7251.219512 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26874.991809 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 26874.991809 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26874.991809 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 26874.991809 # average overall miss latency +system.cpu0.dcache.occ_blocks::cpu0.data 506.341163 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.988948 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.988948 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 7419012 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7419012 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5558431 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5558431 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 176349 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 176349 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 191666 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 191666 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 12977443 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12977443 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 12977443 # number of overall hits +system.cpu0.dcache.overall_hits::total 12977443 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1034980 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1034980 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 291529 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 291529 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16694 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 16694 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 411 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 411 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1326509 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1326509 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1326509 # number of overall misses +system.cpu0.dcache.overall_misses::total 1326509 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 25827814500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 25827814500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 9022984000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 9022984000 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 234039000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 234039000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 2995000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 2995000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 34850798500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 34850798500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 34850798500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 34850798500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8453992 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8453992 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5849960 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5849960 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 193043 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 193043 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 192077 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 192077 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 14303952 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 14303952 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 14303952 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 14303952 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.122425 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.122425 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049834 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.049834 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.086478 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.086478 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.002140 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.002140 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.092737 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.092737 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.092737 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.092737 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 24954.892365 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 24954.892365 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30950.553804 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 30950.553804 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14019.348269 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14019.348269 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7287.104623 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7287.104623 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26272.568448 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 26272.568448 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26272.568448 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 26272.568448 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -791,62 +791,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 786441 # number of writebacks -system.cpu0.dcache.writebacks::total 786441 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1036101 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1036101 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 291536 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 291536 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16544 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16544 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 410 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 410 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1327637 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1327637 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1327637 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1327637 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 23461938500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 23461938500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8235346000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8235346000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 185317000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 185317000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 1743000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1743000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 31697284500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 31697284500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 31697284500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 31697284500 # number of overall MSHR miss cycles +system.cpu0.dcache.writebacks::writebacks 790358 # number of writebacks +system.cpu0.dcache.writebacks::total 790358 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1034980 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 1034980 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 291529 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 291529 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16694 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16694 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 411 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 411 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1326509 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1326509 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1326509 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1326509 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 22722836500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 22722836500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8148397000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8148397000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 183957000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 183957000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 1762000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1762000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 30871233500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 30871233500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 30871233500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 30871233500 # number of overall MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 884470000 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 884470000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1242107000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1242107000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2126577000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2126577000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122512 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.122512 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049821 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049821 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.085698 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.085698 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.002134 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.002134 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092785 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.092785 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092785 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.092785 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 22644.451168 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 22644.451168 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 28248.127161 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 28248.127161 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11201.462766 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11201.462766 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4251.219512 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4251.219512 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23874.963186 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23874.963186 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23874.963186 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23874.963186 # average overall mshr miss latency +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1241998500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1241998500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2126468500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2126468500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122425 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.122425 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049834 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049834 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086478 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086478 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.002140 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.002140 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092737 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.092737 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092737 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.092737 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 21954.855649 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 21954.855649 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27950.553804 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27950.553804 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11019.348269 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11019.348269 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4287.104623 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4287.104623 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23272.539802 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23272.539802 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23272.539802 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23272.539802 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -858,22 +858,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1050117 # DTB read hits +system.cpu1.dtb.read_hits 1049963 # DTB read hits system.cpu1.dtb.read_misses 2992 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations system.cpu1.dtb.read_accesses 239363 # DTB read accesses -system.cpu1.dtb.write_hits 651208 # DTB write hits +system.cpu1.dtb.write_hits 651106 # DTB write hits system.cpu1.dtb.write_misses 341 # DTB write misses system.cpu1.dtb.write_acv 29 # DTB write access violations system.cpu1.dtb.write_accesses 105247 # DTB write accesses -system.cpu1.dtb.data_hits 1701325 # DTB hits +system.cpu1.dtb.data_hits 1701069 # DTB hits system.cpu1.dtb.data_misses 3333 # DTB misses system.cpu1.dtb.data_acv 29 # DTB access violations system.cpu1.dtb.data_accesses 344610 # DTB accesses -system.cpu1.itb.fetch_hits 1493438 # ITB hits +system.cpu1.itb.fetch_hits 1493400 # ITB hits system.cpu1.itb.fetch_misses 1216 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1494654 # ITB accesses +system.cpu1.itb.fetch_accesses 1494616 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -886,51 +886,51 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3917294190 # number of cpu cycles simulated +system.cpu1.numCycles 3915155164 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 5282991 # Number of instructions committed -system.cpu1.committedOps 5282991 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 4948310 # Number of integer alu accesses +system.cpu1.committedInsts 5279868 # Number of instructions committed +system.cpu1.committedOps 5279868 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 4945263 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 34031 # Number of float alu accesses -system.cpu1.num_func_calls 158031 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 510974 # number of instructions that are conditional controls -system.cpu1.num_int_insts 4948310 # number of integer instructions +system.cpu1.num_func_calls 157997 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 510441 # number of instructions that are conditional controls +system.cpu1.num_int_insts 4945263 # number of integer instructions system.cpu1.num_fp_insts 34031 # number of float instructions -system.cpu1.num_int_register_reads 6886066 # number of times the integer registers were read -system.cpu1.num_int_register_writes 3732878 # number of times the integer registers were written +system.cpu1.num_int_register_reads 6880916 # number of times the integer registers were read +system.cpu1.num_int_register_writes 3730475 # number of times the integer registers were written system.cpu1.num_fp_register_reads 22062 # number of times the floating registers were read system.cpu1.num_fp_register_writes 21862 # number of times the floating registers were written -system.cpu1.num_mem_refs 1710778 # number of memory refs -system.cpu1.num_load_insts 1056124 # Number of load instructions -system.cpu1.num_store_insts 654654 # Number of store instructions -system.cpu1.num_idle_cycles 3898237020.998010 # Number of idle cycles -system.cpu1.num_busy_cycles 19057169.001990 # Number of busy cycles -system.cpu1.not_idle_fraction 0.004865 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.995135 # Percentage of idle cycles +system.cpu1.num_mem_refs 1710522 # number of memory refs +system.cpu1.num_load_insts 1055970 # Number of load instructions +system.cpu1.num_store_insts 654552 # Number of store instructions +system.cpu1.num_idle_cycles 3896226886.998010 # Number of idle cycles +system.cpu1.num_busy_cycles 18928277.001990 # Number of busy cycles +system.cpu1.not_idle_fraction 0.004835 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.995165 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2318 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 36191 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 9289 32.15% 32.15% # number of times we switched to this ipl +system.cpu1.kern.inst.quiesce 2314 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 36187 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 9288 32.15% 32.15% # number of times we switched to this ipl system.cpu1.kern.ipl_count::22 1969 6.81% 38.96% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 88 0.30% 39.26% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 17551 60.74% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 28897 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 9279 45.20% 45.20% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_count::30 88 0.30% 39.27% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 17548 60.73% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 28893 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 9278 45.20% 45.20% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::22 1969 9.59% 54.80% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 88 0.43% 55.22% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 9191 44.78% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 20527 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1917878582000 97.92% 97.92% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 507844000 0.03% 97.94% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 54239000 0.00% 97.95% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 40205672000 2.05% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1958646337000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_good::30 88 0.43% 55.23% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 9190 44.77% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 20525 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1917614123000 97.96% 97.96% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 507941000 0.03% 97.98% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 53691000 0.00% 97.99% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 39401069000 2.01% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1957576824000 # number of cycles we spent at this ipl system.cpu1.kern.ipl_used::0 0.998923 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.523674 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.710351 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.523706 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.710380 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed @@ -952,7 +952,7 @@ system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # nu system.cpu1.kern.callpal::swpctx 337 1.14% 1.17% # number of callpals executed system.cpu1.kern.callpal::tbi 3 0.01% 1.18% # number of callpals executed system.cpu1.kern.callpal::wrent 7 0.02% 1.20% # number of callpals executed -system.cpu1.kern.callpal::swpipl 24309 82.25% 83.46% # number of callpals executed +system.cpu1.kern.callpal::swpipl 24305 82.25% 83.46% # number of callpals executed system.cpu1.kern.callpal::rdps 2170 7.34% 90.80% # number of callpals executed system.cpu1.kern.callpal::wrkgp 1 0.00% 90.80% # number of callpals executed system.cpu1.kern.callpal::wrusp 4 0.01% 90.82% # number of callpals executed @@ -961,66 +961,66 @@ system.cpu1.kern.callpal::rti 2530 8.56% 99.39% # nu system.cpu1.kern.callpal::callsys 136 0.46% 99.85% # number of callpals executed system.cpu1.kern.callpal::imb 44 0.15% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 29554 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 804 # number of protection mode switches -system.cpu1.kern.mode_switch::user 464 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2064 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 477 -system.cpu1.kern.mode_good::user 464 +system.cpu1.kern.callpal::total 29550 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 803 # number of protection mode switches +system.cpu1.kern.mode_switch::user 463 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2065 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 476 +system.cpu1.kern.mode_good::user 463 system.cpu1.kern.mode_good::idle 13 -system.cpu1.kern.mode_switch_good::kernel 0.593284 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::kernel 0.592777 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.006298 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.286315 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 3571416000 0.18% 0.18% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1745054000 0.09% 0.27% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1953329865000 99.73% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_switch_good::idle 0.006295 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.285800 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 3531821000 0.18% 0.18% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1727088000 0.09% 0.27% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1952317913000 99.73% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 338 # number of times the context was actually changed -system.cpu1.icache.replacements 86457 # number of replacements -system.cpu1.icache.tagsinuse 419.807616 # Cycle average of tags in use -system.cpu1.icache.total_refs 5199349 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 86969 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 59.783935 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1942711132000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 419.807616 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.819937 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.819937 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 5199349 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 5199349 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 5199349 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 5199349 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 5199349 # number of overall hits -system.cpu1.icache.overall_hits::total 5199349 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 87005 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 87005 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 87005 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 87005 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 87005 # number of overall misses -system.cpu1.icache.overall_misses::total 87005 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1260607500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 1260607500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 1260607500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 1260607500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 1260607500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 1260607500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 5286354 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 5286354 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 5286354 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 5286354 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 5286354 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 5286354 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.016458 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.016458 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.016458 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.016458 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.016458 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.016458 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14488.908683 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 14488.908683 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14488.908683 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 14488.908683 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14488.908683 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 14488.908683 # average overall miss latency +system.cpu1.icache.replacements 86261 # number of replacements +system.cpu1.icache.tagsinuse 419.419440 # Cycle average of tags in use +system.cpu1.icache.total_refs 5196422 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 86773 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 59.885241 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1941709468000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 419.419440 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.819179 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.819179 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 5196422 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 5196422 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 5196422 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 5196422 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 5196422 # number of overall hits +system.cpu1.icache.overall_hits::total 5196422 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 86809 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 86809 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 86809 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 86809 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 86809 # number of overall misses +system.cpu1.icache.overall_misses::total 86809 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1248608500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 1248608500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 1248608500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 1248608500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 1248608500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 1248608500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 5283231 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 5283231 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 5283231 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 5283231 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 5283231 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 5283231 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.016431 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.016431 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.016431 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.016431 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.016431 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.016431 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14383.399187 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 14383.399187 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14383.399187 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 14383.399187 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14383.399187 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 14383.399187 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1031,112 +1031,112 @@ system.cpu1.icache.fast_writes 0 # nu system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.writebacks::writebacks 14 # number of writebacks system.cpu1.icache.writebacks::total 14 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 87005 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 87005 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 87005 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 87005 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 87005 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 87005 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 999558500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 999558500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 999558500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 999558500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 999558500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 999558500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016458 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.016458 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.016458 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.016458 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.016458 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.016458 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11488.517901 # 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number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 988145500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 988145500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 988145500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 988145500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 988145500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 988145500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016431 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.016431 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.016431 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.016431 # 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number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 12762 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 12026 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 12026 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 1677346 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 1677346 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 1677346 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 1677346 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035572 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.035572 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.032036 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.032036 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.073970 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.073970 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.042159 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.042159 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.034228 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.034228 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.034228 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.034228 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13311.332739 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13311.332739 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26940.237092 # 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number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1145,62 +1145,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 29784 # number of writebacks -system.cpu1.dcache.writebacks::total 29784 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 37113 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 37113 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 20421 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 20421 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 982 # 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number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 298050500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 298050500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 309464000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 309464000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035676 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035676 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.032042 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.032042 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.076923 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.076923 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.041975 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.041975 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.034296 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.034296 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034296 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.034296 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11368.577048 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11368.577048 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24265.853778 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24265.853778 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 10318.737271 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10318.737271 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 9704.950495 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 9704.950495 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15946.310008 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15946.310008 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15946.310008 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15946.310008 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 30624 # number of writebacks +system.cpu1.dcache.writebacks::total 30624 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 36999 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 36999 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 20414 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 20414 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 944 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 944 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 507 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 507 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 57413 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 57413 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 57413 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 57413 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 381507000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 381507000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 488716000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 488716000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 8473000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 8473000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4831000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4831000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 870223000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 870223000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 870223000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 870223000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 11412500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 11412500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 298066500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 298066500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 309479000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 309479000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035572 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035572 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.032036 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.032036 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.073970 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.073970 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.042159 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.042159 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.034228 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.034228 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034228 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.034228 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10311.278683 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10311.278683 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23940.237092 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23940.237092 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8975.635593 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8975.635593 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 9528.599606 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 9528.599606 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15157.246617 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15157.246617 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15157.246617 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15157.246617 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout index 33fb3404f..c4cb3c061 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout @@ -1,12 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 14:23:20 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:10:05 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1915548867000 because m5_exit instruction encountered +Exiting @ tick 1915492819000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 42fcfede1..abedba373 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,138 +1,138 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.915549 # Number of seconds simulated -sim_ticks 1915548867000 # Number of ticks simulated -final_tick 1915548867000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.915493 # Number of seconds simulated +sim_ticks 1915492819000 # Number of ticks simulated +final_tick 1915492819000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1238015 # Simulator instruction rate (inst/s) -host_op_rate 1238014 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42244373047 # Simulator tick rate (ticks/s) -host_mem_usage 292960 # Number of bytes of host memory used -host_seconds 45.34 # Real time elapsed on the host -sim_insts 56137087 # Number of instructions simulated -sim_ops 56137087 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 943040 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 26067904 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2652416 # Number of bytes read from this memory -system.physmem.bytes_read::total 29663360 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 943040 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 943040 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 10122368 # Number of bytes written to this memory -system.physmem.bytes_written::total 10122368 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 14735 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 407311 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41444 # Number of read requests responded to by this memory -system.physmem.num_reads::total 463490 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 158162 # Number of write requests responded to by this memory -system.physmem.num_writes::total 158162 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 492308 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13608582 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1384677 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15485567 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 492308 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 492308 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 5284317 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 5284317 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 5284317 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 492308 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13608582 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1384677 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 20769884 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 389289 # number of replacements -system.l2c.tagsinuse 34352.038344 # Cycle average of tags in use -system.l2c.total_refs 2311163 # Total number of references to valid blocks. -system.l2c.sampled_refs 421794 # Sample count of references to valid blocks. -system.l2c.avg_refs 5.479364 # Average number of references to valid blocks. -system.l2c.warmup_cycle 6937912000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 23110.665097 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 3746.363547 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 7495.009700 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.352641 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.057165 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.114365 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.524171 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.inst 913599 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 796862 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1710461 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 826671 # number of Writeback hits -system.l2c.Writeback_hits::total 826671 # number of Writeback hits +host_inst_rate 1853108 # Simulator instruction rate (inst/s) +host_op_rate 1853107 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 63179819624 # Simulator tick rate (ticks/s) +host_mem_usage 294892 # Number of bytes of host memory used +host_seconds 30.32 # Real time elapsed on the host +sim_insts 56182681 # Number of instructions simulated +sim_ops 56182681 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 850496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24846208 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory +system.physmem.bytes_read::total 28349056 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 850496 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 850496 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7388480 # Number of bytes written to this memory +system.physmem.bytes_written::total 7388480 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13289 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388222 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory +system.physmem.num_reads::total 442954 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115445 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115445 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 444009 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12971183 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1384684 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14799876 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 444009 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 444009 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3857221 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3857221 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3857221 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 444009 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12971183 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1384684 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18657097 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 336041 # number of replacements +system.l2c.tagsinuse 65311.191779 # Cycle average of tags in use +system.l2c.total_refs 2447812 # Total number of references to valid blocks. +system.l2c.sampled_refs 401203 # Sample count of references to valid blocks. +system.l2c.avg_refs 6.101181 # Average number of references to valid blocks. +system.l2c.warmup_cycle 5933228000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 55666.496606 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 4774.109125 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 4870.586047 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.849403 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.inst 0.072847 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.074319 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.996570 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.inst 915368 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 814896 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1730264 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 835591 # number of Writeback hits +system.l2c.Writeback_hits::total 835591 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu.data 6 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 6 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 185878 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 185878 # number of ReadExReq hits -system.l2c.demand_hits::cpu.inst 913599 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 982740 # number of demand (read+write) hits -system.l2c.demand_hits::total 1896339 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.inst 913599 # number of overall hits -system.l2c.overall_hits::cpu.data 982740 # number of overall hits -system.l2c.overall_hits::total 1896339 # number of overall hits -system.l2c.ReadReq_misses::cpu.inst 14735 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 289403 # number of ReadReq misses -system.l2c.ReadReq_misses::total 304138 # number of ReadReq misses +system.l2c.ReadExReq_hits::cpu.data 187658 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 187658 # number of ReadExReq hits +system.l2c.demand_hits::cpu.inst 915368 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 1002554 # number of demand (read+write) hits +system.l2c.demand_hits::total 1917922 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.inst 915368 # number of overall hits +system.l2c.overall_hits::cpu.data 1002554 # number of overall hits +system.l2c.overall_hits::total 1917922 # number of overall hits +system.l2c.ReadReq_misses::cpu.inst 13289 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 271916 # number of ReadReq misses +system.l2c.ReadReq_misses::total 285205 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu.data 7 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 7 # 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Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1750545944000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.340325 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.083770 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.083770 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1750543570000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.340010 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.083751 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.083751 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -225,14 +225,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 19940998 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 19940998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 5722300806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 5722300806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 5742241804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 5742241804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 5742241804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 5742241804 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 19939998 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 19939998 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 5720017806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 5720017806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 5739957804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 5739957804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 5739957804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 5739957804 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -249,19 +249,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115265.884393 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 115265.884393 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137714.208847 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 137714.208847 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 137621.133709 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 137621.133709 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 137621.133709 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 137621.133709 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 64604060 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115260.104046 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 115260.104046 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137659.265643 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 137659.265643 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 137566.394344 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 137566.394344 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 137566.394344 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 137566.394344 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 64633068 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 10476 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6166.863307 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6169.632302 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -275,14 +275,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 10944998 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 10944998 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3561447990 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 3561447990 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 3572392988 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 3572392988 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 3572392988 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 3572392988 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 10943998 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 10943998 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3559163998 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 3559163998 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 3570107996 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 3570107996 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 3570107996 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 3570107996 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -291,14 +291,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63265.884393 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 63265.884393 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85710.627407 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 85710.627407 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85617.567118 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 85617.567118 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85617.567118 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 85617.567118 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63260.104046 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 63260.104046 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85655.660329 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 85655.660329 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85562.803978 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 85562.803978 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85562.803978 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 85562.803978 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -316,22 +316,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9057511 # DTB read hits -system.cpu.dtb.read_misses 10312 # DTB read misses +system.cpu.dtb.read_hits 9064877 # DTB read hits +system.cpu.dtb.read_misses 10317 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_accesses 728817 # DTB read accesses -system.cpu.dtb.write_hits 6352446 # DTB write hits +system.cpu.dtb.read_accesses 728824 # DTB read accesses +system.cpu.dtb.write_hits 6356219 # DTB write hits system.cpu.dtb.write_misses 1140 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations system.cpu.dtb.write_accesses 291929 # DTB write accesses -system.cpu.dtb.data_hits 15409957 # DTB hits -system.cpu.dtb.data_misses 11452 # DTB misses +system.cpu.dtb.data_hits 15421096 # DTB hits +system.cpu.dtb.data_misses 11457 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations -system.cpu.dtb.data_accesses 1020746 # DTB accesses -system.cpu.itb.fetch_hits 4973520 # ITB hits +system.cpu.dtb.data_accesses 1020753 # DTB accesses +system.cpu.itb.fetch_hits 4974034 # ITB hits system.cpu.itb.fetch_misses 4997 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4978517 # ITB accesses +system.cpu.itb.fetch_accesses 4979031 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -344,51 +344,51 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3831097734 # number of cpu cycles simulated +system.cpu.numCycles 3830985638 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56137087 # Number of instructions committed -system.cpu.committedOps 56137087 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 52011214 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 324192 # Number of float alu accesses -system.cpu.num_func_calls 1482242 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 6464616 # number of instructions that are conditional controls -system.cpu.num_int_insts 52011214 # number of integer instructions -system.cpu.num_fp_insts 324192 # number of float instructions -system.cpu.num_int_register_reads 71259077 # number of times the integer registers were read -system.cpu.num_int_register_writes 38485860 # number of times the integer registers were written -system.cpu.num_fp_register_reads 163510 # number of times the floating registers were read -system.cpu.num_fp_register_writes 166384 # number of times the floating registers were written -system.cpu.num_mem_refs 15462519 # number of memory refs -system.cpu.num_load_insts 9094324 # Number of load instructions -system.cpu.num_store_insts 6368195 # Number of store instructions -system.cpu.num_idle_cycles 3587943187.998127 # Number of idle cycles -system.cpu.num_busy_cycles 243154546.001873 # Number of busy cycles -system.cpu.not_idle_fraction 0.063469 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.936531 # Percentage of idle cycles +system.cpu.committedInsts 56182681 # Number of instructions committed +system.cpu.committedOps 56182681 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 52054721 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 324259 # Number of float alu accesses +system.cpu.num_func_calls 1483282 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 6468098 # number of instructions that are conditional controls +system.cpu.num_int_insts 52054721 # number of integer instructions +system.cpu.num_fp_insts 324259 # number of float instructions +system.cpu.num_int_register_reads 71321767 # number of times the integer registers were read +system.cpu.num_int_register_writes 38521612 # number of times the integer registers were written +system.cpu.num_fp_register_reads 163543 # number of times the floating registers were read +system.cpu.num_fp_register_writes 166418 # number of times the floating registers were written +system.cpu.num_mem_refs 15473677 # number of memory refs +system.cpu.num_load_insts 9101706 # Number of load instructions +system.cpu.num_store_insts 6371971 # Number of store instructions +system.cpu.num_idle_cycles 3589415321.998127 # Number of idle cycles +system.cpu.num_busy_cycles 241570316.001874 # Number of busy cycles +system.cpu.not_idle_fraction 0.063057 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.936943 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211932 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74887 40.89% 40.89% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6374 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211976 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74903 40.89% 40.89% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1931 1.05% 42.02% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 106197 57.98% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183146 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73520 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 106219 57.98% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183184 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73536 49.31% 49.31% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1931 1.30% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73520 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149102 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1857816228500 96.99% 96.99% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 79988500 0.00% 96.99% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 554693000 0.03% 97.02% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 57097199000 2.98% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1915548109000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981746 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1931 1.29% 50.69% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73536 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149134 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1857766748000 96.99% 96.99% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 79985500 0.00% 96.99% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 554565500 0.03% 97.02% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 57090762000 2.98% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1915492061000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981750 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.692298 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814116 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.692306 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814121 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -424,33 +424,33 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4173 2.16% 2.17% # number of callpals executed +system.cpu.kern.callpal::swpctx 4174 2.16% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175927 91.22% 93.41% # number of callpals executed +system.cpu.kern.callpal::swpipl 175965 91.22% 93.41% # number of callpals executed system.cpu.kern.callpal::rdps 6832 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed -system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed +system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rti 5156 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192868 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5903 # number of protection mode switches -system.cpu.kern.mode_switch::user 1738 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2092 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1906 -system.cpu.kern.mode_good::user 1738 -system.cpu.kern.mode_good::idle 168 -system.cpu.kern.mode_switch_good::kernel 0.322887 # fraction of useful protection mode switches +system.cpu.kern.callpal::total 192907 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5900 # number of protection mode switches +system.cpu.kern.mode_switch::user 1740 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1909 +system.cpu.kern.mode_good::user 1740 +system.cpu.kern.mode_good::idle 169 +system.cpu.kern.mode_switch_good::kernel 0.323559 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080306 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.391657 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 45253274000 2.36% 2.36% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5124228000 0.27% 2.63% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1865170605000 97.37% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4174 # number of times the context was actually changed +system.cpu.kern.mode_switch_good::idle 0.080630 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.392153 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 45078055000 2.35% 2.35% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5087693000 0.27% 2.62% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1865326311000 97.38% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4175 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -482,51 +482,51 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 927683 # number of replacements -system.cpu.icache.tagsinuse 508.721464 # Cycle average of tags in use -system.cpu.icache.total_refs 55220553 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 928194 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 59.492469 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 36307428000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 508.721464 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.993597 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.993597 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 55220553 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 55220553 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 55220553 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 55220553 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 55220553 # number of overall hits -system.cpu.icache.overall_hits::total 55220553 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 928354 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 928354 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 928354 # 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Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.993627 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.993627 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 55265829 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 55265829 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 55265829 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 55265829 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 55265829 # number of overall hits +system.cpu.icache.overall_hits::total 55265829 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 928677 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 928677 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 928677 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 928677 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 928677 # 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average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14601.591834 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14601.591834 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14601.591834 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -537,104 +537,104 @@ system.cpu.icache.fast_writes 0 # nu system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks::writebacks 85 # number of writebacks system.cpu.icache.writebacks::total 85 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928354 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 928354 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 928354 # 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number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9163670000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9163670000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 245084000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 245084000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35559696000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35559696000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35559696000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35559696000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 8884003 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 8884003 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6156644 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6156644 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200246 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200246 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199223 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199223 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15040647 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15040647 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15040647 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15040647 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120390 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120390 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049461 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049461 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086449 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086449 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.091356 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.091356 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.091356 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.091356 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24679.631657 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24679.631657 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30092.869598 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30092.869598 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14157.703195 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14157.703195 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 25879.289114 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 25879.289114 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 25879.289114 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 25879.289114 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -643,54 +643,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 826586 # number of writebacks -system.cpu.dcache.writebacks::total 826586 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069110 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1069110 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304335 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304335 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17201 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17201 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1373445 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1373445 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1373445 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1373445 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23914545000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 23914545000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8315479000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8315479000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 194377000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 194377000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32230024000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 32230024000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32230024000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 32230024000 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 835506 # number of writebacks +system.cpu.dcache.writebacks::total 835506 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069547 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1069547 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304513 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 304513 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17311 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17311 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1374060 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1374060 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1374060 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1374060 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23187340000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23187340000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8250131000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8250131000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 193151000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 193151000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31437471000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 31437471000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31437471000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 31437471000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 862763000 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 862763000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1199607500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1199607500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 2062370500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 2062370500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120441 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120441 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049462 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049462 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085908 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085908 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091383 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091383 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091383 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091383 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22368.647754 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22368.647754 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27323.439631 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27323.439631 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11300.331376 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11300.331376 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23466.555996 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23466.555996 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23466.555996 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23466.555996 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1199604500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1199604500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 2062367500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 2062367500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120390 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120390 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049461 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049461 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086449 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086449 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091356 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091356 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091356 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091356 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21679.589583 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21679.589583 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27092.869598 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27092.869598 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11157.703195 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11157.703195 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22879.256364 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22879.256364 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22879.256364 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22879.256364 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini index 31269f9bd..e2b1a3bea 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini @@ -22,6 +22,7 @@ machine_type=RealView_PBX mem_mode=atomic memories=system.realview.nvmem system.physmem midr_regval=890224640 +multi_proc=true num_work_ids=16 readfile=tests/halt.sh symbolfile= diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout index be4dcf157..50982556e 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 17:25:17 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 00:36:18 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index 002831edb..c0313feaf 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.911654 # Nu sim_ticks 911653589000 # Number of ticks simulated final_tick 911653589000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1520101 # Simulator instruction rate (inst/s) -host_op_rate 1964640 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 22862175544 # Simulator tick rate (ticks/s) -host_mem_usage 382804 # Number of bytes of host memory used -host_seconds 39.88 # Real time elapsed on the host +host_inst_rate 2171864 # Simulator instruction rate (inst/s) +host_op_rate 2807005 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 32664627860 # Simulator tick rate (ticks/s) +host_mem_usage 382740 # Number of bytes of host memory used +host_seconds 27.91 # Real time elapsed on the host sim_insts 60615585 # Number of instructions simulated sim_ops 78342060 # Number of ops (including micro ops) simulated system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory @@ -30,237 +30,237 @@ system.realview.nvmem.bw_total::cpu0.inst 22 # T system.realview.nvmem.bw_total::cpu1.inst 53 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 75 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 661924 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 6760756 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 1152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 341852 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 3873968 # Number of bytes read from this memory -system.physmem.bytes_read::total 50963556 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 661924 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 341852 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1003776 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7197696 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 506468 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 6290740 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 210652 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 3309616 # Number of bytes read from this memory +system.physmem.bytes_read::total 49639524 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 506468 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 210652 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 717120 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4196032 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010088 # Number of bytes written to this memory -system.physmem.bytes_written::total 10224784 # Number of bytes written to this memory +system.physmem.bytes_written::total 7223120 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 4915200 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 12 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 8 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 16561 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 105709 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 16 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 18 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 5423 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 60557 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5103504 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 112464 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 14132 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 98365 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 3373 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 51739 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5082816 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 65563 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752522 # Number of write requests responded to by this memory -system.physmem.num_writes::total 869236 # Number of write requests responded to by this memory +system.physmem.num_writes::total 822335 # Number of write requests responded to by this memory system.physmem.bw_read::realview.clcd 43132173 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 842 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 562 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 726070 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 7415926 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 1123 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 1264 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 374980 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4249386 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 55902326 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 726070 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 374980 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1101050 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 7895209 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 70 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 140 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 555549 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 6900362 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 211 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 70 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 231066 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 3630344 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 54449985 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 555549 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 231066 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 786615 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4602661 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 18647 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 3301789 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 11215646 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 7895209 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 7923097 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4602661 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.clcd 43132173 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 842 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 562 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 726070 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 7434574 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 1123 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 1264 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 374980 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 7551175 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 67117972 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 127935 # number of replacements -system.l2c.tagsinuse 26245.835103 # Cycle average of tags in use -system.l2c.total_refs 1477463 # Total number of references to valid blocks. -system.l2c.sampled_refs 156884 # Sample count of references to valid blocks. -system.l2c.avg_refs 9.417551 # Average number of references to valid blocks. +system.physmem.bw_total::cpu0.dtb.walker 70 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 140 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 555549 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 6919010 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 211 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 70 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 231066 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 6932133 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 62373082 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 70681 # number of replacements +system.l2c.tagsinuse 51554.827924 # Cycle average of tags in use +system.l2c.total_refs 1661073 # Total number of references to valid blocks. +system.l2c.sampled_refs 135855 # Sample count of references to valid blocks. +system.l2c.avg_refs 12.226808 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 16687.001530 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 1.397314 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.122168 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 2780.380300 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 1123.317941 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 4.426009 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.itb.walker 0.092136 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 1942.464102 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 3706.633603 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.254623 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000021 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.042425 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.017140 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000068 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.itb.walker 0.000001 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.029640 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.056559 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.400480 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 5294 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 2199 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 485527 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 213776 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 4291 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1552 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 359854 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 128180 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1200673 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 578200 # number of Writeback hits -system.l2c.Writeback_hits::total 578200 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 835 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 757 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1592 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 134 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 214 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 348 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 68011 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 33233 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 101244 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 5294 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 2199 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 485527 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 281787 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 4291 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 1552 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 359854 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 161413 # number of demand (read+write) hits -system.l2c.demand_hits::total 1301917 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 5294 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 2199 # number of overall hits -system.l2c.overall_hits::cpu0.inst 485527 # number of overall hits -system.l2c.overall_hits::cpu0.data 281787 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 4291 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 1552 # number of overall hits -system.l2c.overall_hits::cpu1.inst 359854 # number of overall hits -system.l2c.overall_hits::cpu1.data 161413 # number of overall hits -system.l2c.overall_hits::total 1301917 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 12 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 8 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 9928 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 9109 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 16 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 18 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 5336 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 10106 # number of ReadReq misses -system.l2c.ReadReq_misses::total 34533 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 6262 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 3142 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 9404 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 731 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 408 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1139 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 98092 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 50861 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 148953 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 12 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 8 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 9928 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 107201 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 16 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 18 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 5336 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 60967 # number of demand (read+write) misses -system.l2c.demand_misses::total 183486 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 12 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 8 # number of overall misses -system.l2c.overall_misses::cpu0.inst 9928 # number of overall misses -system.l2c.overall_misses::cpu0.data 107201 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 16 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 18 # number of overall misses -system.l2c.overall_misses::cpu1.inst 5336 # number of overall misses -system.l2c.overall_misses::cpu1.data 60967 # number of overall misses -system.l2c.overall_misses::total 183486 # number of overall misses -system.l2c.ReadReq_accesses::cpu0.dtb.walker 5306 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 2207 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 495455 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 222885 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 4307 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 1570 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 365190 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 138286 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1235206 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 578200 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 578200 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 7097 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 3899 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 10996 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 865 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 622 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1487 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 166103 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 84094 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 250197 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 5306 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 2207 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 495455 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 388988 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 4307 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 1570 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 365190 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 222380 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1485403 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 5306 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 2207 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 495455 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 388988 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 4307 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 1570 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 365190 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 222380 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1485403 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.002262 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.003625 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.020038 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.040869 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.003715 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.011465 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.014612 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.073080 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.027957 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.882345 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.805848 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.855220 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.845087 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.655949 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.765972 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.590549 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.604811 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.595343 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.002262 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.003625 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.020038 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.275589 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.003715 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.011465 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.014612 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.274157 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.123526 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.002262 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.003625 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.020038 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.275589 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.003715 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.011465 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.014612 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.274157 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.123526 # miss rate for overall accesses +system.l2c.occ_blocks::writebacks 39271.893324 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 0.000049 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 0.000326 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4360.096185 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 2483.383308 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 2.678787 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.itb.walker 0.000776 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 2126.160779 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 3310.614391 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.599242 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.066530 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.037893 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.dtb.walker 0.000041 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.032443 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.050516 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.786664 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 5302 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 2202 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 487741 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 211552 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 4297 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 1568 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 361833 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 130247 # 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number of demand (read+write) misses +system.l2c.demand_misses::total 163339 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses +system.l2c.overall_misses::cpu0.inst 7499 # number of overall misses +system.l2c.overall_misses::cpu0.data 100252 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 3 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses +system.l2c.overall_misses::cpu1.inst 3286 # number of overall misses +system.l2c.overall_misses::cpu1.data 52295 # number of overall misses +system.l2c.overall_misses::total 163339 # number of overall misses +system.l2c.ReadReq_accesses::cpu0.dtb.walker 5303 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 2204 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 495240 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 217934 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 4300 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 1569 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 365119 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 135511 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1227180 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 613260 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 613260 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 7090 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 3758 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 10848 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 857 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 537 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1394 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 165376 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 83237 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 248613 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 5303 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 2204 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 495240 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 383310 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 4300 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 1569 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 365119 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 218748 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1475793 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 5303 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 2204 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 495240 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 383310 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 4300 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 1569 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 365119 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 218748 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1475793 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000189 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000907 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.015142 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.029284 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000698 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000637 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.009000 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.038846 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.018284 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.883357 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.800426 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.854628 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.856476 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.901304 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.873745 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.567616 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.565025 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.566748 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000189 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000907 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.015142 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.261543 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000698 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.000637 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.009000 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.239065 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.110679 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000189 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000907 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.015142 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.261543 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000698 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.000637 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.009000 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.239065 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.110679 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -269,8 +269,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 112464 # number of writebacks -system.l2c.writebacks::total 112464 # number of writebacks +system.l2c.writebacks::writebacks 65563 # number of writebacks +system.l2c.writebacks::total 65563 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -327,7 +327,7 @@ system.cpu0.committedInsts 33900598 # Nu system.cpu0.committedOps 44786074 # Number of ops (including micro ops) committed system.cpu0.num_int_alu_accesses 39685287 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 5074 # Number of float alu accesses -system.cpu0.num_func_calls 1296918 # number of times a function call or return occured +system.cpu0.num_func_calls 1436598 # number of times a function call or return occured system.cpu0.num_conditional_control_insts 4494112 # number of instructions that are conditional controls system.cpu0.num_int_insts 39685287 # number of integer instructions system.cpu0.num_fp_insts 5074 # number of float instructions @@ -344,15 +344,15 @@ system.cpu0.not_idle_fraction 0.025030 # Pe system.cpu0.idle_fraction 0.974970 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 58955 # number of quiesce instructions executed -system.cpu0.icache.replacements 497177 # number of replacements -system.cpu0.icache.tagsinuse 511.014795 # Cycle average of tags in use +system.cpu0.icache.replacements 497178 # number of replacements +system.cpu0.icache.tagsinuse 511.019581 # Cycle average of tags in use system.cpu0.icache.total_refs 34187980 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 497689 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 68.693461 # Average number of references to valid blocks. +system.cpu0.icache.sampled_refs 497690 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 68.693323 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 64536851000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.014795 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.998076 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.998076 # Average percentage of cache occupancy +system.cpu0.icache.occ_blocks::cpu0.inst 511.019581 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.998085 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.998085 # Average percentage of cache occupancy system.cpu0.icache.ReadReq_hits::cpu0.inst 34187980 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 34187980 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 34187980 # number of demand (read+write) hits @@ -385,42 +385,42 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 26062 # number of writebacks -system.cpu0.icache.writebacks::total 26062 # number of writebacks +system.cpu0.icache.writebacks::writebacks 31457 # number of writebacks +system.cpu0.icache.writebacks::total 31457 # number of writebacks system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 385595 # number of replacements -system.cpu0.dcache.tagsinuse 475.569441 # Cycle average of tags in use -system.cpu0.dcache.total_refs 14667576 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 386107 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 37.988371 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 380425 # number of replacements +system.cpu0.dcache.tagsinuse 495.308430 # Cycle average of tags in use +system.cpu0.dcache.total_refs 14671885 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 380937 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 38.515253 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 22115000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 475.569441 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.928847 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.928847 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 7775792 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7775792 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 6519223 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 6519223 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 172927 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 172927 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 175483 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 175483 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 14295015 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 14295015 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 14295015 # number of overall hits -system.cpu0.dcache.overall_hits::total 14295015 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 240570 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 240570 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 186007 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 186007 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9987 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 9987 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7377 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7377 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 426577 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 426577 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 426577 # number of overall misses -system.cpu0.dcache.overall_misses::total 426577 # number of overall misses +system.cpu0.dcache.occ_blocks::cpu0.data 495.308430 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.967399 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.967399 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 7779192 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7779192 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 6519856 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 6519856 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 173153 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 173153 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 175464 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 175464 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 14299048 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 14299048 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 14299048 # number of overall hits +system.cpu0.dcache.overall_hits::total 14299048 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 237170 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 237170 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 185374 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 185374 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9761 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 9761 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7396 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7396 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 422544 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 422544 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 422544 # number of overall misses +system.cpu0.dcache.overall_misses::total 422544 # number of overall misses system.cpu0.dcache.ReadReq_accesses::cpu0.data 8016362 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 8016362 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 6705230 # number of WriteReq accesses(hits+misses) @@ -433,18 +433,18 @@ system.cpu0.dcache.demand_accesses::cpu0.data 14721592 system.cpu0.dcache.demand_accesses::total 14721592 # number of demand (read+write) accesses system.cpu0.dcache.overall_accesses::cpu0.data 14721592 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 14721592 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.030010 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.030010 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027741 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.027741 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054599 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054599 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.040342 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.040342 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.028976 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.028976 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.028976 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.028976 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029586 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.029586 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027646 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.027646 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.053364 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.053364 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.040446 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.040446 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.028702 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.028702 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.028702 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.028702 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -453,8 +453,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 342703 # number of writebacks -system.cpu0.dcache.writebacks::total 342703 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 353901 # number of writebacks +system.cpu0.dcache.writebacks::total 353901 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses @@ -505,7 +505,7 @@ system.cpu1.committedInsts 26714987 # Nu system.cpu1.committedOps 33555986 # Number of ops (including micro ops) committed system.cpu1.num_int_alu_accesses 30087808 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 5643 # Number of float alu accesses -system.cpu1.num_func_calls 723750 # number of times a function call or return occured +system.cpu1.num_func_calls 761024 # number of times a function call or return occured system.cpu1.num_conditional_control_insts 3301562 # number of instructions that are conditional controls system.cpu1.num_int_insts 30087808 # number of integer instructions system.cpu1.num_fp_insts 5643 # number of float instructions @@ -563,42 +563,42 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 12806 # number of writebacks -system.cpu1.icache.writebacks::total 12806 # number of writebacks +system.cpu1.icache.writebacks::writebacks 15197 # number of writebacks +system.cpu1.icache.writebacks::total 15197 # number of writebacks system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 240038 # number of replacements -system.cpu1.dcache.tagsinuse 389.638585 # Cycle average of tags in use -system.cpu1.dcache.total_refs 9512122 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 240396 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 39.568554 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 69263687500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 389.638585 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.761013 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.761013 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 5740038 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 5740038 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 3634687 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 3634687 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 56514 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 56514 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 57060 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 57060 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 9374725 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 9374725 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 9374725 # number of overall hits -system.cpu1.dcache.overall_hits::total 9374725 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 161066 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 161066 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 108913 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 108913 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 10616 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 10616 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10014 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10014 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 269979 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 269979 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 269979 # number of overall misses -system.cpu1.dcache.overall_misses::total 269979 # number of overall misses +system.cpu1.dcache.replacements 236700 # number of replacements +system.cpu1.dcache.tagsinuse 447.071707 # Cycle average of tags in use +system.cpu1.dcache.total_refs 9515102 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 237061 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 40.137779 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 67292773000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 447.071707 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.873187 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.873187 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 5742078 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 5742078 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 3635346 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 3635346 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 56591 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 56591 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 56639 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 56639 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 9377424 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 9377424 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 9377424 # number of overall hits +system.cpu1.dcache.overall_hits::total 9377424 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 159026 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 159026 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 108254 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 108254 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 10539 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 10539 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10435 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10435 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 267280 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 267280 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 267280 # number of overall misses +system.cpu1.dcache.overall_misses::total 267280 # number of overall misses system.cpu1.dcache.ReadReq_accesses::cpu1.data 5901104 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_accesses::total 5901104 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::cpu1.data 3743600 # number of WriteReq accesses(hits+misses) @@ -611,18 +611,18 @@ system.cpu1.dcache.demand_accesses::cpu1.data 9644704 system.cpu1.dcache.demand_accesses::total 9644704 # number of demand (read+write) accesses system.cpu1.dcache.overall_accesses::cpu1.data 9644704 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 9644704 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.027294 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.027294 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.029093 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.029093 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.158141 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.158141 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.149298 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.149298 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027992 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.027992 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.027992 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.027992 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.026949 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.026949 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.028917 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.028917 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.156994 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.156994 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.155574 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.155574 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027713 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.027713 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.027713 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.027713 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -631,8 +631,8 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 196629 # number of writebacks -system.cpu1.dcache.writebacks::total 196629 # number of writebacks +system.cpu1.dcache.writebacks::writebacks 212705 # number of writebacks +system.cpu1.dcache.writebacks::total 212705 # number of writebacks system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini index 99dc32f6e..f14835c6b 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini @@ -22,6 +22,7 @@ machine_type=RealView_PBX mem_mode=atomic memories=system.physmem system.realview.nvmem midr_regval=890224640 +multi_proc=true num_work_ids=16 readfile=tests/halt.sh symbolfile= diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout index f08c091ef..4dbfc774f 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 17:24:24 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 00:35:36 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index 154c8ff44..176436ee7 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -4,51 +4,51 @@ sim_seconds 2.332330 # Nu sim_ticks 2332330037000 # Number of ticks simulated final_tick 2332330037000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1412842 # Simulator instruction rate (inst/s) -host_op_rate 1823742 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 55482154888 # Simulator tick rate (ticks/s) -host_mem_usage 382804 # Number of bytes of host memory used -host_seconds 42.04 # Real time elapsed on the host +host_inst_rate 1988795 # Simulator instruction rate (inst/s) +host_op_rate 2567201 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 78099767101 # Simulator tick rate (ticks/s) +host_mem_usage 382744 # Number of bytes of host memory used +host_seconds 29.86 # Real time elapsed on the host sim_insts 59392246 # Number of instructions simulated sim_ops 76665494 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 1536 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 941920 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10043536 # Number of bytes read from this memory -system.physmem.bytes_read::total 122661296 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 941920 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 941920 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6574400 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 704992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9071568 # Number of bytes read from this memory +system.physmem.bytes_read::total 121450416 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 704992 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 704992 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3703040 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3015816 # Number of bytes written to this memory -system.physmem.bytes_written::total 9590216 # Number of bytes written to this memory +system.physmem.bytes_written::total 6718856 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 13959168 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 24 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 20920 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 156964 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14137091 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 102725 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 17218 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141777 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14118171 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57860 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 753954 # Number of write requests responded to by this memory -system.physmem.num_writes::total 856679 # Number of write requests responded to by this memory +system.physmem.num_writes::total 811814 # Number of write requests responded to by this memory system.physmem.bw_read::realview.clcd 47880592 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 659 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 412 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 403854 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 4306224 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52591740 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 403854 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 403854 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2818812 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 137 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 82 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 302269 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3889487 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52072569 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 302269 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 302269 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1587700 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 1293049 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4111861 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2818812 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2880748 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1587700 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.clcd 47880592 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 659 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 412 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 403854 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5599273 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 56703601 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 137 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 82 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 302269 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5182536 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54953317 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -61,103 +61,103 @@ system.realview.nvmem.bw_inst_read::cpu.inst 9 system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 9 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 117012 # number of replacements -system.l2c.tagsinuse 24288.656748 # Cycle average of tags in use -system.l2c.total_refs 1527554 # Total number of references to valid blocks. -system.l2c.sampled_refs 146810 # Sample count of references to valid blocks. -system.l2c.avg_refs 10.404972 # Average number of references to valid blocks. -system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 13693.996987 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 7.872000 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.itb.walker 1.975558 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 5248.163956 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 5336.648246 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.208954 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.dtb.walker 0.000120 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.itb.walker 0.000030 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.080081 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.081431 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.370615 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 7515 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 3139 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 835264 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 357385 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1203303 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 605735 # number of Writeback hits -system.l2c.Writeback_hits::total 605735 # number of Writeback hits +system.l2c.replacements 62240 # number of replacements +system.l2c.tagsinuse 50004.786190 # Cycle average of tags in use +system.l2c.total_refs 1717775 # Total number of references to valid blocks. +system.l2c.sampled_refs 127625 # Sample count of references to valid blocks. +system.l2c.avg_refs 13.459549 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2316513323500 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 36897.037256 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 2.960071 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.itb.walker 0.993930 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 7014.608709 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 6089.186223 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.563004 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.inst 0.107034 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.092914 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.763012 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 7534 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.itb.walker 3151 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.inst 838895 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 364444 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1214024 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 642748 # number of Writeback hits +system.l2c.Writeback_hits::total 642748 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 106156 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 106156 # number of ReadExReq hits -system.l2c.demand_hits::cpu.dtb.walker 7515 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.itb.walker 3139 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.inst 835264 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 463541 # number of demand (read+write) hits -system.l2c.demand_hits::total 1309459 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.dtb.walker 7515 # number of overall hits -system.l2c.overall_hits::cpu.itb.walker 3139 # number of overall hits -system.l2c.overall_hits::cpu.inst 835264 # number of overall hits -system.l2c.overall_hits::cpu.data 463541 # number of overall hits -system.l2c.overall_hits::total 1309459 # number of overall hits -system.l2c.ReadReq_misses::cpu.dtb.walker 24 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.itb.walker 15 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.inst 14304 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 17465 # number of ReadReq misses -system.l2c.ReadReq_misses::total 31808 # number of ReadReq misses +system.l2c.ReadExReq_hits::cpu.data 113737 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 113737 # number of ReadExReq hits +system.l2c.demand_hits::cpu.dtb.walker 7534 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.itb.walker 3151 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.inst 838895 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 478181 # number of demand (read+write) hits +system.l2c.demand_hits::total 1327761 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.dtb.walker 7534 # number of overall hits +system.l2c.overall_hits::cpu.itb.walker 3151 # number of overall hits +system.l2c.overall_hits::cpu.inst 838895 # number of overall hits +system.l2c.overall_hits::cpu.data 478181 # number of overall hits +system.l2c.overall_hits::total 1327761 # number of overall hits +system.l2c.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.inst 10602 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 9870 # number of ReadReq misses +system.l2c.ReadReq_misses::total 20480 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu.data 2918 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 2918 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 141050 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 141050 # number of ReadExReq misses -system.l2c.demand_misses::cpu.dtb.walker 24 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.itb.walker 15 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.inst 14304 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 158515 # number of demand (read+write) misses -system.l2c.demand_misses::total 172858 # number of demand (read+write) misses -system.l2c.overall_misses::cpu.dtb.walker 24 # number of overall misses -system.l2c.overall_misses::cpu.itb.walker 15 # number of overall misses -system.l2c.overall_misses::cpu.inst 14304 # number of overall misses -system.l2c.overall_misses::cpu.data 158515 # number of overall misses -system.l2c.overall_misses::total 172858 # number of overall misses +system.l2c.ReadExReq_misses::cpu.data 133469 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 133469 # number of ReadExReq misses +system.l2c.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.inst 10602 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 143339 # number of demand (read+write) misses +system.l2c.demand_misses::total 153949 # number of demand (read+write) misses +system.l2c.overall_misses::cpu.dtb.walker 5 # number of overall misses +system.l2c.overall_misses::cpu.itb.walker 3 # number of overall misses +system.l2c.overall_misses::cpu.inst 10602 # number of overall misses +system.l2c.overall_misses::cpu.data 143339 # number of overall misses +system.l2c.overall_misses::total 153949 # number of overall misses system.l2c.ReadReq_accesses::cpu.dtb.walker 7539 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu.itb.walker 3154 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.inst 849568 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 374850 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1235111 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 605735 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 605735 # number of Writeback accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.inst 849497 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 374314 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1234504 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 642748 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 642748 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu.data 2944 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 2944 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu.data 247206 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 247206 # number of ReadExReq accesses(hits+misses) system.l2c.demand_accesses::cpu.dtb.walker 7539 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu.itb.walker 3154 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.inst 849568 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 622056 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1482317 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.inst 849497 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 621520 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1481710 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu.dtb.walker 7539 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu.itb.walker 3154 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.inst 849568 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 622056 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1482317 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.003183 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.004756 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.016837 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.046592 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.025753 # miss rate for ReadReq accesses +system.l2c.overall_accesses::cpu.inst 849497 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.data 621520 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1481710 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000663 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000951 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.inst 0.012480 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.026368 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.016590 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu.data 0.991168 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 0.991168 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.570577 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.570577 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.dtb.walker 0.003183 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.itb.walker 0.004756 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.inst 0.016837 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.254824 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.116613 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.dtb.walker 0.003183 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.itb.walker 0.004756 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.inst 0.016837 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.254824 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.116613 # miss rate for overall accesses +system.l2c.ReadExReq_miss_rate::cpu.data 0.539910 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.539910 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu.dtb.walker 0.000663 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.itb.walker 0.000951 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.inst 0.012480 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.230627 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.103900 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.dtb.walker 0.000663 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.itb.walker 0.000951 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.inst 0.012480 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.230627 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.103900 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -166,8 +166,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 102725 # number of writebacks -system.l2c.writebacks::total 102725 # number of writebacks +system.l2c.writebacks::writebacks 57860 # number of writebacks +system.l2c.writebacks::total 57860 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -224,7 +224,7 @@ system.cpu.committedInsts 59392246 # Nu system.cpu.committedOps 76665494 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 68281415 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses -system.cpu.num_func_calls 1972385 # number of times a function call or return occured +system.cpu.num_func_calls 2136013 # number of times a function call or return occured system.cpu.num_conditional_control_insts 7647793 # number of instructions that are conditional controls system.cpu.num_int_insts 68281415 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions @@ -282,8 +282,8 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 44595 # number of writebacks -system.cpu.icache.writebacks::total 44595 # number of writebacks +system.cpu.icache.writebacks::writebacks 50093 # number of writebacks +system.cpu.icache.writebacks::total 50093 # number of writebacks system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 623347 # number of replacements system.cpu.dcache.tagsinuse 511.997030 # Cycle average of tags in use @@ -346,8 +346,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 561140 # number of writebacks -system.cpu.dcache.writebacks::total 561140 # number of writebacks +system.cpu.dcache.writebacks::writebacks 592655 # number of writebacks +system.cpu.dcache.writebacks::total 592655 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini index 08257cec9..f78b6a8fb 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini @@ -22,6 +22,7 @@ machine_type=RealView_PBX mem_mode=timing memories=system.realview.nvmem system.physmem midr_regval=890224640 +multi_proc=true num_work_ids=16 readfile=tests/halt.sh symbolfile= diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout index dc9f6d387..ccc6b6e90 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 17:26:08 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 00:37:10 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1169707043000 because m5_exit instruction encountered +Exiting @ tick 1169301297000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index c1f17df29..a92b3a054 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.169707 # Number of seconds simulated -sim_ticks 1169707043000 # Number of ticks simulated -final_tick 1169707043000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.169301 # Number of seconds simulated +sim_ticks 1169301297000 # Number of ticks simulated +final_tick 1169301297000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 657704 # Simulator instruction rate (inst/s) -host_op_rate 841119 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 12730829062 # Simulator tick rate (ticks/s) -host_mem_usage 382856 # Number of bytes of host memory used -host_seconds 91.88 # Real time elapsed on the host -sim_insts 60429704 # Number of instructions simulated -sim_ops 77281862 # Number of ops (including micro ops) simulated +host_inst_rate 971844 # Simulator instruction rate (inst/s) +host_op_rate 1242825 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 18805861990 # Simulator tick rate (ticks/s) +host_mem_usage 384788 # Number of bytes of host memory used +host_seconds 62.18 # Real time elapsed on the host +sim_insts 60426768 # Number of instructions simulated +sim_ops 77275723 # Number of ops (including micro ops) simulated system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -30,309 +30,291 @@ system.realview.nvmem.bw_total::cpu0.inst 17 # T system.realview.nvmem.bw_total::cpu1.inst 41 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 58 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 50331648 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 534756 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5211316 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 470236 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5348464 # Number of bytes read from this memory -system.physmem.bytes_read::total 61898788 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 534756 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 470236 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1004992 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7051584 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 394404 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4694964 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 322780 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4800816 # Number of bytes read from this memory +system.physmem.bytes_read::total 60545060 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 394404 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 322780 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 717184 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4092224 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 10078928 # Number of bytes written to this memory +system.physmem.bytes_written::total 7119568 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6291456 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 10 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 14574 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 81499 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 18 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 7429 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 83596 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6478591 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 110181 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 12381 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 73431 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 5125 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 75039 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6457439 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 63941 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 867017 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43029277 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 547 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 219 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 457171 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 4455232 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 985 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 274 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 402012 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4572482 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52918197 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 457171 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 402012 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 859183 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 6028504 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 14534 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2573588 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 8616626 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 6028504 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43029277 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 547 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 219 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 457171 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 4469765 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 985 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 274 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 402012 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 7146070 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 61534823 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 125934 # number of replacements -system.l2c.tagsinuse 27532.100282 # Cycle average of tags in use -system.l2c.total_refs 1500548 # Total number of references to valid blocks. -system.l2c.sampled_refs 155551 # Sample count of references to valid blocks. -system.l2c.avg_refs 9.646663 # Average number of references to valid blocks. +system.physmem.num_writes::total 820777 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43044208 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 55 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 109 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 337299 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 4015188 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 219 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 276045 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4105713 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51778836 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 337299 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 276045 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 613344 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3499717 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 14539 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2574481 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6088737 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3499717 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43044208 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 55 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 109 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 337299 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 4029726 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 219 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 276045 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 6680194 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 57867573 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 69045 # number of replacements +system.l2c.tagsinuse 52660.415221 # Cycle average of tags in use +system.l2c.total_refs 1684870 # Total number of references to valid blocks. +system.l2c.sampled_refs 134185 # Sample count of references to valid blocks. +system.l2c.avg_refs 12.556321 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 17789.012398 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 1.363432 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.117594 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 2294.743571 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 2778.537805 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 5.252408 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.itb.walker 0.023319 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 2406.434925 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 2256.614830 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.271439 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000021 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.035015 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.042397 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000080 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.itb.walker 0.000000 # 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number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1189 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 549 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1738 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 223 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 193 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 416 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 53827 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 49705 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 103532 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 4097 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 1763 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 399350 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 259693 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 5680 # 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number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 31325370500 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 265520000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10016294500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10017042500 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3961000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 152864341000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 163150116500 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.002435 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.002264 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.019497 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.052112 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.003159 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.002559 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.016188 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.055681 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.028163 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.797203 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.868377 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.826789 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.717722 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.700775 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.710105 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.569136 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.605340 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.587311 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.002435 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.002264 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.019497 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.240912 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.003159 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.002559 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.016188 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.307390 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.122213 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.002435 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.002264 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.019497 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.240912 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.003159 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.002559 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.016188 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.307390 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.122213 # mshr miss rate for overall accesses +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 152861899000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 163148422500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000231 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001066 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014118 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.037012 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000726 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.011115 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.024732 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.018073 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.799555 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.881281 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.833064 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.725289 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.817708 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.764576 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.541003 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.578134 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.559705 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000231 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001066 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014118 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.222254 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000726 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011115 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.279646 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.109027 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000231 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001066 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014118 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.222254 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000726 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011115 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.279646 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.109027 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40151.618184 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40082.081640 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40222.222222 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40272.541542 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40145.524636 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40153.009531 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40041.506205 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40064.881281 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40051.711668 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40010.582011 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40075.221239 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40039.254171 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40045.653366 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40117.289052 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40082.720239 # average ReadExReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40135.003479 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40027.198780 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40750 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40262.207225 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40169.925640 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40131.482146 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40029.329908 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40048.630520 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40037.701540 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40017.699115 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40091.295117 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40051.158301 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40032.856544 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40114.530881 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40075.350086 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40151.618184 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40050.655795 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40222.222222 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40272.541542 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40120.061509 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40096.193198 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40135.003479 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40032.260655 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40750 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40262.207225 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40117.173336 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40083.092535 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40151.618184 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40050.655795 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40222.222222 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40272.541542 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40120.061509 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40096.193198 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40135.003479 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40032.260655 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40750 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40262.207225 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40117.173336 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40083.092535 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -528,26 +498,26 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7070142 # DTB read hits -system.cpu0.dtb.read_misses 3739 # DTB read misses -system.cpu0.dtb.write_hits 5655287 # DTB write hits -system.cpu0.dtb.write_misses 802 # DTB write misses +system.cpu0.dtb.read_hits 7070010 # DTB read hits +system.cpu0.dtb.read_misses 3742 # DTB read misses +system.cpu0.dtb.write_hits 5655317 # DTB write hits +system.cpu0.dtb.write_misses 808 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1791 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 1790 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 143 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 141 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7073881 # DTB read accesses -system.cpu0.dtb.write_accesses 5656089 # DTB write accesses +system.cpu0.dtb.read_accesses 7073752 # DTB read accesses +system.cpu0.dtb.write_accesses 5656125 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12725429 # DTB hits -system.cpu0.dtb.misses 4541 # DTB misses -system.cpu0.dtb.accesses 12729970 # DTB accesses -system.cpu0.itb.inst_hits 29439632 # ITB inst hits +system.cpu0.dtb.hits 12725327 # DTB hits +system.cpu0.dtb.misses 4550 # DTB misses +system.cpu0.dtb.accesses 12729877 # DTB accesses +system.cpu0.itb.inst_hits 29439174 # ITB inst hits system.cpu0.itb.inst_misses 2205 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -564,79 +534,79 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 29441837 # ITB inst accesses -system.cpu0.itb.hits 29439632 # DTB hits +system.cpu0.itb.inst_accesses 29441379 # ITB inst accesses +system.cpu0.itb.hits 29439174 # DTB hits system.cpu0.itb.misses 2205 # DTB misses -system.cpu0.itb.accesses 29441837 # DTB accesses -system.cpu0.numCycles 2339414086 # number of cpu cycles simulated +system.cpu0.itb.accesses 29441379 # DTB accesses +system.cpu0.numCycles 2338602594 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 28747266 # Number of instructions committed -system.cpu0.committedOps 37085213 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 33031535 # Number of integer alu accesses +system.cpu0.committedInsts 28746820 # Number of instructions committed +system.cpu0.committedOps 37084824 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 33031249 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses -system.cpu0.num_func_calls 1116936 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4321526 # number of instructions that are conditional controls -system.cpu0.num_int_insts 33031535 # number of integer instructions +system.cpu0.num_func_calls 1241704 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4321371 # number of instructions that are conditional controls +system.cpu0.num_int_insts 33031249 # number of integer instructions system.cpu0.num_fp_insts 3860 # number of float instructions -system.cpu0.num_int_register_reads 189616194 # number of times the integer registers were read -system.cpu0.num_int_register_writes 36089294 # number of times the integer registers were written +system.cpu0.num_int_register_reads 189614137 # number of times the integer registers were read +system.cpu0.num_int_register_writes 36088732 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written -system.cpu0.num_mem_refs 13393398 # number of memory refs -system.cpu0.num_load_insts 7407664 # Number of load instructions -system.cpu0.num_store_insts 5985734 # Number of store instructions -system.cpu0.num_idle_cycles 2203122575.338117 # Number of idle cycles -system.cpu0.num_busy_cycles 136291510.661883 # Number of busy cycles -system.cpu0.not_idle_fraction 0.058259 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.941741 # Percentage of idle cycles +system.cpu0.num_mem_refs 13393278 # number of memory refs +system.cpu0.num_load_insts 7407523 # Number of load instructions +system.cpu0.num_store_insts 5985755 # Number of store instructions +system.cpu0.num_idle_cycles 2203295398.340116 # Number of idle cycles +system.cpu0.num_busy_cycles 135307195.659884 # Number of busy cycles +system.cpu0.not_idle_fraction 0.057858 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.942142 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 46688 # number of quiesce instructions executed -system.cpu0.icache.replacements 408172 # number of replacements -system.cpu0.icache.tagsinuse 509.512645 # Cycle average of tags in use -system.cpu0.icache.total_refs 29030930 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 408684 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 71.035152 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 74928815000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 509.512645 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.995142 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.995142 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 29030930 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 29030930 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 29030930 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 29030930 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 29030930 # number of overall hits -system.cpu0.icache.overall_hits::total 29030930 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 408685 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 408685 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 408685 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 408685 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 408685 # number of overall misses -system.cpu0.icache.overall_misses::total 408685 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6059464500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6059464500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 6059464500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6059464500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 6059464500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6059464500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 29439615 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 29439615 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 29439615 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 29439615 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 29439615 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 29439615 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013882 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.013882 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013882 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.013882 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013882 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.013882 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14826.735750 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14826.735750 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14826.735750 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14826.735750 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14826.735750 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14826.735750 # average overall miss latency +system.cpu0.kern.inst.quiesce 46685 # number of quiesce instructions executed +system.cpu0.icache.replacements 408143 # number of replacements +system.cpu0.icache.tagsinuse 509.526052 # Cycle average of tags in use +system.cpu0.icache.total_refs 29030502 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 408655 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 71.039145 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 74905211000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 509.526052 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.995168 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.995168 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 29030502 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 29030502 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 29030502 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 29030502 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 29030502 # number of overall hits +system.cpu0.icache.overall_hits::total 29030502 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 408655 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 408655 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 408655 # 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number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 29439157 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 29439157 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 29439157 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 29439157 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013881 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.013881 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013881 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.013881 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013881 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.013881 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14596.725845 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14596.725845 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14596.725845 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14596.725845 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14596.725845 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14596.725845 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -645,122 +615,122 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # 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number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4832163500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4832163500 # number of overall MSHR miss cycles +system.cpu0.icache.writebacks::writebacks 20759 # number of writebacks +system.cpu0.icache.writebacks::total 20759 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 408655 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 408655 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 408655 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 408655 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 408655 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 408655 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4737808500 # 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average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11823.686947 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013881 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013881 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013881 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.013881 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013881 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.013881 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11593.663359 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11593.663359 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11593.663359 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11593.663359 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11593.663359 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11593.663359 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 335831 # number of replacements -system.cpu0.dcache.tagsinuse 404.122879 # Cycle average of tags in use -system.cpu0.dcache.total_refs 12265513 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 336343 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 36.467276 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 330129 # number of replacements +system.cpu0.dcache.tagsinuse 459.697251 # Cycle average of tags in use +system.cpu0.dcache.total_refs 12270461 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 330641 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 37.111130 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 663204000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 404.122879 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.789302 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.789302 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6596660 # 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miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.030342 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.030342 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15320.382890 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15320.382890 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35592.072418 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 35592.072418 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11039.558127 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11039.558127 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9145.766345 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9145.766345 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 23054.541807 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 23054.541807 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23054.541807 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 23054.541807 # average overall miss latency +system.cpu0.dcache.occ_blocks::cpu0.data 459.697251 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.897846 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.897846 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6600245 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6600245 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5350394 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5350394 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147923 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 147923 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149677 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 149677 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 11950639 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 11950639 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11950639 # number of overall hits +system.cpu0.dcache.overall_hits::total 11950639 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 227470 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 227470 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 141496 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 141496 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9302 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 9302 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7489 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7489 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 368966 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 368966 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 368966 # number of overall misses +system.cpu0.dcache.overall_misses::total 368966 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3341792500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 3341792500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4877331500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 4877331500 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 98417500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 98417500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 68140000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 68140000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 8219124000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 8219124000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 8219124000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 8219124000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6827715 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6827715 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5491890 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5491890 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157225 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 157225 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157166 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 157166 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12319605 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12319605 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12319605 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12319605 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033316 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.033316 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025765 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.025765 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059164 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059164 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047650 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047650 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029949 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.029949 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029949 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.029949 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14691.135095 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14691.135095 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34469.748261 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 34469.748261 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10580.251559 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10580.251559 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9098.678061 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9098.678061 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 22276.101321 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 22276.101321 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 22276.101321 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 22276.101321 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -769,62 +739,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 287163 # number of writebacks -system.cpu0.dcache.writebacks::total 287163 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 231189 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 231189 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 142616 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 142616 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9505 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9505 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7461 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7461 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 373805 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 373805 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 373805 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 373805 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2848236000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2848236000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4648049500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4648049500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 76416000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 76416000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 45881000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 45881000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7496285500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 7496285500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7496285500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 7496285500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 10423748000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 10423748000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 822757000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 822757000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11246505000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11246505000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033860 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033860 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025969 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025969 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.060456 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.060456 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047474 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047474 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030342 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.030342 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030342 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.030342 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12319.946018 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12319.946018 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32591.360717 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32591.360717 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8039.558127 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8039.558127 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6149.443774 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6149.443774 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20054.000080 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20054.000080 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20054.000080 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20054.000080 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 306018 # number of writebacks +system.cpu0.dcache.writebacks::total 306018 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 227470 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 227470 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141496 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 141496 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9302 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9302 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7484 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7484 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 368966 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 368966 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 368966 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 368966 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2659287000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2659287000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4452739000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4452739000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 70511500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 70511500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 45688000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 45688000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7112026000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 7112026000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7112026000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 7112026000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 10424499500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 10424499500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 822589000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 822589000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11247088500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11247088500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033316 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033316 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025765 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025765 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059164 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059164 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047618 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047618 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029949 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029949 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029949 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.029949 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11690.715259 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11690.715259 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31469.009725 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31469.009725 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7580.251559 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7580.251559 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6104.756815 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6104.756815 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19275.559266 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19275.559266 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19275.559266 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19275.559266 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -834,26 +804,26 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 8313009 # DTB read hits -system.cpu1.dtb.read_misses 3663 # DTB read misses -system.cpu1.dtb.write_hits 5829499 # DTB write hits -system.cpu1.dtb.write_misses 1439 # DTB write misses +system.cpu1.dtb.read_hits 8311514 # DTB read hits +system.cpu1.dtb.read_misses 3660 # DTB read misses +system.cpu1.dtb.write_hits 5828200 # DTB write hits +system.cpu1.dtb.write_misses 1442 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu1.dtb.flush_entries 1967 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 136 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 134 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 8316672 # DTB read accesses -system.cpu1.dtb.write_accesses 5830938 # DTB write accesses +system.cpu1.dtb.read_accesses 8315174 # DTB read accesses +system.cpu1.dtb.write_accesses 5829642 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 14142508 # DTB hits +system.cpu1.dtb.hits 14139714 # DTB hits system.cpu1.dtb.misses 5102 # DTB misses -system.cpu1.dtb.accesses 14147610 # DTB accesses -system.cpu1.itb.inst_hits 32286240 # ITB inst hits +system.cpu1.dtb.accesses 14144816 # DTB accesses +system.cpu1.itb.inst_hits 32283727 # ITB inst hits system.cpu1.itb.inst_misses 2171 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -870,79 +840,79 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 32288411 # ITB inst accesses -system.cpu1.itb.hits 32286240 # DTB hits +system.cpu1.itb.inst_accesses 32285898 # ITB inst accesses +system.cpu1.itb.hits 32283727 # DTB hits system.cpu1.itb.misses 2171 # DTB misses -system.cpu1.itb.accesses 32288411 # DTB accesses -system.cpu1.numCycles 2338003468 # number of cpu cycles simulated +system.cpu1.itb.accesses 32285898 # DTB accesses +system.cpu1.numCycles 2337184534 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 31682438 # Number of instructions committed -system.cpu1.committedOps 40196649 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 36868206 # Number of integer alu accesses +system.cpu1.committedInsts 31679948 # Number of instructions committed +system.cpu1.committedOps 40190899 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 36862651 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses -system.cpu1.num_func_calls 909270 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3487065 # number of instructions that are conditional controls -system.cpu1.num_int_insts 36868206 # number of integer instructions +system.cpu1.num_func_calls 962114 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3486829 # number of instructions that are conditional controls +system.cpu1.num_int_insts 36862651 # number of integer instructions system.cpu1.num_fp_insts 6793 # number of float instructions -system.cpu1.num_int_register_reads 210764243 # number of times the integer registers were read -system.cpu1.num_int_register_writes 38547083 # number of times the integer registers were written +system.cpu1.num_int_register_reads 210732518 # number of times the integer registers were read +system.cpu1.num_int_register_writes 38542658 # number of times the integer registers were written system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written -system.cpu1.num_mem_refs 14680299 # number of memory refs -system.cpu1.num_load_insts 8634860 # Number of load instructions -system.cpu1.num_store_insts 6045439 # Number of store instructions -system.cpu1.num_idle_cycles 1858954745.472398 # Number of idle cycles -system.cpu1.num_busy_cycles 479048722.527602 # Number of busy cycles -system.cpu1.not_idle_fraction 0.204896 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.795104 # Percentage of idle cycles +system.cpu1.num_mem_refs 14677413 # number of memory refs +system.cpu1.num_load_insts 8633313 # Number of load instructions +system.cpu1.num_store_insts 6044100 # Number of store instructions +system.cpu1.num_idle_cycles 1859139408.190032 # Number of idle cycles +system.cpu1.num_busy_cycles 478045125.809968 # Number of busy cycles +system.cpu1.not_idle_fraction 0.204539 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.795461 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 43911 # number of quiesce instructions executed -system.cpu1.icache.replacements 454317 # number of replacements -system.cpu1.icache.tagsinuse 478.423780 # Cycle average of tags in use -system.cpu1.icache.total_refs 31831407 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 454829 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 69.985438 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 91926225000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 478.423780 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.934421 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.934421 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 31831407 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 31831407 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 31831407 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 31831407 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 31831407 # number of overall hits -system.cpu1.icache.overall_hits::total 31831407 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 454829 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 454829 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 454829 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 454829 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 454829 # number of overall misses -system.cpu1.icache.overall_misses::total 454829 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6679957000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 6679957000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 6679957000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 6679957000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 6679957000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 6679957000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 32286236 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 32286236 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 32286236 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 32286236 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 32286236 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 32286236 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014087 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.014087 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014087 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.014087 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014087 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.014087 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14686.743809 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 14686.743809 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14686.743809 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 14686.743809 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14686.743809 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 14686.743809 # average overall miss latency +system.cpu1.kern.inst.quiesce 43902 # number of quiesce instructions executed +system.cpu1.icache.replacements 454250 # number of replacements +system.cpu1.icache.tagsinuse 478.426272 # Cycle average of tags in use +system.cpu1.icache.total_refs 31828961 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 454762 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 69.990371 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 91827158000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 478.426272 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.934426 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.934426 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 31828961 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 31828961 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 31828961 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 31828961 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 31828961 # number of overall hits +system.cpu1.icache.overall_hits::total 31828961 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 454762 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 454762 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 454762 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 454762 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 454762 # number of overall misses +system.cpu1.icache.overall_misses::total 454762 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6579254500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 6579254500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 6579254500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 6579254500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 6579254500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 6579254500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 32283723 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 32283723 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 32283723 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 32283723 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 32283723 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 32283723 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014086 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.014086 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014086 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.014086 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014086 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.014086 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14467.467598 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 14467.467598 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14467.467598 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 14467.467598 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14467.467598 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 14467.467598 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -951,122 +921,122 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 19149 # number of writebacks -system.cpu1.icache.writebacks::total 19149 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 454829 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 454829 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 454829 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 454829 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 454829 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 454829 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5314262500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5314262500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5314262500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5314262500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5314262500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5314262500 # number of overall MSHR miss cycles +system.cpu1.icache.writebacks::writebacks 23283 # number of writebacks +system.cpu1.icache.writebacks::total 23283 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 454762 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 454762 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 454762 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 454762 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 454762 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 454762 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5213754000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5213754000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5213754000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5213754000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5213754000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5213754000 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5250000 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5250000 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5250000 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 5250000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014087 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014087 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014087 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.014087 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014087 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.014087 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11684.088965 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11684.088965 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11684.088965 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11684.088965 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11684.088965 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11684.088965 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014086 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014086 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014086 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.014086 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014086 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.014086 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11464.796971 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11464.796971 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11464.796971 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11464.796971 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11464.796971 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11464.796971 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 294642 # number of replacements -system.cpu1.dcache.tagsinuse 457.752328 # Cycle average of tags in use -system.cpu1.dcache.total_refs 11964721 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 295088 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 40.546281 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 89831748000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 457.752328 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.894048 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.894048 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 6946891 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 6946891 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4828705 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4828705 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 81776 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 81776 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 83111 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 83111 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 11775596 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 11775596 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 11775596 # number of overall hits -system.cpu1.dcache.overall_hits::total 11775596 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 172105 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 172105 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 150416 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 150416 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11123 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 11123 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 9715 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 9715 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 322521 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 322521 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 322521 # number of overall misses -system.cpu1.dcache.overall_misses::total 322521 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2496186500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2496186500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5287724000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 5287724000 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 124574500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 124574500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 73632000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 73632000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 7783910500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 7783910500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 7783910500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 7783910500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 7118996 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 7118996 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 4979121 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 4979121 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 92899 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 92899 # 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miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119732 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.104658 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.104658 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026659 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.026659 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026659 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.026659 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14503.858110 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14503.858110 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 35153.999575 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 35153.999575 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11199.721298 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11199.721298 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7579.207411 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7579.207411 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24134.585035 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 24134.585035 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24134.585035 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 24134.585035 # average overall miss latency +system.cpu1.dcache.replacements 292077 # number of replacements +system.cpu1.dcache.tagsinuse 472.260521 # Cycle average of tags in use +system.cpu1.dcache.total_refs 11962886 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 292453 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 40.905328 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 83467733000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 472.260521 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.922384 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.922384 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 6946947 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 6946947 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4827784 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4827784 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 81815 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 81815 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 82770 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 82770 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 11774731 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 11774731 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 11774731 # number of overall hits +system.cpu1.dcache.overall_hits::total 11774731 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 170577 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 170577 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 150060 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 150060 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11061 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 11061 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10037 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10037 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 320637 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 320637 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 320637 # number of overall misses +system.cpu1.dcache.overall_misses::total 320637 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2293338000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2293338000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5119779000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 5119779000 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 102150000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 102150000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 75382000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 75382000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 7413117000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 7413117000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 7413117000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 7413117000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 7117524 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 7117524 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 4977844 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 4977844 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 92876 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 92876 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92807 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 92807 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 12095368 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 12095368 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 12095368 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 12095368 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023966 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.023966 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030146 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.030146 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119094 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119094 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108149 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108149 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026509 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.026509 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026509 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.026509 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13444.591006 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13444.591006 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34118.212715 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 34118.212715 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9235.150529 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9235.150529 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7510.411478 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7510.411478 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23119.967440 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 23119.967440 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23119.967440 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 23119.967440 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1075,62 +1045,66 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 254584 # number of writebacks -system.cpu1.dcache.writebacks::total 254584 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 172105 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 172105 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 150416 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 150416 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11123 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11123 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9710 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 9710 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 322521 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 322521 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 322521 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 322521 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1979754000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1979754000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4836439500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4836439500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 91205500 # 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mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.104604 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.104604 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026659 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026659 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026659 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026659 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11503.175387 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11503.175387 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32153.756914 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32153.756914 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8199.721298 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8199.721298 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4583.110196 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4583.110196 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 21134.107546 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 21134.107546 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21134.107546 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21134.107546 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 265856 # number of writebacks +system.cpu1.dcache.writebacks::total 265856 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170577 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 170577 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 150060 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 150060 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11061 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11061 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10033 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10033 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 320637 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 320637 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 320637 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 320637 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1781497000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1781497000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4669562000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4669562000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 68967000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 68967000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 45286000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 45286000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6451059000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 6451059000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6451059000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 6451059000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 136551200000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 136551200000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 39714194000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 39714194000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 176265394000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 176265394000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023966 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023966 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030146 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030146 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119094 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119094 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108106 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108106 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026509 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026509 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026509 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026509 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10443.946136 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10443.946136 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31117.966147 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31117.966147 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6235.150529 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6235.150529 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4513.704774 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4513.704774 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20119.508977 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20119.508977 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20119.508977 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20119.508977 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1152,10 +1126,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 550616164273 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 550616164273 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 550616164273 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 550616164273 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 550273882646 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 550273882646 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 550273882646 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 550273882646 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini index 6a942652a..d41ee2fc6 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini @@ -22,6 +22,7 @@ machine_type=RealView_PBX mem_mode=timing memories=system.physmem system.realview.nvmem midr_regval=890224640 +multi_proc=true num_work_ids=16 readfile=tests/halt.sh symbolfile= diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout index b6cf436ae..4f563f8f5 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 17:25:42 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 00:36:57 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2591419000000 because m5_exit instruction encountered +Exiting @ tick 2591087067000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 20ffbfc50..f1beadd55 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,54 +1,54 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.591419 # Number of seconds simulated -sim_ticks 2591419000000 # Number of ticks simulated -final_tick 2591419000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.591087 # Number of seconds simulated +sim_ticks 2591087067000 # Number of ticks simulated +final_tick 2591087067000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 555808 # Simulator instruction rate (inst/s) -host_op_rate 709857 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 24337050134 # Simulator tick rate (ticks/s) -host_mem_usage 383104 # Number of bytes of host memory used -host_seconds 106.48 # Real time elapsed on the host -sim_insts 59182652 # Number of instructions simulated -sim_ops 75585847 # Number of ops (including micro ops) simulated +host_inst_rate 814871 # Simulator instruction rate (inst/s) +host_op_rate 1040723 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 35675794467 # Simulator tick rate (ticks/s) +host_mem_usage 385812 # Number of bytes of host memory used +host_seconds 72.63 # Real time elapsed on the host +sim_insts 59182970 # Number of instructions simulated +sim_ops 75586355 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 1408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 955744 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9990864 # Number of bytes read from this memory -system.physmem.bytes_read::total 133632176 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 955744 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 955744 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6584000 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 706144 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9051344 # Number of bytes read from this memory +system.physmem.bytes_read::total 132441392 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 706144 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 706144 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3678592 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 9600072 # Number of bytes written to this memory +system.physmem.bytes_written::total 6694664 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 22 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 12 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 21136 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 156141 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15512735 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 102875 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 17236 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141461 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15494129 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57478 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 856893 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47342167 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 543 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 296 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 368811 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3855364 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51567182 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 368811 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 368811 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2540693 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1163869 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3704562 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2540693 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47342167 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 543 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 296 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 368811 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5019233 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 55271744 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_writes::total 811496 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47348232 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 124 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 74 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 272528 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3493261 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51114219 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 272528 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 272528 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1419710 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1164018 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2583728 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1419710 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47348232 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 124 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 74 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 272528 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4657279 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53697947 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -61,141 +61,141 @@ system.realview.nvmem.bw_inst_read::cpu.inst 8 system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 117210 # number of replacements -system.l2c.tagsinuse 24850.634634 # Cycle average of tags in use -system.l2c.total_refs 1536782 # Total number of references to valid blocks. -system.l2c.sampled_refs 146347 # Sample count of references to valid blocks. -system.l2c.avg_refs 10.500946 # Average number of references to valid blocks. -system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 14582.980264 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 6.964045 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.itb.walker 0.968003 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 5130.485110 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 5129.237211 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.222519 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.dtb.walker 0.000106 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.078285 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.078266 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.379191 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 8714 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 3541 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 839785 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 361146 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1213186 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 611793 # number of Writeback hits -system.l2c.Writeback_hits::total 611793 # number of Writeback hits +system.l2c.replacements 61946 # number of replacements +system.l2c.tagsinuse 50741.194054 # Cycle average of tags in use +system.l2c.total_refs 1730603 # Total number of references to valid blocks. +system.l2c.sampled_refs 127327 # Sample count of references to valid blocks. +system.l2c.avg_refs 13.591799 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2543210574000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 37737.574743 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 3.884961 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.itb.walker 0.001325 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 6978.831431 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 6020.901593 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.575830 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.inst 0.106489 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.091872 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.774249 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 8734 # 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number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 31207839500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 31207839500 # number of WriteReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131542089000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 131806929000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 31206790500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 31206790500 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu.inst 264840000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu.data 162752588500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 163017428500 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.002518 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.003377 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.016996 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.044928 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.025341 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.991025 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.991025 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.568473 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.568473 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.002518 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.003377 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.inst 0.016996 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.data 0.252085 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.115451 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.002518 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.003377 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.inst 0.016996 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.data 0.252085 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.115451 # mshr miss rate for overall accesses +system.l2c.overall_mshr_uncacheable_latency::cpu.data 162748879500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 163013719500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000572 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000844 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.012429 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.026113 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.016465 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.991013 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.991013 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.537953 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.537953 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000572 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000844 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.012429 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.228821 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.103014 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000572 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000844 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.012429 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.228821 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.103014 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40203.512397 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40113.602920 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40154.867958 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40054.684779 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40054.684779 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40071.298651 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40071.298651 # average ReadExReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40175.800377 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40066.524693 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40123.139245 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40057.202651 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40057.202651 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40140.366945 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40140.366945 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40203.512397 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40075.855073 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40086.598680 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40175.800377 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40135.277384 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40138.070359 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40203.512397 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40075.855073 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40086.598680 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40175.800377 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40135.277384 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40138.070359 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -307,9 +307,9 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 14995950 # DTB read hits -system.cpu.dtb.read_misses 7342 # DTB read misses -system.cpu.dtb.write_hits 11230967 # DTB write hits +system.cpu.dtb.read_hits 14996145 # DTB read hits +system.cpu.dtb.read_misses 7343 # DTB read misses +system.cpu.dtb.write_hits 11231074 # DTB write hits system.cpu.dtb.write_misses 2209 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -320,13 +320,13 @@ system.cpu.dtb.align_faults 0 # Nu system.cpu.dtb.prefetch_faults 184 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 15003292 # DTB read accesses -system.cpu.dtb.write_accesses 11233176 # DTB write accesses +system.cpu.dtb.read_accesses 15003488 # DTB read accesses +system.cpu.dtb.write_accesses 11233283 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 26226917 # DTB hits -system.cpu.dtb.misses 9551 # DTB misses -system.cpu.dtb.accesses 26236468 # DTB accesses -system.cpu.itb.inst_hits 60464458 # ITB inst hits +system.cpu.dtb.hits 26227219 # DTB hits +system.cpu.dtb.misses 9552 # DTB misses +system.cpu.dtb.accesses 26236771 # DTB accesses +system.cpu.itb.inst_hits 60464772 # ITB inst hits system.cpu.itb.inst_misses 4471 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -343,79 +343,79 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 60468929 # ITB inst accesses -system.cpu.itb.hits 60464458 # DTB hits +system.cpu.itb.inst_accesses 60469243 # ITB inst accesses +system.cpu.itb.hits 60464772 # DTB hits system.cpu.itb.misses 4471 # DTB misses -system.cpu.itb.accesses 60468929 # DTB accesses -system.cpu.numCycles 5182838000 # number of cpu cycles simulated +system.cpu.itb.accesses 60469243 # DTB accesses +system.cpu.numCycles 5182174134 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 59182652 # Number of instructions committed -system.cpu.committedOps 75585847 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 68355333 # Number of integer alu accesses +system.cpu.committedInsts 59182970 # Number of instructions committed +system.cpu.committedOps 75586355 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 68355817 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses -system.cpu.num_func_calls 1976025 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7653656 # number of instructions that are conditional controls -system.cpu.num_int_insts 68355333 # number of integer instructions +system.cpu.num_func_calls 2139775 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7653714 # number of instructions that are conditional controls +system.cpu.num_int_insts 68355817 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions -system.cpu.num_int_register_reads 391421263 # number of times the integer registers were read -system.cpu.num_int_register_writes 73137347 # number of times the integer registers were written +system.cpu.num_int_register_reads 391424329 # number of times the integer registers were read +system.cpu.num_int_register_writes 73137723 # number of times the integer registers were written system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written -system.cpu.num_mem_refs 27394170 # number of memory refs -system.cpu.num_load_insts 15659823 # Number of load instructions -system.cpu.num_store_insts 11734347 # Number of store instructions -system.cpu.num_idle_cycles 4573988502.570235 # Number of idle cycles -system.cpu.num_busy_cycles 608849497.429765 # Number of busy cycles -system.cpu.not_idle_fraction 0.117474 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.882526 # Percentage of idle cycles +system.cpu.num_mem_refs 27394520 # number of memory refs +system.cpu.num_load_insts 15660068 # Number of load instructions +system.cpu.num_store_insts 11734452 # Number of store instructions +system.cpu.num_idle_cycles 4574883884.570234 # Number of idle cycles +system.cpu.num_busy_cycles 607290249.429766 # Number of busy cycles +system.cpu.not_idle_fraction 0.117188 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.882812 # 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number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 14788772000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 14788772000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14788772000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13564382 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13564382 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10223756 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10223756 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247702 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 247702 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247701 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247701 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 23788138 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 23788138 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 23788138 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 23788138 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027177 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.027177 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024503 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.024503 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045950 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045950 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.026028 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.026028 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.026028 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.026028 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15056.020627 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15056.020627 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36878.347631 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 36878.347631 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14580.258303 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14580.258303 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23885.450146 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23885.450146 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23885.450146 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23885.450146 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -540,54 +540,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 566088 # number of writebacks -system.cpu.dcache.writebacks::total 566088 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368647 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 368647 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250483 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 250483 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11373 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 11373 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 619130 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 619130 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 619130 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 619130 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4730079000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4730079000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8794683000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8794683000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 151180500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 151180500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13524762000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13524762000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13524762000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13524762000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 146938040000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 146938040000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 40368528500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 40368528500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 187306568500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 187306568500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027178 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027178 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024500 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024500 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.045914 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.045914 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026027 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.026027 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026027 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.026027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12830.916839 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12830.916839 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35110.897746 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35110.897746 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13292.930625 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13292.930625 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21844.785425 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 21844.785425 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21844.785425 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 21844.785425 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 595911 # number of writebacks +system.cpu.dcache.writebacks::total 595911 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368641 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 368641 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250513 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 250513 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11382 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 11382 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 619154 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 619154 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 619154 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 619154 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4444216000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4444216000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8486921500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8486921500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 131806500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 131806500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12931137500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12931137500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12931137500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12931137500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 146935431000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 146935431000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 40367480000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 40367480000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 187302911000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 187302911000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027177 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027177 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024503 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024503 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.045950 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.045950 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026028 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.026028 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026028 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.026028 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12055.674762 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12055.674762 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33878.167999 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33878.167999 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11580.258303 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11580.258303 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20885.171541 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20885.171541 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20885.171541 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20885.171541 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -609,10 +609,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1342278175263 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1342278175263 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1342278175263 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1342278175263 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1341944663355 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1341944663355 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1341944663355 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1341944663355 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout index 0d2987eae..18f4bf90b 100755 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout @@ -1,13 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 13:44:28 -gem5 started Jun 4 2012 15:04:41 +gem5 compiled Jun 28 2012 22:08:09 +gem5 started Jun 28 2012 23:02:50 gem5 executing on zizzer -command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic +command line: build/X86/gem5.fast -d build/X86/tests/fast/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86/tests/fast/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic warning: add_child('terminal'): child 'terminal' already has parent Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 - 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 5112043255000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index 82168f91d..1886c90bb 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -4,145 +4,145 @@ sim_seconds 5.112043 # Nu sim_ticks 5112043255000 # Number of ticks simulated final_tick 5112043255000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1304311 # Simulator instruction rate (inst/s) -host_op_rate 2670670 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 33369516688 # Simulator tick rate (ticks/s) -host_mem_usage 357276 # Number of bytes of host memory used -host_seconds 153.20 # Real time elapsed on the host -sim_insts 199813913 # Number of instructions simulated -sim_ops 409133277 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2786624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 1024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 972736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 11807616 # Number of bytes read from this memory -system.physmem.bytes_read::total 15568704 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 972736 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 972736 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 12232896 # Number of bytes written to this memory -system.physmem.bytes_written::total 12232896 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 43541 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 16 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 11 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 15199 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 184494 # Number of read requests responded to by this memory -system.physmem.num_reads::total 243261 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 191139 # Number of write requests responded to by this memory -system.physmem.num_writes::total 191139 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 545110 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 200 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 138 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 190283 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2309764 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3045495 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 190283 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 190283 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2392956 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2392956 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2392956 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 545110 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 200 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 138 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 190283 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2309764 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 5438452 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 164044 # number of replacements -system.l2c.tagsinuse 36842.944085 # Cycle average of tags in use -system.l2c.total_refs 3332458 # Total number of references to valid blocks. -system.l2c.sampled_refs 196390 # Sample count of references to valid blocks. -system.l2c.avg_refs 16.968573 # Average number of references to valid blocks. +host_inst_rate 1996585 # Simulator instruction rate (inst/s) +host_op_rate 4088150 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 51080652430 # Simulator tick rate (ticks/s) +host_mem_usage 357308 # Number of bytes of host memory used +host_seconds 100.08 # Real time elapsed on the host +sim_insts 199813912 # Number of instructions simulated +sim_ops 409133288 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2464768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 853824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10600192 # Number of bytes read from this memory +system.physmem.bytes_read::total 13919232 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 853824 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 853824 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9292800 # Number of bytes written to this memory +system.physmem.bytes_written::total 9292800 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 38512 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 13341 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 165628 # Number of read requests responded to by this memory +system.physmem.num_reads::total 217488 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 145200 # Number of write requests responded to by this memory +system.physmem.num_writes::total 145200 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 482149 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 25 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 167022 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2073572 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2722831 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 167022 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 167022 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1817825 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1817825 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1817825 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 482149 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 25 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 167022 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2073572 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4540656 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 106561 # number of replacements +system.l2c.tagsinuse 64822.143270 # Cycle average of tags in use +system.l2c.total_refs 3457342 # Total number of references to valid blocks. +system.l2c.sampled_refs 170680 # Sample count of references to valid blocks. +system.l2c.avg_refs 20.256281 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 27139.322665 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 2.054559 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.itb.walker 0.003581 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 1828.819855 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 7872.743425 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.414113 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.dtb.walker 0.000031 # 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number of overall misses -system.l2c.overall_misses::cpu.data 185411 # number of overall misses -system.l2c.overall_misses::total 200638 # number of overall misses -system.l2c.ReadReq_accesses::cpu.dtb.walker 6745 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.itb.walker 2820 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.inst 791301 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 1307588 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2108454 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 1529403 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1529403 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu.data 1823 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 1823 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu.data 313587 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 313587 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu.dtb.walker 6745 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.itb.walker 2820 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.inst 791301 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 1621175 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2422041 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu.dtb.walker 6745 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.itb.walker 2820 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.inst 791301 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 1621175 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2422041 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.002372 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.003901 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.019209 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.031181 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.026559 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu.data 0.982995 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.982995 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.461240 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.461240 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.dtb.walker 0.002372 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.itb.walker 0.003901 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.inst 0.019209 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.114368 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.082838 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.dtb.walker 0.002372 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.itb.walker 0.003901 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.inst 0.019209 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.114368 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.082838 # miss rate for overall accesses +system.l2c.occ_blocks::writebacks 51981.461992 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 0.004954 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.itb.walker 0.132110 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 2434.983597 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 10405.560616 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.793174 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.inst 0.037155 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.158776 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.989107 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 6578 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.itb.walker 2700 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.inst 777957 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 1275395 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2062630 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 1538939 # number of Writeback hits +system.l2c.Writeback_hits::total 1538939 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 28 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu.data 179208 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 179208 # number of ReadExReq hits +system.l2c.demand_hits::cpu.dtb.walker 6578 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.itb.walker 2700 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.inst 777957 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 1454603 # number of demand (read+write) hits +system.l2c.demand_hits::total 2241838 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.dtb.walker 6578 # number of overall hits +system.l2c.overall_hits::cpu.itb.walker 2700 # number of overall hits +system.l2c.overall_hits::cpu.inst 777957 # number of overall hits +system.l2c.overall_hits::cpu.data 1454603 # number of overall hits +system.l2c.overall_hits::total 2241838 # number of overall hits +system.l2c.ReadReq_misses::cpu.dtb.walker 2 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.inst 13342 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 32184 # number of ReadReq misses +system.l2c.ReadReq_misses::total 45533 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu.data 1796 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 1796 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu.data 134377 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 134377 # number of ReadExReq misses +system.l2c.demand_misses::cpu.dtb.walker 2 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.inst 13342 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 166561 # number of demand (read+write) misses +system.l2c.demand_misses::total 179910 # number of demand (read+write) misses +system.l2c.overall_misses::cpu.dtb.walker 2 # number of overall misses +system.l2c.overall_misses::cpu.itb.walker 5 # number of overall misses +system.l2c.overall_misses::cpu.inst 13342 # number of overall misses +system.l2c.overall_misses::cpu.data 166561 # number of overall misses +system.l2c.overall_misses::total 179910 # number of overall misses +system.l2c.ReadReq_accesses::cpu.dtb.walker 6580 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.itb.walker 2705 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.inst 791299 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 1307579 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2108163 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 1538939 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 1538939 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu.data 1824 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 1824 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu.data 313585 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 313585 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu.dtb.walker 6580 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.itb.walker 2705 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.inst 791299 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 1621164 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2421748 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu.dtb.walker 6580 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.itb.walker 2705 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.inst 791299 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.data 1621164 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2421748 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000304 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001848 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.inst 0.016861 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.024613 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.021598 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu.data 0.984649 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.984649 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu.data 0.428519 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.428519 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu.dtb.walker 0.000304 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.itb.walker 0.001848 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.inst 0.016861 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.102742 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.074289 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.dtb.walker 0.000304 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.itb.walker 0.001848 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.inst 0.016861 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.102742 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.074289 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -151,8 +151,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 144472 # number of writebacks -system.l2c.writebacks::total 144472 # number of writebacks +system.l2c.writebacks::writebacks 98533 # number of writebacks +system.l2c.writebacks::total 98533 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 47570 # number of replacements system.iocache.tagsinuse 0.042409 # Cycle average of tags in use @@ -213,32 +213,32 @@ system.pc.south_bridge.ide.disks1.dma_write_txs 1 system.cpu.numCycles 10224086531 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 199813913 # Number of instructions committed -system.cpu.committedOps 409133277 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 374297244 # Number of integer alu accesses +system.cpu.committedInsts 199813912 # Number of instructions committed +system.cpu.committedOps 409133288 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 374297254 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 39954968 # number of instructions that are conditional controls -system.cpu.num_int_insts 374297244 # number of integer instructions +system.cpu.num_conditional_control_insts 39954972 # number of instructions that are conditional controls +system.cpu.num_int_insts 374297254 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 1159028861 # number of times the integer registers were read -system.cpu.num_int_register_writes 636431619 # number of times the integer registers were written +system.cpu.num_int_register_reads 1159028950 # number of times the integer registers were read +system.cpu.num_int_register_writes 636431660 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 35626519 # number of memory refs -system.cpu.num_load_insts 27217784 # Number of load instructions +system.cpu.num_mem_refs 35626517 # number of memory refs +system.cpu.num_load_insts 27217782 # Number of load instructions system.cpu.num_store_insts 8408735 # Number of store instructions -system.cpu.num_idle_cycles 9770605338.086651 # Number of idle cycles -system.cpu.num_busy_cycles 453481192.913350 # Number of busy cycles +system.cpu.num_idle_cycles 9770605328.086651 # Number of idle cycles +system.cpu.num_busy_cycles 453481202.913350 # Number of busy cycles system.cpu.not_idle_fraction 0.044354 # Percentage of non-idle cycles system.cpu.idle_fraction 0.955646 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.icache.replacements 790795 # number of replacements +system.cpu.icache.replacements 790793 # number of replacements system.cpu.icache.tagsinuse 510.627676 # Cycle average of tags in use system.cpu.icache.total_refs 243365777 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 791307 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 307.549127 # Average number of references to valid blocks. +system.cpu.icache.sampled_refs 791305 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 307.549904 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 148763105500 # Cycle when the warmup percentage was hit. system.cpu.icache.occ_blocks::cpu.inst 510.627676 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.997320 # Average percentage of cache occupancy @@ -249,18 +249,18 @@ system.cpu.icache.demand_hits::cpu.inst 243365777 # nu system.cpu.icache.demand_hits::total 243365777 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 243365777 # number of overall hits system.cpu.icache.overall_hits::total 243365777 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 791314 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 791314 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 791314 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 791314 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 791314 # number of overall misses -system.cpu.icache.overall_misses::total 791314 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 244157091 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 244157091 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 244157091 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 244157091 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 244157091 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 244157091 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_misses::cpu.inst 791312 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 791312 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 791312 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 791312 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 791312 # number of overall misses +system.cpu.icache.overall_misses::total 791312 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 244157089 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 244157089 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 244157089 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 244157089 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 244157089 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 244157089 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003241 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.003241 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.003241 # miss rate for demand accesses @@ -278,29 +278,29 @@ system.cpu.icache.cache_copies 0 # nu system.cpu.icache.writebacks::writebacks 809 # number of writebacks system.cpu.icache.writebacks::total 809 # number of writebacks system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 3435 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 3.021701 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 7940 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 3444 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 2.305459 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5105275407500 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.021701 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.188856 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.188856 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7947 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 7947 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 3335 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 3.026444 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 8029 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 3346 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 2.399582 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5102048603500 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.026444 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.189153 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.189153 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 8031 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 8031 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7949 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 7949 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7949 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 7949 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4278 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 4278 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4278 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 4278 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4278 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 4278 # number of overall misses +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 8033 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 8033 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 8033 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 8033 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4194 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 4194 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4194 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 4194 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4194 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 4194 # number of overall misses system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12225 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.ReadReq_accesses::total 12225 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) @@ -309,12 +309,12 @@ system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12227 system.cpu.itb_walker_cache.demand_accesses::total 12227 # number of demand (read+write) accesses system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12227 # number of overall (read+write) accesses system.cpu.itb_walker_cache.overall_accesses::total 12227 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.349939 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.349939 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.349881 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.349881 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.349881 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.349881 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.343067 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.343067 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.343011 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.343011 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.343011 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.343011 # miss rate for overall accesses system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -323,42 +323,42 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 518 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 518 # number of writebacks +system.cpu.itb_walker_cache.writebacks::writebacks 593 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 593 # number of writebacks system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 7755 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 5.010998 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 12854 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 7767 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.654950 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5101232849000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.010998 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.313187 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.313187 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12875 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 12875 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12875 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 12875 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12875 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 12875 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8933 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 8933 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8933 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 8933 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8933 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 8933 # number of overall misses +system.cpu.dtb_walker_cache.replacements 7598 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 5.013733 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 13014 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 7612 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.709669 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5101231664000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.013733 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.313358 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.313358 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13016 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 13016 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13016 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 13016 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13016 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 13016 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8792 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 8792 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8792 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 8792 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8792 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 8792 # number of overall misses system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21808 # number of ReadReq accesses(hits+misses) system.cpu.dtb_walker_cache.ReadReq_accesses::total 21808 # number of ReadReq accesses(hits+misses) system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21808 # number of demand (read+write) accesses system.cpu.dtb_walker_cache.demand_accesses::total 21808 # number of demand (read+write) accesses system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21808 # number of overall (read+write) accesses system.cpu.dtb_walker_cache.overall_accesses::total 21808 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.409620 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.409620 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.409620 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.409620 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.409620 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.409620 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.403155 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.403155 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.403155 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.403155 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.403155 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.403155 # miss rate for overall accesses system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -367,42 +367,42 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 2517 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 2517 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::writebacks 2556 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 2556 # number of writebacks system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1621277 # number of replacements -system.cpu.dcache.tagsinuse 511.999417 # Cycle average of tags in use -system.cpu.dcache.total_refs 20142220 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1621789 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.419754 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1621273 # number of replacements +system.cpu.dcache.tagsinuse 511.999456 # Cycle average of tags in use +system.cpu.dcache.total_refs 20142222 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1621785 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12.419786 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.999417 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 511.999456 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999999 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 12057024 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 12057024 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8082938 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8082938 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 20139962 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20139962 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20139962 # number of overall hits -system.cpu.dcache.overall_hits::total 20139962 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1308207 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1308207 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 315850 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 315850 # number of WriteReq misses +system.cpu.dcache.WriteReq_hits::cpu.data 8082936 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8082936 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 20139960 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20139960 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20139960 # number of overall hits +system.cpu.dcache.overall_hits::total 20139960 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1308205 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1308205 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 315852 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 315852 # number of WriteReq misses system.cpu.dcache.demand_misses::cpu.data 1624057 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 1624057 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1624057 # number of overall misses system.cpu.dcache.overall_misses::total 1624057 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 13365231 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13365231 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 13365229 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13365229 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 8398788 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 8398788 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21764019 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21764019 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21764019 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21764019 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 21764017 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21764017 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21764017 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21764017 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097881 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.097881 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037607 # miss rate for WriteReq accesses @@ -419,8 +419,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1525559 # number of writebacks -system.cpu.dcache.writebacks::total 1525559 # number of writebacks +system.cpu.dcache.writebacks::writebacks 1534981 # number of writebacks +system.cpu.dcache.writebacks::total 1534981 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout index d30404a01..d9a666d01 100755 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout @@ -1,13 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 13:44:28 -gem5 started Jun 4 2012 15:05:12 +gem5 compiled Jun 28 2012 22:08:09 +gem5 started Jun 28 2012 23:04:41 gem5 executing on zizzer -command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing +command line: build/X86/gem5.fast -d build/X86/tests/fast/quick/fs/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86/tests/fast/quick/fs/10.linux-boot/x86/linux/pc-simple-timing warning: add_child('terminal'): child 'terminal' already has parent Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 - 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5195470393000 because m5_exit instruction encountered +Exiting @ tick 5187414160000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index 9cc951eb3..78491477d 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -1,186 +1,168 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.195470 # Number of seconds simulated -sim_ticks 5195470393000 # Number of ticks simulated -final_tick 5195470393000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.187414 # Number of seconds simulated +sim_ticks 5187414160000 # Number of ticks simulated +final_tick 5187414160000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 792632 # Simulator instruction rate (inst/s) -host_op_rate 1521406 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 29811367673 # Simulator tick rate (ticks/s) -host_mem_usage 354100 # Number of bytes of host memory used -host_seconds 174.28 # Real time elapsed on the host -sim_insts 138138472 # Number of instructions simulated -sim_ops 265147881 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2876352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 974400 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9911872 # Number of bytes read from this memory -system.physmem.bytes_read::total 13764096 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 974400 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 974400 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 10427072 # Number of bytes written to this memory -system.physmem.bytes_written::total 10427072 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 44943 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 13 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 10 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 15225 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 154873 # Number of read requests responded to by this memory -system.physmem.num_reads::total 215064 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 162923 # Number of write requests responded to by this memory -system.physmem.num_writes::total 162923 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 553627 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 160 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 123 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 187548 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1907791 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2649249 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 187548 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 187548 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2006954 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2006954 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2006954 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 553627 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 123 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 187548 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1907791 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4656204 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 136133 # number of replacements -system.l2c.tagsinuse 31389.895470 # Cycle average of tags in use -system.l2c.total_refs 3363370 # Total number of references to valid blocks. -system.l2c.sampled_refs 168244 # Sample count of references to valid blocks. -system.l2c.avg_refs 19.991025 # Average number of references to valid blocks. +host_inst_rate 1218225 # Simulator instruction rate (inst/s) +host_op_rate 2338274 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45751964384 # Simulator tick rate (ticks/s) +host_mem_usage 354108 # Number of bytes of host memory used +host_seconds 113.38 # Real time elapsed on the host +sim_insts 138123832 # Number of instructions simulated +sim_ops 265116381 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2873600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 823872 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9013056 # Number of bytes read from this memory +system.physmem.bytes_read::total 12710848 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 823872 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 823872 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8119168 # Number of bytes written to this memory +system.physmem.bytes_written::total 8119168 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 44900 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12873 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 140829 # Number of read requests responded to by this memory +system.physmem.num_reads::total 198607 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 126862 # Number of write requests responded to by this memory +system.physmem.num_writes::total 126862 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 553956 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 158821 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1737485 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2450324 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 158821 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 158821 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1565167 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1565167 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1565167 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 553956 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 158821 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1737485 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4015491 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 87121 # number of replacements +system.l2c.tagsinuse 64744.373482 # Cycle average of tags in use +system.l2c.total_refs 3489902 # Total number of references to valid blocks. +system.l2c.sampled_refs 151833 # Sample count of references to valid blocks. +system.l2c.avg_refs 22.985135 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 23478.740830 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 0.248367 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.itb.walker 0.010497 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 1900.597036 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 6010.298740 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.358257 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.dtb.walker 0.000004 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.029001 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.091710 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.478972 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 6528 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 3033 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 773419 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 1274463 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2057443 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 1534567 # number of Writeback hits -system.l2c.Writeback_hits::total 1534567 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu.data 320 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 320 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 192958 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 192958 # number of ReadExReq hits -system.l2c.demand_hits::cpu.dtb.walker 6528 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.itb.walker 3033 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.inst 773419 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 1467421 # number of demand (read+write) hits -system.l2c.demand_hits::total 2250401 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.dtb.walker 6528 # number of overall hits -system.l2c.overall_hits::cpu.itb.walker 3033 # number of overall hits -system.l2c.overall_hits::cpu.inst 773419 # number of overall hits -system.l2c.overall_hits::cpu.data 1467421 # number of overall hits -system.l2c.overall_hits::total 2250401 # number of overall hits -system.l2c.ReadReq_misses::cpu.dtb.walker 13 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.itb.walker 10 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.inst 15226 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 35581 # number of ReadReq misses -system.l2c.ReadReq_misses::total 50830 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 1369 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1369 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 120168 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 120168 # number of ReadExReq misses -system.l2c.demand_misses::cpu.dtb.walker 13 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.itb.walker 10 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.inst 15226 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 155749 # number of demand (read+write) misses -system.l2c.demand_misses::total 170998 # number of demand (read+write) misses -system.l2c.overall_misses::cpu.dtb.walker 13 # number of overall misses -system.l2c.overall_misses::cpu.itb.walker 10 # number of overall misses -system.l2c.overall_misses::cpu.inst 15226 # number of overall misses -system.l2c.overall_misses::cpu.data 155749 # number of overall misses -system.l2c.overall_misses::total 170998 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu.dtb.walker 676000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.itb.walker 520000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.inst 791868000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.data 1863058500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 2656122500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu.data 33778000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 33778000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu.data 6249324500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6249324500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu.dtb.walker 676000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.itb.walker 520000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.inst 791868000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.data 8112383000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 8905447000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu.dtb.walker 676000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.itb.walker 520000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.inst 791868000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.data 8112383000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 8905447000 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu.dtb.walker 6541 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.itb.walker 3043 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.inst 788645 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 1310044 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2108273 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 1534567 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1534567 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu.data 1689 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 1689 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu.data 313126 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 313126 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu.dtb.walker 6541 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.itb.walker 3043 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.inst 788645 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 1623170 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2421399 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu.dtb.walker 6541 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.itb.walker 3043 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.inst 788645 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 1623170 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2421399 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.001987 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.003286 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.019307 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.027160 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.024110 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu.data 0.810539 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.810539 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.383769 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.383769 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.dtb.walker 0.001987 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.itb.walker 0.003286 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.inst 0.019307 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.095954 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.070620 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.dtb.walker 0.001987 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.itb.walker 0.003286 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.inst 0.019307 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.095954 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.070620 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52000 # average ReadReq miss latency +system.l2c.occ_blocks::writebacks 50159.542434 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.itb.walker 0.140418 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 3477.361346 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 11107.329284 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.765374 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.inst 0.053060 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.169484 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.987921 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 6932 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.itb.walker 2996 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.inst 775163 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 1280771 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2065862 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 1543668 # number of Writeback hits +system.l2c.Writeback_hits::total 1543668 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu.data 305 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 305 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu.data 199243 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 199243 # number of ReadExReq hits +system.l2c.demand_hits::cpu.dtb.walker 6932 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.itb.walker 2996 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.inst 775163 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 1480014 # number of demand (read+write) hits +system.l2c.demand_hits::total 2265105 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.dtb.walker 6932 # number of overall hits +system.l2c.overall_hits::cpu.itb.walker 2996 # number of overall hits +system.l2c.overall_hits::cpu.inst 775163 # number of overall hits +system.l2c.overall_hits::cpu.data 1480014 # number of overall hits +system.l2c.overall_hits::total 2265105 # number of overall hits +system.l2c.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.inst 12874 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 28308 # number of ReadReq misses +system.l2c.ReadReq_misses::total 41187 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu.data 1396 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 1396 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu.data 113412 # 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average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40087.626699 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -280,39 +250,39 @@ system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 47510 # number of replacements -system.iocache.tagsinuse 0.120586 # Cycle average of tags in use +system.iocache.replacements 47504 # number of replacements +system.iocache.tagsinuse 0.096008 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47526 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47520 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 5048756072000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.120586 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.007537 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.007537 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 844 # number of ReadReq misses -system.iocache.ReadReq_misses::total 844 # number of ReadReq misses +system.iocache.warmup_cycle 5048726357000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::pc.south_bridge.ide 0.096008 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.006001 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.006001 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 839 # number of ReadReq misses +system.iocache.ReadReq_misses::total 839 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47564 # number of demand (read+write) misses -system.iocache.demand_misses::total 47564 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47564 # number of overall misses -system.iocache.overall_misses::total 47564 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 106575932 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 106575932 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 6391379160 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 6391379160 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 6497955092 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 6497955092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 6497955092 # number of overall miss cycles -system.iocache.overall_miss_latency::total 6497955092 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 844 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 844 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47559 # number of demand (read+write) misses +system.iocache.demand_misses::total 47559 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47559 # number of overall misses +system.iocache.overall_misses::total 47559 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 105990932 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 105990932 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 6391870160 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 6391870160 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 6497861092 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 6497861092 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 6497861092 # number of overall miss cycles +system.iocache.overall_miss_latency::total 6497861092 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 839 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 839 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47564 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47564 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47564 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47564 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47559 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47559 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47559 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47559 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -321,40 +291,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 126274.800948 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 126274.800948 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 136801.779966 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 136801.779966 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 136614.983853 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 136614.983853 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 136614.983853 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 136614.983853 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 69564644 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 126330.073897 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 126330.073897 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 136812.289384 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 136812.289384 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 136627.370046 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 136627.370046 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 136627.370046 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 136627.370046 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 69487644 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 11299 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 11303 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6156.708027 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6147.716889 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 46668 # number of writebacks -system.iocache.writebacks::total 46668 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 844 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 844 # number of ReadReq MSHR misses +system.iocache.writebacks::writebacks 46667 # number of writebacks +system.iocache.writebacks::total 46667 # number of writebacks +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 839 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 839 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47564 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47564 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47564 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47564 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 62666978 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 62666978 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 3961676998 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 3961676998 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4024343976 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 4024343976 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4024343976 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 4024343976 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47559 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47559 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47559 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47559 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 62341978 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 62341978 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 3962173996 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 3962173996 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4024515974 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 4024515974 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4024515974 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 4024515974 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -363,14 +333,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 74249.973934 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 74249.973934 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 84796.168622 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 84796.168622 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 84609.031536 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 84609.031536 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 84609.031536 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 84609.031536 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 74305.098927 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 74305.098927 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 84806.806421 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 84806.806421 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 84621.543220 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 84621.543220 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 84621.543220 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 84621.543220 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -384,75 +354,75 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 10390940786 # number of cpu cycles simulated +system.cpu.numCycles 10374828320 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 138138472 # Number of instructions committed -system.cpu.committedOps 265147881 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 249556386 # Number of integer alu accesses +system.cpu.committedInsts 138123832 # Number of instructions committed +system.cpu.committedOps 265116381 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 249524959 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 24882695 # number of instructions that are conditional controls -system.cpu.num_int_insts 249556386 # number of integer instructions +system.cpu.num_conditional_control_insts 24879442 # number of instructions that are conditional controls +system.cpu.num_int_insts 249524959 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 778086007 # number of times the integer registers were read -system.cpu.num_int_register_writes 422921187 # number of times the integer registers were written +system.cpu.num_int_register_reads 777989618 # number of times the integer registers were read +system.cpu.num_int_register_writes 422868687 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 23169904 # number of memory refs -system.cpu.num_load_insts 14812525 # Number of load instructions -system.cpu.num_store_insts 8357379 # Number of store instructions -system.cpu.num_idle_cycles 9787777240.878117 # Number of idle cycles -system.cpu.num_busy_cycles 603163545.121884 # Number of busy cycles -system.cpu.not_idle_fraction 0.058047 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.941953 # Percentage of idle cycles +system.cpu.num_mem_refs 23163323 # number of memory refs +system.cpu.num_load_insts 14806608 # Number of load instructions +system.cpu.num_store_insts 8356715 # Number of store instructions +system.cpu.num_idle_cycles 9773126970.350117 # Number of idle cycles +system.cpu.num_busy_cycles 601701349.649884 # Number of busy cycles +system.cpu.not_idle_fraction 0.057996 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.942004 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.icache.replacements 788139 # number of replacements -system.cpu.icache.tagsinuse 510.361283 # Cycle average of tags in use -system.cpu.icache.total_refs 158433932 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 788651 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 200.892324 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 160047116000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.361283 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996799 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996799 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 158433932 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 158433932 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 158433932 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 158433932 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 158433932 # number of overall hits -system.cpu.icache.overall_hits::total 158433932 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 788658 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 788658 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 788658 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 788658 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 788658 # number of overall misses -system.cpu.icache.overall_misses::total 788658 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11681762500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11681762500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11681762500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11681762500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11681762500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11681762500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 159222590 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 159222590 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 159222590 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 159222590 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 159222590 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 159222590 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.004953 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.004953 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.004953 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.004953 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.004953 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.004953 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14812.203135 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14812.203135 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14812.203135 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14812.203135 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14812.203135 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14812.203135 # average overall miss latency +system.cpu.icache.replacements 787531 # number of replacements +system.cpu.icache.tagsinuse 510.360069 # Cycle average of tags in use +system.cpu.icache.total_refs 158416168 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 788043 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 201.024777 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 159962400000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.360069 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.996797 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.996797 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 158416168 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 158416168 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 158416168 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 158416168 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 158416168 # number of overall hits +system.cpu.icache.overall_hits::total 158416168 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 788050 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 788050 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 788050 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 788050 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 788050 # number of overall misses +system.cpu.icache.overall_misses::total 788050 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11574503000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11574503000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11574503000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11574503000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11574503000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11574503000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 159204218 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 159204218 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 159204218 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 159204218 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 159204218 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 159204218 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.004950 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.004950 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.004950 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.004950 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.004950 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.004950 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14687.523634 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14687.523634 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14687.523634 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14687.523634 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14687.523634 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14687.523634 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -461,82 +431,82 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 805 # number of writebacks -system.cpu.icache.writebacks::total 805 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 788658 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 788658 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 788658 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 788658 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 788658 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 788658 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9314744000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9314744000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9314744000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9314744000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9314744000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9314744000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.004953 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.004953 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.004953 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.004953 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.004953 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.004953 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11810.878733 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11810.878733 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11810.878733 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11810.878733 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11810.878733 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11810.878733 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 1027 # number of writebacks +system.cpu.icache.writebacks::total 1027 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 788050 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 788050 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 788050 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 788050 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 788050 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 788050 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9209308000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9209308000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9209308000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9209308000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9209308000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9209308000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.004950 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.004950 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.004950 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.004950 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.004950 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.004950 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11686.197576 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11686.197576 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11686.197576 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11686.197576 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11686.197576 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11686.197576 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 3754 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 3.070606 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 7549 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 3765 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 2.005046 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5178573163000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.070606 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.191913 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.191913 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7619 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 7619 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 3928 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 3.062395 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 7428 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 3940 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 1.885279 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5163621004000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.062395 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.191400 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.191400 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7428 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 7428 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7621 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 7621 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7621 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 7621 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4602 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 4602 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4602 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 4602 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4602 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 4602 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 50817000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 50817000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 50817000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 50817000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 50817000 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 50817000 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12221 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 12221 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7430 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 7430 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7430 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 7430 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4796 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 4796 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4796 # 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number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 12224 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12223 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 12223 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12223 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 12223 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.376565 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.376565 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.376503 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.376503 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.376503 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.376503 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11042.372881 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11042.372881 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11042.372881 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11042.372881 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11042.372881 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11042.372881 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12226 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 12226 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12226 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 12226 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.392343 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.392343 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.392279 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.392279 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.392279 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.392279 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10675.354462 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10675.354462 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10675.354462 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10675.354462 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10675.354462 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10675.354462 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -545,78 +515,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 826 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 826 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4602 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4602 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4602 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 4602 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4602 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 4602 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 37011000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 37011000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 37011000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 37011000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 37011000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 37011000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.376565 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.376565 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.376503 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.376503 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.376503 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.376503 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8042.372881 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8042.372881 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8042.372881 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8042.372881 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8042.372881 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8042.372881 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 763 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 763 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4796 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4796 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4796 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 4796 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4796 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 4796 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 36811000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 36811000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 36811000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 36811000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 36811000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 36811000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.392343 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.392343 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.392279 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.392279 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.392279 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.392279 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 7675.354462 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 7675.354462 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 7675.354462 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7675.354462 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7675.354462 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7675.354462 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 7704 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 5.052403 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 13051 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 7716 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.691420 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5160674969000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.052403 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.315775 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.315775 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13051 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 13051 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13051 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 13051 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13051 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 13051 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8896 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 8896 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8896 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 8896 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8896 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 8896 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 103895500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 103895500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 103895500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 103895500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 103895500 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 103895500 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21947 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 21947 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21947 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 21947 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21947 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 21947 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.405340 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.405340 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.405340 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.405340 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.405340 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.405340 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 11678.900629 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 11678.900629 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 11678.900629 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 11678.900629 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 11678.900629 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 11678.900629 # average overall miss latency +system.cpu.dtb_walker_cache.replacements 8715 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 5.044713 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 12138 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 8729 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.390537 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5162053528000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.044713 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.315295 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.315295 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12140 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 12140 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12140 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 12140 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12140 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 12140 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 9925 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 9925 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 9925 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 9925 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 9925 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 9925 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 112013000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 112013000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 112013000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 112013000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 112013000 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 112013000 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22065 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 22065 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22065 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 22065 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22065 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 22065 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.449807 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.449807 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.449807 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.449807 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.449807 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.449807 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 11285.944584 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 11285.944584 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 11285.944584 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 11285.944584 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 11285.944584 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 11285.944584 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -625,90 +595,90 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 2985 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 2985 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8896 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8896 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8896 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 8896 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8896 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 8896 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 77207000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 77207000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 77207000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 77207000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 77207000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 77207000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.405340 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.405340 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.405340 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.405340 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.405340 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.405340 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8678.844424 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8678.844424 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8678.844424 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8678.844424 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8678.844424 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8678.844424 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 2933 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 2933 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 9925 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 9925 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 9925 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 9925 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 9925 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 9925 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 82238000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 82238000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 82238000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 82238000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 82238000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 82238000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.449807 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.449807 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.449807 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.449807 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.449807 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.449807 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8285.944584 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8285.944584 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8285.944584 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8285.944584 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8285.944584 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8285.944584 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1623424 # number of replacements -system.cpu.dcache.tagsinuse 511.997312 # Cycle average of tags in use -system.cpu.dcache.total_refs 20011404 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1623936 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.322779 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1621962 # number of replacements +system.cpu.dcache.tagsinuse 511.997374 # Cycle average of tags in use +system.cpu.dcache.total_refs 20006252 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1622474 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12.330707 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 44345000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.997312 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 511.997374 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999995 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 11977182 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11977182 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8032009 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8032009 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 20009191 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20009191 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20009191 # number of overall hits -system.cpu.dcache.overall_hits::total 20009191 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1310824 # 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