diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-15 08:09:54 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-15 08:09:54 -0400 |
| commit | 54227f9e57f625a66e3fd1d0d67fbd53b5408bf2 (patch) | |
| tree | 77faeed4436765032a90ede56ba9d231f1c717aa /tests/quick/fs/10.linux-boot/ref | |
| parent | 1c321b88473d65ff4bd9a7b65a91351781fd31d8 (diff) | |
| download | gem5-54227f9e57f625a66e3fd1d0d67fbd53b5408bf2.tar.xz | |
Stats: Update stats for new default L1-to-L2 bus clock and width
This patch updates the stats to reflect the changes in the clock speed
and width for the bus connecting the L1 and L2 caches.
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref')
3 files changed, 1594 insertions, 1594 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 88df9e22a..23658f386 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,222 +1,52 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.920895 # Number of seconds simulated -sim_ticks 1920895294000 # Number of ticks simulated -final_tick 1920895294000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.914421 # Number of seconds simulated +sim_ticks 1914420945000 # Number of ticks simulated +final_tick 1914420945000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1271848 # Simulator instruction rate (inst/s) -host_op_rate 1271848 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 43474553061 # Simulator tick rate (ticks/s) -host_mem_usage 295012 # Number of bytes of host memory used -host_seconds 44.18 # Real time elapsed on the host -sim_insts 56195754 # Number of instructions simulated -sim_ops 56195754 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 850496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24859968 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory -system.physmem.bytes_read::total 28362816 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 850496 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 850496 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7404288 # Number of bytes written to this memory -system.physmem.bytes_written::total 7404288 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 13289 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388437 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 443169 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115692 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115692 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 442760 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12941865 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1380789 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14765415 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 442760 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 442760 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3854603 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3854603 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3854603 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 442760 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12941865 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1380789 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18620018 # Total bandwidth to/from this memory (bytes/s) -system.cpu.l2cache.replacements 336257 # number of replacements -system.cpu.l2cache.tagsinuse 65308.063316 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2448454 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 401419 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 6.099497 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 6040304000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 55656.590733 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 4765.137084 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 4886.335499 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.849252 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.072710 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.074560 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.996522 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 916463 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 814985 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1731448 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 835257 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 835257 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 187565 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 187565 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 916463 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1002550 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1919013 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 916463 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1002550 # number of overall hits -system.cpu.l2cache.overall_hits::total 1919013 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 13289 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 271966 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 285255 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 13 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 13 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 116861 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 116861 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 13289 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 388827 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 402116 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 13289 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 388827 # number of overall misses -system.cpu.l2cache.overall_misses::total 402116 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 691205000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14147611000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 14838816000 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 248000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 248000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6077413000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6077413000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 691205000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 20225024000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20916229000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 691205000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 20225024000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20916229000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 929752 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1086951 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2016703 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 835257 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 835257 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 304426 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 304426 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 929752 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1391377 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2321129 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 929752 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1391377 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2321129 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014293 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250210 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.141446 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.764706 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.764706 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383873 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.383873 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014293 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.279455 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.173242 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014293 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.279455 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.173242 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52013.319287 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52019.778208 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52019.477310 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 19076.923077 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 19076.923077 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52005.485149 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52005.485149 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52013.319287 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52015.482464 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52015.410976 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52013.319287 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52015.482464 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52015.410976 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 74180 # number of writebacks -system.cpu.l2cache.writebacks::total 74180 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13289 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271966 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 285255 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116861 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 116861 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 13289 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 388827 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 402116 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 13289 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 388827 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 402116 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 531734000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10884019000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11415753000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 560000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 560000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4675081000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4675081000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 531734000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15559100000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16090834000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 531734000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15559100000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16090834000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1331550000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1331550000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1892958000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1892958000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3224508000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3224508000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014293 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250210 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141446 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383873 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383873 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014293 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279455 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.173242 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014293 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279455 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.173242 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40013.093536 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40019.778208 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40019.466793 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 43076.923077 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 43076.923077 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40005.485149 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40005.485149 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40013.093536 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40015.482464 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40015.403515 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40013.093536 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40015.482464 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40015.403515 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +host_inst_rate 1284205 # Simulator instruction rate (inst/s) +host_op_rate 1284205 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43773036105 # Simulator tick rate (ticks/s) +host_mem_usage 295308 # Number of bytes of host memory used +host_seconds 43.74 # Real time elapsed on the host +sim_insts 56164879 # Number of instructions simulated +sim_ops 56164879 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 850560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24860096 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2652096 # Number of bytes read from this memory +system.physmem.bytes_read::total 28362752 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 850560 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 850560 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7404800 # Number of bytes written to this memory +system.physmem.bytes_written::total 7404800 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13290 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388439 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41439 # Number of read requests responded to by this memory +system.physmem.num_reads::total 443168 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115700 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115700 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 444291 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12985700 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1385325 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14815316 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 444291 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 444291 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3867906 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3867906 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3867906 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 444291 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12985700 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1385325 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18683222 # Total bandwidth to/from this memory (bytes/s) system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.347775 # Cycle average of tags in use +system.iocache.tagsinuse 1.347664 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1754498131000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.347775 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.084236 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.084236 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1748614160000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.347664 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.084229 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.084229 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -227,12 +57,12 @@ system.iocache.overall_misses::tsunami.ide 41725 # system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 20672998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 20672998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 11448538806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 11448538806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 11469211804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 11469211804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 11469211804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 11469211804 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 11444054806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 11444054806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 11464727804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 11464727804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 11464727804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 11464727804 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -251,17 +81,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119497.098266 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 119497.098266 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 275523.171111 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 275523.171111 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 274876.256537 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 274876.256537 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 274876.256537 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 274876.256537 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 199147000 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 275415.258134 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 275415.258134 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 274768.790989 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 274768.790989 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 274768.790989 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 274768.790989 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 199052000 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 24626 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 24614 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8086.859417 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8086.942391 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -277,12 +107,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41725 system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11676000 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 11676000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9287684000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 9287684000 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 9299360000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9299360000 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 9299360000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9299360000 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9283200000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 9283200000 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 9294876000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9294876000 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 9294876000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9294876000 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -293,12 +123,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67491.329480 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 67491.329480 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 223519.541779 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 223519.541779 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 222872.618334 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 222872.618334 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 222872.618334 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 222872.618334 # average overall mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 223411.628802 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 223411.628802 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 222765.152786 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 222765.152786 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 222765.152786 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 222765.152786 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -316,22 +146,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9066995 # DTB read hits +system.cpu.dtb.read_hits 9062432 # DTB read hits system.cpu.dtb.read_misses 10329 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations system.cpu.dtb.read_accesses 728856 # DTB read accesses -system.cpu.dtb.write_hits 6357563 # DTB write hits +system.cpu.dtb.write_hits 6354530 # DTB write hits system.cpu.dtb.write_misses 1142 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations system.cpu.dtb.write_accesses 291931 # DTB write accesses -system.cpu.dtb.data_hits 15424558 # DTB hits +system.cpu.dtb.data_hits 15416962 # DTB hits system.cpu.dtb.data_misses 11471 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations system.cpu.dtb.data_accesses 1020787 # DTB accesses -system.cpu.itb.fetch_hits 4975749 # ITB hits +system.cpu.itb.fetch_hits 4974475 # ITB hits system.cpu.itb.fetch_misses 5006 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4980755 # ITB accesses +system.cpu.itb.fetch_accesses 4979481 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -344,51 +174,51 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3841790588 # number of cpu cycles simulated +system.cpu.numCycles 3828841890 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56195754 # Number of instructions committed -system.cpu.committedOps 56195754 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 52066962 # Number of integer alu accesses +system.cpu.committedInsts 56164879 # Number of instructions committed +system.cpu.committedOps 56164879 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 52037464 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 324393 # Number of float alu accesses -system.cpu.num_func_calls 1483816 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 6469707 # number of instructions that are conditional controls -system.cpu.num_int_insts 52066962 # number of integer instructions +system.cpu.num_func_calls 1482804 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 6466141 # number of instructions that are conditional controls +system.cpu.num_int_insts 52037464 # number of integer instructions system.cpu.num_fp_insts 324393 # number of float instructions -system.cpu.num_int_register_reads 71340235 # number of times the integer registers were read -system.cpu.num_int_register_writes 38530699 # number of times the integer registers were written +system.cpu.num_int_register_reads 71294843 # number of times the integer registers were read +system.cpu.num_int_register_writes 38508157 # number of times the integer registers were written system.cpu.num_fp_register_reads 163609 # number of times the floating registers were read system.cpu.num_fp_register_writes 166486 # number of times the floating registers were written -system.cpu.num_mem_refs 15477180 # number of memory refs -system.cpu.num_load_insts 9103852 # Number of load instructions -system.cpu.num_store_insts 6373328 # Number of store instructions -system.cpu.num_idle_cycles 3586858626.998133 # Number of idle cycles -system.cpu.num_busy_cycles 254931961.001867 # Number of busy cycles -system.cpu.not_idle_fraction 0.066358 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.933642 # Percentage of idle cycles +system.cpu.num_mem_refs 15469580 # number of memory refs +system.cpu.num_load_insts 9099291 # Number of load instructions +system.cpu.num_store_insts 6370289 # Number of store instructions +system.cpu.num_idle_cycles 3589214946.998125 # Number of idle cycles +system.cpu.num_busy_cycles 239626943.001875 # Number of busy cycles +system.cpu.not_idle_fraction 0.062585 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.937415 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 212106 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74929 40.88% 40.88% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 131 0.07% 40.95% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1936 1.06% 42.01% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 106288 57.99% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183284 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73562 49.31% 49.31% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1936 1.30% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73562 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149191 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1860148981000 96.84% 96.84% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 104328000 0.01% 96.84% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 779009000 0.04% 96.88% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 59862143000 3.12% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1920894461000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981756 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211993 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74900 40.89% 40.89% # number of times we switched to this ipl +system.cpu.kern.ipl_count::21 133 0.07% 40.96% # number of times we switched to this ipl +system.cpu.kern.ipl_count::22 1930 1.05% 42.02% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 106213 57.98% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183176 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73533 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::21 133 0.09% 49.40% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::22 1930 1.29% 50.69% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73534 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149130 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1856400078000 96.97% 96.97% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 92059500 0.00% 96.97% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 736279500 0.04% 97.01% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 57191794000 2.99% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1914420211000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981749 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.692101 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.813988 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.692326 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814135 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -427,29 +257,29 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.16% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 176055 91.22% 93.41% # number of callpals executed -system.cpu.kern.callpal::rdps 6837 3.54% 96.96% # number of callpals executed +system.cpu.kern.callpal::swpipl 175957 91.22% 93.41% # number of callpals executed +system.cpu.kern.callpal::rdps 6832 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed -system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed +system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal::rti 5161 2.67% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5156 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 193009 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5906 # number of protection mode switches -system.cpu.kern.mode_switch::user 1739 # number of protection mode switches +system.cpu.kern.callpal::total 192901 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5901 # number of protection mode switches +system.cpu.kern.mode_switch::user 1740 # number of protection mode switches system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1909 -system.cpu.kern.mode_good::user 1739 +system.cpu.kern.mode_good::kernel 1910 +system.cpu.kern.mode_good::user 1740 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.323231 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.323674 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.391911 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 46683787000 2.43% 2.43% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5260006000 0.27% 2.70% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1868950661000 97.30% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::total 0.392278 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 45169028500 2.36% 2.36% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5015931500 0.26% 2.62% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1864235249000 97.38% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -482,51 +312,51 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 929101 # number of replacements -system.cpu.icache.tagsinuse 508.704776 # Cycle average of tags in use -system.cpu.icache.total_refs 55277821 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 929612 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 59.463326 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 36213864000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 508.704776 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.993564 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.993564 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 55277821 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 55277821 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 55277821 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 55277821 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 55277821 # number of overall hits -system.cpu.icache.overall_hits::total 55277821 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 929772 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 929772 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 929772 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 929772 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 929772 # number of overall misses -system.cpu.icache.overall_misses::total 929772 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13856924500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13856924500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13856924500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13856924500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13856924500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13856924500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 56207593 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 56207593 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 56207593 # 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miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23683.271185 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 23683.271185 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29128.935239 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 29128.935239 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13158.031838 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13158.031838 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 24889.817487 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 24889.817487 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 24889.817487 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 24889.817487 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -641,54 +471,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 835257 # number of writebacks -system.cpu.dcache.writebacks::total 835257 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069678 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1069678 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304443 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304443 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17273 # 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average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52016.606272 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52017.062113 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52030.398796 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52016.606272 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52017.062113 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.writebacks::writebacks 74188 # number of writebacks +system.cpu.l2cache.writebacks::total 74188 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13290 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271970 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 285260 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116859 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 116859 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 13290 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 388829 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 402119 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 13290 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 388829 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 402119 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 531884000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10884274000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11416158000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 560000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 560000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4675219000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4675219000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 531884000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15559493000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16091377000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 531884000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15559493000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16091377000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1332180000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1332180000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1892328500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1892328500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3224508500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3224508500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014313 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250259 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141549 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383925 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383925 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014313 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279505 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.173353 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014313 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279505 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.173353 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40021.369451 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40020.127220 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40020.185094 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 43076.923077 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 43076.923077 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40007.350739 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40007.350739 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40021.369451 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40016.287365 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40016.455328 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40021.369451 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40016.287365 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40016.455328 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 4a0324f9e..07e356a30 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,54 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.629150 # Number of seconds simulated -sim_ticks 2629149747000 # Number of ticks simulated -final_tick 2629149747000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.624688 # Number of seconds simulated +sim_ticks 2624688029000 # Number of ticks simulated +final_tick 2624688029000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 556259 # Simulator instruction rate (inst/s) -host_op_rate 707830 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 24290841486 # Simulator tick rate (ticks/s) -host_mem_usage 380276 # Number of bytes of host memory used -host_seconds 108.24 # Real time elapsed on the host -sim_insts 60207390 # Number of instructions simulated -sim_ops 76612873 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 705696 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9115408 # Number of bytes read from this memory -system.physmem.bytes_read::total 134077744 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 705696 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 705696 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3736256 # Number of bytes written to this memory -system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6752328 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 15532032 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 17229 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142462 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15691729 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 58379 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 812397 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47261004 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 97 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 268412 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3467055 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50996618 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 268412 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 268412 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1421089 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1147166 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2568255 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1421089 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47261004 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 97 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 268412 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4614222 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53564873 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 388710 # Simulator instruction rate (inst/s) +host_op_rate 494628 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 16947208284 # Simulator tick rate (ticks/s) +host_mem_usage 385844 # Number of bytes of host memory used +host_seconds 154.87 # Real time elapsed on the host +sim_insts 60201138 # Number of instructions simulated +sim_ops 76605123 # Number of ops (including micro ops) simulated system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -61,244 +23,44 @@ system.realview.nvmem.bw_inst_read::cpu.inst 8 system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.cpu.l2cache.replacements 62933 # number of replacements -system.cpu.l2cache.tagsinuse 51862.510726 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1683379 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 128318 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 13.118806 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 2576532162000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 38450.903251 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.dtb.walker 2.914018 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000670 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 7005.048584 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 6403.644203 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.586714 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000044 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.106889 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.097712 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.791359 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8836 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3549 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 844195 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 370308 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1226888 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 596416 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 596416 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 113846 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 113846 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 8836 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 3549 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 844195 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 484154 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1340734 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 8836 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 3549 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 844195 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 484154 # number of overall hits -system.cpu.l2cache.overall_hits::total 1340734 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 4 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 10613 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 10261 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 20880 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 2845 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2845 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 133824 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133824 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 4 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 10613 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 144085 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 154704 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 4 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 10613 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 144085 # number of overall misses -system.cpu.l2cache.overall_misses::total 154704 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 208000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 104000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 553137500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 534185000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1087634500 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1040000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 1040000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6961477000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6961477000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 208000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 104000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 553137500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7495662000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 8049111500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 208000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 104000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 553137500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7495662000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 8049111500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8840 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3551 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 854808 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 380569 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1247768 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 596416 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 596416 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2871 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2871 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 247670 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 247670 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 8840 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 3551 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 854808 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 628239 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1495438 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 8840 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 3551 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 854808 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 628239 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1495438 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000452 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000563 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012416 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026962 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.016734 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.990944 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.990944 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.540332 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.540332 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000452 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000563 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012416 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.229347 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.103451 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000452 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000563 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012416 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.229347 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.103451 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52118.863658 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52059.740766 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52089.774904 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 365.553603 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 365.553603 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52019.645206 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52019.645206 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52118.863658 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52022.500607 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52029.110430 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52118.863658 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52022.500607 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52029.110430 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 58379 # number of writebacks -system.cpu.l2cache.writebacks::total 58379 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 4 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10613 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10261 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 20880 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2845 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 2845 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133824 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 133824 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 4 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 10613 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 144085 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 154704 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 4 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 10613 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 144085 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 154704 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 160000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 80000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 425775500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 411049000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 837064500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 114083000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 114083000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5355569000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5355569000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 160000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 80000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 425775500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5766618000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6192633500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 160000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 80000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 425775500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5766618000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6192633500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 264840000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166753837500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167018677500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 31852864000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 31852864000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 264840000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 198606701500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 198871541500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000452 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000563 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012416 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026962 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016734 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990944 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990944 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.540332 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.540332 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000452 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000563 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012416 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229347 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.103451 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000452 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000563 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012416 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229347 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.103451 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40118.298313 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40059.350940 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40089.295977 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40099.472759 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40099.472759 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40019.495756 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40019.495756 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40118.298313 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40022.334039 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40028.916512 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40118.298313 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40022.334039 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40028.916512 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 705824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9049616 # Number of bytes read from this memory +system.physmem.bytes_read::total 134012208 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 705824 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 705824 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3676928 # Number of bytes written to this memory +system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory +system.physmem.bytes_written::total 6693000 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 15532032 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 17231 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141434 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15690705 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57452 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory +system.physmem.num_writes::total 811470 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47341343 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 122 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 73 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 268917 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3447883 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51058338 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 268917 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 268917 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1400901 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1149116 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2550017 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1400901 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47341343 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 122 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 73 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 268917 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4596999 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53608355 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). @@ -307,26 +69,26 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 14998169 # DTB read hits -system.cpu.dtb.read_misses 7372 # DTB read misses -system.cpu.dtb.write_hits 11231565 # DTB write hits -system.cpu.dtb.write_misses 2270 # DTB write misses +system.cpu.dtb.read_hits 14996726 # DTB read hits +system.cpu.dtb.read_misses 7357 # DTB read misses +system.cpu.dtb.write_hits 11231612 # DTB write hits +system.cpu.dtb.write_misses 2211 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3524 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 3491 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 231 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 186 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 15005541 # DTB read accesses -system.cpu.dtb.write_accesses 11233835 # DTB write accesses +system.cpu.dtb.read_accesses 15004083 # DTB read accesses +system.cpu.dtb.write_accesses 11233823 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 26229734 # DTB hits -system.cpu.dtb.misses 9642 # DTB misses -system.cpu.dtb.accesses 26239376 # DTB accesses -system.cpu.itb.inst_hits 61501359 # ITB inst hits +system.cpu.dtb.hits 26228338 # DTB hits +system.cpu.dtb.misses 9568 # DTB misses +system.cpu.dtb.accesses 26237906 # DTB accesses +system.cpu.itb.inst_hits 61495107 # ITB inst hits system.cpu.itb.inst_misses 4471 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -343,79 +105,79 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 61505830 # ITB inst accesses -system.cpu.itb.hits 61501359 # DTB hits +system.cpu.itb.inst_accesses 61499578 # ITB inst accesses +system.cpu.itb.hits 61495107 # DTB hits system.cpu.itb.misses 4471 # DTB misses -system.cpu.itb.accesses 61505830 # DTB accesses -system.cpu.numCycles 5258299494 # number of cpu cycles simulated +system.cpu.itb.accesses 61499578 # DTB accesses +system.cpu.numCycles 5249376058 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60207390 # Number of instructions committed -system.cpu.committedOps 76612873 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 68878830 # Number of integer alu accesses +system.cpu.committedInsts 60201138 # Number of instructions committed +system.cpu.committedOps 76605123 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 68872510 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses -system.cpu.num_func_calls 2140176 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7948958 # number of instructions that are conditional controls -system.cpu.num_int_insts 68878830 # number of integer instructions +system.cpu.num_func_calls 2139913 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7948064 # number of instructions that are conditional controls +system.cpu.num_int_insts 68872510 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions -system.cpu.num_int_register_reads 394820534 # number of times the integer registers were read -system.cpu.num_int_register_writes 74191435 # number of times the integer registers were written +system.cpu.num_int_register_reads 394780312 # number of times the integer registers were read +system.cpu.num_int_register_writes 74180713 # number of times the integer registers were written system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written -system.cpu.num_mem_refs 27397151 # number of memory refs -system.cpu.num_load_insts 15662227 # Number of load instructions -system.cpu.num_store_insts 11734924 # Number of store instructions -system.cpu.num_idle_cycles 4567780450.602262 # Number of idle cycles -system.cpu.num_busy_cycles 690519043.397737 # Number of busy cycles -system.cpu.not_idle_fraction 0.131320 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.868680 # Percentage of idle cycles +system.cpu.num_mem_refs 27395681 # number of memory refs +system.cpu.num_load_insts 15660705 # Number of load instructions +system.cpu.num_store_insts 11734976 # Number of store instructions +system.cpu.num_idle_cycles 4573668194.612258 # Number of idle cycles +system.cpu.num_busy_cycles 675707863.387743 # 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number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11565472500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11565472500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 61495107 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 61495107 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 61495107 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 61495107 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 61495107 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 61495107 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013926 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.013926 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.013926 # 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average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13504.913065 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13504.913065 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13504.913065 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13504.913065 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -424,112 +186,112 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856442 # 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number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5201080500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8976707500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8976707500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 154794000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 154794000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 14177788000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 14177788000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 14177788000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14177788000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13564964 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13564964 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10224293 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10224293 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247691 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 247691 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247690 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247690 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 23789257 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 23789257 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 23789257 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 23789257 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027181 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.027181 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024501 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.024501 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046025 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046025 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.026029 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.026029 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.026029 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.026029 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14106.423056 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14106.423056 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35833.729192 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35833.729192 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13578.421053 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13578.421053 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22896.463737 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22896.463737 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22896.463737 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22896.463737 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -538,54 +300,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 596416 # number of writebacks -system.cpu.dcache.writebacks::total 596416 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 369069 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 369069 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250541 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 250541 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11500 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 11500 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 619610 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 619610 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 619610 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 619610 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4633803000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4633803000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8509109000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8509109000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 136482000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 136482000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13142912000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13142912000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13142912000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13142912000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182150932500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182150932500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41013343500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41013343500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 223164276000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 223164276000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027206 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027206 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024506 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024506 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046333 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046333 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026045 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.026045 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026045 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.026045 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12555.383953 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12555.383953 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33962.940197 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33962.940197 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11868 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11868 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21211.587934 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 21211.587934 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21211.587934 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 21211.587934 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 595968 # number of writebacks +system.cpu.dcache.writebacks::total 595968 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368703 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 368703 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250510 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 250510 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11400 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 11400 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 619213 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 619213 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 619213 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 619213 # 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number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182162796000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182162796000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41387867000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41387867000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 223550663000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 223550663000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027181 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027181 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024501 # 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average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33833.729192 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11578.421053 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11578.421053 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20896.463737 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20896.463737 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20896.463737 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20896.463737 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -593,6 +355,244 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 61913 # number of replacements +system.cpu.l2cache.tagsinuse 50867.983375 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1683054 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 127295 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 13.221682 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 2574063802000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 37864.330216 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.dtb.walker 3.885586 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 200000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 120000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 425853000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5730455000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6156628000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 264840000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166763732500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167028572500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 31856780000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 31856780000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 264840000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 198620512500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 198885352500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000570 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000844 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012419 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025935 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016422 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991031 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991031 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.537844 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.537844 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000570 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000844 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012419 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.227865 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.102795 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000570 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000844 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012419 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.227865 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.102795 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40118.040509 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40042.402110 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40081.587813 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40033.762617 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40033.762617 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40065.154382 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40065.154382 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40118.040509 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40063.586280 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40067.344800 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40118.040509 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40063.586280 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40067.344800 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. @@ -607,10 +607,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1358668189629 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1358668189629 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1358668189629 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1358668189629 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1358750753218 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1358750753218 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1358750753218 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1358750753218 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index 944044d4e..358803d5d 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -1,264 +1,56 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.196023 # Number of seconds simulated -sim_ticks 5196022575000 # Number of ticks simulated -final_tick 5196022575000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.187896 # Number of seconds simulated +sim_ticks 5187896410000 # Number of ticks simulated +final_tick 5187896410000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1315892 # Simulator instruction rate (inst/s) -host_op_rate 2536713 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 53344387183 # Simulator tick rate (ticks/s) -host_mem_usage 354072 # Number of bytes of host memory used -host_seconds 97.41 # Real time elapsed on the host -sim_insts 128174734 # Number of instructions simulated -sim_ops 247089109 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2880320 # Number of bytes read from this memory +host_inst_rate 834857 # Simulator instruction rate (inst/s) +host_op_rate 1609393 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 33766110220 # Simulator tick rate (ticks/s) +host_mem_usage 354356 # Number of bytes of host memory used +host_seconds 153.64 # Real time elapsed on the host +sim_insts 128269216 # Number of instructions simulated +sim_ops 247270559 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2867328 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 824192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8956288 # Number of bytes read from this memory -system.physmem.bytes_read::total 12661120 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 824192 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 824192 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8085888 # Number of bytes written to this memory -system.physmem.bytes_written::total 8085888 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 45005 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu.inst 826944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8996288 # Number of bytes read from this memory +system.physmem.bytes_read::total 12690880 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 826944 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 826944 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8107200 # Number of bytes written to this memory +system.physmem.bytes_written::total 8107200 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 44802 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12878 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 139942 # Number of read requests responded to by this memory -system.physmem.num_reads::total 197830 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 126342 # Number of write requests responded to by this memory -system.physmem.num_writes::total 126342 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 554332 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu.inst 12921 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 140567 # Number of read requests responded to by this memory +system.physmem.num_reads::total 198295 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 126675 # Number of write requests responded to by this memory +system.physmem.num_writes::total 126675 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 552696 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 158620 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1723682 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2436695 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 158620 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 158620 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1556169 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1556169 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1556169 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 554332 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 159399 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1734092 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2446248 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 159399 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 159399 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1562714 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1562714 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1562714 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 552696 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 158620 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1723682 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3992863 # Total bandwidth to/from this memory (bytes/s) -system.cpu.l2cache.replacements 86330 # number of replacements -system.cpu.l2cache.tagsinuse 64759.737076 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3491284 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 151054 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 23.112821 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 50074.264340 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.140725 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 3394.913598 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 11290.418413 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.764073 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.051802 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.172278 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.988155 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6719 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2994 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 778172 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1280323 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2068208 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1543462 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1543462 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 302 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 302 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 200678 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 200678 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 6719 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 2994 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 778172 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1481001 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2268886 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 6719 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 2994 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 778172 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1481001 # number of overall hits -system.cpu.l2cache.overall_hits::total 2268886 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 12879 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 28353 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 41237 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 1338 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 1338 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 112514 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 112514 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 12879 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 140867 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 153751 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 12879 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 140867 # number of overall misses -system.cpu.l2cache.overall_misses::total 153751 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 260000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 670083000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1488776500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2159119500 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 33785000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 33785000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5852520000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5852520000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 260000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 670083000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7341296500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 8011639500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 260000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 670083000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7341296500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 8011639500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6719 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2999 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 791051 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1308676 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2109445 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1543462 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1543462 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1640 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 1640 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 313192 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 313192 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6719 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 2999 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 791051 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1621868 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2422637 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6719 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 2999 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 791051 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1621868 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2422637 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001667 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016281 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021665 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.019549 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.815854 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.815854 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.359249 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.359249 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001667 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016281 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.086855 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.063464 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001667 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016281 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.086855 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.063464 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52029.117167 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52508.605791 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52358.791862 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 25250.373692 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 25250.373692 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52015.926907 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52015.926907 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52029.117167 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52115.090830 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52107.885477 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52029.117167 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52115.090830 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52107.885477 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 79675 # number of writebacks -system.cpu.l2cache.writebacks::total 79675 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12879 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 28353 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 41237 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1338 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 1338 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 112514 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 112514 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 12879 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 140867 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 153751 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 12879 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 140867 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 153751 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 200000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 515526000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1148536000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1664262000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 53936000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 53936000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4502349000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4502349000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 200000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 515526000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5650885000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6166611000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 200000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 515526000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5650885000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6166611000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86117450000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86117450000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2306155000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2306155000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 88423605000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 88423605000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001667 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016281 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021665 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019549 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.815854 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.815854 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.359249 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.359249 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001667 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016281 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.086855 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.063464 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001667 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016281 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.086855 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.063464 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40028.418355 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40508.447078 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40358.464486 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40310.911809 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40310.911809 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40015.900244 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40015.900244 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40028.418355 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40115.037589 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40107.778161 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40028.418355 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40115.037589 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40107.778161 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.physmem.bw_total::cpu.inst 159399 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1734092 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4008962 # Total bandwidth to/from this memory (bytes/s) system.iocache.replacements 47503 # number of replacements -system.iocache.tagsinuse 0.108744 # Cycle average of tags in use +system.iocache.tagsinuse 0.106662 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 47519 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 5053216388000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.108744 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.006796 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.006796 # Average percentage of cache occupancy +system.iocache.warmup_cycle 5044925516000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::pc.south_bridge.ide 0.106662 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.006666 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.006666 # Average percentage of cache occupancy system.iocache.ReadReq_misses::pc.south_bridge.ide 838 # number of ReadReq misses system.iocache.ReadReq_misses::total 838 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses @@ -267,14 +59,14 @@ system.iocache.demand_misses::pc.south_bridge.ide 47558 system.iocache.demand_misses::total 47558 # number of demand (read+write) misses system.iocache.overall_misses::pc.south_bridge.ide 47558 # number of overall misses system.iocache.overall_misses::total 47558 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 129993932 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 129993932 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10714208160 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10714208160 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 10844202092 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10844202092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 10844202092 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10844202092 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 130045932 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 130045932 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10696163160 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10696163160 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 10826209092 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10826209092 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 10826209092 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10826209092 # number of overall miss cycles system.iocache.ReadReq_accesses::pc.south_bridge.ide 838 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 838 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) @@ -291,19 +83,19 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 155124.023866 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 155124.023866 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 229328.085616 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 229328.085616 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 228020.566298 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 228020.566298 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 228020.566298 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 228020.566298 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 89624012 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 155186.076372 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 155186.076372 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 228941.848459 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 228941.848459 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 227642.228269 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 227642.228269 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 227642.228269 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 227642.228269 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 90077012 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 10977 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 11025 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8164.709119 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8170.250522 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -317,14 +109,14 @@ system.iocache.demand_mshr_misses::pc.south_bridge.ide 47558 system.iocache.demand_mshr_misses::total 47558 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::pc.south_bridge.ide 47558 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 47558 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 86387000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 86387000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8284511992 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8284511992 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8370898992 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8370898992 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8370898992 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8370898992 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 86439000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 86439000 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8266468944 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8266468944 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8352907944 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8352907944 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8352907944 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8352907944 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -333,14 +125,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 103087.112172 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 103087.112172 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 177322.602568 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 177322.602568 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 176014.529459 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 176014.529459 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 176014.529459 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 176014.529459 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 103149.164678 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 103149.164678 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 176936.407192 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 176936.407192 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 175636.232474 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 175636.232474 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 175636.232474 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 175636.232474 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -354,75 +146,75 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 10392045150 # number of cpu cycles simulated +system.cpu.numCycles 10375792820 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 128174734 # Number of instructions committed -system.cpu.committedOps 247089109 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 231827885 # Number of integer alu accesses +system.cpu.committedInsts 128269216 # Number of instructions committed +system.cpu.committedOps 247270559 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 232005526 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 23138722 # number of instructions that are conditional controls -system.cpu.num_int_insts 231827885 # number of integer instructions +system.cpu.num_conditional_control_insts 23152914 # number of instructions that are conditional controls +system.cpu.num_int_insts 232005526 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 566609561 # number of times the integer registers were read -system.cpu.num_int_register_writes 292994515 # number of times the integer registers were written +system.cpu.num_int_register_reads 567048885 # number of times the integer registers were read +system.cpu.num_int_register_writes 293217624 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 22210252 # number of memory refs -system.cpu.num_load_insts 13855140 # Number of load instructions -system.cpu.num_store_insts 8355112 # Number of store instructions -system.cpu.num_idle_cycles 9776628704.958118 # Number of idle cycles -system.cpu.num_busy_cycles 615416445.041882 # Number of busy cycles -system.cpu.not_idle_fraction 0.059220 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.940780 # Percentage of idle cycles +system.cpu.num_mem_refs 22238817 # number of memory refs +system.cpu.num_load_insts 13875768 # Number of load instructions +system.cpu.num_store_insts 8363049 # Number of store instructions +system.cpu.num_idle_cycles 9774979498.742117 # Number of idle cycles +system.cpu.num_busy_cycles 600813321.257884 # Number of busy cycles +system.cpu.not_idle_fraction 0.057905 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.942095 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.icache.replacements 790545 # number of replacements -system.cpu.icache.tagsinuse 510.338891 # Cycle average of tags in use -system.cpu.icache.total_refs 144363546 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 791057 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 182.494493 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 160970951000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.338891 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996756 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996756 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 144363546 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 144363546 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 144363546 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 144363546 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 144363546 # number of overall hits -system.cpu.icache.overall_hits::total 144363546 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 791064 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 791064 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 791064 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 791064 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 791064 # number of overall misses -system.cpu.icache.overall_misses::total 791064 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11792673000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11792673000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11792673000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11792673000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11792673000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11792673000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 145154610 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 145154610 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 145154610 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 145154610 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 145154610 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 145154610 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005450 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.005450 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.005450 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.005450 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.005450 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.005450 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14907.356421 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14907.356421 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14907.356421 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14907.356421 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14907.356421 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14907.356421 # average overall miss latency +system.cpu.icache.replacements 793131 # number of replacements +system.cpu.icache.tagsinuse 510.350730 # Cycle average of tags in use +system.cpu.icache.total_refs 144484487 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 793643 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 182.052241 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 160314386000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.350730 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.996779 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.996779 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 144484487 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 144484487 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 144484487 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 144484487 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 144484487 # number of overall hits +system.cpu.icache.overall_hits::total 144484487 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 793650 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 793650 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 793650 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 793650 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 793650 # number of overall misses +system.cpu.icache.overall_misses::total 793650 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 10860662000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 10860662000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 10860662000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 10860662000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 10860662000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 10860662000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 145278137 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 145278137 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 145278137 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 145278137 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 145278137 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 145278137 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005463 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.005463 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.005463 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.005463 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.005463 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.005463 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13684.447804 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13684.447804 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13684.447804 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13684.447804 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13684.447804 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13684.447804 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -431,80 +223,80 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 791064 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 791064 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 791064 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 791064 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 791064 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 791064 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9418462000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9418462000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9418462000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9418462000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9418462000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9418462000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005450 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005450 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005450 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.005450 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005450 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.005450 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11906.068283 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11906.068283 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11906.068283 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11906.068283 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11906.068283 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11906.068283 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 793650 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 793650 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 793650 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 793650 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 793650 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 793650 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9273362000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9273362000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9273362000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9273362000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9273362000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9273362000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005463 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005463 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005463 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.005463 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005463 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.005463 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11684.447804 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11684.447804 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11684.447804 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11684.447804 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11684.447804 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11684.447804 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 3550 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 3.065778 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 7809 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 3562 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 2.192308 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5171078849000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.065778 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.191611 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.191611 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7809 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 7809 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 3599 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 3.063919 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 7874 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 3610 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 2.181163 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5162043257000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.063919 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.191495 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.191495 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7876 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 7876 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7811 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 7811 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7811 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 7811 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4415 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 4415 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4415 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 4415 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4415 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 4415 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 53239000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 53239000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 53239000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 53239000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 53239000 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 53239000 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12224 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 12224 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7878 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 7878 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7878 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 7878 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4455 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 4455 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4455 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 4455 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4455 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 4455 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 43455000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 43455000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 43455000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 43455000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 43455000 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 43455000 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12331 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 12331 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12226 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 12226 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12226 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 12226 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.361175 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.361175 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.361116 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.361116 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.361116 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.361116 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 12058.663647 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 12058.663647 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 12058.663647 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 12058.663647 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 12058.663647 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 12058.663647 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12333 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 12333 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12333 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 12333 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.361285 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.361285 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.361226 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.361226 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.361226 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.361226 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 9754.208754 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 9754.208754 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 9754.208754 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9754.208754 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9754.208754 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9754.208754 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -513,78 +305,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 830 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 830 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4415 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4415 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4415 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 4415 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4415 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 4415 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 39994000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 39994000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 39994000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 39994000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 39994000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 39994000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.361175 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.361175 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.361116 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.361116 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.361116 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.361116 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9058.663647 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9058.663647 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9058.663647 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9058.663647 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9058.663647 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9058.663647 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 700 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 700 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4455 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4455 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4455 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 4455 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4455 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 4455 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 34545000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 34545000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 34545000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 34545000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 34545000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 34545000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.361285 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.361285 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.361226 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.361226 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.361226 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.361226 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 7754.208754 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 7754.208754 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 7754.208754 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7754.208754 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7754.208754 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7754.208754 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 7810 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 5.052392 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 12921 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 7826 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.651035 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5166488673000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.052392 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.315774 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.315774 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12921 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 12921 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12921 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 12921 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12921 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 12921 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 9010 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 9010 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 9010 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 9010 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 9010 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 9010 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 118862500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 118862500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 118862500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 118862500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 118862500 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 118862500 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21931 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 21931 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21931 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 21931 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21931 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 21931 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.410834 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.410834 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.410834 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.410834 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.410834 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.410834 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 13192.286349 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 13192.286349 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 13192.286349 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 13192.286349 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 13192.286349 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 13192.286349 # average overall miss latency +system.cpu.dtb_walker_cache.replacements 7423 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 5.046109 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 13594 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 7438 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.827642 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5159593477000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.046109 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.315382 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.315382 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13598 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 13598 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13598 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 13598 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13598 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 13598 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8635 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 8635 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8635 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 8635 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8635 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 8635 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 91582000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 91582000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 91582000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 91582000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 91582000 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 91582000 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22233 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 22233 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22233 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 22233 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22233 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 22233 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.388387 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.388387 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.388387 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.388387 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.388387 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.388387 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10605.906196 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10605.906196 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10605.906196 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10605.906196 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10605.906196 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10605.906196 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -593,90 +385,90 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 3142 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 3142 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 9010 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 9010 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 9010 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 9010 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 9010 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 9010 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 91832000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 91832000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 91832000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 91832000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 91832000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 91832000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.410834 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.410834 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.410834 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.410834 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.410834 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.410834 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10192.230855 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10192.230855 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10192.230855 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10192.230855 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10192.230855 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10192.230855 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 2904 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 2904 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8635 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8635 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8635 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 8635 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8635 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 8635 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 74312000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 74312000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 74312000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 74312000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 74312000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 74312000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.388387 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.388387 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.388387 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.388387 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.388387 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.388387 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8605.906196 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8605.906196 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8605.906196 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8605.906196 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8605.906196 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8605.906196 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1622132 # number of replacements -system.cpu.dcache.tagsinuse 511.997396 # Cycle average of tags in use -system.cpu.dcache.total_refs 20004026 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1622644 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.328044 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 45838000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.997396 # Average occupied blocks per requestor +system.cpu.dcache.replacements 1618325 # number of replacements +system.cpu.dcache.tagsinuse 511.997377 # Cycle average of tags in use +system.cpu.dcache.total_refs 20032981 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1618837 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12.374922 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 43788000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.997377 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999995 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 11972131 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11972131 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8029723 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8029723 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 20001854 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20001854 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20001854 # number of overall hits -system.cpu.dcache.overall_hits::total 20001854 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1309489 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1309489 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 315369 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 315369 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1624858 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1624858 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1624858 # number of overall misses -system.cpu.dcache.overall_misses::total 1624858 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 19885711500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 19885711500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9346101000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9346101000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 29231812500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 29231812500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 29231812500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 29231812500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13281620 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13281620 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8345092 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8345092 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21626712 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21626712 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21626712 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21626712 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098594 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.098594 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037791 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037791 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.075132 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.075132 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.075132 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.075132 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15185.856086 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15185.856086 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29635.446096 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 29635.446096 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 17990.379775 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 17990.379775 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 17990.379775 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 17990.379775 # average overall miss latency +system.cpu.dcache.ReadReq_hits::cpu.data 11992560 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11992560 # 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average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -685,46 +477,46 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1539490 # number of writebacks -system.cpu.dcache.writebacks::total 1539490 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1309489 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1309489 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315369 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 315369 # 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average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52123.171352 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52116.778371 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.writebacks::writebacks 80008 # number of writebacks +system.cpu.l2cache.writebacks::total 80008 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12922 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 28238 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 41165 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1345 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 1345 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 113260 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 113260 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 12922 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 141498 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 154425 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 12922 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 141498 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 154425 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 200000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 517329000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1144074500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1661603500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 54186500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 54186500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4533030500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4533030500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 200000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 517329000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5677105000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6194634000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 200000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 517329000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5677105000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6194634000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86587561000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86587561000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2305699000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2305699000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 88893260000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 88893260000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001770 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016282 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021630 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019525 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.811218 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.811218 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.362308 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.362308 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001770 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016282 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087447 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.063788 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001770 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016282 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087447 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.063788 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40034.746943 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40515.422480 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40364.472246 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40287.360595 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40287.360595 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40023.225322 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40023.225322 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40034.746943 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40121.450480 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40114.191355 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40034.746943 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40121.450480 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40114.191355 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |