diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-06-27 05:49:51 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-06-27 05:49:51 -0400 |
| commit | 5a15909bac241dc795c691d49c4e2c68cab745f4 (patch) | |
| tree | d0ae694e320c725ed8116943c7179516567279f3 /tests/quick/fs/10.linux-boot/ref | |
| parent | ac515d7a9b131ffc9e128bd209fcddb2f383808b (diff) | |
| download | gem5-5a15909bac241dc795c691d49c4e2c68cab745f4.tar.xz | |
stats: Update stats for monitor, cache and bus changes
This patch removes the sparse histogram total from the CommMonitor
stats. It also bumps the stats after the unit fixes in the atomic
cache access. Lastly, it updates the stats to match the new port
ordering. All numbers are the same, and the only thing that changes is
which master corresponds to what port index.
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref')
11 files changed, 6209 insertions, 6196 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index e45dffe9c..59af5be58 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -1,53 +1,53 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.870325 # Number of seconds simulated -sim_ticks 1870325497500 # Number of ticks simulated -final_tick 1870325497500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.870336 # Number of seconds simulated +sim_ticks 1870335643500 # Number of ticks simulated +final_tick 1870335643500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3096593 # Simulator instruction rate (inst/s) -host_op_rate 3096591 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 91710635166 # Simulator tick rate (ticks/s) +host_inst_rate 1417566 # Simulator instruction rate (inst/s) +host_op_rate 1417565 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 41981821830 # Simulator tick rate (ticks/s) host_mem_usage 308248 # Number of bytes of host memory used -host_seconds 20.39 # Real time elapsed on the host -sim_insts 63151114 # Number of instructions simulated -sim_ops 63151114 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 760896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 66666560 # Number of bytes read from this memory +host_seconds 44.55 # Real time elapsed on the host +sim_insts 63154034 # Number of instructions simulated +sim_ops 63154034 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 761216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 66693056 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2649600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 111168 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 681792 # Number of bytes read from this memory -system.physmem.bytes_read::total 70870016 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 760896 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 111168 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 872064 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7852480 # Number of bytes written to this memory -system.physmem.bytes_written::total 7852480 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 11889 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 1041665 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu1.inst 110976 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 668672 # Number of bytes read from this memory +system.physmem.bytes_read::total 70883520 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 761216 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 110976 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 872192 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7861504 # Number of bytes written to this memory +system.physmem.bytes_written::total 7861504 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 11894 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 1042079 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41400 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1737 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10653 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1107344 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 122695 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122695 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 406825 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 35644362 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1416652 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 59438 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 364531 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 37891809 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 406825 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 59438 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 466263 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4198456 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4198456 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4198456 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 406825 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 35644362 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1416652 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 59438 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 364531 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 42090265 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu1.inst 1734 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10448 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1107555 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 122836 # Number of write requests responded to by this memory +system.physmem.num_writes::total 122836 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 406994 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 35658336 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1416644 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 59335 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 357514 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 37898823 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 406994 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 59335 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 466329 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4203258 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4203258 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4203258 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 406994 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 35658336 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1416644 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 59335 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 357514 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42102082 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 0 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady @@ -194,126 +194,126 @@ system.physmem.writeRowHits 0 # Nu system.physmem.readRowHitRate nan # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap nan # Average gap between requests -system.membus.throughput 42148404 # Throughput (bytes/s) -system.membus.data_through_bus 78831234 # Total data (bytes) +system.membus.throughput 42160246 # Throughput (bytes/s) +system.membus.data_through_bus 78853810 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.l2c.replacements 1000406 # number of replacements -system.l2c.tagsinuse 65381.817483 # Cycle average of tags in use -system.l2c.total_refs 2465980 # Total number of references to valid blocks. -system.l2c.sampled_refs 1065550 # Sample count of references to valid blocks. -system.l2c.avg_refs 2.314279 # Average number of references to valid blocks. -system.l2c.warmup_cycle 838081000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 56158.126694 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4894.240575 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 4135.004261 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 174.436811 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 20.009142 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.856905 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.074680 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.063095 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.002662 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.000305 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.997647 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 872724 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 763064 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 102911 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 36889 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1775588 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 816811 # number of Writeback hits -system.l2c.Writeback_hits::total 816811 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 138 # number of UpgradeReq hits +system.l2c.tags.replacements 1000626 # number of replacements +system.l2c.tags.tagsinuse 65381.922487 # Cycle average of tags in use +system.l2c.tags.total_refs 2464723 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1065768 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.312626 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 838081000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 56158.706931 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4894.235246 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4134.598984 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 174.423126 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 19.958201 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.856914 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.074680 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.063089 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.002661 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.000305 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.997649 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 873088 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 763068 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 101908 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 36743 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1774807 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 816628 # number of Writeback hits +system.l2c.Writeback_hits::total 816628 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 135 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 37 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 175 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 172 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu0.data 14 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.data 9 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 23 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 166434 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 14300 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 180734 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 872724 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 929498 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 102911 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 51189 # number of demand (read+write) hits -system.l2c.demand_hits::total 1956322 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 872724 # number of overall hits -system.l2c.overall_hits::cpu0.data 929498 # number of overall hits -system.l2c.overall_hits::cpu1.inst 102911 # number of overall hits -system.l2c.overall_hits::cpu1.data 51189 # number of overall hits -system.l2c.overall_hits::total 1956322 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 11889 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 926770 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 1737 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 918 # number of ReadReq misses -system.l2c.ReadReq_misses::total 941314 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2441 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 575 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3016 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 67 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 103 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 170 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 115282 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 9862 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 125144 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 11889 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 1042052 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1737 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 10780 # number of demand (read+write) misses -system.l2c.demand_misses::total 1066458 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 11889 # number of overall misses -system.l2c.overall_misses::cpu0.data 1042052 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1737 # number of overall misses -system.l2c.overall_misses::cpu1.data 10780 # number of overall misses -system.l2c.overall_misses::total 1066458 # number of overall misses -system.l2c.ReadReq_accesses::cpu0.inst 884613 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 1689834 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 104648 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 37807 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2716902 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 816811 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 816811 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 2579 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 612 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 3191 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 81 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 112 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 193 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 281716 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 24162 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 305878 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 884613 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1971550 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 104648 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 61969 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 3022780 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 884613 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1971550 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 104648 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 61969 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 3022780 # number of overall (read+write) accesses +system.l2c.ReadExReq_hits::cpu0.data 166235 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 14287 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 180522 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 873088 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 929303 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 101908 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 51030 # number of demand (read+write) hits +system.l2c.demand_hits::total 1955329 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 873088 # number of overall hits +system.l2c.overall_hits::cpu0.data 929303 # number of overall hits +system.l2c.overall_hits::cpu1.inst 101908 # number of overall hits +system.l2c.overall_hits::cpu1.data 51030 # number of overall hits +system.l2c.overall_hits::total 1955329 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 11894 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 926761 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 1734 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 908 # number of ReadReq misses +system.l2c.ReadReq_misses::total 941297 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 2442 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 570 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 3012 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 65 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 100 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 165 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 115706 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 9662 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 125368 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.inst 11894 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 1042467 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 1734 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 10570 # number of demand (read+write) misses +system.l2c.demand_misses::total 1066665 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 11894 # number of overall misses +system.l2c.overall_misses::cpu0.data 1042467 # number of overall misses +system.l2c.overall_misses::cpu1.inst 1734 # number of overall misses +system.l2c.overall_misses::cpu1.data 10570 # number of overall misses +system.l2c.overall_misses::total 1066665 # number of overall misses +system.l2c.ReadReq_accesses::cpu0.inst 884982 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 1689829 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 103642 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 37651 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2716104 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 816628 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 816628 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 2577 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 607 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 3184 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 79 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 109 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 188 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 281941 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 23949 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 305890 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 884982 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1971770 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 103642 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 61600 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 3021994 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 884982 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1971770 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 103642 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 61600 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 3021994 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.inst 0.013440 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.548438 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.016599 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.024281 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.346466 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.946491 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.939542 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.945158 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.827160 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.919643 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.880829 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.409214 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.408162 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.409130 # miss rate for ReadExReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.548435 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.016731 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.024116 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.346561 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.947614 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.939044 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.945980 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.822785 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.917431 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.877660 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.410391 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.403441 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.409847 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.inst 0.013440 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.528545 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.016599 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.173958 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.352807 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.528696 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.016731 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.171591 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.352967 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.inst 0.013440 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.528545 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.016599 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.173958 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.352807 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.528696 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.016731 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.171591 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.352967 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -322,34 +322,34 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 81175 # number of writebacks -system.l2c.writebacks::total 81175 # number of writebacks +system.l2c.writebacks::writebacks 81316 # number of writebacks +system.l2c.writebacks::total 81316 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 41694 # number of replacements -system.iocache.tagsinuse 0.435353 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 41710 # Sample count of references to valid blocks. -system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1685787105067 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 0.435353 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.027210 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.027210 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses -system.iocache.ReadReq_misses::total 174 # number of ReadReq misses +system.iocache.tags.replacements 41695 # number of replacements +system.iocache.tags.tagsinuse 0.435438 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 1685787165017 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.435438 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.027215 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.027215 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses +system.iocache.ReadReq_misses::total 175 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses -system.iocache.demand_misses::total 41726 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses -system.iocache.overall_misses::total 41726 # number of overall misses -system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 41727 # number of demand (read+write) misses +system.iocache.demand_misses::total 41727 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 41727 # number of overall misses +system.iocache.overall_misses::total 41727 # number of overall misses +system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41727 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41727 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses @@ -385,22 +385,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 9148429 # DTB read hits +system.cpu0.dtb.read_hits 9154530 # DTB read hits system.cpu0.dtb.read_misses 7079 # DTB read misses system.cpu0.dtb.read_acv 152 # DTB read access violations system.cpu0.dtb.read_accesses 508987 # DTB read accesses -system.cpu0.dtb.write_hits 5932048 # DTB write hits +system.cpu0.dtb.write_hits 5936899 # DTB write hits system.cpu0.dtb.write_misses 726 # DTB write misses system.cpu0.dtb.write_acv 99 # DTB write access violations system.cpu0.dtb.write_accesses 189050 # DTB write accesses -system.cpu0.dtb.data_hits 15080477 # DTB hits +system.cpu0.dtb.data_hits 15091429 # DTB hits system.cpu0.dtb.data_misses 7805 # DTB misses system.cpu0.dtb.data_acv 251 # DTB access violations system.cpu0.dtb.data_accesses 698037 # DTB accesses -system.cpu0.itb.fetch_hits 3854196 # ITB hits +system.cpu0.itb.fetch_hits 3855556 # ITB hits system.cpu0.itb.fetch_misses 3485 # ITB misses system.cpu0.itb.fetch_acv 127 # ITB acv -system.cpu0.itb.fetch_accesses 3857681 # ITB accesses +system.cpu0.itb.fetch_accesses 3859041 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -413,55 +413,55 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3740650883 # number of cpu cycles simulated +system.cpu0.numCycles 3740671175 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 57184467 # Number of instructions committed -system.cpu0.committedOps 57184467 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 53214865 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 299670 # Number of float alu accesses -system.cpu0.num_func_calls 1398025 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 6803964 # number of instructions that are conditional controls -system.cpu0.num_int_insts 53214865 # number of integer instructions -system.cpu0.num_fp_insts 299670 # number of float instructions -system.cpu0.num_int_register_reads 73271755 # number of times the integer registers were read -system.cpu0.num_int_register_writes 39802131 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 147658 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 150767 # number of times the floating registers were written -system.cpu0.num_mem_refs 15124548 # number of memory refs -system.cpu0.num_load_insts 9178366 # Number of load instructions -system.cpu0.num_store_insts 5946182 # Number of store instructions -system.cpu0.num_idle_cycles 3683454681.064560 # Number of idle cycles -system.cpu0.num_busy_cycles 57196201.935440 # Number of busy cycles -system.cpu0.not_idle_fraction 0.015290 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.984710 # Percentage of idle cycles +system.cpu0.committedInsts 57222076 # Number of instructions committed +system.cpu0.committedOps 57222076 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 53249924 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 299810 # Number of float alu accesses +system.cpu0.num_func_calls 1399585 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 6808233 # number of instructions that are conditional controls +system.cpu0.num_int_insts 53249924 # number of integer instructions +system.cpu0.num_fp_insts 299810 # number of float instructions +system.cpu0.num_int_register_reads 73318596 # number of times the integer registers were read +system.cpu0.num_int_register_writes 39827534 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 147724 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 150835 # number of times the floating registers were written +system.cpu0.num_mem_refs 15135515 # number of memory refs +system.cpu0.num_load_insts 9184477 # Number of load instructions +system.cpu0.num_store_insts 5951038 # Number of store instructions +system.cpu0.num_idle_cycles 3683437331.313678 # Number of idle cycles +system.cpu0.num_busy_cycles 57233843.686322 # Number of busy cycles +system.cpu0.not_idle_fraction 0.015300 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.984700 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6280 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 196965 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 70940 40.60% 40.60% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 6283 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 197120 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 71004 40.60% 40.60% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 243 0.14% 40.74% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1908 1.09% 41.83% # number of times we switched to this ipl system.cpu0.kern.ipl_count::30 8 0.00% 41.84% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 101631 58.16% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 174730 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 69573 49.24% 49.24% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::31 101705 58.16% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 174868 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 69637 49.24% 49.24% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 243 0.17% 49.41% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1908 1.35% 50.76% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::30 8 0.01% 50.77% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 69565 49.23% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 141297 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1852985718000 99.07% 99.07% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_good::31 69629 49.23% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 141425 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1852989887500 99.07% 99.07% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::21 20110000 0.00% 99.07% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::22 82044000 0.00% 99.08% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::30 949500 0.00% 99.08% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 17236468500 0.92% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1870325290000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.980730 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_ticks::31 17242445000 0.92% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1870335436000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.980748 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.684486 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.808659 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.684617 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.808753 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 6 2.65% 2.65% # number of syscalls executed system.cpu0.kern.syscall::3 19 8.41% 11.06% # number of syscalls executed system.cpu0.kern.syscall::4 2 0.88% 11.95% # number of syscalls executed @@ -494,37 +494,37 @@ system.cpu0.kern.syscall::144 2 0.88% 99.12% # nu system.cpu0.kern.syscall::147 2 0.88% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 226 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 111 0.06% 0.06% # number of callpals executed +system.cpu0.kern.callpal::wripir 110 0.06% 0.06% # number of callpals executed system.cpu0.kern.callpal::wrmces 1 0.00% 0.06% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.06% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.06% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3760 2.05% 2.12% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3762 2.05% 2.11% # number of callpals executed system.cpu0.kern.callpal::tbi 38 0.02% 2.14% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.14% # number of callpals executed -system.cpu0.kern.callpal::swpipl 167897 91.68% 93.82% # number of callpals executed -system.cpu0.kern.callpal::rdps 6134 3.35% 97.17% # number of callpals executed +system.cpu0.kern.callpal::swpipl 168035 91.68% 93.82% # number of callpals executed +system.cpu0.kern.callpal::rdps 6150 3.36% 97.17% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 97.17% # number of callpals executed system.cpu0.kern.callpal::wrusp 3 0.00% 97.17% # number of callpals executed -system.cpu0.kern.callpal::rdusp 7 0.00% 97.17% # number of callpals executed +system.cpu0.kern.callpal::rdusp 7 0.00% 97.18% # number of callpals executed system.cpu0.kern.callpal::whami 2 0.00% 97.18% # number of callpals executed system.cpu0.kern.callpal::rti 4673 2.55% 99.73% # number of callpals executed system.cpu0.kern.callpal::callsys 357 0.19% 99.92% # number of callpals executed system.cpu0.kern.callpal::imb 142 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 183136 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7089 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1156 # number of protection mode switches +system.cpu0.kern.callpal::total 183291 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7091 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1158 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1155 -system.cpu0.kern.mode_good::user 1156 +system.cpu0.kern.mode_good::kernel 1157 +system.cpu0.kern.mode_good::user 1158 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.162928 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.163165 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.280291 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1869368290000 99.95% 99.95% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 956999000 0.05% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.280640 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1869378426000 99.95% 99.95% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 957009000 0.05% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3761 # number of times the context was actually changed +system.cpu0.kern.swap_context 3763 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -556,44 +556,44 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.throughput 131960056 # Throughput (bytes/s) -system.toL2Bus.data_through_bus 246797826 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 10432 # Total snoop data (bytes) -system.iobus.throughput 1460513 # Throughput (bytes/s) -system.iobus.data_through_bus 2731634 # Total data (bytes) -system.cpu0.icache.replacements 883989 # number of replacements -system.cpu0.icache.tagsinuse 511.244895 # Cycle average of tags in use -system.cpu0.icache.total_refs 56307893 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 884501 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 63.660632 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 9786576500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.244895 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.998525 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.998525 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 56307893 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 56307893 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 56307893 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 56307893 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 56307893 # number of overall hits -system.cpu0.icache.overall_hits::total 56307893 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 884630 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 884630 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 884630 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 884630 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 884630 # number of overall misses -system.cpu0.icache.overall_misses::total 884630 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 57192523 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 57192523 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 57192523 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 57192523 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 57192523 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 57192523 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015468 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.015468 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015468 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.015468 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015468 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.015468 # miss rate for overall accesses +system.toL2Bus.throughput 131930075 # Throughput (bytes/s) +system.toL2Bus.data_through_bus 246743154 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 10368 # Total snoop data (bytes) +system.iobus.throughput 1460500 # Throughput (bytes/s) +system.iobus.data_through_bus 2731626 # Total data (bytes) +system.cpu0.icache.tags.replacements 884406 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.244754 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 56345130 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 884918 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 63.672713 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 9786576500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.244754 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998525 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998525 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 56345130 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 56345130 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 56345130 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 56345130 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 56345130 # number of overall hits +system.cpu0.icache.overall_hits::total 56345130 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 885002 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 885002 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 885002 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 885002 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 885002 # number of overall misses +system.cpu0.icache.overall_misses::total 885002 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 57230132 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 57230132 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 57230132 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 57230132 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 57230132 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 57230132 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015464 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.015464 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015464 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.015464 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015464 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.015464 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -603,63 +603,63 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1978248 # number of replacements -system.cpu0.dcache.tagsinuse 507.129590 # Cycle average of tags in use -system.cpu0.dcache.total_refs 13113195 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1978760 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 6.626976 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 507.129590 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.990487 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.990487 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 7292594 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7292594 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5457787 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5457787 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 171977 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 171977 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 186443 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 186443 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 12750381 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12750381 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 12750381 # number of overall hits -system.cpu0.dcache.overall_hits::total 12750381 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1683136 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1683136 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 285798 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 285798 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16152 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 16152 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 726 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 726 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1968934 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1968934 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1968934 # number of overall misses -system.cpu0.dcache.overall_misses::total 1968934 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8975730 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8975730 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5743585 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5743585 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 188129 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 188129 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 187169 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 187169 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 14719315 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 14719315 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 14719315 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 14719315 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.187521 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.187521 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049760 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.049760 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085856 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085856 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003879 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.003879 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.133765 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.133765 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.133765 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.133765 # miss rate for overall accesses +system.cpu0.dcache.tags.replacements 1978683 # number of replacements +system.cpu0.dcache.tags.tagsinuse 507.129817 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 13123756 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1979195 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 6.630855 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 507.129817 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.990488 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.990488 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 7298341 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7298341 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5462261 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5462261 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 172144 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 172144 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 186623 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 186623 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 12760602 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12760602 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 12760602 # number of overall hits +system.cpu0.dcache.overall_hits::total 12760602 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1683328 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1683328 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 286000 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 286000 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16153 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 16153 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 715 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 715 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1969328 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1969328 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1969328 # number of overall misses +system.cpu0.dcache.overall_misses::total 1969328 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8981669 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8981669 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5748261 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5748261 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 188297 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 188297 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 187338 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 187338 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 14729930 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 14729930 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 14729930 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 14729930 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.187418 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.187418 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049754 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.049754 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085785 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085785 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003817 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.003817 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.133696 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.133696 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.133696 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.133696 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -668,29 +668,29 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 775494 # number of writebacks -system.cpu0.dcache.writebacks::total 775494 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 775614 # number of writebacks +system.cpu0.dcache.writebacks::total 775614 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1169160 # DTB read hits +system.cpu1.dtb.read_hits 1163439 # DTB read hits system.cpu1.dtb.read_misses 3277 # DTB read misses system.cpu1.dtb.read_acv 58 # DTB read access violations system.cpu1.dtb.read_accesses 220342 # DTB read accesses -system.cpu1.dtb.write_hits 755883 # DTB write hits +system.cpu1.dtb.write_hits 751446 # DTB write hits system.cpu1.dtb.write_misses 415 # DTB write misses system.cpu1.dtb.write_acv 58 # DTB write access violations system.cpu1.dtb.write_accesses 103280 # DTB write accesses -system.cpu1.dtb.data_hits 1925043 # DTB hits +system.cpu1.dtb.data_hits 1914885 # DTB hits system.cpu1.dtb.data_misses 3692 # DTB misses system.cpu1.dtb.data_acv 116 # DTB access violations system.cpu1.dtb.data_accesses 323622 # DTB accesses -system.cpu1.itb.fetch_hits 1469677 # ITB hits +system.cpu1.itb.fetch_hits 1468399 # ITB hits system.cpu1.itb.fetch_misses 1539 # ITB misses system.cpu1.itb.fetch_acv 57 # ITB acv -system.cpu1.itb.fetch_accesses 1471216 # ITB accesses +system.cpu1.itb.fetch_accesses 1469938 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -703,51 +703,51 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3740237218 # number of cpu cycles simulated +system.cpu1.numCycles 3740249123 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 5966647 # Number of instructions committed -system.cpu1.committedOps 5966647 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 5582916 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 28730 # Number of float alu accesses -system.cpu1.num_func_calls 184190 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 581489 # number of instructions that are conditional controls -system.cpu1.num_int_insts 5582916 # number of integer instructions -system.cpu1.num_fp_insts 28730 # number of float instructions -system.cpu1.num_int_register_reads 7700123 # number of times the integer registers were read -system.cpu1.num_int_register_writes 4186358 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 17955 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 17751 # number of times the floating registers were written -system.cpu1.num_mem_refs 1936419 # number of memory refs -system.cpu1.num_load_insts 1176619 # Number of load instructions -system.cpu1.num_store_insts 759800 # Number of store instructions -system.cpu1.num_idle_cycles 3734265828.606121 # Number of idle cycles -system.cpu1.num_busy_cycles 5971389.393879 # Number of busy cycles -system.cpu1.not_idle_fraction 0.001597 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.998403 # Percentage of idle cycles +system.cpu1.committedInsts 5931958 # Number of instructions committed +system.cpu1.committedOps 5931958 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 5550578 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 28590 # Number of float alu accesses +system.cpu1.num_func_calls 182742 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 577190 # number of instructions that are conditional controls +system.cpu1.num_int_insts 5550578 # number of integer instructions +system.cpu1.num_fp_insts 28590 # number of float instructions +system.cpu1.num_int_register_reads 7657288 # number of times the integer registers were read +system.cpu1.num_int_register_writes 4163275 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 17889 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 17683 # number of times the floating registers were written +system.cpu1.num_mem_refs 1926244 # number of memory refs +system.cpu1.num_load_insts 1170888 # Number of load instructions +system.cpu1.num_store_insts 755356 # Number of store instructions +system.cpu1.num_idle_cycles 3734312432.077611 # Number of idle cycles +system.cpu1.num_busy_cycles 5936690.922389 # Number of busy cycles +system.cpu1.not_idle_fraction 0.001587 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.998413 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2208 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 39691 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 10388 33.53% 33.53% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1907 6.15% 39.68% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 111 0.36% 40.04% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 18579 59.96% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 30985 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 10378 45.79% 45.79% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1907 8.41% 54.21% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 111 0.49% 54.70% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 10267 45.30% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 22663 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1859112376500 99.41% 99.41% # number of cycles we spent at this ipl +system.cpu1.kern.inst.quiesce 2204 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 39554 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 10328 33.46% 33.46% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1907 6.18% 39.64% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 110 0.36% 40.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 18518 60.00% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 30863 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 10318 45.77% 45.77% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1907 8.46% 54.23% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 110 0.49% 54.72% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 10208 45.28% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 22543 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1859123129500 99.41% 99.41% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks::22 82001000 0.00% 99.42% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 14176500 0.00% 99.42% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 10910041500 0.58% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1870118595500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.999037 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_ticks::30 14064500 0.00% 99.42% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 10905353000 0.58% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1870124548000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.999032 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.552613 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.731418 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.551247 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.730422 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::2 2 2.00% 2.00% # number of syscalls executed system.cpu1.kern.syscall::3 11 11.00% 13.00% # number of syscalls executed system.cpu1.kern.syscall::4 2 2.00% 15.00% # number of syscalls executed @@ -770,67 +770,67 @@ system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu1.kern.callpal::wripir 8 0.02% 0.03% # number of callpals executed system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::swpctx 472 1.46% 1.50% # number of callpals executed +system.cpu1.kern.callpal::swpctx 470 1.46% 1.50% # number of callpals executed system.cpu1.kern.callpal::tbi 15 0.05% 1.54% # number of callpals executed system.cpu1.kern.callpal::wrent 7 0.02% 1.57% # number of callpals executed -system.cpu1.kern.callpal::swpipl 26358 81.69% 83.25% # number of callpals executed -system.cpu1.kern.callpal::rdps 2589 8.02% 91.28% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 91.28% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 91.29% # number of callpals executed -system.cpu1.kern.callpal::rdusp 2 0.01% 91.30% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 91.31% # number of callpals executed -system.cpu1.kern.callpal::rti 2608 8.08% 99.39% # number of callpals executed +system.cpu1.kern.callpal::swpipl 26238 81.66% 83.22% # number of callpals executed +system.cpu1.kern.callpal::rdps 2576 8.02% 91.24% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 91.25% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 91.26% # number of callpals executed +system.cpu1.kern.callpal::rdusp 2 0.01% 91.26% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 91.27% # number of callpals executed +system.cpu1.kern.callpal::rti 2607 8.11% 99.39% # number of callpals executed system.cpu1.kern.callpal::callsys 158 0.49% 99.88% # number of callpals executed system.cpu1.kern.callpal::imb 38 0.12% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 32267 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1034 # number of protection mode switches +system.cpu1.kern.callpal::total 32131 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1033 # number of protection mode switches system.cpu1.kern.mode_switch::user 580 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2048 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 613 +system.cpu1.kern.mode_switch::idle 2046 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 612 system.cpu1.kern.mode_good::user 580 -system.cpu1.kern.mode_good::idle 33 -system.cpu1.kern.mode_switch_good::kernel 0.592843 # fraction of useful protection mode switches +system.cpu1.kern.mode_good::idle 32 +system.cpu1.kern.mode_switch_good::kernel 0.592449 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.016113 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.334790 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 1393260500 0.07% 0.07% # number of ticks spent at the given mode +system.cpu1.kern.mode_switch_good::idle 0.015640 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.334518 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 1373906500 0.07% 0.07% # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::user 508289000 0.03% 0.10% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1867980072500 99.90% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 473 # number of times the context was actually changed -system.cpu1.icache.replacements 104103 # number of replacements -system.cpu1.icache.tagsinuse 427.138444 # Cycle average of tags in use -system.cpu1.icache.total_refs 5865807 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 104615 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 56.070420 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1868930362000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 427.138444 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.834255 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.834255 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 5865807 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 5865807 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 5865807 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 5865807 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 5865807 # number of overall hits -system.cpu1.icache.overall_hits::total 5865807 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 104648 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 104648 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 104648 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 104648 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 104648 # number of overall misses -system.cpu1.icache.overall_misses::total 104648 # number of overall misses -system.cpu1.icache.ReadReq_accesses::cpu1.inst 5970455 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 5970455 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 5970455 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 5970455 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 5970455 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 5970455 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.017528 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.017528 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.017528 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.017528 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.017528 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.017528 # miss rate for overall accesses +system.cpu1.kern.mode_ticks::idle 1868002681000 99.90% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 471 # number of times the context was actually changed +system.cpu1.icache.tags.replacements 103103 # number of replacements +system.cpu1.icache.tags.tagsinuse 427.126317 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 5832124 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 103615 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 56.286484 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1868933191000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 427.126317 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.834231 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.834231 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 5832124 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 5832124 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 5832124 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 5832124 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 5832124 # number of overall hits +system.cpu1.icache.overall_hits::total 5832124 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 103642 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 103642 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 103642 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 103642 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 103642 # number of overall misses +system.cpu1.icache.overall_misses::total 103642 # number of overall misses +system.cpu1.icache.ReadReq_accesses::cpu1.inst 5935766 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 5935766 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 5935766 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 5935766 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 5935766 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 5935766 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.017461 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.017461 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.017461 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.017461 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.017461 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.017461 # miss rate for overall accesses system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -840,63 +840,63 @@ system.cpu1.icache.avg_blocked_cycles::no_targets nan system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 62444 # number of replacements -system.cpu1.dcache.tagsinuse 421.660465 # Cycle average of tags in use -system.cpu1.dcache.total_refs 1845254 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 62784 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 29.390514 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 1851113732500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 421.660465 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.823556 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.823556 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 1114890 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1114890 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 711494 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 711494 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 15278 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 15278 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 15743 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 15743 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 1826384 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 1826384 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 1826384 # number of overall hits -system.cpu1.dcache.overall_hits::total 1826384 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 41651 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 41651 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 26091 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 26091 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1291 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 1291 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 751 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 751 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 67742 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 67742 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 67742 # number of overall misses -system.cpu1.dcache.overall_misses::total 67742 # number of overall misses -system.cpu1.dcache.ReadReq_accesses::cpu1.data 1156541 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1156541 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 737585 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 737585 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 16569 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 16569 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 16494 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 16494 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 1894126 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 1894126 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 1894126 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 1894126 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036013 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.036013 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.035374 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.035374 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.077917 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.077917 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.045532 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.045532 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035764 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.035764 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035764 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.035764 # miss rate for overall accesses +system.cpu1.dcache.tags.replacements 62052 # number of replacements +system.cpu1.dcache.tags.tagsinuse 421.569557 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 1836045 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 62390 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 29.428514 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 1851115695500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 421.569557 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.823378 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.823378 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 1109514 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1109514 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 707455 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 707455 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 15133 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 15133 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 15610 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 15610 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 1816969 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 1816969 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 1816969 # number of overall hits +system.cpu1.dcache.overall_hits::total 1816969 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 41451 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 41451 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 25850 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 25850 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1285 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 1285 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 735 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 735 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 67301 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 67301 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 67301 # number of overall misses +system.cpu1.dcache.overall_misses::total 67301 # number of overall misses +system.cpu1.dcache.ReadReq_accesses::cpu1.data 1150965 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1150965 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 733305 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 733305 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 16418 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 16418 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 16345 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 16345 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 1884270 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 1884270 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 1884270 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 1884270 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036014 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.036014 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.035251 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.035251 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.078268 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.078268 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.044968 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.044968 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035717 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.035717 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035717 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.035717 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -905,8 +905,8 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 41317 # number of writebacks -system.cpu1.dcache.writebacks::total 41317 # number of writebacks +system.cpu1.dcache.writebacks::writebacks 41014 # number of writebacks +system.cpu1.dcache.writebacks::total 41014 # number of writebacks system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index 5057d01db..7cff7197d 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -1,43 +1,43 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.829331 # Number of seconds simulated -sim_ticks 1829330593000 # Number of ticks simulated -final_tick 1829330593000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.829332 # Number of seconds simulated +sim_ticks 1829332269000 # Number of ticks simulated +final_tick 1829332269000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1529223 # Simulator instruction rate (inst/s) -host_op_rate 1529222 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 46594888750 # Simulator tick rate (ticks/s) -host_mem_usage 306208 # Number of bytes of host memory used -host_seconds 39.26 # Real time elapsed on the host -sim_insts 60037737 # Number of instructions simulated -sim_ops 60037737 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 857856 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 66839296 # Number of bytes read from this memory +host_inst_rate 1710493 # Simulator instruction rate (inst/s) +host_op_rate 1710492 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 52117657653 # Simulator tick rate (ticks/s) +host_mem_usage 306192 # Number of bytes of host memory used +host_seconds 35.10 # Real time elapsed on the host +sim_insts 60038305 # Number of instructions simulated +sim_ops 60038305 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 857984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 66839424 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory -system.physmem.bytes_read::total 70349440 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 857856 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 857856 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7411136 # Number of bytes written to this memory -system.physmem.bytes_written::total 7411136 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 13404 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1044364 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 70349696 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 857984 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 857984 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7411392 # Number of bytes written to this memory +system.physmem.bytes_written::total 7411392 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13406 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1044366 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1099210 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115799 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115799 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 468945 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 36537571 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1449868 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 38456384 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 468945 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 468945 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4051283 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4051283 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4051283 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 468945 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 36537571 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1449868 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 42507667 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::total 1099214 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115803 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115803 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 469015 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 36537607 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1449867 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 38456489 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 469015 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 469015 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4051419 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4051419 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4051419 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 469015 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 36537607 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1449867 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42507908 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 0 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady @@ -184,18 +184,18 @@ system.physmem.writeRowHits 0 # Nu system.physmem.readRowHitRate nan # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap nan # Average gap between requests -system.membus.throughput 42552299 # Throughput (bytes/s) -system.membus.data_through_bus 77842222 # Total data (bytes) +system.membus.throughput 42552540 # Throughput (bytes/s) +system.membus.data_through_bus 77842734 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.iocache.replacements 41686 # number of replacements -system.iocache.tagsinuse 1.225558 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 41702 # Sample count of references to valid blocks. -system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1685780599067 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.225558 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.076597 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.076597 # Average percentage of cache occupancy +system.iocache.tags.replacements 41686 # number of replacements +system.iocache.tags.tagsinuse 1.225570 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 41702 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 1685780659017 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.225570 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.076598 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.076598 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses system.iocache.ReadReq_misses::total 174 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -247,22 +247,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9710417 # DTB read hits +system.cpu.dtb.read_hits 9710427 # DTB read hits system.cpu.dtb.read_misses 10329 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations system.cpu.dtb.read_accesses 728856 # DTB read accesses -system.cpu.dtb.write_hits 6352487 # DTB write hits +system.cpu.dtb.write_hits 6352498 # DTB write hits system.cpu.dtb.write_misses 1142 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations system.cpu.dtb.write_accesses 291931 # DTB write accesses -system.cpu.dtb.data_hits 16062904 # DTB hits +system.cpu.dtb.data_hits 16062925 # DTB hits system.cpu.dtb.data_misses 11471 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations system.cpu.dtb.data_accesses 1020787 # DTB accesses -system.cpu.itb.fetch_hits 4974615 # ITB hits +system.cpu.itb.fetch_hits 4974648 # ITB hits system.cpu.itb.fetch_misses 5006 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4979621 # ITB accesses +system.cpu.itb.fetch_accesses 4979654 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -275,51 +275,51 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3658661078 # number of cpu cycles simulated +system.cpu.numCycles 3658664430 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60037737 # Number of instructions committed -system.cpu.committedOps 60037737 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 55912968 # Number of integer alu accesses +system.cpu.committedInsts 60038305 # Number of instructions committed +system.cpu.committedOps 60038305 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 55913521 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses -system.cpu.num_func_calls 1484174 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7110641 # number of instructions that are conditional controls -system.cpu.num_int_insts 55912968 # number of integer instructions +system.cpu.num_func_calls 1484182 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7110746 # number of instructions that are conditional controls +system.cpu.num_int_insts 55913521 # number of integer instructions system.cpu.num_fp_insts 324460 # number of float instructions -system.cpu.num_int_register_reads 76953007 # number of times the integer registers were read -system.cpu.num_int_register_writes 41739788 # number of times the integer registers were written +system.cpu.num_int_register_reads 76953934 # number of times the integer registers were read +system.cpu.num_int_register_writes 41740225 # number of times the integer registers were written system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written -system.cpu.num_mem_refs 16115688 # number of memory refs -system.cpu.num_load_insts 9747503 # Number of load instructions -system.cpu.num_store_insts 6368185 # Number of store instructions -system.cpu.num_idle_cycles 3598606249.772791 # Number of idle cycles -system.cpu.num_busy_cycles 60054828.227209 # Number of busy cycles -system.cpu.not_idle_fraction 0.016414 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.983586 # Percentage of idle cycles +system.cpu.num_mem_refs 16115709 # number of memory refs +system.cpu.num_load_insts 9747513 # Number of load instructions +system.cpu.num_store_insts 6368196 # Number of store instructions +system.cpu.num_idle_cycles 3598609001.180807 # Number of idle cycles +system.cpu.num_busy_cycles 60055428.819193 # Number of busy cycles +system.cpu.not_idle_fraction 0.016415 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.983585 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211316 # number of hwrei instructions executed +system.cpu.kern.inst.hwrei 211319 # number of hwrei instructions executed system.cpu.kern.ipl_count::0 74830 40.99% 40.99% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 243 0.13% 41.12% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1866 1.02% 42.14% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105620 57.86% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182559 # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105623 57.86% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182562 # number of times we switched to this ipl system.cpu.kern.ipl_good::0 73463 49.29% 49.29% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1866 1.25% 50.71% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::31 73463 49.29% 100.00% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::total 149035 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1811925911500 99.05% 99.05% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::0 1811927418500 99.05% 99.05% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks::21 20110000 0.00% 99.05% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks::22 80238000 0.00% 99.05% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 17304126000 0.95% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1829330385500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 17304295000 0.95% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1829332061500 # number of cycles we spent at this ipl system.cpu.kern.ipl_used::0 0.981732 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.695541 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.816366 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.695521 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.816353 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -358,7 +358,7 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4177 2.17% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175246 91.19% 93.40% # number of callpals executed +system.cpu.kern.callpal::swpipl 175249 91.19% 93.40% # number of callpals executed system.cpu.kern.callpal::rdps 6771 3.52% 96.92% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed @@ -367,20 +367,20 @@ system.cpu.kern.callpal::whami 2 0.00% 96.93% # nu system.cpu.kern.callpal::rti 5203 2.71% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192177 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5948 # number of protection mode switches -system.cpu.kern.mode_switch::user 1735 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2098 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1906 -system.cpu.kern.mode_good::user 1735 +system.cpu.kern.callpal::total 192180 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5949 # number of protection mode switches +system.cpu.kern.mode_switch::user 1738 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1909 +system.cpu.kern.mode_good::user 1738 system.cpu.kern.mode_good::idle 171 -system.cpu.kern.mode_switch_good::kernel 0.320444 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.320894 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081506 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.389735 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 26832734500 1.47% 1.47% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 1465059000 0.08% 1.55% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1801032591000 98.45% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.390229 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 26834202500 1.47% 1.47% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 1465074000 0.08% 1.55% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1801032784000 98.45% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4178 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -413,35 +413,35 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.iobus.throughput 1480182 # Throughput (bytes/s) +system.iobus.throughput 1480181 # Throughput (bytes/s) system.iobus.data_through_bus 2707742 # Total data (bytes) -system.cpu.icache.replacements 919577 # number of replacements -system.cpu.icache.tagsinuse 511.215229 # Cycle average of tags in use -system.cpu.icache.total_refs 59129371 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 920089 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 64.264839 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.215229 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.998467 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.998467 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 59129371 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 59129371 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 59129371 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 59129371 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 59129371 # number of overall hits -system.cpu.icache.overall_hits::total 59129371 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 920204 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 920204 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 920204 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 920204 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 920204 # number of overall misses -system.cpu.icache.overall_misses::total 920204 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 60049575 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 60049575 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 60049575 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 60049575 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 60049575 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 60049575 # number of overall (read+write) accesses +system.cpu.icache.tags.replacements 919609 # number of replacements +system.cpu.icache.tags.tagsinuse 511.215244 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 59129907 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 920121 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 64.263186 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.215244 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.998467 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.998467 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 59129907 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 59129907 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 59129907 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 59129907 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 59129907 # number of overall hits +system.cpu.icache.overall_hits::total 59129907 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 920236 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 920236 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 920236 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 920236 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 920236 # number of overall misses +system.cpu.icache.overall_misses::total 920236 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 60050143 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 60050143 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 60050143 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 60050143 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 60050143 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 60050143 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015324 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.015324 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.015324 # miss rate for demand accesses @@ -457,75 +457,75 @@ system.cpu.icache.avg_blocked_cycles::no_targets nan system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 992297 # number of replacements -system.cpu.l2cache.tagsinuse 65424.375500 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2433228 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 1057460 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.301012 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 56309.097197 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 4867.351143 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 4247.927159 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.859209 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.074270 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.064818 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.998297 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 906782 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 811231 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1718013 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 833491 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 833491 # number of Writeback hits +system.cpu.l2cache.tags.replacements 992301 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65424.374219 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2433263 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1057464 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.301036 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 56309.127841 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 4867.327126 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 4247.919252 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.859209 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.074270 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.064818 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.998297 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 906812 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 811232 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1718044 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 833497 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 833497 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 187234 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 187234 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 906782 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 998465 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1905247 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 906782 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 998465 # number of overall hits -system.cpu.l2cache.overall_hits::total 1905247 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 13404 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_hits::cpu.data 187230 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 187230 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 906812 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 998462 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1905274 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 906812 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 998462 # number of overall hits +system.cpu.l2cache.overall_hits::total 1905274 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 13406 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 927640 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 941044 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 941046 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 12 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 117115 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 117115 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 13404 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1044755 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1058159 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 13404 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1044755 # number of overall misses -system.cpu.l2cache.overall_misses::total 1058159 # number of overall misses -system.cpu.l2cache.ReadReq_accesses::cpu.inst 920186 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1738871 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2659057 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 833491 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 833491 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_misses::cpu.data 117117 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 117117 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 13406 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1044757 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1058163 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 13406 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1044757 # number of overall misses +system.cpu.l2cache.overall_misses::total 1058163 # number of overall misses +system.cpu.l2cache.ReadReq_accesses::cpu.inst 920218 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1738872 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2659090 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 833497 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 833497 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 304349 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 304349 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 920186 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2043220 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2963406 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 920186 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2043220 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2963406 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014567 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.533473 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.353901 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 304347 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 304347 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 920218 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2043219 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2963437 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 920218 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2043219 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2963437 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014568 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.533472 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.353898 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384805 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.384805 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014567 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.511328 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.357075 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014567 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.511328 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.357075 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384814 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.384814 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014568 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.511329 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.357073 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014568 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.511329 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.357073 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -534,58 +534,58 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 74287 # number of writebacks -system.cpu.l2cache.writebacks::total 74287 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 74291 # number of writebacks +system.cpu.l2cache.writebacks::total 74291 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2042707 # number of replacements -system.cpu.dcache.tagsinuse 511.997802 # Cycle average of tags in use -system.cpu.dcache.total_refs 14038405 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2043219 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 6.870729 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 7807769 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7807769 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5848199 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5848199 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 183140 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183140 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 199281 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 199281 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13655968 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13655968 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13655968 # number of overall hits -system.cpu.dcache.overall_hits::total 13655968 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1721709 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1721709 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 304365 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 304365 # number of WriteReq misses +system.cpu.dcache.tags.replacements 2042706 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.997802 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 14038427 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2043218 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 6.870744 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 7807777 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7807777 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5848211 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5848211 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183141 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183141 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199282 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13655988 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13655988 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13655988 # number of overall hits +system.cpu.dcache.overall_hits::total 13655988 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1721710 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1721710 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304363 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304363 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2026074 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2026074 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2026074 # number of overall misses -system.cpu.dcache.overall_misses::total 2026074 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 9529478 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9529478 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6152564 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6152564 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200302 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200302 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 199281 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 199281 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15682042 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15682042 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15682042 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15682042 # number of overall (read+write) accesses +system.cpu.dcache.demand_misses::cpu.data 2026073 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2026073 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2026073 # number of overall misses +system.cpu.dcache.overall_misses::total 2026073 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 9529487 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9529487 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6152574 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6152574 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200303 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199282 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199282 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15682061 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15682061 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15682061 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15682061 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180672 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.180672 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049470 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.049470 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085681 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085681 # miss rate for LoadLockedReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049469 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049469 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085680 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085680 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.129197 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.129197 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.129197 # miss rate for overall accesses @@ -598,11 +598,11 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 833491 # number of writebacks -system.cpu.dcache.writebacks::total 833491 # number of writebacks +system.cpu.dcache.writebacks::writebacks 833497 # number of writebacks +system.cpu.dcache.writebacks::total 833497 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 132867618 # Throughput (bytes/s) -system.cpu.toL2Bus.data_through_bus 243048686 # Total data (bytes) +system.cpu.toL2Bus.throughput 132868790 # Throughput (bytes/s) +system.cpu.toL2Bus.data_through_bus 243051054 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 10112 # Total snoop data (bytes) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index a249cee6b..900001468 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,132 +1,132 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.959865 # Number of seconds simulated -sim_ticks 1959865139500 # Number of ticks simulated -final_tick 1959865139500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.961841 # Number of seconds simulated +sim_ticks 1961841175000 # Number of ticks simulated +final_tick 1961841175000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1047911 # Simulator instruction rate (inst/s) -host_op_rate 1047910 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 33678986014 # Simulator tick rate (ticks/s) -host_mem_usage 308256 # Number of bytes of host memory used -host_seconds 58.19 # Real time elapsed on the host -sim_insts 60980539 # Number of instructions simulated -sim_ops 60980539 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 833408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24886848 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2650880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 31616 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 338688 # Number of bytes read from this memory -system.physmem.bytes_read::total 28741440 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 833408 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 31616 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 865024 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7743232 # Number of bytes written to this memory -system.physmem.bytes_written::total 7743232 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13022 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 388857 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41420 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 494 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 5292 # Number of read requests responded to by this memory -system.physmem.num_reads::total 449085 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 120988 # Number of write requests responded to by this memory -system.physmem.num_writes::total 120988 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 425237 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12698245 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1352583 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 16132 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 172812 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14665009 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 425237 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 16132 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 441369 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3950900 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3950900 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3950900 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 425237 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12698245 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1352583 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 16132 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 172812 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18615909 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 449085 # Total number of read requests seen -system.physmem.writeReqs 120988 # Total number of write requests seen -system.physmem.cpureqs 577269 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28741440 # Total number of bytes read from memory -system.physmem.bytesWritten 7743232 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28741440 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7743232 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 62 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 7195 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28163 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 28468 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 28046 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 27665 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 27762 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 27794 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 28266 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 27878 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 28077 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 27763 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 27645 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 28133 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 28181 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 28495 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 28656 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 28031 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7932 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7895 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7532 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7157 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7275 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7314 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7754 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7257 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7316 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7137 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7066 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7523 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7683 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 8132 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 8336 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7679 # Track writes on a per bank basis +host_inst_rate 1094895 # Simulator instruction rate (inst/s) +host_op_rate 1094895 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 36191186298 # Simulator tick rate (ticks/s) +host_mem_usage 308248 # Number of bytes of host memory used +host_seconds 54.21 # Real time elapsed on the host +sim_insts 59351715 # Number of instructions simulated +sim_ops 59351715 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 831360 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24914752 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 32192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 287808 # Number of bytes read from this memory +system.physmem.bytes_read::total 28716928 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 831360 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 32192 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 863552 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7746368 # Number of bytes written to this memory +system.physmem.bytes_written::total 7746368 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 12990 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 389293 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41419 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 503 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 4497 # Number of read requests responded to by this memory +system.physmem.num_reads::total 448702 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 121037 # Number of write requests responded to by this memory +system.physmem.num_writes::total 121037 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 423765 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12699678 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1351188 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 16409 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 146703 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14637744 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 423765 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 16409 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 440174 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3948519 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3948519 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3948519 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 423765 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12699678 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1351188 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 16409 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 146703 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18586263 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 448702 # Total number of read requests seen +system.physmem.writeReqs 121037 # Total number of write requests seen +system.physmem.cpureqs 572905 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28716928 # Total number of bytes read from memory +system.physmem.bytesWritten 7746368 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28716928 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7746368 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 73 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 3165 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 27842 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 28115 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 28314 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 28019 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 27858 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 28118 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 27836 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 27466 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 27905 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 27953 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 27826 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 28040 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 28428 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 28581 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 28092 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 28236 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7663 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7614 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7774 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7534 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7350 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7579 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7314 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 6876 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7222 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7326 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7279 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7591 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7943 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 8207 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7875 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7890 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 1 # Number of times wr buffer was full causing retry -system.physmem.totGap 1959858128500 # Total gap between requests +system.physmem.totGap 1961833946000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 449085 # Categorize read packet sizes +system.physmem.readPktSize::6 448702 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 120988 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 408321 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 7066 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5331 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3258 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3264 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3003 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1531 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1505 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1476 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1451 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1408 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1429 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1415 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 2044 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 2352 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2212 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1198 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 461 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 203 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 95 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 121037 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 407897 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 7065 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5297 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3282 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3277 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2995 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1539 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1507 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1468 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1448 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1445 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1437 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1400 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 2065 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 2339 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2218 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1196 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 434 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 219 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 99 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -138,391 +138,386 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3817 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3924 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4968 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3809 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3916 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4987 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 5260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5259 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1444 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1454 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 40092 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 909.867305 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 223.303664 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 2368.170282 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 14180 35.37% 35.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 6168 15.38% 50.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 3902 9.73% 60.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 2490 6.21% 66.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 1693 4.22% 70.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 1359 3.39% 74.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 1096 2.73% 77.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 872 2.17% 79.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 629 1.57% 80.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 634 1.58% 82.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 494 1.23% 83.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 427 1.07% 84.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 257 0.64% 85.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 230 0.57% 85.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 171 0.43% 86.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 248 0.62% 86.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 146 0.36% 87.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 121 0.30% 87.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 95 0.24% 87.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 102 0.25% 88.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 86 0.21% 88.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 112 0.28% 88.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 1028 2.56% 91.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 203 0.51% 91.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 118 0.29% 91.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 93 0.23% 92.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 68 0.17% 92.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 46 0.11% 92.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 38 0.09% 92.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 17 0.04% 92.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 17 0.04% 92.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 32 0.08% 92.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 19 0.05% 92.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 9 0.02% 92.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 6 0.01% 92.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 5 0.01% 92.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 9 0.02% 92.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 7 0.02% 92.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 3 0.01% 92.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 3 0.01% 92.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 8 0.02% 92.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 5 0.01% 92.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 2 0.00% 92.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 4 0.01% 92.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 5 0.01% 92.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 3 0.01% 92.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 2 0.00% 92.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 1 0.00% 92.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 2 0.00% 92.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 2 0.00% 92.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 2 0.00% 92.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 3 0.01% 92.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 2 0.00% 92.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 2 0.00% 92.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 3 0.01% 92.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 1 0.00% 92.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 1 0.00% 92.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3843 1 0.00% 92.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3971 2 0.00% 93.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 4 0.01% 93.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 2 0.00% 93.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4163 2 0.00% 93.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 3 0.01% 93.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 1 0.00% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 1 0.00% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4483 3 0.01% 93.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4547 1 0.00% 93.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4675 1 0.00% 93.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4739 1 0.00% 93.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4803 1 0.00% 93.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4867 1 0.00% 93.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 1 0.00% 93.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5379 1 0.00% 93.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5571 1 0.00% 93.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5763 2 0.00% 93.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6147 3 0.01% 93.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6403 1 0.00% 93.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6787 1 0.00% 93.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6851 1 0.00% 93.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 2 0.00% 93.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7235 1 0.00% 93.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7299 2 0.00% 93.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7363 1 0.00% 93.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7555 1 0.00% 93.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7619 2 0.00% 93.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7683 2 0.00% 93.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7747 1 0.00% 93.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7811 1 0.00% 93.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7939 2 0.00% 93.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8003 3 0.01% 93.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8131 6 0.01% 93.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 2435 6.07% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9987 1 0.00% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11200-11203 1 0.00% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13760-13763 1 0.00% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14083 1 0.00% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 39515 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 922.589599 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 226.543369 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 2381.494153 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 13878 35.12% 35.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 6056 15.33% 50.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 3741 9.47% 59.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 2391 6.05% 65.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 1744 4.41% 70.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 1425 3.61% 73.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 1039 2.63% 76.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 750 1.90% 78.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 668 1.69% 80.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 592 1.50% 81.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 528 1.34% 83.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 459 1.16% 84.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 301 0.76% 84.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 245 0.62% 85.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 187 0.47% 86.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 264 0.67% 86.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 137 0.35% 87.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 111 0.28% 87.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 92 0.23% 87.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 96 0.24% 87.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 88 0.22% 88.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 105 0.27% 88.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 1100 2.78% 91.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 187 0.47% 91.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 132 0.33% 91.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 88 0.22% 92.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 54 0.14% 92.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 43 0.11% 92.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 23 0.06% 92.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 21 0.05% 92.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 20 0.05% 92.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 29 0.07% 92.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 19 0.05% 92.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 11 0.03% 92.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 14 0.04% 92.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 4 0.01% 92.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 9 0.02% 92.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 6 0.02% 92.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 1 0.00% 92.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 3 0.01% 92.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 5 0.01% 92.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 3 0.01% 92.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2755 1 0.00% 92.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 6 0.02% 92.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 5 0.01% 92.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 2 0.01% 92.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 2 0.01% 92.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 2 0.01% 92.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3203 1 0.00% 92.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3267 2 0.01% 92.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3331 4 0.01% 92.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3395 4 0.01% 92.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 2 0.01% 92.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3587 3 0.01% 92.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3715 1 0.00% 92.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3779 2 0.01% 92.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3843 1 0.00% 92.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3971 3 0.01% 92.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4035 2 0.01% 92.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4099 1 0.00% 92.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4163 3 0.01% 92.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4227 2 0.01% 92.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4291 1 0.00% 92.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4355 4 0.01% 92.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4419 1 0.00% 92.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4483 2 0.01% 92.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4547 1 0.00% 92.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4675 1 0.00% 92.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4739 1 0.00% 92.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4803 1 0.00% 92.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4867 1 0.00% 92.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4931 1 0.00% 92.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5571 1 0.00% 92.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5763 2 0.01% 92.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6147 3 0.01% 92.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6403 1 0.00% 92.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6787 1 0.00% 92.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6851 1 0.00% 92.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7171 2 0.01% 92.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7235 1 0.00% 92.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7299 2 0.01% 92.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7363 1 0.00% 93.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7555 1 0.00% 93.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7619 2 0.01% 93.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7683 2 0.01% 93.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7747 1 0.00% 93.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7811 1 0.00% 93.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7939 2 0.01% 93.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8003 3 0.01% 93.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8131 6 0.02% 93.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8195 2432 6.15% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8384-8387 2 0.01% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12352-12355 1 0.00% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13059 1 0.00% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13696-13699 1 0.00% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13827 1 0.00% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14272-14275 3 0.01% 99.23% # Bytes accessed per row activation system.physmem.bytesPerActivate::14400-14403 1 0.00% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14720-14723 1 0.00% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15040-15043 1 0.00% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15107 1 0.00% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15235 1 0.00% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 16 0.04% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15424-15427 2 0.00% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15488-15491 1 0.00% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15744-15747 1 0.00% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15875 1 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16320-16323 1 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 243 0.61% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16448-16451 6 0.01% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16512-16515 10 0.02% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16576-16579 4 0.01% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16643 5 0.01% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16704-16707 2 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14528-14531 2 0.01% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14595 1 0.00% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15107 2 0.01% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15296-15299 2 0.01% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 16 0.04% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15488-15491 2 0.01% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 242 0.61% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16448-16451 10 0.03% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16512-16515 6 0.02% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16576-16579 1 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16643 6 0.02% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16704-16707 4 0.01% 99.98% # Bytes accessed per row activation system.physmem.bytesPerActivate::16768-16771 1 0.00% 99.98% # Bytes accessed per row activation system.physmem.bytesPerActivate::16832-16835 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16899 2 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16960-16963 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16960-16963 2 0.01% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::17024-17027 4 0.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17088-17091 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17155 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 40092 # Bytes accessed per row activation -system.physmem.totQLat 3740449750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12011516000 # Sum of mem lat for all requests -system.physmem.totBusLat 2245115000 # Total cycles spent in databus access -system.physmem.totBankLat 6025951250 # Total cycles spent in bank access -system.physmem.avgQLat 8330.20 # Average queueing delay per request -system.physmem.avgBankLat 13420.14 # Average bank access latency per request +system.physmem.bytesPerActivate::17984-17987 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 39515 # Bytes accessed per row activation +system.physmem.totQLat 3750140000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 12006448750 # Sum of mem lat for all requests +system.physmem.totBusLat 2243145000 # Total cycles spent in databus access +system.physmem.totBankLat 6013163750 # Total cycles spent in bank access +system.physmem.avgQLat 8359.11 # Average queueing delay per request +system.physmem.avgBankLat 13403.42 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26750.34 # Average memory access latency -system.physmem.avgRdBW 14.67 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 26762.53 # Average memory access latency +system.physmem.avgRdBW 14.64 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 3.95 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 14.67 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 14.64 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 3.95 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 10.21 # Average write queue length over time -system.physmem.readRowHits 433314 # Number of row buffer hits during reads -system.physmem.writeRowHits 96597 # Number of row buffer hits during writes -system.physmem.readRowHitRate 96.50 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.84 # Row buffer hit rate for writes -system.physmem.avgGap 3437907.30 # Average gap between requests -system.membus.throughput 18676649 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 292796 # Transaction distribution -system.membus.trans_dist::ReadResp 292796 # Transaction distribution -system.membus.trans_dist::WriteReq 14151 # Transaction distribution -system.membus.trans_dist::WriteResp 14151 # Transaction distribution -system.membus.trans_dist::Writeback 120988 # Transaction distribution -system.membus.trans_dist::UpgradeReq 16779 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 11846 # Transaction distribution -system.membus.trans_dist::UpgradeResp 7198 # Transaction distribution -system.membus.trans_dist::ReadExReq 164928 # Transaction distribution -system.membus.trans_dist::ReadExResp 164057 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42700 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 931752 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 974452 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124666 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124666 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.bridge.slave 42700 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 1056418 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1099118 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 82626 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31176512 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 31259138 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5308160 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 5308160 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.bridge.slave 82626 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 36484672 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 36567298 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 36567298 # Total data (bytes) -system.membus.snoop_data_through_bus 36416 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 43346000 # Layer occupancy (ticks) +system.physmem.avgWrQLen 6.90 # Average write queue length over time +system.physmem.readRowHits 433153 # Number of row buffer hits during reads +system.physmem.writeRowHits 96987 # Number of row buffer hits during writes +system.physmem.readRowHitRate 96.55 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.13 # Row buffer hit rate for writes +system.physmem.avgGap 3443390.65 # Average gap between requests +system.membus.throughput 18639952 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 292620 # Transaction distribution +system.membus.trans_dist::ReadResp 292620 # Transaction distribution +system.membus.trans_dist::WriteReq 12397 # Transaction distribution +system.membus.trans_dist::WriteResp 12397 # Transaction distribution +system.membus.trans_dist::Writeback 121037 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4186 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 858 # Transaction distribution +system.membus.trans_dist::UpgradeResp 3168 # Transaction distribution +system.membus.trans_dist::ReadExReq 163944 # Transaction distribution +system.membus.trans_dist::ReadExResp 163855 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39192 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 902644 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 941836 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124669 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124669 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.bridge.slave 39192 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 1027313 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1066505 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 68594 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31155200 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 31223794 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5308096 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 5308096 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.bridge.slave 68594 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 36463296 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 36531890 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 36531890 # Total data (bytes) +system.membus.snoop_data_through_bus 36736 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 39129000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1579141500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1559666750 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 3832845053 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3812357322 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 376210250 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 376257250 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.l2c.replacements 342163 # number of replacements -system.l2c.tagsinuse 65224.613124 # Cycle average of tags in use -system.l2c.total_refs 2440483 # Total number of references to valid blocks. -system.l2c.sampled_refs 407350 # Sample count of references to valid blocks. -system.l2c.avg_refs 5.991121 # Average number of references to valid blocks. -system.l2c.warmup_cycle 8355445750 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 55361.728852 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4802.377103 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 4855.919486 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 161.173506 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 43.414178 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.844753 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.073278 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.074095 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.002459 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.000662 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.995249 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 678870 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 661225 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 323259 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 109447 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1772801 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 790404 # number of Writeback hits -system.l2c.Writeback_hits::total 790404 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 182 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 565 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 747 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 38 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 23 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 61 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 127727 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 43997 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 171724 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 678870 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 788952 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 323259 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 153444 # number of demand (read+write) hits -system.l2c.demand_hits::total 1944525 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 678870 # number of overall hits -system.l2c.overall_hits::cpu0.data 788952 # number of overall hits -system.l2c.overall_hits::cpu1.inst 323259 # number of overall hits -system.l2c.overall_hits::cpu1.data 153444 # number of overall hits -system.l2c.overall_hits::total 1944525 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 13022 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 271666 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 505 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 241 # number of ReadReq misses -system.l2c.ReadReq_misses::total 285434 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2971 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1796 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 4767 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 957 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 952 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1909 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 117966 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 5061 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 123027 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 13022 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 389632 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 505 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 5302 # number of demand (read+write) misses -system.l2c.demand_misses::total 408461 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 13022 # number of overall misses -system.l2c.overall_misses::cpu0.data 389632 # number of overall misses -system.l2c.overall_misses::cpu1.inst 505 # number of overall misses -system.l2c.overall_misses::cpu1.data 5302 # number of overall misses -system.l2c.overall_misses::total 408461 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 1040882000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 16855181499 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 39850000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 21000500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 17956913999 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 1322500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 10129500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 11452000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 954000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 204000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 1158000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 7822362000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 373828000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 8196190000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 1040882000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 24677543499 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 39850000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 394828500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 26153103999 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 1040882000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 24677543499 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 39850000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 394828500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 26153103999 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 691892 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 932891 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 323764 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 109688 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2058235 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 790404 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 790404 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 3153 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 2361 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 5514 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 995 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 975 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1970 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 245693 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 49058 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 294751 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 691892 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1178584 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 323764 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 158746 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2352986 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 691892 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1178584 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 323764 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 158746 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2352986 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.018821 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.291209 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.001560 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.002197 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.138679 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.942277 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.760695 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.864527 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.961809 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.976410 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.969036 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.480136 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.103164 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.417393 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.018821 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.330593 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.001560 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.033399 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.173593 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.018821 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.330593 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.001560 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.033399 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.173593 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 79932.575641 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 62043.765134 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 78910.891089 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 87139.004149 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 62910.914604 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 445.136318 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5640.033408 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 2402.349486 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 996.865204 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 214.285714 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 606.600314 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 66310.309750 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 73864.453665 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 66621.066920 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 79932.575641 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 63335.515304 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 78910.891089 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 74467.842324 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 64028.399282 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 79932.575641 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 63335.515304 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 78910.891089 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 74467.842324 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 64028.399282 # average overall miss latency +system.l2c.tags.replacements 341780 # number of replacements +system.l2c.tags.tagsinuse 65282.130402 # Cycle average of tags in use +system.l2c.tags.total_refs 2491702 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 406958 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 6.122750 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 8422138750 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 55415.399962 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4783.359658 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4905.357732 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 160.897835 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 17.115216 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.845572 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.072988 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.074850 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.002455 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.000261 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.996126 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 908184 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 776732 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 79667 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 28709 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1793292 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 820882 # number of Writeback hits +system.l2c.Writeback_hits::total 820882 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 160 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 41 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 201 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 18 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 18 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 36 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 176285 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 7535 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 183820 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 908184 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 953017 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 79667 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 36244 # number of demand (read+write) hits +system.l2c.demand_hits::total 1977112 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 908184 # number of overall hits +system.l2c.overall_hits::cpu0.data 953017 # number of overall hits +system.l2c.overall_hits::cpu1.inst 79667 # number of overall hits +system.l2c.overall_hits::cpu1.data 36244 # number of overall hits +system.l2c.overall_hits::total 1977112 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 12993 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 271572 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 511 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 178 # number of ReadReq misses +system.l2c.ReadReq_misses::total 285254 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 2440 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 483 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2923 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 33 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 73 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 106 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 118111 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 4331 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 122442 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.inst 12993 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 389683 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 511 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 4509 # number of demand (read+write) misses +system.l2c.demand_misses::total 407696 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 12993 # number of overall misses +system.l2c.overall_misses::cpu0.data 389683 # number of overall misses +system.l2c.overall_misses::cpu1.inst 511 # number of overall misses +system.l2c.overall_misses::cpu1.data 4509 # number of overall misses +system.l2c.overall_misses::total 407696 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.inst 1030661993 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 16900238244 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 41124000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 15490750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 17987514987 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 1078963 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 302487 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 1381450 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 69997 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 92496 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 162493 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 7866556623 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 326108488 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 8192665111 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 1030661993 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 24766794867 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 41124000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 341599238 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 26180180098 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 1030661993 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 24766794867 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 41124000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 341599238 # number of overall miss cycles +system.l2c.overall_miss_latency::total 26180180098 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.inst 921177 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 1048304 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 80178 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 28887 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2078546 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 820882 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 820882 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 2600 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 524 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 3124 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 51 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 91 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 142 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 294396 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 11866 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 306262 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 921177 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1342700 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 80178 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 40753 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2384808 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 921177 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1342700 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 80178 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 40753 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2384808 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.014105 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.259058 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.006373 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.006162 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.137237 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.938462 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.921756 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.935659 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.647059 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.802198 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.746479 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.401198 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.364992 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.399795 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.014105 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.290223 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.006373 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.110642 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.170955 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.014105 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.290223 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.006373 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.110642 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.170955 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 79324.404910 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 62231.151385 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 80477.495108 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 87026.685393 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 63057.888713 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 442.197951 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 626.267081 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 472.613753 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2121.121212 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1267.068493 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 1532.952830 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 66603.082041 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 75296.349111 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 66910.578976 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 79324.404910 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 63556.262057 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 80477.495108 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 75759.422932 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 64214.954520 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 79324.404910 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 63556.262057 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 80477.495108 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 75759.422932 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 64214.954520 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -531,119 +526,122 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 79468 # number of writebacks -system.l2c.writebacks::total 79468 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu1.inst 11 # number of ReadReq MSHR hits +system.l2c.writebacks::writebacks 79517 # number of writebacks +system.l2c.writebacks::total 79517 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0.inst 3 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.inst 8 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 11 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 3 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 8 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 11 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 3 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 8 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.inst 13022 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 271666 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 494 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 241 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 285423 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 2971 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 1796 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 4767 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 957 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 952 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1909 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 117966 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 5061 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 123027 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 13022 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 389632 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 494 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 5302 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 408450 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 13022 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 389632 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 494 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 5302 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 408450 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 877008002 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 13524537499 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 32847250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 18012000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 14452404751 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 29895468 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 17998795 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 47894263 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 9591457 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 9520952 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 19112409 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6366934262 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 311018260 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 6677952522 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 877008002 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 19891471761 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 32847250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 329030260 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 21130357273 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 877008002 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 19891471761 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 32847250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 329030260 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 21130357273 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1373163000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_misses::cpu0.inst 12990 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 271572 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 503 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 178 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 285243 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 2440 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 483 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 2923 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 33 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 73 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 106 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 118111 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 4331 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 122442 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 12990 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 389683 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 503 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 4509 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 407685 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 12990 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 389683 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 503 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 4509 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 407685 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 866381257 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 13503893756 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 34165000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 13232750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 14417672763 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 24556937 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4864483 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 29421420 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 330033 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 730073 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 1060106 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6385916377 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 270944012 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 6656860389 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 866381257 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 19889810133 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 34165000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 284176762 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 21074533152 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 866381257 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 19889810133 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 34165000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 284176762 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 21074533152 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1373141500 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 17611000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 1390774000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2158791500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 683644500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 2842436000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3531954500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 701255500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 4233210000 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.018821 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.291209 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.001526 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.002197 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.138674 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.942277 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.760695 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.864527 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.961809 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.976410 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.969036 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.480136 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.103164 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.417393 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018821 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.330593 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.001526 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.033399 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.173588 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018821 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.330593 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.001526 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.033399 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.173588 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 67348.180157 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 49783.695785 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 66492.408907 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 74738.589212 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 50635.039051 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10062.426119 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10021.600780 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10047.044892 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10022.421108 # average SCUpgradeReq mshr miss latency +system.l2c.ReadReq_mshr_uncacheable_latency::total 1390752500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1974248000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 499178500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2473426500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3347389500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 516789500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 3864179000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014102 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.259058 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.006274 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.006162 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.137232 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.938462 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.921756 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.935659 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.647059 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.802198 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.746479 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.401198 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.364992 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.399795 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014102 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.290223 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.006274 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.110642 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.170951 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014102 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.290223 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.006274 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.110642 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.170951 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 66696.016705 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 49724.911832 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 67922.465209 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 74341.292135 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 50545.229026 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10064.318443 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10071.393375 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10065.487513 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10011.738607 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 53972.621450 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61453.914246 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 54280.381721 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 67348.180157 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 51051.945839 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 66492.408907 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62057.763108 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 51733.032863 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 67348.180157 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 51051.945839 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 66492.408907 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62057.763108 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 51733.032863 # average overall mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 54067.075692 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62559.226968 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 54367.458789 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 66696.016705 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 51041.000334 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 67922.465209 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 63024.342870 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 51693.177703 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 66696.016705 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 51041.000334 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 67922.465209 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63024.342870 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 51693.177703 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -654,39 +652,39 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 41694 # number of replacements -system.iocache.tagsinuse 0.570240 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 41710 # Sample count of references to valid blocks. -system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1753558786000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 0.570240 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.035640 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.035640 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses -system.iocache.ReadReq_misses::total 174 # number of ReadReq misses +system.iocache.tags.replacements 41698 # number of replacements +system.iocache.tags.tagsinuse 0.564923 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 41714 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 1754539957000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.564923 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.035308 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.035308 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::tsunami.ide 178 # number of ReadReq misses +system.iocache.ReadReq_misses::total 178 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses -system.iocache.demand_misses::total 41726 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses -system.iocache.overall_misses::total 41726 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21457883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21457883 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 10416109037 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10416109037 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 10437566920 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10437566920 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 10437566920 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10437566920 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 41730 # number of demand (read+write) misses +system.iocache.demand_misses::total 41730 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 41730 # number of overall misses +system.iocache.overall_misses::total 41730 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 21912883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21912883 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 10439154521 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10439154521 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 10461067404 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10461067404 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 10461067404 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10461067404 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 178 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 178 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41730 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41730 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41730 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41730 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses @@ -695,40 +693,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 123321.166667 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 123321.166667 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 250676.478557 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 250676.478557 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 250145.399032 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 250145.399032 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 250145.399032 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 250145.399032 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 272227 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 123106.084270 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 123106.084270 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 251231.096482 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 251231.096482 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 250684.577139 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 250684.577139 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 250684.577139 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 250684.577139 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 274830 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27211 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27442 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.004300 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.014941 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 178 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 178 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41726 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41726 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41726 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41726 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12409133 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12409133 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8254729537 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8254729537 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 8267138670 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8267138670 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 8267138670 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8267138670 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 41730 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41730 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41730 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41730 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12655383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12655383 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8277077521 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8277077521 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 8289732904 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8289732904 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 8289732904 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8289732904 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -737,14 +735,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 71316.856322 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 71316.856322 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 198660.221818 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 198660.221818 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 198129.192110 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 198129.192110 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 198129.192110 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 198129.192110 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 71097.657303 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 71097.657303 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 199198.053547 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 199198.053547 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 198651.639204 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 198651.639204 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 198651.639204 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 198651.639204 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -762,22 +760,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7504093 # DTB read hits +system.cpu0.dtb.read_hits 8725663 # DTB read hits system.cpu0.dtb.read_misses 7765 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations system.cpu0.dtb.read_accesses 524069 # DTB read accesses -system.cpu0.dtb.write_hits 5095666 # DTB write hits +system.cpu0.dtb.write_hits 6139453 # DTB write hits system.cpu0.dtb.write_misses 910 # DTB write misses system.cpu0.dtb.write_acv 133 # DTB write access violations system.cpu0.dtb.write_accesses 202595 # DTB write accesses -system.cpu0.dtb.data_hits 12599759 # DTB hits +system.cpu0.dtb.data_hits 14865116 # DTB hits system.cpu0.dtb.data_misses 8675 # DTB misses system.cpu0.dtb.data_acv 343 # DTB access violations system.cpu0.dtb.data_accesses 726664 # DTB accesses -system.cpu0.itb.fetch_hits 3641096 # ITB hits +system.cpu0.itb.fetch_hits 4015307 # ITB hits system.cpu0.itb.fetch_misses 3984 # ITB misses system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 3645080 # ITB accesses +system.cpu0.itb.fetch_accesses 4019291 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -790,55 +788,55 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3919730279 # number of cpu cycles simulated +system.cpu0.numCycles 3923682350 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 47851975 # Number of instructions committed -system.cpu0.committedOps 47851975 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 44398232 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 209056 # Number of float alu accesses -system.cpu0.num_func_calls 1198231 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 5625657 # number of instructions that are conditional controls -system.cpu0.num_int_insts 44398232 # number of integer instructions -system.cpu0.num_fp_insts 209056 # number of float instructions -system.cpu0.num_int_register_reads 61087554 # number of times the integer registers were read -system.cpu0.num_int_register_writes 33073995 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 102127 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 103890 # number of times the floating registers were written -system.cpu0.num_mem_refs 12640550 # number of memory refs -system.cpu0.num_load_insts 7531710 # Number of load instructions -system.cpu0.num_store_insts 5108840 # Number of store instructions -system.cpu0.num_idle_cycles 3699529015.998113 # Number of idle cycles -system.cpu0.num_busy_cycles 220201263.001888 # Number of busy cycles -system.cpu0.not_idle_fraction 0.056178 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.943822 # Percentage of idle cycles +system.cpu0.committedInsts 54601969 # Number of instructions committed +system.cpu0.committedOps 54601969 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 50544405 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 297630 # Number of float alu accesses +system.cpu0.num_func_calls 1438477 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 6291508 # number of instructions that are conditional controls +system.cpu0.num_int_insts 50544405 # number of integer instructions +system.cpu0.num_fp_insts 297630 # number of float instructions +system.cpu0.num_int_register_reads 69247284 # number of times the integer registers were read +system.cpu0.num_int_register_writes 37427910 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 145753 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 148838 # number of times the floating registers were written +system.cpu0.num_mem_refs 14912078 # number of memory refs +system.cpu0.num_load_insts 8757685 # Number of load instructions +system.cpu0.num_store_insts 6154393 # Number of store instructions +system.cpu0.num_idle_cycles 3674902109.498127 # Number of idle cycles +system.cpu0.num_busy_cycles 248780240.501873 # Number of busy cycles +system.cpu0.not_idle_fraction 0.063405 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.936595 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6830 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 164217 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 56358 40.22% 40.22% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.09% 40.31% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1973 1.41% 41.72% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 445 0.32% 42.04% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 81223 57.96% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 140130 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 55870 49.08% 49.08% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.12% 49.19% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1973 1.73% 50.92% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 445 0.39% 51.31% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 55425 48.69% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 113844 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1901694919500 97.03% 97.03% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 94927000 0.00% 97.04% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 766727000 0.04% 97.08% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 329552000 0.02% 97.09% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 56978256500 2.91% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1959864382000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.991341 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6366 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 204697 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 73289 40.68% 40.68% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.07% 40.75% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1975 1.10% 41.85% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 6 0.00% 41.85% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 104766 58.15% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 180167 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 71920 49.28% 49.28% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.09% 49.37% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1975 1.35% 50.72% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 6 0.00% 50.73% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 71914 49.27% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 145946 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1899196330000 96.81% 96.81% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 95025500 0.00% 96.81% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 769055500 0.04% 96.85% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 5164500 0.00% 96.85% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 61774827500 3.15% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1961840403000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.981321 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.682381 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.812417 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.686425 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.810060 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed @@ -870,37 +868,37 @@ system.cpu0.kern.syscall::144 2 0.85% 99.15% # nu system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 234 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 528 0.36% 0.36% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.36% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.36% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.36% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3061 2.06% 2.42% # number of callpals executed -system.cpu0.kern.callpal::tbi 51 0.03% 2.45% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.46% # number of callpals executed -system.cpu0.kern.callpal::swpipl 133182 89.70% 92.16% # number of callpals executed -system.cpu0.kern.callpal::rdps 6700 4.51% 96.67% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.67% # number of callpals executed -system.cpu0.kern.callpal::wrusp 4 0.00% 96.67% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 96.68% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.68% # number of callpals executed -system.cpu0.kern.callpal::rti 4398 2.96% 99.64% # number of callpals executed -system.cpu0.kern.callpal::callsys 394 0.27% 99.91% # number of callpals executed -system.cpu0.kern.callpal::imb 139 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 148480 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6996 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1373 # number of protection mode switches +system.cpu0.kern.callpal::wripir 88 0.05% 0.05% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.05% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.05% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.05% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3942 2.08% 2.13% # number of callpals executed +system.cpu0.kern.callpal::tbi 51 0.03% 2.16% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.16% # number of callpals executed +system.cpu0.kern.callpal::swpipl 173212 91.45% 93.61% # number of callpals executed +system.cpu0.kern.callpal::rdps 6702 3.54% 97.15% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 97.15% # number of callpals executed +system.cpu0.kern.callpal::wrusp 4 0.00% 97.16% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.00% 97.16% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 97.16% # number of callpals executed +system.cpu0.kern.callpal::rti 4842 2.56% 99.72% # number of callpals executed +system.cpu0.kern.callpal::callsys 394 0.21% 99.93% # number of callpals executed +system.cpu0.kern.callpal::imb 139 0.07% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 189397 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7440 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1369 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1372 -system.cpu0.kern.mode_good::user 1373 +system.cpu0.kern.mode_good::kernel 1368 +system.cpu0.kern.mode_good::user 1369 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.196112 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.183871 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.327996 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1956039363000 99.80% 99.80% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3825014500 0.20% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.310705 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1958025785500 99.81% 99.81% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3814613000 0.19% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3062 # number of times the context was actually changed +system.cpu0.kern.swap_context 3943 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -932,47 +930,47 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.throughput 103923821 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2101274 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2101259 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 14151 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 14151 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 790404 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 17004 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 11907 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 28911 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 338243 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 296693 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 1383805 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 3109039 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 647529 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 472865 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count 5613238 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 44281088 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 118941040 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 20720896 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 17326866 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size 201269890 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 201259586 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 2417088 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4784493652 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks) +system.toL2Bus.throughput 105075557 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2099191 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2099176 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 12397 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 12397 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 820882 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 4248 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 894 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 5142 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 348581 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 307031 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 1842377 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 3534341 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 160357 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 115223 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count 5652298 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 58955328 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 137106504 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 5131392 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 4050090 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size 205243314 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 205232754 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 908800 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4911962990 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 742500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3113609997 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4148559004 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 5406966495 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 6195378103 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 1456953977 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 808879499 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 360929992 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 206344318 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 1400220 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 7373 # Transaction distribution -system.iobus.trans_dist::ReadResp 7373 # Transaction distribution -system.iobus.trans_dist::WriteReq 55703 # Transaction distribution -system.iobus.trans_dist::WriteResp 55703 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14090 # Packet count per connected master and slave (bytes) +system.iobus.throughput 1391673 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7377 # Transaction distribution +system.iobus.trans_dist::ReadResp 7377 # Transaction distribution +system.iobus.trans_dist::WriteReq 53949 # Transaction distribution +system.iobus.trans_dist::WriteResp 53949 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10582 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -984,10 +982,10 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 42700 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.cchip.pio 14090 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 39192 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83460 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83460 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.tsunami.cchip.pio 10582 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -998,10 +996,10 @@ system.iobus.pkt_count::system.tsunami.ide.pio 6672 system.iobus.pkt_count::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.iocache.cpu_side 83460 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 126152 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 56360 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 122652 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 42328 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -1013,10 +1011,10 @@ system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 82626 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.cchip.pio 56360 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 68594 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661648 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661648 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.tsunami.cchip.pio 42328 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -1027,11 +1025,11 @@ system.iobus.tot_pkt_size::system.tsunami.ide.pio 4193 system.iobus.tot_pkt_size::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.iocache.cpu_side 2661648 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 2744242 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 2744242 # Total data (bytes) -system.iobus.reqLayer0.occupancy 13445000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::total 2730242 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 2730242 # Total data (bytes) +system.iobus.reqLayer0.occupancy 9937000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1053,59 +1051,59 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 378246920 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 378297154 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 28549000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 26795000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42012000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 43124750 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.replacements 691283 # number of replacements -system.cpu0.icache.tagsinuse 508.523038 # Cycle average of tags in use -system.cpu0.icache.total_refs 47169081 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 691795 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 68.183611 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 38900732000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 508.523038 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.993209 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.993209 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 47169081 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 47169081 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 47169081 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 47169081 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 47169081 # number of overall hits -system.cpu0.icache.overall_hits::total 47169081 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 691913 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 691913 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 691913 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 691913 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 691913 # number of overall misses -system.cpu0.icache.overall_misses::total 691913 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9946018500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 9946018500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 9946018500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 9946018500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 9946018500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 9946018500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 47860994 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 47860994 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 47860994 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 47860994 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 47860994 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 47860994 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014457 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014457 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014457 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014457 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014457 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014457 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14374.666324 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14374.666324 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14374.666324 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14374.666324 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14374.666324 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14374.666324 # average overall miss latency +system.cpu0.icache.tags.replacements 920572 # number of replacements +system.cpu0.icache.tags.tagsinuse 508.501962 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 53689788 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 921084 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 58.289785 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 39101383250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.501962 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.993168 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.993168 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 53689788 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 53689788 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 53689788 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 53689788 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 53689788 # number of overall hits +system.cpu0.icache.overall_hits::total 53689788 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 921200 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 921200 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 921200 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 921200 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 921200 # number of overall misses +system.cpu0.icache.overall_misses::total 921200 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12937764004 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 12937764004 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 12937764004 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 12937764004 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 12937764004 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 12937764004 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 54610988 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 54610988 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 54610988 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 54610988 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 54610988 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 54610988 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016868 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.016868 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016868 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.016868 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016868 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.016868 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14044.468089 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14044.468089 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14044.468089 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14044.468089 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14044.468089 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14044.468089 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1114,112 +1112,112 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 691913 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 691913 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 691913 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 691913 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 691913 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 691913 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8562191003 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 8562191003 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8562191003 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 8562191003 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8562191003 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 8562191003 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014457 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014457 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014457 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014457 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014457 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014457 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12374.664160 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12374.664160 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12374.664160 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12374.664160 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12374.664160 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12374.664160 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 921200 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 921200 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 921200 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 921200 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 921200 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 921200 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11089045996 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 11089045996 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11089045996 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11089045996 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11089045996 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11089045996 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.016868 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.016868 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.016868 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.016868 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.016868 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.016868 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12037.609635 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12037.609635 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12037.609635 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12037.609635 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12037.609635 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12037.609635 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1181525 # number of replacements -system.cpu0.dcache.tagsinuse 505.231432 # Cycle average of tags in use -system.cpu0.dcache.total_refs 11411955 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1182037 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 9.654482 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 105721000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 505.231432 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.986780 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.986780 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6427043 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6427043 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4684362 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4684362 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139576 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 139576 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 146814 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 146814 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 11111405 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 11111405 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11111405 # number of overall hits -system.cpu0.dcache.overall_hits::total 11111405 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 936498 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 936498 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 255602 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 255602 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13508 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13508 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5738 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 5738 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1192100 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1192100 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1192100 # number of overall misses -system.cpu0.dcache.overall_misses::total 1192100 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 26205591500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 26205591500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 9945079500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 9945079500 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 146904500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 146904500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44028500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 44028500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 36150671000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 36150671000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 36150671000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 36150671000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7363541 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7363541 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4939964 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4939964 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 153084 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 153084 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 152552 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 152552 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12303505 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12303505 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12303505 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12303505 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127180 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.127180 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051742 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.051742 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088239 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088239 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.037613 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.037613 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.096891 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.096891 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.096891 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.096891 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27982.538671 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 27982.538671 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38908.457289 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38908.457289 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10875.370151 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10875.370151 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7673.143953 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7673.143953 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 30325.200067 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 30325.200067 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 30325.200067 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 30325.200067 # average overall miss latency +system.cpu0.dcache.tags.replacements 1349865 # number of replacements +system.cpu0.dcache.tags.tagsinuse 506.612721 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 13528796 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1350377 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 10.018533 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 105754250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.612721 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.989478 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.989478 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 7507195 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7507195 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5646858 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5646858 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 177791 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 177791 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 193304 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 193304 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 13154053 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 13154053 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 13154053 # number of overall hits +system.cpu0.dcache.overall_hits::total 13154053 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1040730 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1040730 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 297940 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 297940 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16884 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 16884 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 399 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 399 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1338670 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1338670 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1338670 # number of overall misses +system.cpu0.dcache.overall_misses::total 1338670 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 27787431256 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 27787431256 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10644315314 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 10644315314 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 223091000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 223091000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 2495533 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 2495533 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 38431746570 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 38431746570 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 38431746570 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 38431746570 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8547925 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8547925 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5944798 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5944798 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 194675 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 194675 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 193703 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 193703 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 14492723 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 14492723 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 14492723 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 14492723 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.121752 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.121752 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.050118 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.050118 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.086729 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.086729 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.002060 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.002060 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.092368 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.092368 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.092368 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.092368 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26699.942594 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 26699.942594 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35726.372135 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 35726.372135 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13213.160389 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13213.160389 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6254.468672 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6254.468672 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 28708.902545 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 28708.902545 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 28708.902545 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 28708.902545 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1228,62 +1226,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 678820 # number of writebacks -system.cpu0.dcache.writebacks::total 678820 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 936498 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 936498 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 255602 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 255602 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13508 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13508 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5737 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 5737 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1192100 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1192100 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1192100 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1192100 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 24332593005 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 24332593005 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9433875500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9433875500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 119888500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 119888500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 32554500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 32554500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 33766468505 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 33766468505 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 33766468505 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 33766468505 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465600500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465600500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2289389000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2289389000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3754989500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3754989500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127180 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127180 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051742 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051742 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088239 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088239 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.037607 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.037607 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096891 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.096891 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096891 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.096891 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 25982.536006 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 25982.536006 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36908.457289 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36908.457289 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8875.370151 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8875.370151 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5674.481436 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5674.481436 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 28325.197974 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28325.197974 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 28325.197974 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 28325.197974 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 798646 # number of writebacks +system.cpu0.dcache.writebacks::total 798646 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1040730 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 1040730 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 297940 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 297940 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16884 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16884 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 399 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 399 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1338670 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1338670 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1338670 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1338670 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25571734744 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25571734744 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9990567686 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9990567686 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 189290000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 189290000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 1697467 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1697467 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 35562302430 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 35562302430 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 35562302430 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 35562302430 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465580500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465580500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2094321000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2094321000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3559901500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3559901500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.121752 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.121752 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050118 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050118 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086729 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086729 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.002060 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.002060 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092368 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.092368 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092368 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.092368 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 24570.959561 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 24570.959561 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33532.146358 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33532.146358 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11211.205875 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11211.205875 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4254.303258 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4254.303258 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26565.398814 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26565.398814 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26565.398814 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26565.398814 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1295,22 +1293,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2417907 # DTB read hits +system.cpu1.dtb.read_hits 957039 # DTB read hits system.cpu1.dtb.read_misses 2620 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations system.cpu1.dtb.read_accesses 205337 # DTB read accesses -system.cpu1.dtb.write_hits 1735068 # DTB write hits +system.cpu1.dtb.write_hits 556340 # DTB write hits system.cpu1.dtb.write_misses 235 # DTB write misses system.cpu1.dtb.write_acv 24 # DTB write access violations system.cpu1.dtb.write_accesses 89739 # DTB write accesses -system.cpu1.dtb.data_hits 4152975 # DTB hits +system.cpu1.dtb.data_hits 1513379 # DTB hits system.cpu1.dtb.data_misses 2855 # DTB misses system.cpu1.dtb.data_acv 24 # DTB access violations system.cpu1.dtb.data_accesses 295076 # DTB accesses -system.cpu1.itb.fetch_hits 1826925 # ITB hits +system.cpu1.itb.fetch_hits 1320031 # ITB hits system.cpu1.itb.fetch_misses 1064 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1827989 # ITB accesses +system.cpu1.itb.fetch_accesses 1321095 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1323,51 +1321,51 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3917974909 # number of cpu cycles simulated +system.cpu1.numCycles 3921887017 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 13128564 # Number of instructions committed -system.cpu1.committedOps 13128564 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 12090481 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 177902 # Number of float alu accesses -system.cpu1.num_func_calls 416956 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1297332 # number of instructions that are conditional controls -system.cpu1.num_int_insts 12090481 # number of integer instructions -system.cpu1.num_fp_insts 177902 # number of float instructions -system.cpu1.num_int_register_reads 16603924 # number of times the integer registers were read -system.cpu1.num_int_register_writes 8888139 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 92328 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 94344 # number of times the floating registers were written -system.cpu1.num_mem_refs 4176284 # number of memory refs -system.cpu1.num_load_insts 2431879 # Number of load instructions -system.cpu1.num_store_insts 1744405 # Number of store instructions -system.cpu1.num_idle_cycles 3867819461.141509 # Number of idle cycles -system.cpu1.num_busy_cycles 50155447.858491 # Number of busy cycles -system.cpu1.not_idle_fraction 0.012801 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.987199 # Percentage of idle cycles +system.cpu1.committedInsts 4749746 # Number of instructions committed +system.cpu1.committedOps 4749746 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 4446088 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 30301 # Number of float alu accesses +system.cpu1.num_func_calls 145582 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 455512 # number of instructions that are conditional controls +system.cpu1.num_int_insts 4446088 # number of integer instructions +system.cpu1.num_fp_insts 30301 # number of float instructions +system.cpu1.num_int_register_reads 6169769 # number of times the integer registers were read +system.cpu1.num_int_register_writes 3384887 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 19629 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 19442 # number of times the floating registers were written +system.cpu1.num_mem_refs 1521715 # number of memory refs +system.cpu1.num_load_insts 962201 # Number of load instructions +system.cpu1.num_store_insts 559514 # Number of store instructions +system.cpu1.num_idle_cycles 3904242469.193159 # Number of idle cycles +system.cpu1.num_busy_cycles 17644547.806841 # Number of busy cycles +system.cpu1.not_idle_fraction 0.004499 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.995501 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2741 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 79425 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 27091 38.34% 38.34% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1969 2.79% 41.13% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 528 0.75% 41.87% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 41074 58.13% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 70662 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 26202 48.19% 48.19% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1969 3.62% 51.81% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 528 0.97% 52.78% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 25675 47.22% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 54374 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1908747944000 97.44% 97.44% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 700841000 0.04% 97.47% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 369371500 0.02% 97.49% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 49169268000 2.51% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1958987424500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.967185 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2329 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 33659 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 8392 30.97% 30.97% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1970 7.27% 38.24% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 88 0.32% 38.57% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 16645 61.43% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 27095 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 8384 44.74% 44.74% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1970 10.51% 55.26% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 88 0.47% 55.73% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 8296 44.27% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 18738 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1917649813500 97.79% 97.79% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 700167000 0.04% 97.83% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 60318500 0.00% 97.83% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 42533179500 2.17% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1960943478500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.999047 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.625091 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.769494 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.498408 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.691567 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed @@ -1383,81 +1381,81 @@ system.cpu1.kern.syscall::74 9 9.78% 96.74% # nu system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 92 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 445 0.61% 0.61% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.61% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.61% # number of callpals executed -system.cpu1.kern.callpal::swpctx 2045 2.80% 3.42% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.00% 3.42% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 3.43% # number of callpals executed -system.cpu1.kern.callpal::swpipl 64414 88.26% 91.69% # number of callpals executed -system.cpu1.kern.callpal::rdps 2145 2.94% 94.63% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 94.63% # number of callpals executed -system.cpu1.kern.callpal::wrusp 3 0.00% 94.63% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 94.64% # number of callpals executed -system.cpu1.kern.callpal::rti 3751 5.14% 99.78% # number of callpals executed -system.cpu1.kern.callpal::callsys 121 0.17% 99.94% # number of callpals executed -system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 6 0.02% 0.03% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal::swpctx 283 1.02% 1.06% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.01% 1.07% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.03% 1.09% # number of callpals executed +system.cpu1.kern.callpal::swpipl 22604 81.73% 82.82% # number of callpals executed +system.cpu1.kern.callpal::rdps 2147 7.76% 90.59% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 90.59% # number of callpals executed +system.cpu1.kern.callpal::wrusp 3 0.01% 90.60% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 90.61% # number of callpals executed +system.cpu1.kern.callpal::rti 2432 8.79% 99.41% # number of callpals executed +system.cpu1.kern.callpal::callsys 121 0.44% 99.84% # number of callpals executed +system.cpu1.kern.callpal::imb 42 0.15% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 72984 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1994 # number of protection mode switches -system.cpu1.kern.mode_switch::user 369 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2923 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 821 -system.cpu1.kern.mode_good::user 369 -system.cpu1.kern.mode_good::idle 452 -system.cpu1.kern.mode_switch_good::kernel 0.411735 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 27656 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 652 # number of protection mode switches +system.cpu1.kern.mode_switch::user 367 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2065 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 379 +system.cpu1.kern.mode_good::user 367 +system.cpu1.kern.mode_good::idle 12 +system.cpu1.kern.mode_switch_good::kernel 0.581288 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.154636 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.310632 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 18283551000 0.93% 0.93% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1485621000 0.08% 1.01% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1938326244500 98.99% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 2046 # number of times the context was actually changed -system.cpu1.icache.replacements 323214 # number of replacements -system.cpu1.icache.tagsinuse 446.824291 # Cycle average of tags in use -system.cpu1.icache.total_refs 12807678 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 323725 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 39.563450 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1958057375000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 446.824291 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.872704 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.872704 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 12807678 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 12807678 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 12807678 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 12807678 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 12807678 # number of overall hits -system.cpu1.icache.overall_hits::total 12807678 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 323765 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 323765 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 323765 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 323765 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 323765 # number of overall misses -system.cpu1.icache.overall_misses::total 323765 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4261948000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4261948000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4261948000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4261948000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4261948000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4261948000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 13131443 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 13131443 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 13131443 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 13131443 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 13131443 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 13131443 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024656 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.024656 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024656 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.024656 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024656 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.024656 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13163.708245 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13163.708245 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13163.708245 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13163.708245 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13163.708245 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13163.708245 # average overall miss latency +system.cpu1.kern.mode_switch_good::idle 0.005811 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.245785 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 2892019000 0.15% 0.15% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1487213000 0.08% 0.22% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1955685685000 99.78% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 284 # number of times the context was actually changed +system.cpu1.icache.tags.replacements 79630 # number of replacements +system.cpu1.icache.tags.tagsinuse 421.213832 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 4672446 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 80140 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 58.303544 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1959882431000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 421.213832 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.822683 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.822683 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 4672446 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 4672446 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 4672446 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 4672446 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 4672446 # number of overall hits +system.cpu1.icache.overall_hits::total 4672446 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 80179 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 80179 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 80179 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 80179 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 80179 # number of overall misses +system.cpu1.icache.overall_misses::total 80179 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1082064992 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 1082064992 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 1082064992 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 1082064992 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 1082064992 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 1082064992 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 4752625 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 4752625 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 4752625 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 4752625 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 4752625 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 4752625 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.016870 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.016870 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.016870 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.016870 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.016870 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.016870 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13495.615959 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13495.615959 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13495.615959 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13495.615959 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13495.615959 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13495.615959 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1466,112 +1464,112 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 323765 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 323765 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 323765 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 323765 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 323765 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 323765 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3614406523 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3614406523 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3614406523 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3614406523 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3614406523 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3614406523 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024656 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024656 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024656 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.024656 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024656 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.024656 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11163.672797 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11163.672797 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11163.672797 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11163.672797 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11163.672797 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11163.672797 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 80179 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 80179 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 80179 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 80179 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 80179 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 80179 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 921458008 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 921458008 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 921458008 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 921458008 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 921458008 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 921458008 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016870 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.016870 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.016870 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.016870 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.016870 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.016870 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11492.510608 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11492.510608 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11492.510608 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11492.510608 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11492.510608 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11492.510608 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 161925 # number of replacements -system.cpu1.dcache.tagsinuse 486.809606 # Cycle average of tags in use -system.cpu1.dcache.total_refs 3976206 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 162254 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 24.506058 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 70872567000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 486.809606 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.950800 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.950800 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 2251927 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2251927 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1621193 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1621193 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 49026 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 49026 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 51669 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 51669 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 3873120 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 3873120 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 3873120 # number of overall hits -system.cpu1.dcache.overall_hits::total 3873120 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 118911 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 118911 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 58093 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 58093 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9306 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 9306 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 6171 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 6171 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 177004 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 177004 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 177004 # number of overall misses -system.cpu1.dcache.overall_misses::total 177004 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1440878500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1440878500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1041850000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 1041850000 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 84410500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 84410500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 44897500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 44897500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 2482728500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 2482728500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 2482728500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 2482728500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2370838 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2370838 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1679286 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1679286 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 58332 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 58332 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 57840 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 57840 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 4050124 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 4050124 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 4050124 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 4050124 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.050156 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.050156 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034594 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.034594 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.159535 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.159535 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106691 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106691 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.043703 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.043703 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043703 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.043703 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12117.285196 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12117.285196 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17934.174513 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 17934.174513 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9070.545884 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9070.545884 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7275.563118 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7275.563118 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14026.397709 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 14026.397709 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14026.397709 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 14026.397709 # average overall miss latency +system.cpu1.dcache.tags.replacements 40890 # number of replacements +system.cpu1.dcache.tags.tagsinuse 416.865345 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 1457107 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 41228 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 35.342655 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 1941571028000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 416.865345 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.814190 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.814190 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 917421 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 917421 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 531046 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 531046 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 9250 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 9250 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 9554 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 9554 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 1448467 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 1448467 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 1448467 # number of overall hits +system.cpu1.dcache.overall_hits::total 1448467 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 31971 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 31971 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 13337 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 13337 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 850 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 850 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 495 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 495 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 45308 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 45308 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 45308 # number of overall misses +system.cpu1.dcache.overall_misses::total 45308 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 398942000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 398942000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 455916495 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 455916495 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 9380250 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 9380250 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3699073 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 3699073 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 854858495 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 854858495 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 854858495 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 854858495 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 949392 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 949392 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 544383 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 544383 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 10100 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 10100 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 10049 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 10049 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 1493775 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 1493775 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 1493775 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 1493775 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.033675 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.033675 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.024499 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.024499 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.084158 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.084158 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.049259 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.049259 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.030331 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.030331 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.030331 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.030331 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12478.245910 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12478.245910 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34184.336432 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 34184.336432 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11035.588235 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11035.588235 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7472.874747 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7472.874747 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18867.716408 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 18867.716408 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18867.716408 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 18867.716408 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1580,66 +1578,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 111584 # number of writebacks -system.cpu1.dcache.writebacks::total 111584 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 118911 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 118911 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 58093 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 58093 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9306 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9306 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6171 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 6171 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 177004 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 177004 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 177004 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 177004 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1203056001 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1203056001 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 925664000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 925664000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 65798500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 65798500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32557500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32557500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2128720001 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2128720001 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2128720001 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2128720001 # number of overall MSHR miss cycles +system.cpu1.dcache.writebacks::writebacks 22236 # number of writebacks +system.cpu1.dcache.writebacks::total 22236 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 31971 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 31971 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 13337 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 13337 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 850 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 850 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 495 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 495 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 45308 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 45308 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 45308 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 45308 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 334917000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 334917000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 427133505 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 427133505 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 7677750 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 7677750 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 2708927 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 2708927 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 762050505 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 762050505 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 762050505 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 762050505 # number of overall MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18768000 # number of ReadReq MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18768000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 722866000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 722866000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 741634000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 741634000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.050156 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.050156 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034594 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034594 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.159535 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.159535 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106691 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106691 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043703 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.043703 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043703 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.043703 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10117.281000 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10117.281000 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15934.174513 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15934.174513 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7070.545884 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7070.545884 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5275.887214 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5275.887214 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12026.394889 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12026.394889 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12026.394889 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12026.394889 # average overall mshr miss latency +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 527878500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 527878500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 546646500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 546646500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033675 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033675 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.024499 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.024499 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.084158 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.084158 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.049259 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.049259 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030331 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.030331 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030331 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.030331 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10475.649808 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10475.649808 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32026.205668 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32026.205668 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9032.647059 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9032.647059 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5472.579798 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5472.579798 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16819.336651 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16819.336651 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16819.336651 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16819.336651 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index e58c25cf4..fef6394c6 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,121 +1,121 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.918467 # Number of seconds simulated -sim_ticks 1918467182000 # Number of ticks simulated -final_tick 1918467182000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.918473 # Number of seconds simulated +sim_ticks 1918473094000 # Number of ticks simulated +final_tick 1918473094000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 829809 # Simulator instruction rate (inst/s) -host_op_rate 829809 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 28329510825 # Simulator tick rate (ticks/s) -host_mem_usage 306208 # Number of bytes of host memory used -host_seconds 67.72 # Real time elapsed on the host -sim_insts 56194431 # Number of instructions simulated -sim_ops 56194431 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 850752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24859200 # Number of bytes read from this memory +host_inst_rate 813863 # Simulator instruction rate (inst/s) +host_op_rate 813863 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 27788392408 # Simulator tick rate (ticks/s) +host_mem_usage 306196 # Number of bytes of host memory used +host_seconds 69.04 # Real time elapsed on the host +sim_insts 56188014 # Number of instructions simulated +sim_ops 56188014 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 850688 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24847488 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory -system.physmem.bytes_read::total 28362304 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 850752 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 850752 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7404544 # Number of bytes written to this memory -system.physmem.bytes_written::total 7404544 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 13293 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388425 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 28350528 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 850688 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 850688 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7389888 # Number of bytes written to this memory +system.physmem.bytes_written::total 7389888 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13292 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388242 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 443161 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115696 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115696 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 443454 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12957845 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1382537 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14783836 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 443454 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 443454 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3859615 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3859615 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3859615 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 443454 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12957845 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1382537 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18643451 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 443161 # Total number of read requests seen -system.physmem.writeReqs 115696 # Total number of write requests seen -system.physmem.cpureqs 558987 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28362304 # Total number of bytes read from memory -system.physmem.bytesWritten 7404544 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28362304 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7404544 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 54 # Number of read reqs serviced by write Q +system.physmem.num_reads::total 442977 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115467 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115467 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 443419 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12951700 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1382533 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14777652 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 443419 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 443419 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3851963 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3851963 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3851963 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 443419 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12951700 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1382533 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18629615 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 442977 # Total number of read requests seen +system.physmem.writeReqs 115467 # Total number of write requests seen +system.physmem.cpureqs 558574 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28350528 # Total number of bytes read from memory +system.physmem.bytesWritten 7389888 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28350528 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7389888 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 50 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 130 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 27850 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 28128 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 28329 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 28032 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 27520 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 27540 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 26738 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 26867 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 27896 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 27091 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 27744 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 27474 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 27482 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 28202 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 28119 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 28095 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7621 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7634 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7863 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7544 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7117 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 6982 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 6321 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6315 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7316 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6513 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7108 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6910 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7064 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7822 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7859 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7707 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 27963 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 28090 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 28297 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 28045 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 27408 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 27547 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 26911 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 26768 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 27805 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 27257 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 27713 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 27329 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 27431 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 28072 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 28025 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 28266 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7723 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7594 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7833 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7543 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7011 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 6984 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 6467 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 6223 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7221 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 6661 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7097 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 6780 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7013 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7721 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7774 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7822 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 1918455311000 # Total gap between requests +system.physmem.totGap 1918461222000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 443161 # Categorize read packet sizes +system.physmem.readPktSize::6 442977 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 115696 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 402425 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 6960 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5341 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3282 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3278 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3029 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1564 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1523 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1479 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1447 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1416 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1406 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1371 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 2035 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 2356 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2252 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1207 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 414 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 213 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 104 # What read queue length does an incoming req see +system.physmem.writePktSize::6 115467 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 402244 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 7043 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5311 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3263 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3253 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3011 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1562 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1513 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1478 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1450 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1424 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1426 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1399 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 2029 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 2311 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2193 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1221 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 460 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 219 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 112 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -128,236 +128,237 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3570 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3665 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5028 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5029 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5030 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5030 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5030 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5030 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5030 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5030 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5030 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5030 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5030 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5030 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5030 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5030 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5030 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5030 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5030 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5030 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5030 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5030 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1461 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1366 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 294 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3591 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5021 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1430 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1325 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 37346 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 957.575108 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 229.677714 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 2441.521254 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 13136 35.17% 35.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 5703 15.27% 50.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 3412 9.14% 59.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 2227 5.96% 65.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 1623 4.35% 69.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 1358 3.64% 73.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 966 2.59% 76.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 781 2.09% 78.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 632 1.69% 79.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 563 1.51% 81.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 543 1.45% 82.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 430 1.15% 84.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 310 0.83% 84.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 236 0.63% 85.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 166 0.44% 85.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 218 0.58% 86.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 124 0.33% 86.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 90 0.24% 87.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 81 0.22% 87.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 99 0.27% 87.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 87 0.23% 87.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 95 0.25% 88.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 1075 2.88% 90.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 150 0.40% 91.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 90 0.24% 91.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 48 0.13% 91.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 42 0.11% 91.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 35 0.09% 91.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 29 0.08% 91.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 22 0.06% 92.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 18 0.05% 92.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 29 0.08% 92.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 17 0.05% 92.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 5 0.01% 92.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 12 0.03% 92.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 7 0.02% 92.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 8 0.02% 92.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 4 0.01% 92.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 3 0.01% 92.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 3 0.01% 92.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 6 0.02% 92.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 5 0.01% 92.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 3 0.01% 92.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 5 0.01% 92.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 4 0.01% 92.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 2 0.01% 92.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 2 0.01% 92.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 4 0.01% 92.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 2 0.01% 92.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 6 0.02% 92.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 4 0.01% 92.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 5 0.01% 92.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 2 0.01% 92.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 1 0.00% 92.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 3 0.01% 92.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 1 0.00% 92.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3715 2 0.01% 92.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 3 0.01% 92.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3843 1 0.00% 92.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 3 0.01% 92.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3971 3 0.01% 92.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 1 0.00% 92.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 1 0.00% 92.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 1 0.00% 92.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 2 0.01% 92.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 1 0.00% 92.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4675 1 0.00% 92.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4739 2 0.01% 92.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 4 0.01% 92.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4995 1 0.00% 92.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5123 1 0.00% 92.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5315 2 0.01% 92.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5379 2 0.01% 92.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5699 2 0.01% 92.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5891 1 0.00% 92.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6083 1 0.00% 92.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6403 1 0.00% 92.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6595 1 0.00% 92.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6851 1 0.00% 92.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 2 0.01% 92.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7235 2 0.01% 92.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7299 2 0.01% 92.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7363 1 0.00% 92.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7555 1 0.00% 92.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7619 1 0.00% 92.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7683 1 0.00% 92.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7747 1 0.00% 92.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7811 1 0.00% 92.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7939 4 0.01% 92.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8003 3 0.01% 92.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8131 4 0.01% 92.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 2437 6.53% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9024-9027 1 0.00% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9219 1 0.00% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 37132 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 962.378541 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 229.718891 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 2449.750918 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 13161 35.44% 35.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 5591 15.06% 50.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 3357 9.04% 59.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 2263 6.09% 65.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 1589 4.28% 69.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 1303 3.51% 73.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 971 2.61% 76.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 731 1.97% 78.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 647 1.74% 79.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 569 1.53% 81.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 543 1.46% 82.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 425 1.14% 83.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 308 0.83% 84.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 237 0.64% 85.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 163 0.44% 85.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 235 0.63% 86.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 101 0.27% 86.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 93 0.25% 86.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 98 0.26% 87.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 98 0.26% 87.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 85 0.23% 87.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 107 0.29% 88.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 1046 2.82% 90.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 157 0.42% 91.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 87 0.23% 91.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 55 0.15% 91.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 46 0.12% 91.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 40 0.11% 91.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 31 0.08% 91.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 18 0.05% 91.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 16 0.04% 92.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 26 0.07% 92.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 19 0.05% 92.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 8 0.02% 92.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 8 0.02% 92.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 15 0.04% 92.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 14 0.04% 92.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 3 0.01% 92.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 3 0.01% 92.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 6 0.02% 92.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 4 0.01% 92.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 4 0.01% 92.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2755 1 0.00% 92.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 3 0.01% 92.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 2 0.01% 92.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 4 0.01% 92.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 2 0.01% 92.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 1 0.00% 92.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 3 0.01% 92.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3203 4 0.01% 92.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3267 2 0.01% 92.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3331 3 0.01% 92.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3395 3 0.01% 92.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 1 0.00% 92.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3523 4 0.01% 92.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3587 3 0.01% 92.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3651 1 0.00% 92.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3779 2 0.01% 92.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3843 1 0.00% 92.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3907 1 0.00% 92.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3971 1 0.00% 92.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4035 1 0.00% 92.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4099 1 0.00% 92.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4227 2 0.01% 92.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4291 1 0.00% 92.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4355 1 0.00% 92.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4419 3 0.01% 92.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4483 2 0.01% 92.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4675 1 0.00% 92.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4931 4 0.01% 92.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4995 2 0.01% 92.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5059 2 0.01% 92.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5123 1 0.00% 92.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5315 2 0.01% 92.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5443 2 0.01% 92.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5699 1 0.00% 92.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5763 1 0.00% 92.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5891 1 0.00% 92.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6083 1 0.00% 92.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6403 1 0.00% 92.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6595 1 0.00% 92.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6851 1 0.00% 92.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7171 3 0.01% 92.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7235 1 0.00% 92.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7299 2 0.01% 92.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7363 2 0.01% 92.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7555 1 0.00% 92.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7683 1 0.00% 92.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7747 1 0.00% 92.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7811 1 0.00% 92.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7939 3 0.01% 92.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8003 3 0.01% 92.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8131 4 0.01% 92.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8195 2437 6.56% 99.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8512-8515 1 0.00% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.15% # Bytes accessed per row activation system.physmem.bytesPerActivate::9728-9731 1 0.00% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10432-10435 1 0.00% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11712-11715 1 0.00% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13440-13443 1 0.00% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14211 1 0.00% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14272-14275 2 0.01% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14464-14467 2 0.01% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14528-14531 1 0.00% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14656-14659 1 0.00% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14720-14723 1 0.00% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14912-14915 2 0.01% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-14979 1 0.00% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15235 1 0.00% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15296-15299 1 0.00% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 15 0.04% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15744-15747 1 0.00% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15936-15939 1 0.00% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 239 0.64% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16448-16451 9 0.02% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16512-16515 8 0.02% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16576-16579 4 0.01% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16643 3 0.01% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16704-16707 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10176-10179 1 0.00% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10368-10371 1 0.00% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13760-13763 1 0.00% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14211 1 0.00% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14339 1 0.00% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14464-14467 1 0.00% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14656-14659 2 0.01% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14851 1 0.00% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14915 1 0.00% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15040-15043 1 0.00% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15296-15299 1 0.00% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 16 0.04% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15488-15491 1 0.00% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15744-15747 1 0.00% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 242 0.65% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16448-16451 9 0.02% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16512-16515 9 0.02% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16576-16579 3 0.01% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16643 3 0.01% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16704-16707 2 0.01% 99.97% # Bytes accessed per row activation system.physmem.bytesPerActivate::16768-16771 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16832-16835 2 0.01% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16899 2 0.01% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16960-16963 2 0.01% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17024-17027 4 0.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17536-17539 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 37346 # Bytes accessed per row activation -system.physmem.totQLat 3689041500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11833576500 # Sum of mem lat for all requests -system.physmem.totBusLat 2215535000 # Total cycles spent in databus access -system.physmem.totBankLat 5929000000 # Total cycles spent in bank access -system.physmem.avgQLat 8325.40 # Average queueing delay per request -system.physmem.avgBankLat 13380.52 # Average bank access latency per request +system.physmem.bytesPerActivate::16832-16835 4 0.01% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16960-16963 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17024-17027 3 0.01% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17344-17347 2 0.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 37132 # Bytes accessed per row activation +system.physmem.totQLat 3659130000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11798708750 # Sum of mem lat for all requests +system.physmem.totBusLat 2214635000 # Total cycles spent in databus access +system.physmem.totBankLat 5924943750 # Total cycles spent in bank access +system.physmem.avgQLat 8261.25 # Average queueing delay per request +system.physmem.avgBankLat 13376.80 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26705.91 # Average memory access latency +system.physmem.avgMemAccLat 26638.04 # Average memory access latency system.physmem.avgRdBW 14.78 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 3.86 # Average achieved write bandwidth in MB/s +system.physmem.avgWrBW 3.85 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 14.78 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 3.86 # Average consumed write bandwidth in MB/s +system.physmem.avgConsumedWrBW 3.85 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 11.67 # Average write queue length over time -system.physmem.readRowHits 427971 # Number of row buffer hits during reads -system.physmem.writeRowHits 93480 # Number of row buffer hits during writes -system.physmem.readRowHitRate 96.58 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.80 # Row buffer hit rate for writes -system.physmem.avgGap 3432819.69 # Average gap between requests -system.membus.throughput 18685123 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 292355 # Transaction distribution -system.membus.trans_dist::ReadResp 292355 # Transaction distribution +system.physmem.avgWrQLen 13.19 # Average write queue length over time +system.physmem.readRowHits 427838 # Number of row buffer hits during reads +system.physmem.writeRowHits 93417 # Number of row buffer hits during writes +system.physmem.readRowHitRate 96.59 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.90 # Row buffer hit rate for writes +system.physmem.avgGap 3435369.03 # Average gap between requests +system.membus.throughput 18671288 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 292313 # Transaction distribution +system.membus.trans_dist::ReadResp 292313 # Transaction distribution system.membus.trans_dist::WriteReq 9649 # Transaction distribution system.membus.trans_dist::WriteResp 9649 # Transaction distribution -system.membus.trans_dist::Writeback 115696 # Transaction distribution +system.membus.trans_dist::Writeback 115467 # Transaction distribution system.membus.trans_dist::UpgradeReq 132 # Transaction distribution system.membus.trans_dist::UpgradeResp 132 # Transaction distribution -system.membus.trans_dist::ReadExReq 158289 # Transaction distribution -system.membus.trans_dist::ReadExResp 158289 # Transaction distribution +system.membus.trans_dist::ReadExReq 158147 # Transaction distribution +system.membus.trans_dist::ReadExResp 158147 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33158 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878153 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911311 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 877556 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 910714 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124680 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124680 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.bridge.slave 33158 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 1002833 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1035991 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 1002236 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1035394 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44556 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30457728 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30502284 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30431296 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30475852 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309120 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 5309120 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::system.bridge.slave 44556 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 35766848 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 35811404 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 35811404 # Total data (bytes) +system.membus.tot_pkt_size::system.physmem.port 35740416 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 35784972 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 35784972 # Total data (bytes) system.membus.snoop_data_through_bus 35392 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 32374500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 32373000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1489970000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1487941500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 3747469854 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3745756604 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 376209000 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 376206000 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.345466 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. -system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1752554384000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.345466 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.084092 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.084092 # Average percentage of cache occupancy +system.iocache.tags.replacements 41685 # number of replacements +system.iocache.tags.tagsinuse 1.345474 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 1752558313000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.345474 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.084092 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.084092 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -366,14 +367,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21342883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21342883 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 10435666030 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10435666030 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 10457008913 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10457008913 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 10457008913 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10457008913 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21343633 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21343633 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 10434225282 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10434225282 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 10455568915 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10455568915 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 10455568915 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10455568915 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -390,19 +391,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 123369.265896 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 123369.265896 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 251147.141654 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 251147.141654 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 250617.349623 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 250617.349623 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 250617.349623 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 250617.349623 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 271244 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 123373.601156 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 123373.601156 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 251112.468281 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 251112.468281 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 250582.837987 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 250582.837987 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 250582.837987 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 250582.837987 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 272640 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27003 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27184 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.044958 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.029429 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -418,12 +419,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41725 system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12346133 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 12346133 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8274278780 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8274278780 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 8286624913 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8286624913 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 8286624913 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8286624913 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8272160782 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8272160782 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 8284506915 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8284506915 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 8284506915 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8284506915 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -434,12 +435,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 71364.930636 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 71364.930636 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 199130.698402 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 199130.698402 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 198600.956573 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 198600.956573 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 198600.956573 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 198600.956573 # average overall mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 199079.726174 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 199079.726174 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 198550.195686 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 198550.195686 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 198550.195686 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 198550.195686 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -457,22 +458,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9066498 # DTB read hits +system.cpu.dtb.read_hits 9065600 # DTB read hits system.cpu.dtb.read_misses 10324 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations system.cpu.dtb.read_accesses 728853 # DTB read accesses -system.cpu.dtb.write_hits 6357377 # DTB write hits +system.cpu.dtb.write_hits 6356756 # DTB write hits system.cpu.dtb.write_misses 1142 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations system.cpu.dtb.write_accesses 291931 # DTB write accesses -system.cpu.dtb.data_hits 15423875 # DTB hits +system.cpu.dtb.data_hits 15422356 # DTB hits system.cpu.dtb.data_misses 11466 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations system.cpu.dtb.data_accesses 1020784 # DTB accesses -system.cpu.itb.fetch_hits 4974559 # ITB hits +system.cpu.itb.fetch_hits 4974352 # ITB hits system.cpu.itb.fetch_misses 5010 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4979569 # ITB accesses +system.cpu.itb.fetch_accesses 4979362 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -485,51 +486,51 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3836934364 # number of cpu cycles simulated +system.cpu.numCycles 3836946188 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56194431 # Number of instructions committed -system.cpu.committedOps 56194431 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 52065988 # Number of integer alu accesses +system.cpu.committedInsts 56188014 # Number of instructions committed +system.cpu.committedOps 56188014 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 52059797 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 324527 # Number of float alu accesses -system.cpu.num_func_calls 1483664 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 6469615 # number of instructions that are conditional controls -system.cpu.num_int_insts 52065988 # number of integer instructions +system.cpu.num_func_calls 1483456 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 6468822 # number of instructions that are conditional controls +system.cpu.num_int_insts 52059797 # number of integer instructions system.cpu.num_fp_insts 324527 # number of float instructions -system.cpu.num_int_register_reads 71339773 # number of times the integer registers were read -system.cpu.num_int_register_writes 38529890 # number of times the integer registers were written +system.cpu.num_int_register_reads 71330046 # number of times the integer registers were read +system.cpu.num_int_register_writes 38525190 # number of times the integer registers were written system.cpu.num_fp_register_reads 163675 # number of times the floating registers were read system.cpu.num_fp_register_writes 166554 # number of times the floating registers were written -system.cpu.num_mem_refs 15476497 # number of memory refs -system.cpu.num_load_insts 9103354 # Number of load instructions -system.cpu.num_store_insts 6373143 # Number of store instructions -system.cpu.num_idle_cycles 3587701469.998130 # Number of idle cycles -system.cpu.num_busy_cycles 249232894.001870 # Number of busy cycles -system.cpu.not_idle_fraction 0.064956 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.935044 # Percentage of idle cycles +system.cpu.num_mem_refs 15474978 # number of memory refs +system.cpu.num_load_insts 9102456 # Number of load instructions +system.cpu.num_store_insts 6372522 # Number of store instructions +system.cpu.num_idle_cycles 3586988416.498130 # Number of idle cycles +system.cpu.num_busy_cycles 249957771.501870 # Number of busy cycles +system.cpu.not_idle_fraction 0.065145 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.934855 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6375 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 212005 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74904 40.89% 40.89% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211982 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74893 40.89% 40.89% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1931 1.05% 42.01% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 106221 57.99% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183187 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73537 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 106209 57.99% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183164 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73526 49.31% 49.31% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1931 1.29% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73537 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149136 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1857459158500 96.82% 96.82% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 91312500 0.00% 96.82% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 736664500 0.04% 96.86% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 60179312500 3.14% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1918466448000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981750 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::31 73526 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149114 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1857159489000 96.80% 96.80% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 91367000 0.00% 96.81% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 736929000 0.04% 96.85% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 60484575000 3.15% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1918472360000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981747 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.692302 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814119 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.692277 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814101 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -568,7 +569,7 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4178 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175968 91.22% 93.42% # number of callpals executed +system.cpu.kern.callpal::swpipl 175945 91.21% 93.41% # number of callpals executed system.cpu.kern.callpal::rdps 6832 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed @@ -577,20 +578,20 @@ system.cpu.kern.callpal::whami 2 0.00% 96.97% # nu system.cpu.kern.callpal::rti 5156 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192914 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5904 # number of protection mode switches +system.cpu.kern.callpal::total 192891 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5903 # number of protection mode switches system.cpu.kern.mode_switch::user 1740 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches system.cpu.kern.mode_good::kernel 1911 system.cpu.kern.mode_good::user 1740 system.cpu.kern.mode_good::idle 171 -system.cpu.kern.mode_switch_good::kernel 0.323679 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.323734 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081584 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::total 0.392402 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 46102035000 2.40% 2.40% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5243076000 0.27% 2.68% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1867121335000 97.32% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::kernel 46124802000 2.40% 2.40% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5245072500 0.27% 2.68% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1867102483500 97.32% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4179 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -623,7 +624,7 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.iobus.throughput 1410587 # Throughput (bytes/s) +system.iobus.throughput 1410582 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution system.iobus.trans_dist::WriteReq 51201 # Transaction distribution @@ -709,59 +710,59 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 378256913 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 378268915 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23509000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42010000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 43091000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.replacements 928573 # number of replacements -system.cpu.icache.tagsinuse 508.447268 # Cycle average of tags in use -system.cpu.icache.total_refs 55277021 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 929084 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 59.496258 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 38501717000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 508.447268 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.993061 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.993061 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 55277021 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 55277021 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 55277021 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 55277021 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 55277021 # number of overall hits -system.cpu.icache.overall_hits::total 55277021 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 929244 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 929244 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 929244 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 929244 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 929244 # number of overall misses -system.cpu.icache.overall_misses::total 929244 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12990910500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12990910500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12990910500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12990910500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12990910500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12990910500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 56206265 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 56206265 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 56206265 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 56206265 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 56206265 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 56206265 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016533 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.016533 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.016533 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.016533 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.016533 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.016533 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13980.085424 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13980.085424 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13980.085424 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13980.085424 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13980.085424 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13980.085424 # average overall miss latency +system.cpu.icache.tags.replacements 928665 # number of replacements +system.cpu.icache.tags.tagsinuse 508.413691 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 55270512 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 929176 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 59.483362 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 38814414250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 508.413691 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.992995 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.992995 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 55270512 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 55270512 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 55270512 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 55270512 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 55270512 # number of overall hits +system.cpu.icache.overall_hits::total 55270512 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 929336 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 929336 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 929336 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 929336 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 929336 # number of overall misses +system.cpu.icache.overall_misses::total 929336 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13015346257 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13015346257 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13015346257 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13015346257 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13015346257 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13015346257 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 56199848 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 56199848 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 56199848 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 56199848 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 56199848 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 56199848 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016536 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.016536 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.016536 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.016536 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.016536 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.016536 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14004.995241 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14004.995241 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14004.995241 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14004.995241 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14004.995241 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14004.995241 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -770,126 +771,126 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929244 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 929244 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 929244 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 929244 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 929244 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 929244 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11132422500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11132422500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11132422500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11132422500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11132422500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11132422500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016533 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016533 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016533 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.016533 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016533 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.016533 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11980.085424 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11980.085424 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11980.085424 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11980.085424 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11980.085424 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11980.085424 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929336 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 929336 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 929336 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 929336 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 929336 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 929336 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11150220743 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11150220743 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11150220743 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11150220743 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11150220743 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11150220743 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016536 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016536 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016536 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.016536 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016536 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.016536 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11998.051020 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11998.051020 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11998.051020 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11998.051020 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11998.051020 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11998.051020 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 336249 # number of replacements -system.cpu.l2cache.tagsinuse 65299.317705 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2448334 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 401410 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 6.099335 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 6517964750 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 55625.043454 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 4760.305477 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 4913.968774 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.848771 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.072636 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.074981 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.996389 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 915931 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 815128 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1731059 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 835526 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 835526 # number of Writeback hits +system.cpu.l2cache.tags.replacements 336065 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65300.870394 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2448301 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 401226 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 6.102050 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 6580892750 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 55613.136753 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 4759.199410 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 4928.534231 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.848589 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072620 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.075203 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.996412 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 916024 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 814969 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1730993 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 835407 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 835407 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 187585 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 187585 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 915931 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1002713 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1918644 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 915931 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1002713 # number of overall hits -system.cpu.l2cache.overall_hits::total 1918644 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 13293 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 271959 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 285252 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_hits::cpu.data 187779 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 187779 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 916024 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1002748 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1918772 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 916024 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1002748 # number of overall hits +system.cpu.l2cache.overall_hits::total 1918772 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 13292 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 271918 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 285210 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 13 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 13 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 116856 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 116856 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 13293 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 388815 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 402108 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 13293 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 388815 # number of overall misses -system.cpu.l2cache.overall_misses::total 402108 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1043848500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 16878045500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 17921894000 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 189500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 189500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7749920500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 7749920500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1043848500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 24627966000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 25671814500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1043848500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 24627966000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 25671814500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 929224 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1087087 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2016311 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 835526 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 835526 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_misses::cpu.data 116714 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 116714 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 13292 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 388632 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 401924 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 13292 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 388632 # number of overall misses +system.cpu.l2cache.overall_misses::total 401924 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1060624743 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 16925556244 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 17986180987 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 190498 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 190498 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7757662128 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 7757662128 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1060624743 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 24683218372 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 25743843115 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1060624743 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 24683218372 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 25743843115 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 929316 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1086887 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2016203 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 835407 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 835407 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 304441 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 304441 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 929224 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1391528 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2320752 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 929224 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1391528 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2320752 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014305 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250172 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.141472 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 304493 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 304493 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 929316 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1391380 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2320696 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 929316 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1391380 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2320696 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014303 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250181 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.141459 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.764706 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.764706 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383838 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.383838 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014305 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.279416 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.173266 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014305 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.279416 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.173266 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 78526.179192 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 62060.992650 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 62828.285165 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 14576.923077 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 14576.923077 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66320.261690 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66320.261690 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78526.179192 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 63341.090236 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 63843.083202 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78526.179192 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 63341.090236 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 63843.083202 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383306 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.383306 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014303 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.279314 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.173191 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014303 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.279314 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.173191 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79794.217800 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 62245.074780 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 63062.939543 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 14653.692308 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 14653.692308 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66467.280086 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66467.280086 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79794.217800 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 63513.087888 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 64051.519976 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79794.217800 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 63513.087888 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 64051.519976 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -898,66 +899,66 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 74184 # number of writebacks -system.cpu.l2cache.writebacks::total 74184 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13293 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271959 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 285252 # number of ReadReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 73955 # number of writebacks +system.cpu.l2cache.writebacks::total 73955 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13292 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271918 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 285210 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116856 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 116856 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 13293 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 388815 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 402108 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 13293 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 388815 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 402108 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 879542258 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13544515256 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14424057514 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116714 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 116714 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 13292 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 388632 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 401924 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 13292 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 388632 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 401924 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 893093257 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13525299756 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14418393013 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 230011 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 230011 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6316543121 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6316543121 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 879542258 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19861058377 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 20740600635 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 879542258 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19861058377 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 20740600635 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334145000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334145000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6297401372 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6297401372 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 893093257 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19822701128 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 20715794385 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 893093257 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19822701128 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 20715794385 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334143500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334143500 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1895431500 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1895431500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3229576500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3229576500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014305 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250172 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141472 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3229575000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3229575000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014303 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250181 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141459 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383838 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383838 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014305 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279416 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.173266 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014305 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279416 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.173266 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66165.820958 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 49803.519119 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 50566.017115 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383306 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383306 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014303 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279314 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.173191 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014303 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279314 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.173191 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67190.284156 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 49740.362006 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 50553.602654 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17693.153846 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17693.153846 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54054.076136 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54054.076136 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66165.820958 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 51080.998359 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 51579.676691 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66165.820958 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 51080.998359 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 51579.676691 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 53955.835392 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53955.835392 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67190.284156 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 51006.353383 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 51541.571006 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67190.284156 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 51006.353383 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 51541.571006 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -965,79 +966,79 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1391015 # number of replacements -system.cpu.dcache.tagsinuse 511.979232 # Cycle average of tags in use -system.cpu.dcache.total_refs 14051400 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1391527 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 10.097828 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 105127000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.979232 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999959 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999959 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 7815804 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7815804 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5853333 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5853333 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 182999 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 182999 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 199247 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 199247 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13669137 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13669137 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13669137 # number of overall hits -system.cpu.dcache.overall_hits::total 13669137 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1069817 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1069817 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 304458 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 304458 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17270 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17270 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1374275 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1374275 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1374275 # number of overall misses -system.cpu.dcache.overall_misses::total 1374275 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 28060990500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 28060990500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10539571500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10539571500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 229596000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 229596000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 38600562000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 38600562000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 38600562000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 38600562000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 8885621 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 8885621 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6157791 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6157791 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200269 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200269 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 199247 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 199247 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15043412 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15043412 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15043412 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15043412 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120399 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.120399 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049443 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.049443 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086234 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086234 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.091354 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.091354 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.091354 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.091354 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26229.710782 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 26229.710782 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34617.489112 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34617.489112 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13294.499131 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13294.499131 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 28087.946008 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 28087.946008 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 28087.946008 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 28087.946008 # average overall miss latency +system.cpu.dcache.tags.replacements 1390866 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.979110 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 14050029 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1391378 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 10.097924 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 105729250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.979110 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999959 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999959 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 7815067 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7815067 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5852671 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5852671 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183038 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183038 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199236 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 199236 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13667738 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13667738 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13667738 # number of overall hits +system.cpu.dcache.overall_hits::total 13667738 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1069668 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1069668 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304510 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304510 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17219 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17219 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1374178 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1374178 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1374178 # number of overall misses +system.cpu.dcache.overall_misses::total 1374178 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 28240934256 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 28240934256 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10606589383 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10606589383 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 229410500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 229410500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 38847523639 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 38847523639 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 38847523639 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 38847523639 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 8884735 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 8884735 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6157181 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6157181 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200257 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200257 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199236 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199236 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15041916 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15041916 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15041916 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15041916 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120394 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120394 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049456 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049456 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085985 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085985 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.091357 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.091357 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.091357 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.091357 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26401.588396 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26401.588396 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34831.661959 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34831.661959 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13323.102387 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13323.102387 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 28269.644572 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 28269.644572 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 28269.644572 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 28269.644572 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1046,54 +1047,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 835526 # number of writebacks -system.cpu.dcache.writebacks::total 835526 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069817 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1069817 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304458 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304458 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17270 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17270 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1374275 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1374275 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1374275 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1374275 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 25921356500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 25921356500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9930655500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9930655500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 195056000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 195056000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 35852012000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 35852012000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 35852012000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 35852012000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424235000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424235000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.writebacks::writebacks 835407 # number of writebacks +system.cpu.dcache.writebacks::total 835407 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069668 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1069668 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304510 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 304510 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17219 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17219 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1374178 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1374178 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1374178 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1374178 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 25967193744 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 25967193744 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9940394617 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9940394617 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 194939500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 194939500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 35907588361 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 35907588361 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 35907588361 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 35907588361 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424233500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424233500 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011219500 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011219500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435454500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435454500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120399 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120399 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049443 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049443 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086234 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086234 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091354 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091354 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091354 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091354 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24229.710782 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24229.710782 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32617.489112 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32617.489112 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11294.499131 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11294.499131 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26087.946008 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26087.946008 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26087.946008 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26087.946008 # average overall mshr miss latency +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435453000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435453000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120394 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120394 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049456 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049456 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085985 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085985 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091357 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091357 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091357 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091357 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24275.937715 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24275.937715 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32643.902062 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32643.902062 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11321.185899 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11321.185899 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26130.230844 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26130.230844 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26130.230844 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26130.230844 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1101,31 +1102,31 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 105322456 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2023434 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2023417 # Transaction distribution +system.cpu.toL2Bus.throughput 105316327 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2023326 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2023309 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9649 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9649 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 835526 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 835407 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 345993 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304442 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1858468 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3651931 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 5510399 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 59470336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 142586060 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 202056396 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 202046348 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 11328 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2426797500 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::ReadExReq 346045 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304495 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1858652 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3651517 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 5510169 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 59476224 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 142569036 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 202045260 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 202035148 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 11392 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 2426591000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 237000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1393866000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1397230757 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2099055000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2194639139 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index 57671b2bd..29541c768 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -233,29 +233,29 @@ system.realview.nvmem.bw_total::total 75 # To system.membus.throughput 64986577 # Throughput (bytes/s) system.membus.data_through_bus 59274047 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.l2c.replacements 70658 # number of replacements -system.l2c.tagsinuse 51560.149653 # Cycle average of tags in use -system.l2c.total_refs 1623339 # Total number of references to valid blocks. -system.l2c.sampled_refs 135810 # Sample count of references to valid blocks. -system.l2c.avg_refs 11.953015 # Average number of references to valid blocks. -system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 39278.694978 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 0.000049 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.001108 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4358.955639 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 2482.445004 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 2.678940 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 2126.451282 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 3310.922653 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.599345 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.066512 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.037879 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000041 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.032447 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.050521 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.786745 # Average percentage of cache occupancy +system.l2c.tags.replacements 70658 # number of replacements +system.l2c.tags.tagsinuse 51560.149653 # Cycle average of tags in use +system.l2c.tags.total_refs 1623339 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 135810 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 11.953015 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 39278.694978 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000049 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001108 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4358.955639 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2482.445004 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.678940 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2126.451282 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3310.922653 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.599345 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.066512 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.037879 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000041 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.032447 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.050521 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.786745 # Average percentage of cache occupancy system.l2c.ReadReq_hits::cpu0.dtb.walker 3874 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 1919 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.inst 421038 # number of ReadReq hits @@ -486,15 +486,15 @@ system.cpu0.not_idle_fraction 0.021750 # Pe system.cpu0.idle_fraction 0.978250 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 49966 # number of quiesce instructions executed -system.cpu0.icache.replacements 428546 # number of replacements -system.cpu0.icache.tagsinuse 511.015216 # Cycle average of tags in use -system.cpu0.icache.total_refs 29811115 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 429058 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 69.480385 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 64537139000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.015216 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.998077 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.998077 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 428546 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.015216 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 29811115 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 429058 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 69.480385 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 64537139000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.015216 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998077 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998077 # Average percentage of cache occupancy system.cpu0.icache.ReadReq_hits::cpu0.inst 29811115 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 29811115 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 29811115 # number of demand (read+write) hits @@ -528,15 +528,15 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 323609 # number of replacements -system.cpu0.dcache.tagsinuse 494.763091 # Cycle average of tags in use -system.cpu0.dcache.total_refs 12467604 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 323981 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 38.482516 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 22115000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 494.763091 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.966334 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.966334 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 323609 # number of replacements +system.cpu0.dcache.tags.tagsinuse 494.763091 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 12467604 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 323981 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 38.482516 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 22115000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.763091 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966334 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.966334 # Average percentage of cache occupancy system.cpu0.dcache.ReadReq_hits::cpu0.data 6512305 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 6512305 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 5630881 # number of WriteReq hits @@ -662,15 +662,15 @@ system.cpu1.not_idle_fraction 0.022362 # Pe system.cpu1.idle_fraction 0.977638 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 40379 # number of quiesce instructions executed -system.cpu1.icache.replacements 433942 # number of replacements -system.cpu1.icache.tagsinuse 475.447912 # Cycle average of tags in use -system.cpu1.icache.total_refs 31979125 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 434454 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 73.607620 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 69967763000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 475.447912 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.928609 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.928609 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 433942 # number of replacements +system.cpu1.icache.tags.tagsinuse 475.447912 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 31979125 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 434454 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 73.607620 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 69967763000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 475.447912 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.928609 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.928609 # Average percentage of cache occupancy system.cpu1.icache.ReadReq_hits::cpu1.inst 31979125 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 31979125 # number of ReadReq hits system.cpu1.icache.demand_hits::cpu1.inst 31979125 # number of demand (read+write) hits @@ -704,15 +704,15 @@ system.cpu1.icache.avg_blocked_cycles::no_targets nan system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 294289 # number of replacements -system.cpu1.dcache.tagsinuse 447.573682 # Cycle average of tags in use -system.cpu1.dcache.total_refs 11707745 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 294801 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 39.714061 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 67293493000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 447.573682 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.874167 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.874167 # Average percentage of cache occupancy +system.cpu1.dcache.tags.replacements 294289 # number of replacements +system.cpu1.dcache.tags.tagsinuse 447.573682 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 11707745 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 294801 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 39.714061 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 67293493000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 447.573682 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.874167 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.874167 # Average percentage of cache occupancy system.cpu1.dcache.ReadReq_hits::cpu1.data 7002209 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 7002209 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 4520313 # number of WriteReq hits @@ -772,12 +772,12 @@ system.cpu1.dcache.cache_copies 0 # nu system.cpu1.dcache.writebacks::writebacks 266849 # number of writebacks system.cpu1.dcache.writebacks::total 266849 # number of writebacks system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 0 # number of replacements -system.iocache.tagsinuse 0 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.avg_refs nan # Average number of references to valid blocks. -system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.iocache.tags.replacements 0 # number of replacements +system.iocache.tags.tagsinuse 0 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs nan # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index 979b75345..486d98045 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -284,15 +284,15 @@ system.cpu.not_idle_fraction 0.016889 # Pe system.cpu.idle_fraction 0.983111 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 82795 # number of quiesce instructions executed -system.cpu.icache.replacements 850590 # number of replacements -system.cpu.icache.tagsinuse 511.678593 # Cycle average of tags in use -system.cpu.icache.total_refs 60583498 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 851102 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 71.182418 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 5709383000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.678593 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.999372 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.999372 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 850590 # number of replacements +system.cpu.icache.tags.tagsinuse 511.678593 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 60583498 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 851102 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 71.182418 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 5709383000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.678593 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999372 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999372 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 60583498 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 60583498 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 60583498 # number of demand (read+write) hits @@ -326,23 +326,23 @@ system.cpu.icache.avg_blocked_cycles::no_targets nan system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 62243 # number of replacements -system.cpu.l2cache.tagsinuse 50007.272909 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1669922 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 127628 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 13.084292 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 2316901489000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 36899.582990 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.dtb.walker 2.960148 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.993931 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 7014.720482 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 6089.015357 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.563043 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.107036 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.092911 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.763050 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 62243 # number of replacements +system.cpu.l2cache.tags.tagsinuse 50007.272909 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1669922 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 127628 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 13.084292 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 2316901489000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 36899.582990 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.960148 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.993931 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 7014.720482 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 6089.015357 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.563043 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.107036 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.092911 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.763050 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7507 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3129 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.inst 838871 # number of ReadReq hits @@ -434,15 +434,15 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks::writebacks 57863 # number of writebacks system.cpu.l2cache.writebacks::total 57863 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 623337 # number of replacements -system.cpu.dcache.tagsinuse 511.997031 # Cycle average of tags in use -system.cpu.dcache.total_refs 23628343 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 623849 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 37.875100 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 21763000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.997031 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 623337 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.997031 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 23628343 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 623849 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37.875100 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 21763000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.997031 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 13180066 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 13180066 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 9962072 # number of WriteReq hits @@ -501,12 +501,12 @@ system.cpu.dcache.no_allocate_misses 0 # Nu system.cpu.toL2Bus.throughput 59102649 # Throughput (bytes/s) system.cpu.toL2Bus.data_through_bus 137875266 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.iocache.replacements 0 # number of replacements -system.iocache.tagsinuse 0 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.avg_refs nan # Average number of references to valid blocks. -system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.iocache.tags.replacements 0 # number of replacements +system.iocache.tags.tagsinuse 0 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs nan # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 7372967ce..7e08761d9 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,104 +1,104 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.194897 # Number of seconds simulated -sim_ticks 1194896580500 # Number of ticks simulated -final_tick 1194896580500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.194911 # Number of seconds simulated +sim_ticks 1194911360500 # Number of ticks simulated +final_tick 1194911360500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 311660 # Simulator instruction rate (inst/s) -host_op_rate 397163 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6068013925 # Simulator tick rate (ticks/s) -host_mem_usage 403588 # Number of bytes of host memory used -host_seconds 196.92 # Real time elapsed on the host -sim_insts 61371297 # Number of instructions simulated -sim_ops 78208202 # Number of ops (including micro ops) simulated +host_inst_rate 773513 # Simulator instruction rate (inst/s) +host_op_rate 985724 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15060857671 # Simulator tick rate (ticks/s) +host_mem_usage 403580 # Number of bytes of host memory used +host_seconds 79.34 # Real time elapsed on the host +sim_insts 61369589 # Number of instructions simulated +sim_ops 78206230 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 463972 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 6626100 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 464036 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 6626228 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 255836 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2904240 # Number of bytes read from this memory -system.physmem.bytes_read::total 62155108 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 463972 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 255836 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 719808 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4136192 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 256092 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2904304 # Number of bytes read from this memory +system.physmem.bytes_read::total 62155620 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 464036 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 256092 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 720128 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4136576 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 3027304 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 7163536 # Number of bytes written to this memory +system.physmem.bytes_written::total 7163920 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 13468 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 103605 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 13469 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 103607 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 4079 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 45405 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6654628 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 64628 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.inst 4083 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 45406 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6654636 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 64634 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 756826 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 821464 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43438497 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 821470 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43437960 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 214 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 107 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 388295 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 5545333 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 388343 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 5545372 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 54 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 214107 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2430537 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52017144 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 388295 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 214107 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 602402 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3461548 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 2533528 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 214319 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 2430560 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52016930 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 388343 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 214319 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 602662 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3461827 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 2533497 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 33 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 5995110 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3461548 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43438497 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 5995357 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3461827 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43437960 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 214 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 107 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 388295 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 8078862 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 388343 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 8078869 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 54 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 214107 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2430570 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 58012254 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6654628 # Total number of read requests seen -system.physmem.writeReqs 821464 # Total number of write requests seen +system.physmem.bw_total::cpu1.inst 214319 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2430594 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 58012286 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 6654636 # Total number of read requests seen +system.physmem.writeReqs 821470 # Total number of write requests seen system.physmem.cpureqs 235013 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 425896192 # Total number of bytes read from memory -system.physmem.bytesWritten 52573696 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 62155108 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7163536 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 139 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 10646 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 415731 # Track reads on a per bank basis +system.physmem.bytesRead 425896704 # Total number of bytes read from memory +system.physmem.bytesWritten 52574080 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 62155620 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7163920 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 138 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 10632 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 415730 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 415559 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 414958 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 414961 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 415336 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 422399 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 415419 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 415520 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 415298 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 415301 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 415351 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 415631 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 415270 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 414902 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 415547 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 416079 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 416081 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 415762 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 415727 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 415729 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 50036 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 49924 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 51324 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 51325 # Track writes on a per bank basis system.physmem.perBankWrReqs::3 51581 # Track writes on a per bank basis system.physmem.perBankWrReqs::4 51864 # Track writes on a per bank basis system.physmem.perBankWrReqs::5 51435 # Track writes on a per bank basis system.physmem.perBankWrReqs::6 51646 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51464 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51467 # Track writes on a per bank basis system.physmem.perBankWrReqs::8 51327 # Track writes on a per bank basis system.physmem.perBankWrReqs::9 51592 # Track writes on a per bank basis system.physmem.perBankWrReqs::10 51318 # Track writes on a per bank basis @@ -106,41 +106,41 @@ system.physmem.perBankWrReqs::11 51082 # Tr system.physmem.perBankWrReqs::12 51567 # Track writes on a per bank basis system.physmem.perBankWrReqs::13 51872 # Track writes on a per bank basis system.physmem.perBankWrReqs::14 51738 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51694 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51696 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 1194892168500 # Total gap between requests +system.physmem.totGap 1194906959500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 6825 # Categorize read packet sizes system.physmem.readPktSize::3 6488064 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 159739 # Categorize read packet sizes +system.physmem.readPktSize::6 159747 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 756836 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 64628 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 581008 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 419779 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 439715 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1589810 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1189300 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1185139 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1157962 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 13029 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 10446 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 15424 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 20310 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 15138 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 4570 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 4445 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 4292 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 4046 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 75 # What read queue length does an incoming req see +system.physmem.writePktSize::6 64634 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 581277 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 421174 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 435266 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1590102 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1186915 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1183214 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1164468 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 13127 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 10448 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 15751 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 21053 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 15489 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 4169 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 4068 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 3980 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 3919 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 77 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -156,10 +156,10 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 35692 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 35713 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 35715 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 35715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 35694 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 35715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 35716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 35716 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 35716 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 35716 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 35716 # What write queue length does an incoming req see @@ -175,304 +175,302 @@ system.physmem.wrQLenPdf::15 35716 # Wh system.physmem.wrQLenPdf::16 35716 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 35716 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 35716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35715 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35715 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35715 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35715 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 34609 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 13824.665723 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 735.190153 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 27804.066503 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-127 7914 22.87% 22.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-191 4043 11.68% 34.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-255 2692 7.78% 42.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-319 1927 5.57% 47.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-383 1400 4.05% 51.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-447 1123 3.24% 55.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-511 878 2.54% 57.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-575 878 2.54% 60.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-639 638 1.84% 62.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-703 541 1.56% 63.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-767 480 1.39% 65.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-831 476 1.38% 66.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-895 262 0.76% 67.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-959 253 0.73% 67.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-1023 191 0.55% 68.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1087 292 0.84% 69.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1151 145 0.42% 69.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1215 146 0.42% 70.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1279 123 0.36% 70.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1343 107 0.31% 70.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1407 79 0.23% 71.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1471 170 0.49% 71.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1535 949 2.74% 74.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1599 246 0.71% 74.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1663 151 0.44% 75.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1727 129 0.37% 75.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1791 98 0.28% 76.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1855 72 0.21% 76.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1919 65 0.19% 76.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1983 51 0.15% 76.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-2047 51 0.15% 76.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2111 71 0.21% 76.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2175 44 0.13% 77.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2239 29 0.08% 77.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2303 19 0.05% 77.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 34668 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 13801.223030 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 734.240341 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 27780.651463 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-127 7945 22.92% 22.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-191 4005 11.55% 34.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-255 2676 7.72% 42.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-319 1963 5.66% 47.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-383 1415 4.08% 51.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-447 1138 3.28% 55.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-511 895 2.58% 57.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-575 859 2.48% 60.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-639 666 1.92% 62.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-703 565 1.63% 63.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-767 463 1.34% 65.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-831 439 1.27% 66.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-895 280 0.81% 67.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-959 254 0.73% 67.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-1023 189 0.55% 68.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1087 312 0.90% 69.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1151 134 0.39% 69.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1215 136 0.39% 70.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1279 130 0.37% 70.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1343 99 0.29% 70.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1407 89 0.26% 71.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1471 164 0.47% 71.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1535 949 2.74% 74.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1599 269 0.78% 75.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1663 135 0.39% 75.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1727 116 0.33% 75.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1791 100 0.29% 76.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1855 85 0.25% 76.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1919 65 0.19% 76.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1983 50 0.14% 76.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-2047 50 0.14% 76.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2111 59 0.17% 77.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2175 33 0.10% 77.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2239 32 0.09% 77.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2303 20 0.06% 77.24% # Bytes accessed per row activation system.physmem.bytesPerActivate::2304-2367 23 0.07% 77.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2431 27 0.08% 77.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2495 13 0.04% 77.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2559 27 0.08% 77.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2623 12 0.03% 77.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2687 9 0.03% 77.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2751 14 0.04% 77.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2815 11 0.03% 77.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2879 12 0.03% 77.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2943 14 0.04% 77.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-3007 6 0.02% 77.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3071 7 0.02% 77.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3135 15 0.04% 77.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3199 4 0.01% 77.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3263 7 0.02% 77.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3327 4 0.01% 77.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3391 14 0.04% 77.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3455 11 0.03% 77.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3519 7 0.02% 77.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3583 7 0.02% 77.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3647 11 0.03% 77.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2431 11 0.03% 77.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2495 23 0.07% 77.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2559 27 0.08% 77.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2623 12 0.03% 77.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2687 11 0.03% 77.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2751 15 0.04% 77.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2815 7 0.02% 77.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2879 13 0.04% 77.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2943 8 0.02% 77.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-3007 13 0.04% 77.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3071 9 0.03% 77.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3135 14 0.04% 77.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3199 9 0.03% 77.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3263 16 0.05% 77.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3327 6 0.02% 77.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3391 9 0.03% 77.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3455 7 0.02% 77.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3519 9 0.03% 77.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3583 6 0.02% 77.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3647 6 0.02% 77.98% # Bytes accessed per row activation system.physmem.bytesPerActivate::3648-3711 8 0.02% 78.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3775 5 0.01% 78.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3839 12 0.03% 78.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3903 4 0.01% 78.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3967 5 0.01% 78.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-4031 8 0.02% 78.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4095 6 0.02% 78.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4159 41 0.12% 78.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4223 3 0.01% 78.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4287 4 0.01% 78.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4351 5 0.01% 78.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4415 4 0.01% 78.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4479 5 0.01% 78.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4543 4 0.01% 78.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4607 5 0.01% 78.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4671 9 0.03% 78.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4735 4 0.01% 78.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4799 2 0.01% 78.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4863 4 0.01% 78.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4927 4 0.01% 78.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4991 1 0.00% 78.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-5055 5 0.01% 78.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5119 3 0.01% 78.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5183 10 0.03% 78.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5247 3 0.01% 78.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5375 2 0.01% 78.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5439 5 0.01% 78.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5503 2 0.01% 78.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5631 5 0.01% 78.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5695 3 0.01% 78.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5759 6 0.02% 78.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5823 2 0.01% 78.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5887 3 0.01% 78.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5951 5 0.01% 78.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-6015 4 0.01% 78.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6079 3 0.01% 78.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6143 3 0.01% 78.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6207 170 0.49% 79.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6271 3 0.01% 79.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6335 1 0.00% 79.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6399 4 0.01% 79.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6463 4 0.01% 79.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6591 1 0.00% 79.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6655 2 0.01% 79.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6719 5 0.01% 79.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6783 3 0.01% 79.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3775 9 0.03% 78.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3839 8 0.02% 78.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3903 6 0.02% 78.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3967 7 0.02% 78.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-4031 9 0.03% 78.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4095 6 0.02% 78.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4159 45 0.13% 78.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4223 4 0.01% 78.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4287 6 0.02% 78.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4351 9 0.03% 78.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4415 2 0.01% 78.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4479 4 0.01% 78.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4543 6 0.02% 78.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4607 8 0.02% 78.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4671 6 0.02% 78.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4735 4 0.01% 78.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4799 3 0.01% 78.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4863 3 0.01% 78.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4927 5 0.01% 78.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4991 2 0.01% 78.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-5055 8 0.02% 78.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5119 2 0.01% 78.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5183 3 0.01% 78.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5247 1 0.00% 78.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5439 2 0.01% 78.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5503 1 0.00% 78.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5567 1 0.00% 78.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5631 5 0.01% 78.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5695 6 0.02% 78.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5759 2 0.01% 78.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5823 1 0.00% 78.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5887 1 0.00% 78.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5951 6 0.02% 78.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6079 6 0.02% 78.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6207 180 0.52% 79.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6271 1 0.00% 79.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6335 4 0.01% 79.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6399 1 0.00% 79.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6463 5 0.01% 79.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6527 1 0.00% 79.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6591 1 0.00% 79.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6655 1 0.00% 79.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6719 3 0.01% 79.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6783 2 0.01% 79.14% # Bytes accessed per row activation system.physmem.bytesPerActivate::6784-6847 21 0.06% 79.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6911 3 0.01% 79.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6911 2 0.01% 79.21% # Bytes accessed per row activation system.physmem.bytesPerActivate::6912-6975 1 0.00% 79.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7103 1 0.00% 79.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7167 1 0.00% 79.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7231 4 0.01% 79.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7295 3 0.01% 79.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7359 2 0.01% 79.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7423 1 0.00% 79.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7487 3 0.01% 79.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7551 4 0.01% 79.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-7039 1 0.00% 79.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7103 2 0.01% 79.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7167 2 0.01% 79.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7231 6 0.02% 79.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7359 1 0.00% 79.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7423 1 0.00% 79.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7551 3 0.01% 79.26% # Bytes accessed per row activation system.physmem.bytesPerActivate::7552-7615 3 0.01% 79.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7679 3 0.01% 79.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7743 4 0.01% 79.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7807 2 0.01% 79.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7935 5 0.01% 79.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7999 2 0.01% 79.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8063 2 0.01% 79.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8127 7 0.02% 79.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8191 4 0.01% 79.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8255 318 0.92% 80.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8511 1 0.00% 80.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8767 1 0.00% 80.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-9023 2 0.01% 80.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9279 4 0.01% 80.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9408-9471 1 0.00% 80.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9535 2 0.01% 80.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9600-9663 1 0.00% 80.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9791 2 0.01% 80.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10303 17 0.05% 80.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10559 2 0.01% 80.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10815 1 0.00% 80.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11071 2 0.01% 80.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11200-11263 1 0.00% 80.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7679 3 0.01% 79.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7743 3 0.01% 79.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7807 1 0.00% 79.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7871 3 0.01% 79.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7935 6 0.02% 79.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7999 6 0.02% 79.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8063 3 0.01% 79.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8127 7 0.02% 79.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8191 5 0.01% 79.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8255 319 0.92% 80.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8511 2 0.01% 80.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8767 1 0.00% 80.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-9023 1 0.00% 80.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9279 2 0.01% 80.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9408-9471 1 0.00% 80.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9535 1 0.00% 80.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9600-9663 1 0.00% 80.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-10047 2 0.01% 80.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10303 18 0.05% 80.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10559 2 0.01% 80.38% # Bytes accessed per row activation system.physmem.bytesPerActivate::11264-11327 2 0.01% 80.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11583 2 0.01% 80.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11583 1 0.00% 80.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11839 1 0.00% 80.39% # Bytes accessed per row activation system.physmem.bytesPerActivate::12032-12095 1 0.00% 80.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12736-12799 1 0.00% 80.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13375 1 0.00% 80.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13631 2 0.01% 80.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13887 1 0.00% 80.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14399 1 0.00% 80.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15423 2 0.01% 80.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15679 1 0.00% 80.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15935 1 0.00% 80.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16191 1 0.00% 80.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16447 1 0.00% 80.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16704-16767 1 0.00% 80.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17215 1 0.00% 80.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17280-17343 1 0.00% 80.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17471 2 0.01% 80.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17728-17791 1 0.00% 80.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17856-17919 1 0.00% 80.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18239 1 0.00% 80.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18495 2 0.01% 80.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19263 1 0.00% 80.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20543 13 0.04% 80.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20799 1 0.00% 80.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-21055 1 0.00% 80.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21567 2 0.01% 80.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21823 1 0.00% 80.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22591 3 0.01% 80.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22847 1 0.00% 80.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23040-23103 2 0.01% 80.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23615 3 0.01% 80.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23808-23871 1 0.00% 80.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24127 1 0.00% 80.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24128-24191 1 0.00% 80.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24383 1 0.00% 80.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24639 1 0.00% 80.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24895 2 0.01% 80.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25216-25279 1 0.00% 80.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25663 3 0.01% 80.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25919 2 0.01% 80.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26687 1 0.00% 80.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26880-26943 3 0.01% 80.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27199 1 0.00% 80.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27455 2 0.01% 80.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27711 1 0.00% 80.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27840-27903 1 0.00% 80.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27967 1 0.00% 80.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27968-28031 1 0.00% 80.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28479 1 0.00% 80.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28735 2 0.01% 80.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28991 2 0.01% 80.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29247 1 0.00% 80.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29504-29567 1 0.00% 80.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29759 4 0.01% 80.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-30015 5 0.01% 80.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30271 1 0.00% 80.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30527 1 0.00% 80.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30783 1 0.00% 80.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31040-31103 1 0.00% 80.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31360-31423 1 0.00% 80.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31680-31743 1 0.00% 80.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31807 2 0.01% 80.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32000-32063 2 0.01% 80.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32319 1 0.00% 80.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32831 6 0.02% 80.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33343 1 0.00% 80.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33472-33535 5 0.01% 80.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33599 49 0.14% 80.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33600-33663 2 0.01% 80.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34879 1 0.00% 80.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35072-35135 1 0.00% 80.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35903 1 0.00% 80.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38016-38079 1 0.00% 80.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38400-38463 1 0.00% 80.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39424-39487 1 0.00% 80.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-41023 1 0.00% 80.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-42047 2 0.01% 80.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42112-42175 1 0.00% 80.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43071 1 0.00% 80.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43264-43327 1 0.00% 80.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46848-46911 1 0.00% 80.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48447 1 0.00% 80.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48576-48639 1 0.00% 80.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::53248-53311 1 0.00% 80.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::53504-53567 1 0.00% 80.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::53760-53823 1 0.00% 80.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::54016-54079 1 0.00% 80.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::54272-54335 1 0.00% 80.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::54528-54591 1 0.00% 80.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::55296-55359 1 0.00% 80.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::55744-55807 1 0.00% 80.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::55808-55871 2 0.01% 80.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::56320-56383 3 0.01% 80.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::56576-56639 1 0.00% 80.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::58880-58943 1 0.00% 80.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::59520-59583 1 0.00% 80.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::60416-60479 1 0.00% 80.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::60608-60671 1 0.00% 80.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::62464-62527 1 0.00% 80.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::63488-63551 1 0.00% 80.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65024-65087 7 0.02% 80.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65152-65215 2 0.01% 81.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65216-65279 1 0.00% 81.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65344-65407 1 0.00% 81.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65472-65535 6 0.02% 81.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65536-65599 6201 17.92% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65920-65983 1 0.00% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::66304-66367 1 0.00% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::74240-74303 1 0.00% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::76480-76543 1 0.00% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::76864-76927 1 0.00% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::84416-84479 1 0.00% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::86848-86911 1 0.00% 98.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::87040-87103 1 0.00% 98.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::87424-87487 1 0.00% 98.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::97024-97087 1 0.00% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::97472-97535 1 0.00% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::97600-97663 1 0.00% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::99520-99583 1 0.00% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12607 1 0.00% 80.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12863 2 0.01% 80.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12928-12991 1 0.00% 80.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13119 1 0.00% 80.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13375 3 0.01% 80.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13887 1 0.00% 80.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14143 1 0.00% 80.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14399 1 0.00% 80.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14784-14847 1 0.00% 80.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15167 2 0.01% 80.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15423 3 0.01% 80.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15679 1 0.00% 80.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16447 1 0.00% 80.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16703 2 0.01% 80.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16832-16895 1 0.00% 80.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16959 2 0.01% 80.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17215 2 0.01% 80.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17727 1 0.00% 80.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18239 2 0.01% 80.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18495 1 0.00% 80.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18752-18815 1 0.00% 80.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19328-19391 1 0.00% 80.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19519 4 0.01% 80.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19712-19775 1 0.00% 80.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20287 1 0.00% 80.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20543 13 0.04% 80.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20736-20799 1 0.00% 80.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-21055 2 0.01% 80.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21567 2 0.01% 80.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21823 1 0.00% 80.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22016-22079 2 0.01% 80.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22272-22335 2 0.01% 80.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22591 1 0.00% 80.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22847 1 0.00% 80.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23615 4 0.01% 80.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24383 2 0.01% 80.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24639 4 0.01% 80.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25344-25407 1 0.00% 80.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25663 3 0.01% 80.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25856-25919 1 0.00% 80.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26175 2 0.01% 80.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26431 3 0.01% 80.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26687 2 0.01% 80.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27455 2 0.01% 80.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27711 1 0.00% 80.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28479 1 0.00% 80.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28735 1 0.00% 80.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29312-29375 1 0.00% 80.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29504-29567 1 0.00% 80.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29759 3 0.01% 80.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-30015 1 0.00% 80.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30271 2 0.01% 80.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30400-30463 1 0.00% 80.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30527 3 0.01% 80.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30783 6 0.02% 80.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31295 2 0.01% 80.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31551 3 0.01% 80.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31807 2 0.01% 80.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31872-31935 1 0.00% 80.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32319 1 0.00% 80.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32575 1 0.00% 80.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33087 16 0.05% 80.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33088-33151 1 0.00% 80.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33152-33215 2 0.01% 80.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33343 36 0.10% 80.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34304-34367 1 0.00% 80.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35584-35647 1 0.00% 80.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35903 1 0.00% 80.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38207 1 0.00% 80.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38463 1 0.00% 80.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39488-39551 1 0.00% 80.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41279 1 0.00% 80.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41344-41407 1 0.00% 80.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-42047 1 0.00% 80.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43071 1 0.00% 80.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43584-43647 1 0.00% 80.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44095 1 0.00% 80.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44607 1 0.00% 80.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45119 1 0.00% 80.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45887 1 0.00% 80.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48703 2 0.01% 80.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49215 1 0.00% 80.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50176-50239 1 0.00% 80.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50432-50495 2 0.01% 80.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51520-51583 1 0.00% 80.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52224-52287 4 0.01% 80.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52800-52863 1 0.00% 80.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::54272-54335 2 0.01% 80.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::55296-55359 1 0.00% 80.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::56064-56127 1 0.00% 80.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::56320-56383 2 0.01% 80.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::61440-61503 2 0.01% 81.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::61696-61759 1 0.00% 81.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::62080-62143 1 0.00% 81.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::62208-62271 1 0.00% 81.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::62464-62527 1 0.00% 81.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::62976-63039 1 0.00% 81.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::63488-63551 2 0.01% 81.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::64512-64575 2 0.01% 81.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::64832-64895 1 0.00% 81.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65024-65087 6 0.02% 81.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65152-65215 2 0.01% 81.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65216-65279 1 0.00% 81.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65344-65407 1 0.00% 81.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65472-65535 6 0.02% 81.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65536-65599 6196 17.87% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::72768-72831 1 0.00% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::73920-73983 1 0.00% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::75008-75071 1 0.00% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::82944-83007 1 0.00% 98.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::84480-84543 1 0.00% 98.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::85376-85439 1 0.00% 98.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::85568-85631 1 0.00% 98.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::94656-94719 1 0.00% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::95552-95615 1 0.00% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::98944-99007 1 0.00% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::99520-99583 1 0.00% 98.98% # Bytes accessed per row activation system.physmem.bytesPerActivate::109120-109183 1 0.00% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::109696-109759 1 0.00% 98.98% # Bytes accessed per row activation system.physmem.bytesPerActivate::110080-110143 1 0.00% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::111168-111231 1 0.00% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::114496-114559 1 0.00% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::120896-120959 1 0.00% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::121152-121215 1 0.00% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::121728-121791 1 0.00% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::122112-122175 1 0.00% 99.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::117440-117503 1 0.00% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::117952-118015 1 0.00% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::120256-120319 1 0.00% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::120640-120703 1 0.00% 99.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::121152-121215 1 0.00% 99.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::129856-129919 1 0.00% 99.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::130112-130175 1 0.00% 99.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::131072-131135 336 0.97% 99.97% # Bytes accessed per row activation system.physmem.bytesPerActivate::131200-131263 1 0.00% 99.98% # Bytes accessed per row activation system.physmem.bytesPerActivate::132096-132159 3 0.01% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::136576-136639 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::196032-196095 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::196160-196223 1 0.00% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::196608-196671 2 0.01% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::420352-420415 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 34609 # Bytes accessed per row activation -system.physmem.totQLat 134116991750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 175932036750 # Sum of mem lat for all requests -system.physmem.totBusLat 33272445000 # Total cycles spent in databus access -system.physmem.totBankLat 8542600000 # Total cycles spent in bank access -system.physmem.avgQLat 20154.36 # Average queueing delay per request -system.physmem.avgBankLat 1283.73 # Average bank access latency per request +system.physmem.bytesPerActivate::total 34668 # Bytes accessed per row activation +system.physmem.totQLat 132807422500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 174630638750 # Sum of mem lat for all requests +system.physmem.totBusLat 33272490000 # Total cycles spent in databus access +system.physmem.totBankLat 8550726250 # Total cycles spent in bank access +system.physmem.avgQLat 19957.54 # Average queueing delay per request +system.physmem.avgBankLat 1284.95 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26438.10 # Average memory access latency +system.physmem.avgMemAccLat 26242.50 # Average memory access latency system.physmem.avgRdBW 356.43 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 44.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 52.02 # Average consumed read bandwidth in MB/s @@ -480,12 +478,12 @@ system.physmem.avgConsumedWrBW 6.00 # Av system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.13 # Data bus utilization in percentage system.physmem.avgRdQLen 0.15 # Average read queue length over time -system.physmem.avgWrQLen 12.03 # Average write queue length over time -system.physmem.readRowHits 6636609 # Number of row buffer hits during reads -system.physmem.writeRowHits 804716 # Number of row buffer hits during writes +system.physmem.avgWrQLen 11.97 # Average write queue length over time +system.physmem.readRowHits 6636574 # Number of row buffer hits during reads +system.physmem.writeRowHits 804724 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.73 # Row buffer hit rate for reads system.physmem.writeRowHitRate 97.96 # Row buffer hit rate for writes -system.physmem.avgGap 159828.45 # Average gap between requests +system.physmem.avgGap 159830.13 # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -504,298 +502,298 @@ system.realview.nvmem.bw_inst_read::total 57 # I system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 60028731 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 7703147 # Transaction distribution -system.membus.trans_dist::ReadResp 7703147 # Transaction distribution +system.membus.throughput 60028739 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 7703151 # Transaction distribution +system.membus.trans_dist::ReadResp 7703151 # Transaction distribution system.membus.trans_dist::WriteReq 767201 # Transaction distribution system.membus.trans_dist::WriteResp 767201 # Transaction distribution -system.membus.trans_dist::Writeback 64628 # Transaction distribution -system.membus.trans_dist::UpgradeReq 27727 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 16403 # Transaction distribution -system.membus.trans_dist::UpgradeResp 10646 # Transaction distribution -system.membus.trans_dist::ReadExReq 137752 # Transaction distribution -system.membus.trans_dist::ReadExResp 137298 # Transaction distribution +system.membus.trans_dist::Writeback 64634 # Transaction distribution +system.membus.trans_dist::UpgradeReq 27614 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 16407 # Transaction distribution +system.membus.trans_dist::UpgradeResp 10632 # Transaction distribution +system.membus.trans_dist::ReadExReq 137758 # Transaction distribution +system.membus.trans_dist::ReadExResp 137302 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382564 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1966658 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1966559 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 8856 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 906 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4359022 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4358923 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12976128 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 12976128 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.bridge.slave 2382564 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 14942786 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 14942687 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.realview.gic.pio 8856 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.realview.local_cpu_timer.pio 906 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 17335150 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 17335051 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389882 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17414132 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17415028 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 17712 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1812 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 19823614 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 19824510 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 51904512 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 51904512 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::system.bridge.slave 2389882 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 69318644 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 69319540 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::system.realview.gic.pio 17712 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::system.realview.local_cpu_timer.pio 1812 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 71728126 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 71728126 # Total data (bytes) +system.membus.tot_pkt_size::total 71729022 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 71729022 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1224802500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1208299500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 18000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 9206920000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 9149149500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.8 # Layer utilization (%) -system.membus.reqLayer3.occupancy 7965000 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 7960500 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) system.membus.reqLayer5.occupancy 2500 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) system.membus.reqLayer6.occupancy 777000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 5076821641 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 5034294617 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.respLayer2.occupancy 14663419999 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 14663453747 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.2 # Layer utilization (%) -system.l2c.replacements 69621 # number of replacements -system.l2c.tagsinuse 53152.412760 # Cycle average of tags in use -system.l2c.total_refs 1651309 # Total number of references to valid blocks. -system.l2c.sampled_refs 134782 # Sample count of references to valid blocks. -system.l2c.avg_refs 12.251703 # Average number of references to valid blocks. -system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 40039.064508 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 2.667880 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.001518 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4643.192238 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 5788.281913 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.itb.walker 0.001659 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 1923.389950 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 755.813095 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.610948 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000041 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.070849 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.088322 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.029349 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.011533 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.811041 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 4524 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 1439 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 483114 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 241880 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 3782 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1868 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 372301 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 110577 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1219485 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 576235 # number of Writeback hits -system.l2c.Writeback_hits::total 576235 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1306 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 431 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1737 # number of UpgradeReq hits +system.l2c.tags.replacements 69629 # number of replacements +system.l2c.tags.tagsinuse 53155.534639 # Cycle average of tags in use +system.l2c.tags.total_refs 1651678 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 134776 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 12.254986 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 40041.185718 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.667860 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001521 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4638.655043 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 5789.348152 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.001660 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1927.060090 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 756.614595 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.610980 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000041 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.070780 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.088338 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.029405 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.011545 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.811089 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 4625 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 1507 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 482925 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 242050 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 3554 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 1806 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 372304 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 110721 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1219492 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 576641 # number of Writeback hits +system.l2c.Writeback_hits::total 576641 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 1408 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 418 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1826 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu0.data 257 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 99 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 356 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 65556 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 45402 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 110958 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 4524 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 1439 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 483114 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 307436 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 3782 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 1868 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 372301 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 155979 # number of demand (read+write) hits -system.l2c.demand_hits::total 1330443 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 4524 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 1439 # number of overall hits -system.l2c.overall_hits::cpu0.inst 483114 # number of overall hits -system.l2c.overall_hits::cpu0.data 307436 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 3782 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 1868 # number of overall hits -system.l2c.overall_hits::cpu1.inst 372301 # number of overall hits -system.l2c.overall_hits::cpu1.data 155979 # number of overall hits -system.l2c.overall_hits::total 1330443 # number of overall hits +system.l2c.SCUpgradeReq_hits::cpu1.data 96 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 353 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 65574 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 45429 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 111003 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 4625 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 1507 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 482925 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 307624 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 3554 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 1806 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 372304 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 156150 # number of demand (read+write) hits +system.l2c.demand_hits::total 1330495 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 4625 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 1507 # number of overall hits +system.l2c.overall_hits::cpu0.inst 482925 # number of overall hits +system.l2c.overall_hits::cpu0.data 307624 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 3554 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 1806 # number of overall hits +system.l2c.overall_hits::cpu1.inst 372304 # number of overall hits +system.l2c.overall_hits::cpu1.data 156150 # number of overall hits +system.l2c.overall_hits::total 1330495 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 4 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 6836 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 9717 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 6837 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 9715 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 3992 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1890 # number of ReadReq misses -system.l2c.ReadReq_misses::total 22442 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 3986 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 3365 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 7351 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 384 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 475 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 859 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 95133 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 44601 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 139734 # number of ReadExReq misses +system.l2c.ReadReq_misses::cpu1.inst 3996 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 1891 # number of ReadReq misses +system.l2c.ReadReq_misses::total 22446 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 3988 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 3371 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 7359 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 387 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 473 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 860 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 95120 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 44595 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 139715 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 4 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 6836 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 104850 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 6837 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 104835 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 3992 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 46491 # number of demand (read+write) misses -system.l2c.demand_misses::total 162176 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 3996 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 46486 # number of demand (read+write) misses +system.l2c.demand_misses::total 162161 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 4 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 6836 # number of overall misses -system.l2c.overall_misses::cpu0.data 104850 # number of overall misses +system.l2c.overall_misses::cpu0.inst 6837 # number of overall misses +system.l2c.overall_misses::cpu0.data 104835 # number of overall misses system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 3992 # number of overall misses -system.l2c.overall_misses::cpu1.data 46491 # number of overall misses -system.l2c.overall_misses::total 162176 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 395000 # number of ReadReq miss cycles +system.l2c.overall_misses::cpu1.inst 3996 # number of overall misses +system.l2c.overall_misses::cpu1.data 46486 # number of overall misses +system.l2c.overall_misses::total 162161 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 395750 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.itb.walker 122500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 487167000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 686875999 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 89000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 283916500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 153770500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1612336499 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 11351000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 12155500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 23506500 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1843000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1049000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 2892000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 6211024494 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 2810090500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 9021114994 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 395000 # number of demand (read+write) miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 486019750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 691389999 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.itb.walker 89250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 282135750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 152148250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1612301249 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 11489505 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 12402970 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 23892475 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1837921 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1069454 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 2907375 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 6199806193 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 2820905645 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 9020711838 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 395750 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.itb.walker 122500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 487167000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 6897900493 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 89000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 283916500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 2963861000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 10633451493 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 395000 # number of overall miss cycles +system.l2c.demand_miss_latency::cpu0.inst 486019750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 6891196192 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 89250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 282135750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 2973053895 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 10633013087 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 395750 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.itb.walker 122500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 487167000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 6897900493 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 89000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 283916500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 2963861000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 10633451493 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 4528 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 1441 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 489950 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 251597 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 3782 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 1869 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 376293 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 112467 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1241927 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 576235 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 576235 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 5292 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 3796 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 9088 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 641 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 574 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1215 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 160689 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 90003 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 250692 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 4528 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 1441 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 489950 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 412286 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 3782 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 1869 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 376293 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 202470 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1492619 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 4528 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 1441 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 489950 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 412286 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 3782 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 1869 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 376293 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 202470 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1492619 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000883 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001388 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.013952 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.038621 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000535 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.010609 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.016805 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.018070 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.753212 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.886459 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.808869 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.599064 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.827526 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.706996 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.592032 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.495550 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.557393 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000883 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.001388 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.013952 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.254314 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.000535 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.010609 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.229619 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.108652 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000883 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.001388 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.013952 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.254314 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.000535 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.010609 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.229619 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.108652 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 98750 # average ReadReq miss latency +system.l2c.overall_miss_latency::cpu0.inst 486019750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 6891196192 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 89250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 282135750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 2973053895 # number of overall miss cycles +system.l2c.overall_miss_latency::total 10633013087 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 4629 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 1509 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 489762 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 251765 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 3554 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 1807 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 376300 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 112612 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1241938 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 576641 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 576641 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 5396 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 3789 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 9185 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 644 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 569 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1213 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 160694 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 90024 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 250718 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 4629 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 1509 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 489762 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 412459 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 3554 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 1807 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 376300 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 202636 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1492656 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 4629 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 1509 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 489762 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 412459 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 3554 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 1807 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 376300 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 202636 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1492656 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000864 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001325 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.013960 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.038588 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000553 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.010619 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.016792 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.018073 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.739066 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.889681 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.801198 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.600932 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.831283 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.708986 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.591932 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.495368 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.557260 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000864 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.001325 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.013960 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.254171 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.000553 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.010619 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.229406 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.108639 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000864 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.001325 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.013960 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.254171 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.000553 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.010619 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.229406 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.108639 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 98937.500000 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 61250 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 71264.921006 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 70688.072347 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 89000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 71121.367735 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 81360.052910 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 71844.599367 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2847.717010 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3612.332838 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 3197.728200 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 4799.479167 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2208.421053 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 3366.705471 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 65287.802277 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 63005.100782 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 64559.198148 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 98750 # average overall miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 71086.697382 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 71167.267010 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 89250 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 70604.542042 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 80459.148599 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 71830.225831 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2881.019308 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3679.314743 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 3246.701318 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 4749.149871 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2261.002114 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 3380.668605 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 65178.786722 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 63256.096984 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 64565.092066 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 98937.500000 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.itb.walker 61250 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 71264.921006 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 65788.273658 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 89000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 71121.367735 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 63751.285195 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 65567.355792 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 98750 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 71086.697382 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 65733.735794 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.itb.walker 89250 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 70604.542042 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 63955.898443 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 65570.717293 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 98937.500000 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 61250 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 71264.921006 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 65788.273658 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 89000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 71121.367735 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 63751.285195 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 65567.355792 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 71086.697382 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 65733.735794 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.itb.walker 89250 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 70604.542042 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 63955.898443 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 65570.717293 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -804,8 +802,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 64628 # number of writebacks -system.l2c.writebacks::total 64628 # number of writebacks +system.l2c.writebacks::writebacks 64634 # number of writebacks +system.l2c.writebacks::total 64634 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits @@ -814,149 +812,149 @@ system.l2c.overall_mshr_hits::cpu0.inst 1 # nu system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 4 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 6835 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 9717 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 6836 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 9715 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 3992 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 1890 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 22441 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 3986 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 3365 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 7351 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 384 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 475 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 859 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 95133 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 44601 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 139734 # number of ReadExReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 3996 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 1891 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 22445 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 3988 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 3371 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 7359 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 387 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 473 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 860 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 95120 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 44595 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 139715 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu0.dtb.walker 4 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 6835 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 104850 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 6836 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 104835 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 3992 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 46491 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 162175 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 3996 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 46486 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 162160 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0.dtb.walker 4 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 6835 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 104850 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 6836 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 104835 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 3992 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 46491 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 162175 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 345500 # number of ReadReq MSHR miss cycles +system.l2c.overall_mshr_misses::cpu1.inst 3996 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 46486 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 162160 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 344250 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 97500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 401430000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 565873249 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 399672500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 568184999 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 76250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 233821750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 130194500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1331838749 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 39898978 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 33754347 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 73653325 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 3848381 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4768474 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 8616855 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5004861313 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2258786863 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 7263648176 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 345500 # number of demand (read+write) MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 231686750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 128101750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1328163999 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 39911983 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 33802856 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 73714839 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 3872886 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4731473 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 8604359 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5007372803 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2261009853 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 7268382656 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 344250 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 97500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 401430000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 5570734562 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 399672500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 5575557802 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 76250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 233821750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 2388981363 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 8595486925 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 345500 # number of overall MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 231686750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 2389111603 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 8596546655 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 344250 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 97500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 401430000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 5570734562 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 399672500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 5575557802 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 76250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 233821750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 2388981363 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 8595486925 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 340227750 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12648650244 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 4863250 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154086171248 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 167079912492 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 16271278232 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 486203500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 16757481732 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 340227750 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 28919928476 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 4863250 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 154572374748 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 183837394224 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000883 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001388 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013950 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.038621 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000535 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010609 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.016805 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.018070 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.753212 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.886459 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.808869 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.599064 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.827526 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.706996 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.592032 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.495550 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.557393 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000883 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001388 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013950 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.254314 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000535 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010609 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.229619 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.108651 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000883 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001388 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013950 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.254314 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000535 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010609 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.229619 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.108651 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 86375 # average ReadReq mshr miss latency +system.l2c.overall_mshr_miss_latency::cpu1.inst 231686750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 2389111603 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 8596546655 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 340200250 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12647628243 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 4849500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154070714500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 167063392493 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 16272290763 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 486202500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 16758493263 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 340200250 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 28919919006 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 4849500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 154556917000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 183821885756 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000864 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001325 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013958 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.038588 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000553 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010619 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.016792 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.018073 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.739066 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.889681 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.801198 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.600932 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.831283 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.708986 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.591932 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.495368 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.557260 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000864 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001325 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013958 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.254171 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000553 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010619 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.229406 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.108639 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000864 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001325 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013958 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.254171 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000553 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010619 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.229406 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.108639 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 86062.500000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 58731.528895 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 58235.386333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 58465.842598 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 58485.331858 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58572.582665 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 68885.978836 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 59348.458135 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10009.778726 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10031.009510 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10019.497347 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10021.825521 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10038.892632 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10031.263097 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 52609.097926 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 50644.309836 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 51981.966994 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 86375 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 57979.667167 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 67742.860920 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 59174.159011 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10008.019809 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10027.545535 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10016.964126 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10007.457364 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10003.114165 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10005.068605 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 52642.691369 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 50700.972149 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 52022.922779 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 86062.500000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 58731.528895 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53130.515613 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 58465.842598 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53184.125550 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58572.582665 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 51385.888946 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 53001.306767 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 86375 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 57979.667167 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 51394.217678 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 53012.744542 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 86062.500000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 58731.528895 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53130.515613 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 58465.842598 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53184.125550 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58572.582665 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 51385.888946 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 53001.306767 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 57979.667167 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 51394.217678 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 53012.744542 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -977,56 +975,56 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 118409228 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2504917 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2504917 # Transaction distribution +system.toL2Bus.throughput 118431561 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2504925 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2504925 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 767201 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 767201 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 576235 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 27028 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 16759 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 576641 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 27027 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 16760 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 43787 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 262464 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 262464 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 993919 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 2951089 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma 5837 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma 14921 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 753559 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 2879854 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma 6195 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma 11995 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count 7617369 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 31383352 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 53719796 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 5764 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 18112 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 24083148 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 27940806 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma 7476 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma 15128 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size 137173582 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 137173582 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 4313200 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4765991701 # Layer occupancy (ticks) +system.toL2Bus.trans_dist::ReadExReq 262499 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 262499 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 993555 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 2951402 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma 5905 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma 15026 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 753554 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 2880607 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma 6133 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma 11768 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count 7617950 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 31371320 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 53730420 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 6036 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 18516 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 24083596 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 27977862 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma 7228 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma 14216 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size 137209194 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 137209194 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 4306024 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4767819743 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2214801410 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2217282985 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 2446229482 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 2471819696 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 4396000 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 4396500 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 10393499 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 10398000 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 1696938433 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.occupancy 1697865710 # Layer occupancy (ticks) system.toL2Bus.respLayer4.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 2203617971 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.occupancy 2215426419 # Layer occupancy (ticks) system.toL2Bus.respLayer5.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 4326998 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.occupancy 4326250 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 8213499 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 8214499 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 45438572 # Throughput (bytes/s) +system.iobus.throughput 45438010 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 7671400 # Transaction distribution system.iobus.trans_dist::ReadResp 7671400 # Transaction distribution system.iobus.trans_dist::WriteReq 7946 # Transaction distribution @@ -1184,13 +1182,13 @@ system.iobus.reqLayer25.occupancy 6488064000 # La system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%) system.iobus.respLayer0.occupancy 2374618000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.2 # Layer utilization (%) -system.iobus.respLayer1.occupancy 12976128000 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 1.1 # Layer utilization (%) +system.iobus.respLayer1.occupancy 17765827253 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 9653493 # DTB read hits -system.cpu0.dtb.read_misses 3738 # DTB read misses -system.cpu0.dtb.write_hits 7597651 # DTB write hits +system.cpu0.dtb.read_hits 9651794 # DTB read hits +system.cpu0.dtb.read_misses 3741 # DTB read misses +system.cpu0.dtb.write_hits 7596285 # DTB write hits system.cpu0.dtb.write_misses 1585 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -1198,16 +1196,16 @@ system.cpu0.dtb.flush_tlb_mva_asid 1439 # Nu system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu0.dtb.flush_entries 1811 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 134 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 138 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 9657231 # DTB read accesses -system.cpu0.dtb.write_accesses 7599236 # DTB write accesses +system.cpu0.dtb.read_accesses 9655535 # DTB read accesses +system.cpu0.dtb.write_accesses 7597870 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 17251144 # DTB hits -system.cpu0.dtb.misses 5323 # DTB misses -system.cpu0.dtb.accesses 17256467 # DTB accesses -system.cpu0.itb.inst_hits 43299111 # ITB inst hits +system.cpu0.dtb.hits 17248079 # DTB hits +system.cpu0.dtb.misses 5326 # DTB misses +system.cpu0.dtb.accesses 17253405 # DTB accesses +system.cpu0.itb.inst_hits 43295611 # ITB inst hits system.cpu0.itb.inst_misses 2205 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -1224,79 +1222,79 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 43301316 # ITB inst accesses -system.cpu0.itb.hits 43299111 # DTB hits +system.cpu0.itb.inst_accesses 43297816 # ITB inst accesses +system.cpu0.itb.hits 43295611 # DTB hits system.cpu0.itb.misses 2205 # DTB misses -system.cpu0.itb.accesses 43301316 # DTB accesses -system.cpu0.numCycles 2389793161 # number of cpu cycles simulated +system.cpu0.itb.accesses 43297816 # DTB accesses +system.cpu0.numCycles 2389822721 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 42572187 # Number of instructions committed -system.cpu0.committedOps 53304847 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 48061724 # Number of integer alu accesses +system.cpu0.committedInsts 42568710 # Number of instructions committed +system.cpu0.committedOps 53298123 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 48055390 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses -system.cpu0.num_func_calls 1403541 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 5582883 # number of instructions that are conditional controls -system.cpu0.num_int_insts 48061724 # number of integer instructions +system.cpu0.num_func_calls 1403445 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 5582451 # number of instructions that are conditional controls +system.cpu0.num_int_insts 48055390 # number of integer instructions system.cpu0.num_fp_insts 3860 # number of float instructions -system.cpu0.num_int_register_reads 272457591 # number of times the integer registers were read -system.cpu0.num_int_register_writes 52272439 # number of times the integer registers were written +system.cpu0.num_int_register_reads 272420788 # number of times the integer registers were read +system.cpu0.num_int_register_writes 52266741 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written -system.cpu0.num_mem_refs 18020656 # number of memory refs -system.cpu0.num_load_insts 10037354 # Number of load instructions -system.cpu0.num_store_insts 7983302 # Number of store instructions -system.cpu0.num_idle_cycles 2150335736.878201 # Number of idle cycles -system.cpu0.num_busy_cycles 239457424.121800 # Number of busy cycles -system.cpu0.not_idle_fraction 0.100200 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.899800 # Percentage of idle cycles +system.cpu0.num_mem_refs 18017454 # number of memory refs +system.cpu0.num_load_insts 10035613 # Number of load instructions +system.cpu0.num_store_insts 7981841 # Number of store instructions +system.cpu0.num_idle_cycles 2150296210.870201 # Number of idle cycles +system.cpu0.num_busy_cycles 239526510.129800 # Number of busy cycles +system.cpu0.not_idle_fraction 0.100228 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.899772 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 51313 # number of quiesce instructions executed -system.cpu0.icache.replacements 490180 # number of replacements -system.cpu0.icache.tagsinuse 509.396236 # Cycle average of tags in use -system.cpu0.icache.total_refs 42808401 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 490692 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 87.240878 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 76020026000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 509.396236 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.994915 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.994915 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 42808401 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 42808401 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 42808401 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 42808401 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 42808401 # number of overall hits -system.cpu0.icache.overall_hits::total 42808401 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 490693 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 490693 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 490693 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 490693 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 490693 # number of overall misses -system.cpu0.icache.overall_misses::total 490693 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6812744000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6812744000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 6812744000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6812744000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 6812744000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6812744000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 43299094 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 43299094 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 43299094 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 43299094 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 43299094 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 43299094 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011333 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.011333 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011333 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.011333 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011333 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.011333 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13883.923349 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13883.923349 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13883.923349 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13883.923349 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13883.923349 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13883.923349 # average overall miss latency +system.cpu0.kern.inst.quiesce 51308 # number of quiesce instructions executed +system.cpu0.icache.tags.replacements 490004 # number of replacements +system.cpu0.icache.tags.tagsinuse 509.392438 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 42805077 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 490516 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 87.265404 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 76030513250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.392438 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994907 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.994907 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 42805077 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 42805077 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 42805077 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 42805077 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 42805077 # number of overall hits +system.cpu0.icache.overall_hits::total 42805077 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 490517 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 490517 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 490517 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 490517 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 490517 # number of overall misses +system.cpu0.icache.overall_misses::total 490517 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6812396235 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 6812396235 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 6812396235 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 6812396235 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 6812396235 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 6812396235 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 43295594 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 43295594 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 43295594 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 43295594 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 43295594 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 43295594 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011329 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.011329 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011329 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.011329 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011329 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.011329 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13888.195995 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13888.195995 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13888.195995 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13888.195995 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13888.195995 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13888.195995 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1305,120 +1303,120 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 490693 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 490693 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 490693 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 490693 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 490693 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 490693 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5831313090 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 5831313090 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5831313090 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 5831313090 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5831313090 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 5831313090 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 430167000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 430167000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 430167000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 430167000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011333 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011333 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011333 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.011333 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011333 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.011333 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11883.831826 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11883.831826 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11883.831826 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11883.831826 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11883.831826 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11883.831826 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 490517 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 490517 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 490517 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 490517 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 490517 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 490517 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5828002765 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 5828002765 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5828002765 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 5828002765 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5828002765 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 5828002765 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 431776750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 431776750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 431776750 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 431776750 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011329 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011329 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011329 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.011329 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011329 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.011329 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11881.347160 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11881.347160 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11881.347160 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11881.347160 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11881.347160 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11881.347160 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 406656 # number of replacements -system.cpu0.dcache.tagsinuse 471.250698 # Cycle average of tags in use -system.cpu0.dcache.total_refs 15968393 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 407168 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 39.218192 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 652579000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 471.250698 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.920412 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.920412 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 9137588 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 9137588 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 6495058 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 6495058 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 156529 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 156529 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 159015 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 159015 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 15632646 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 15632646 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 15632646 # number of overall hits -system.cpu0.dcache.overall_hits::total 15632646 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 263671 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 263671 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 176701 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 176701 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9917 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 9917 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7374 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7374 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 440372 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 440372 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 440372 # number of overall misses -system.cpu0.dcache.overall_misses::total 440372 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3870373500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 3870373500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7511792500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 7511792500 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 99127000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 99127000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 40277500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 40277500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 11382166000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 11382166000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 11382166000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 11382166000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 9401259 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 9401259 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 6671759 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 6671759 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 166446 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 166446 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 166389 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 166389 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 16073018 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 16073018 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 16073018 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 16073018 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028046 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.028046 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.026485 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.026485 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059581 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059581 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.044318 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.044318 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027398 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.027398 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.027398 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.027398 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14678.798579 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14678.798579 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42511.318555 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 42511.318555 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9995.664011 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9995.664011 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5462.096555 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5462.096555 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25846.706875 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 25846.706875 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 25846.706875 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 25846.706875 # average overall miss latency +system.cpu0.dcache.tags.replacements 406612 # number of replacements +system.cpu0.dcache.tags.tagsinuse 470.882465 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 15965290 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 407124 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 39.214809 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 659626250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 470.882465 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.919692 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.919692 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 9135819 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 9135819 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 6493762 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 6493762 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 156506 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 156506 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 158999 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 158999 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 15629581 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 15629581 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 15629581 # number of overall hits +system.cpu0.dcache.overall_hits::total 15629581 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 263761 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 263761 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 176647 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 176647 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9920 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 9920 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7375 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7375 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 440408 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 440408 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 440408 # number of overall misses +system.cpu0.dcache.overall_misses::total 440408 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3882137498 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 3882137498 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7549327791 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 7549327791 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 98498000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 98498000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 40527887 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 40527887 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 11431465289 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 11431465289 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 11431465289 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 11431465289 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 9399580 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 9399580 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 6670409 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 6670409 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 166426 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 166426 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 166374 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 166374 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 16069989 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 16069989 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 16069989 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 16069989 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028061 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.028061 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.026482 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.026482 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059606 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059606 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.044328 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.044328 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027406 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.027406 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.027406 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.027406 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14718.390884 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14718.390884 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42736.801593 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 42736.801593 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9929.233871 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9929.233871 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5495.306712 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5495.306712 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25956.534143 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 25956.534143 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 25956.534143 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 25956.534143 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1427,66 +1425,66 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 376588 # number of writebacks -system.cpu0.dcache.writebacks::total 376588 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 263671 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 263671 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 176701 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 176701 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9917 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9917 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7370 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7370 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 440372 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 440372 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 440372 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 440372 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3343027009 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3343027009 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7158388504 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7158388504 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 79292501 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 79292501 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 25539500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 25539500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.writebacks::writebacks 376581 # number of writebacks +system.cpu0.dcache.writebacks::total 376581 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 263761 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 263761 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 176647 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 176647 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9920 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9920 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7371 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7371 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 440408 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 440408 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 440408 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 440408 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3349960502 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3349960502 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7149928209 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7149928209 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 78594000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 78594000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 25787113 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 25787113 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10501415513 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10501415513 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10501415513 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10501415513 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13765210500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13765210500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 25807067504 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 25807067504 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 39572278004 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 39572278004 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028046 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.028046 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.026485 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.026485 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059581 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059581 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.044294 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.044294 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027398 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.027398 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027398 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.027398 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12678.781546 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12678.781546 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40511.307259 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40511.307259 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7995.613694 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7995.613694 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3465.332429 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3465.332429 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10499888711 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10499888711 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10499888711 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10499888711 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13764207250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13764207250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 25807935730 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 25807935730 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 39572142980 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 39572142980 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028061 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.028061 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.026482 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.026482 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059606 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059606 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.044304 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.044304 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027406 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.027406 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027406 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.027406 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12700.742346 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12700.742346 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40475.797545 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40475.797545 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7922.782258 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7922.782258 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3498.455162 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3498.455162 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23846.692144 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23846.692144 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23846.692144 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23846.692144 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23841.276069 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23841.276069 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23841.276069 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23841.276069 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1496,26 +1494,26 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 5706432 # DTB read hits -system.cpu1.dtb.read_misses 3576 # DTB read misses -system.cpu1.dtb.write_hits 3873109 # DTB write hits -system.cpu1.dtb.write_misses 645 # DTB write misses +system.cpu1.dtb.read_hits 5707792 # DTB read hits +system.cpu1.dtb.read_misses 3579 # DTB read misses +system.cpu1.dtb.write_hits 3874264 # DTB write hits +system.cpu1.dtb.write_misses 643 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu1.dtb.flush_entries 1989 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 144 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 150 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 5710008 # DTB read accesses -system.cpu1.dtb.write_accesses 3873754 # DTB write accesses +system.cpu1.dtb.read_accesses 5711371 # DTB read accesses +system.cpu1.dtb.write_accesses 3874907 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 9579541 # DTB hits -system.cpu1.dtb.misses 4221 # DTB misses -system.cpu1.dtb.accesses 9583762 # DTB accesses -system.cpu1.itb.inst_hits 19379683 # ITB inst hits +system.cpu1.dtb.hits 9582056 # DTB hits +system.cpu1.dtb.misses 4222 # DTB misses +system.cpu1.dtb.accesses 9586278 # DTB accesses +system.cpu1.itb.inst_hits 19381456 # ITB inst hits system.cpu1.itb.inst_misses 2171 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -1532,79 +1530,79 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 19381854 # ITB inst accesses -system.cpu1.itb.hits 19379683 # DTB hits +system.cpu1.itb.inst_accesses 19383627 # ITB inst accesses +system.cpu1.itb.hits 19381456 # DTB hits system.cpu1.itb.misses 2171 # DTB misses -system.cpu1.itb.accesses 19381854 # DTB accesses -system.cpu1.numCycles 2388360365 # number of cpu cycles simulated +system.cpu1.itb.accesses 19383627 # DTB accesses +system.cpu1.numCycles 2388389320 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 18799110 # Number of instructions committed -system.cpu1.committedOps 24903355 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 22267252 # Number of integer alu accesses +system.cpu1.committedInsts 18800879 # Number of instructions committed +system.cpu1.committedOps 24908107 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 22271769 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses -system.cpu1.num_func_calls 796685 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 2514656 # number of instructions that are conditional controls -system.cpu1.num_int_insts 22267252 # number of integer instructions +system.cpu1.num_func_calls 796713 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 2514831 # number of instructions that are conditional controls +system.cpu1.num_int_insts 22271769 # number of integer instructions system.cpu1.num_fp_insts 6793 # number of float instructions -system.cpu1.num_int_register_reads 130770555 # number of times the integer registers were read -system.cpu1.num_int_register_writes 23319815 # number of times the integer registers were written +system.cpu1.num_int_register_reads 130796956 # number of times the integer registers were read +system.cpu1.num_int_register_writes 23323418 # number of times the integer registers were written system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written -system.cpu1.num_mem_refs 10014978 # number of memory refs -system.cpu1.num_load_insts 5983060 # Number of load instructions -system.cpu1.num_store_insts 4031918 # Number of store instructions -system.cpu1.num_idle_cycles 1968746844.438183 # Number of idle cycles -system.cpu1.num_busy_cycles 419613520.561817 # Number of busy cycles -system.cpu1.not_idle_fraction 0.175691 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.824309 # Percentage of idle cycles +system.cpu1.num_mem_refs 10017504 # number of memory refs +system.cpu1.num_load_insts 5984439 # Number of load instructions +system.cpu1.num_store_insts 4033065 # Number of store instructions +system.cpu1.num_idle_cycles 1968748229.220572 # Number of idle cycles +system.cpu1.num_busy_cycles 419641090.779428 # Number of busy cycles +system.cpu1.not_idle_fraction 0.175700 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.824300 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 39066 # number of quiesce instructions executed -system.cpu1.icache.replacements 376556 # number of replacements -system.cpu1.icache.tagsinuse 474.951242 # Cycle average of tags in use -system.cpu1.icache.total_refs 19002611 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 377068 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 50.395714 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 327008186500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 474.951242 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.927639 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.927639 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 19002611 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 19002611 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 19002611 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 19002611 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 19002611 # number of overall hits -system.cpu1.icache.overall_hits::total 19002611 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 377068 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 377068 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 377068 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 377068 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 377068 # number of overall misses -system.cpu1.icache.overall_misses::total 377068 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5155062500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 5155062500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 5155062500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 5155062500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 5155062500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 5155062500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 19379679 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 19379679 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 19379679 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 19379679 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 19379679 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 19379679 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.019457 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.019457 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.019457 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.019457 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.019457 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.019457 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13671.439899 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13671.439899 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13671.439899 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13671.439899 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13671.439899 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13671.439899 # average overall miss latency +system.cpu1.kern.inst.quiesce 39064 # number of quiesce instructions executed +system.cpu1.icache.tags.replacements 376544 # number of replacements +system.cpu1.icache.tags.tagsinuse 474.938465 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 19004396 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 377056 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 50.402052 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 327017678500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 474.938465 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.927614 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.927614 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 19004396 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 19004396 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 19004396 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 19004396 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 19004396 # number of overall hits +system.cpu1.icache.overall_hits::total 19004396 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 377056 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 377056 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 377056 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 377056 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 377056 # number of overall misses +system.cpu1.icache.overall_misses::total 377056 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5154731460 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 5154731460 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 5154731460 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 5154731460 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 5154731460 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 5154731460 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 19381452 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 19381452 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 19381452 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 19381452 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 19381452 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 19381452 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.019454 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.019454 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.019454 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.019454 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.019454 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.019454 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13670.997040 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13670.997040 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13670.997040 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13670.997040 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13670.997040 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13670.997040 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1613,120 +1611,120 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 377068 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 377068 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 377068 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 377068 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 377068 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 377068 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4400893067 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 4400893067 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4400893067 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 4400893067 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4400893067 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 4400893067 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6177000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6177000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6177000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 6177000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.019457 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.019457 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.019457 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.019457 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.019457 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.019457 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11671.351234 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11671.351234 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11671.351234 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11671.351234 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11671.351234 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11671.351234 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 377056 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 377056 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 377056 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 377056 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 377056 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 377056 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4398633040 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 4398633040 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4398633040 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 4398633040 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4398633040 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 4398633040 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6184500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6184500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6184500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 6184500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.019454 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.019454 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.019454 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.019454 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.019454 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.019454 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11665.728804 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11665.728804 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11665.728804 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11665.728804 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11665.728804 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11665.728804 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 220463 # number of replacements -system.cpu1.dcache.tagsinuse 471.524014 # Cycle average of tags in use -system.cpu1.dcache.total_refs 8230847 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 220830 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 37.272323 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 106217593500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 471.524014 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.920945 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.920945 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 4389322 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 4389322 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 3673243 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 3673243 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 73459 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 73459 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 73734 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 73734 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 8062565 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 8062565 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 8062565 # number of overall hits -system.cpu1.dcache.overall_hits::total 8062565 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 133853 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 133853 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 112791 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 112791 # number of WriteReq misses +system.cpu1.dcache.tags.replacements 220840 # number of replacements +system.cpu1.dcache.tags.tagsinuse 471.619758 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 8232994 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 221207 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 37.218506 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 106228428000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 471.619758 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.921132 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.921132 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 4390579 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 4390579 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 3674302 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 3674302 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 73464 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 73464 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 73742 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 73742 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 8064881 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 8064881 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 8064881 # number of overall hits +system.cpu1.dcache.overall_hits::total 8064881 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 133951 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 133951 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 112879 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 112879 # number of WriteReq misses system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9745 # number of LoadLockedReq misses system.cpu1.dcache.LoadLockedReq_misses::total 9745 # number of LoadLockedReq misses system.cpu1.dcache.StoreCondReq_misses::cpu1.data 9392 # number of StoreCondReq misses system.cpu1.dcache.StoreCondReq_misses::total 9392 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 246644 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 246644 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 246644 # number of overall misses -system.cpu1.dcache.overall_misses::total 246644 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1652691000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1652691000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3703180000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 3703180000 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 77927500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 77927500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 48937000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 48937000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 5355871000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 5355871000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 5355871000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 5355871000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 4523175 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 4523175 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 3786034 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 3786034 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 83204 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 83204 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 83126 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 83126 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 8309209 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 8309209 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 8309209 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 8309209 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.029593 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.029593 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.029791 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.029791 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.117122 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.117122 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.112985 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.112985 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029683 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.029683 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.029683 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.029683 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12347.059834 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12347.059834 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32832.229522 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 32832.229522 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 7996.664956 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 7996.664956 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5210.498296 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5210.498296 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21714.985972 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 21714.985972 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21714.985972 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 21714.985972 # average overall miss latency +system.cpu1.dcache.demand_misses::cpu1.data 246830 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 246830 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 246830 # number of overall misses +system.cpu1.dcache.overall_misses::total 246830 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1653824236 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1653824236 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3737179210 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 3737179210 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 78087000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 78087000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 49049473 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 49049473 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 5391003446 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 5391003446 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 5391003446 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 5391003446 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 4524530 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 4524530 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 3787181 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 3787181 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 83209 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 83209 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 83134 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 83134 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 8311711 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 8311711 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 8311711 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 8311711 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.029606 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.029606 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.029806 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.029806 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.117115 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.117115 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.112974 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.112974 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029697 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.029697 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.029697 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.029697 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12346.486670 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12346.486670 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 33107.834141 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 33107.834141 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8013.032324 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8013.032324 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5222.473701 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5222.473701 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21840.957120 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 21840.957120 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21840.957120 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 21840.957120 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1735,66 +1733,66 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 199647 # number of writebacks -system.cpu1.dcache.writebacks::total 199647 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 133853 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 133853 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 112791 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 112791 # number of WriteReq MSHR misses +system.cpu1.dcache.writebacks::writebacks 200060 # number of writebacks +system.cpu1.dcache.writebacks::total 200060 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 133951 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 133951 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 112879 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 112879 # number of WriteReq MSHR misses system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9745 # number of LoadLockedReq MSHR misses system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9745 # number of LoadLockedReq MSHR misses system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9391 # number of StoreCondReq MSHR misses system.cpu1.dcache.StoreCondReq_mshr_misses::total 9391 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 246644 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 246644 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 246644 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 246644 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1384976517 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1384976517 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 3477593010 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 3477593010 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 58436502 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 58436502 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 30157000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30157000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_misses::cpu1.data 246830 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 246830 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 246830 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 246830 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1384995764 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1384995764 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 3490409790 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 3490409790 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 58580000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 58580000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 30268527 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30268527 # number of StoreCondReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4862569527 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4862569527 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4862569527 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4862569527 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168387734500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168387734500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 531024500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 531024500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 168918759000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 168918759000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.029593 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.029593 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.029791 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.029791 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.117122 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.117122 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.112973 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.112973 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029683 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.029683 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.029683 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.029683 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10346.996459 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10346.996459 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30832.185281 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 30832.185281 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 5996.562545 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 5996.562545 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3211.266106 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3211.266106 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4875405554 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4875405554 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4875405554 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4875405554 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168372273000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168372273000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 531015000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 531015000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 168903288000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 168903288000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.029606 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.029606 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.029806 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.029806 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.117115 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.117115 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.112962 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.112962 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029697 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.029697 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.029697 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.029697 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10339.570171 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10339.570171 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30921.693052 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 30921.693052 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6011.287840 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6011.287840 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3223.142051 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3223.142051 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19714.931346 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19714.931346 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19714.931346 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19714.931346 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19752.078572 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19752.078572 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19752.078572 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19752.078572 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1802,12 +1800,12 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 0 # number of replacements -system.iocache.tagsinuse 0 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.avg_refs nan # Average number of references to valid blocks. -system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.iocache.tags.replacements 0 # number of replacements +system.iocache.tags.tagsinuse 0 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs nan # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1816,10 +1814,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 626235127001 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 626235127001 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 626235127001 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 626235127001 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 624927975253 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 624927975253 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 624927975253 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 624927975253 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 934a4cb6c..955e513bb 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,129 +1,129 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.615622 # Number of seconds simulated -sim_ticks 2615622384000 # Number of ticks simulated -final_tick 2615622384000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.615733 # Number of seconds simulated +sim_ticks 2615733285000 # Number of ticks simulated +final_tick 2615733285000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 264818 # Simulator instruction rate (inst/s) -host_op_rate 336993 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 11506330329 # Simulator tick rate (ticks/s) -host_mem_usage 396436 # Number of bytes of host memory used -host_seconds 227.32 # Real time elapsed on the host -sim_insts 60198587 # Number of instructions simulated -sim_ops 76605405 # Number of ops (including micro ops) simulated +host_inst_rate 250012 # Simulator instruction rate (inst/s) +host_op_rate 318151 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 10863402189 # Simulator tick rate (ticks/s) +host_mem_usage 396412 # Number of bytes of host memory used +host_seconds 240.78 # Real time elapsed on the host +sim_insts 60198861 # Number of instructions simulated +sim_ops 76605713 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 704800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9093200 # Number of bytes read from this memory -system.physmem.bytes_read::total 132481840 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 704800 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 704800 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3709760 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 704864 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9093712 # Number of bytes read from this memory +system.physmem.bytes_read::total 132482416 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 704864 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 704864 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3710144 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6725832 # Number of bytes written to this memory +system.physmem.bytes_written::total 6726216 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 17215 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142115 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15494761 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57965 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 17216 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142123 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15494770 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57971 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811983 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 46904092 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 811989 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46902103 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 122 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 269458 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3476496 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50650216 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 269458 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 269458 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1418309 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1153099 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2571408 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1418309 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 46904092 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 269471 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3476544 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50648289 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 269471 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 269471 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1418395 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1153050 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2571446 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1418395 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46902103 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 122 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 269458 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4629595 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53221624 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15494761 # Total number of read requests seen -system.physmem.writeReqs 811983 # Total number of write requests seen -system.physmem.cpureqs 215166 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 991664704 # Total number of bytes read from memory -system.physmem.bytesWritten 51966912 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 132481840 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6725832 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 301 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4516 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 968108 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 967904 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 967765 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 967946 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 974722 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 968494 # Track reads on a per bank basis +system.physmem.bw_total::cpu.inst 269471 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4629594 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53219735 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15494770 # Total number of read requests seen +system.physmem.writeReqs 811989 # Total number of write requests seen +system.physmem.cpureqs 215180 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 991665280 # Total number of bytes read from memory +system.physmem.bytesWritten 51967296 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 132482416 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6726216 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 299 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4515 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 968107 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 967905 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 967771 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 967944 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 974725 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 968490 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 967971 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 967832 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 968523 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 968301 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 967958 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 967840 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 968519 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 968300 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 967957 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 967809 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 967930 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 967935 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 967629 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 967885 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 967683 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 49152 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 49010 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50853 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 50913 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 51127 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 51430 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 51157 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51246 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51368 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50878 # Track writes on a per bank basis +system.physmem.perBankRdReqs::14 967887 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 967682 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 49150 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 49013 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50857 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 50909 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51128 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 51425 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 51159 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51254 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51364 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51157 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50876 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 50797 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 50871 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 50874 # Track writes on a per bank basis system.physmem.perBankWrReqs::13 50522 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 50825 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 50676 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 50827 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 50677 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 2615618000000 # Total gap between requests +system.physmem.totGap 2615728912000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 6652 # Categorize read packet sizes system.physmem.readPktSize::3 15335424 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 152685 # Categorize read packet sizes +system.physmem.readPktSize::6 152694 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 754018 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 57965 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1126555 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 973164 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1018253 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3775658 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2831038 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2826406 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2774250 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 21901 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 19136 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 31670 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 43534 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 30921 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 5697 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 5598 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 5455 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 5184 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 40 # What read queue length does an incoming req see +system.physmem.writePktSize::6 57971 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1128832 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 975833 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1007328 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3775576 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2827750 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2822812 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2787859 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 21456 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 18919 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 32464 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 45819 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 32079 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 4562 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 4458 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 4371 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 4308 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 45 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -139,8 +139,8 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 35284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 35302 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 35288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 35301 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 35303 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 35304 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 35304 # What write queue length does an incoming req see @@ -153,17 +153,17 @@ system.physmem.wrQLenPdf::10 35304 # Wh system.physmem.wrQLenPdf::11 35304 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 35304 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 35304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35304 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 35303 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 35303 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 35303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see @@ -171,308 +171,327 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 38567 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 27059.676926 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 2495.376643 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 33105.439598 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-127 5489 14.23% 14.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-191 3331 8.64% 22.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-255 2176 5.64% 28.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-319 1697 4.40% 32.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-383 1162 3.01% 35.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-447 1046 2.71% 38.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-511 828 2.15% 40.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-575 748 1.94% 42.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-639 582 1.51% 44.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-703 509 1.32% 45.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-767 411 1.07% 46.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-831 479 1.24% 47.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-895 285 0.74% 48.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-959 248 0.64% 49.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-1023 187 0.48% 49.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1087 239 0.62% 50.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1151 141 0.37% 50.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1215 137 0.36% 51.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1279 106 0.27% 51.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1343 105 0.27% 51.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1407 92 0.24% 51.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1471 151 0.39% 52.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1535 970 2.52% 54.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1599 203 0.53% 55.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1663 135 0.35% 55.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1727 110 0.29% 55.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1791 91 0.24% 56.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1855 77 0.20% 56.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1919 66 0.17% 56.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1983 47 0.12% 56.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-2047 51 0.13% 56.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2111 64 0.17% 56.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2175 37 0.10% 57.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2239 25 0.06% 57.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2303 18 0.05% 57.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2367 25 0.06% 57.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2431 26 0.07% 57.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2495 13 0.03% 57.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2559 25 0.06% 57.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2623 11 0.03% 57.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2687 14 0.04% 57.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2751 8 0.02% 57.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2815 18 0.05% 57.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2879 9 0.02% 57.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2943 8 0.02% 57.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-3007 14 0.04% 57.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3071 7 0.02% 57.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3135 17 0.04% 57.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3199 7 0.02% 57.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3263 8 0.02% 57.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3327 12 0.03% 57.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3391 12 0.03% 57.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3455 3 0.01% 57.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3519 9 0.02% 57.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3583 3 0.01% 57.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3647 6 0.02% 57.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3711 12 0.03% 57.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3775 9 0.02% 57.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3839 7 0.02% 57.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3903 9 0.02% 57.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3967 4 0.01% 57.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-4031 6 0.02% 57.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4095 9 0.02% 57.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4159 44 0.11% 58.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4223 3 0.01% 58.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4287 2 0.01% 58.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4351 3 0.01% 58.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4415 5 0.01% 58.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4479 6 0.02% 58.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4543 2 0.01% 58.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4607 5 0.01% 58.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4671 2 0.01% 58.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4735 1 0.00% 58.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4799 1 0.00% 58.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4863 3 0.01% 58.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4927 7 0.02% 58.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-5055 6 0.02% 58.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5119 1 0.00% 58.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5183 12 0.03% 58.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5247 1 0.00% 58.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5311 5 0.01% 58.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5375 3 0.01% 58.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5439 5 0.01% 58.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5503 7 0.02% 58.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5567 2 0.01% 58.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5631 2 0.01% 58.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5695 2 0.01% 58.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5759 6 0.02% 58.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5887 3 0.01% 58.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5951 2 0.01% 58.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-6015 3 0.01% 58.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6079 2 0.01% 58.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6143 2 0.01% 58.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6207 180 0.47% 58.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6271 1 0.00% 58.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6335 1 0.00% 58.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6399 3 0.01% 58.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6463 5 0.01% 58.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6527 2 0.01% 58.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6591 3 0.01% 58.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6655 1 0.00% 58.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6719 2 0.01% 58.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6783 1 0.00% 58.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6847 15 0.04% 58.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6911 3 0.01% 58.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6975 1 0.00% 58.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-7039 2 0.01% 58.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7103 2 0.01% 58.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7231 4 0.01% 58.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7295 3 0.01% 58.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7423 1 0.00% 58.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7487 2 0.01% 58.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7551 3 0.01% 58.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7615 3 0.01% 58.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7679 3 0.01% 58.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7743 11 0.03% 59.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7807 3 0.01% 59.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7871 4 0.01% 59.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7935 4 0.01% 59.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7999 3 0.01% 59.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8063 1 0.00% 59.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8127 6 0.02% 59.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8191 4 0.01% 59.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8255 327 0.85% 59.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8511 5 0.01% 59.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8832-8895 1 0.00% 59.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-9023 1 0.00% 59.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9279 3 0.01% 59.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9535 2 0.01% 59.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9791 1 0.00% 59.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10303 18 0.05% 59.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10559 1 0.00% 59.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10815 1 0.00% 60.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11200-11263 1 0.00% 60.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11327 2 0.01% 60.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11583 2 0.01% 60.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11584-11647 1 0.00% 60.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11839 1 0.00% 60.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12095 1 0.00% 60.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12351 3 0.01% 60.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12607 1 0.00% 60.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13119 1 0.00% 60.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13631 1 0.00% 60.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14143 1 0.00% 60.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14399 2 0.01% 60.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14655 2 0.01% 60.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15423 3 0.01% 60.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15680-15743 1 0.00% 60.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15935 1 0.00% 60.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16191 2 0.01% 60.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16447 1 0.00% 60.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17471 2 0.01% 60.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17727 1 0.00% 60.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17983 1 0.00% 60.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18239 1 0.00% 60.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18495 2 0.01% 60.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19008-19071 1 0.00% 60.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19263 1 0.00% 60.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19519 3 0.01% 60.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19775 3 0.01% 60.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-20031 1 0.00% 60.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20287 1 0.00% 60.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20543 2 0.01% 60.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20799 1 0.00% 60.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21311 1 0.00% 60.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21567 1 0.00% 60.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21823 2 0.01% 60.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22591 4 0.01% 60.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22847 1 0.00% 60.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23040-23103 3 0.01% 60.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23359 1 0.00% 60.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23615 5 0.01% 60.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23808-23871 1 0.00% 60.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24127 2 0.01% 60.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24639 1 0.00% 60.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24895 1 0.00% 60.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24960-25023 1 0.00% 60.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25663 3 0.01% 60.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25919 2 0.01% 60.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26431 1 0.00% 60.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26687 4 0.01% 60.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26880-26943 1 0.00% 60.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27199 1 0.00% 60.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27967 1 0.00% 60.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28096-28159 1 0.00% 60.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28735 1 0.00% 60.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28991 1 0.00% 60.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29376-29439 1 0.00% 60.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29759 6 0.02% 60.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-30015 2 0.01% 60.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30527 3 0.01% 60.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30783 3 0.01% 60.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31168-31231 1 0.00% 60.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31295 2 0.01% 60.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31807 5 0.01% 60.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32000-32063 1 0.00% 60.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32831 2 0.01% 60.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33343 4 0.01% 60.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33599 56 0.15% 60.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33600-33663 1 0.00% 60.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34048-34111 1 0.00% 60.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34879 1 0.00% 60.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35903 1 0.00% 60.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37376-37439 1 0.00% 60.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38912-38975 1 0.00% 60.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39936-39999 2 0.01% 60.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42240-42303 1 0.00% 60.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42496-42559 2 0.01% 60.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43071 1 0.00% 60.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43520-43583 1 0.00% 60.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45056-45119 1 0.00% 60.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45568-45631 1 0.00% 60.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46143 1 0.00% 60.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47423 1 0.00% 60.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48191 1 0.00% 60.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49215 2 0.01% 60.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49664-49727 2 0.01% 60.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50176-50239 1 0.00% 60.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51200-51263 1 0.00% 60.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52480-52543 1 0.00% 60.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52992-53055 1 0.00% 60.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::56320-56383 3 0.01% 60.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::57088-57151 1 0.00% 60.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::59392-59455 1 0.00% 60.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::60416-60479 2 0.01% 60.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::61440-61503 1 0.00% 60.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::63488-63551 2 0.01% 60.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::63808-63871 1 0.00% 60.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::64512-64575 1 0.00% 60.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65024-65087 19 0.05% 60.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65088-65151 6 0.02% 60.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65152-65215 2 0.01% 60.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65280-65343 6 0.02% 60.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65344-65407 6 0.02% 60.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65408-65471 14 0.04% 60.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65472-65535 6 0.02% 60.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65536-65599 14789 38.35% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::71360-71423 1 0.00% 99.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::73984-74047 1 0.00% 99.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::83008-83071 1 0.00% 99.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 38488 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 27115.229266 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 2500.122459 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 33119.773163 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-127 5498 14.28% 14.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-191 3288 8.54% 22.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-255 2221 5.77% 28.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-319 1687 4.38% 32.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-383 1187 3.08% 36.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-447 1056 2.74% 38.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-511 814 2.11% 40.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-575 739 1.92% 42.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-639 550 1.43% 44.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-703 512 1.33% 45.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-767 421 1.09% 46.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-831 397 1.03% 47.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-895 314 0.82% 48.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-959 250 0.65% 49.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-1023 198 0.51% 49.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1087 236 0.61% 50.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1151 133 0.35% 50.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1215 138 0.36% 51.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1279 98 0.25% 51.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1343 109 0.28% 51.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1407 78 0.20% 51.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1471 154 0.40% 52.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1535 969 2.52% 54.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1599 195 0.51% 55.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1663 143 0.37% 55.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1727 120 0.31% 55.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1791 89 0.23% 56.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1855 73 0.19% 56.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1919 63 0.16% 56.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1983 55 0.14% 56.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-2047 51 0.13% 56.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2111 51 0.13% 56.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2175 31 0.08% 56.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2239 29 0.08% 57.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2303 27 0.07% 57.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2367 16 0.04% 57.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2431 18 0.05% 57.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2495 16 0.04% 57.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2559 22 0.06% 57.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2623 11 0.03% 57.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2687 16 0.04% 57.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2751 9 0.02% 57.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2815 14 0.04% 57.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2879 16 0.04% 57.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2943 11 0.03% 57.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-3007 14 0.04% 57.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3071 8 0.02% 57.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3135 19 0.05% 57.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3199 9 0.02% 57.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3263 4 0.01% 57.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3327 13 0.03% 57.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3391 10 0.03% 57.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3455 6 0.02% 57.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3519 7 0.02% 57.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3583 3 0.01% 57.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3647 6 0.02% 57.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3711 13 0.03% 57.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3775 10 0.03% 57.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3839 5 0.01% 57.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3903 10 0.03% 57.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3967 3 0.01% 57.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-4031 7 0.02% 57.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4095 8 0.02% 57.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4159 40 0.10% 57.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4223 2 0.01% 57.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4287 4 0.01% 58.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4351 3 0.01% 58.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4415 6 0.02% 58.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4479 4 0.01% 58.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4543 3 0.01% 58.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4607 5 0.01% 58.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4671 6 0.02% 58.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4735 1 0.00% 58.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4799 1 0.00% 58.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4863 3 0.01% 58.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4927 9 0.02% 58.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4991 2 0.01% 58.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-5055 3 0.01% 58.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5119 2 0.01% 58.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5183 9 0.02% 58.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5247 2 0.01% 58.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5311 5 0.01% 58.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5375 4 0.01% 58.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5439 3 0.01% 58.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5503 5 0.01% 58.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5567 4 0.01% 58.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5631 4 0.01% 58.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5695 6 0.02% 58.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5759 2 0.01% 58.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5951 4 0.01% 58.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-6015 1 0.00% 58.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6079 2 0.01% 58.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6143 1 0.00% 58.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6207 184 0.48% 58.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6271 2 0.01% 58.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6335 1 0.00% 58.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6463 2 0.01% 58.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6527 3 0.01% 58.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6591 4 0.01% 58.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6655 1 0.00% 58.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6719 2 0.01% 58.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6783 1 0.00% 58.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6847 15 0.04% 58.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6911 3 0.01% 58.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6975 1 0.00% 58.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-7039 2 0.01% 58.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7103 3 0.01% 58.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7231 4 0.01% 58.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7295 4 0.01% 58.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7359 1 0.00% 58.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7487 2 0.01% 58.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7551 3 0.01% 58.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7615 5 0.01% 58.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7679 3 0.01% 58.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7743 6 0.02% 58.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7807 4 0.01% 58.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7871 4 0.01% 58.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7935 4 0.01% 58.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7999 1 0.00% 58.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8063 1 0.00% 58.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8127 6 0.02% 58.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8191 3 0.01% 58.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8255 327 0.85% 59.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8256-8319 1 0.00% 59.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8576-8639 1 0.00% 59.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8767 1 0.00% 59.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8832-8895 1 0.00% 59.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9279 5 0.01% 59.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9791 1 0.00% 59.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9856-9919 1 0.00% 59.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-10047 1 0.00% 59.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10112-10175 2 0.01% 59.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10303 20 0.05% 59.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10624-10687 1 0.00% 59.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11071 1 0.00% 59.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12095 1 0.00% 59.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12351 2 0.01% 59.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12607 1 0.00% 59.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12672-12735 1 0.00% 59.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12863 1 0.00% 59.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13119 1 0.00% 59.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13696-13759 1 0.00% 59.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13887 1 0.00% 59.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14143 2 0.01% 59.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14399 3 0.01% 59.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15423 4 0.01% 59.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15679 1 0.00% 59.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15680-15743 1 0.00% 59.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16191 1 0.00% 59.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16447 1 0.00% 59.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17024-17087 1 0.00% 59.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17215 3 0.01% 59.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17983 1 0.00% 59.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18048-18111 1 0.00% 59.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18239 1 0.00% 60.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18304-18367 1 0.00% 60.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18495 3 0.01% 60.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18688-18751 1 0.00% 60.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19263 1 0.00% 60.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19519 1 0.00% 60.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19712-19775 2 0.01% 60.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19968-20031 1 0.00% 60.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20096-20159 1 0.00% 60.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20288-20351 1 0.00% 60.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20543 1 0.00% 60.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20736-20799 1 0.00% 60.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21248-21311 1 0.00% 60.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21567 1 0.00% 60.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21823 1 0.00% 60.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22016-22079 1 0.00% 60.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22272-22335 2 0.01% 60.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22400-22463 1 0.00% 60.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22591 3 0.01% 60.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23040-23103 2 0.01% 60.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23296-23359 1 0.00% 60.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23424-23487 1 0.00% 60.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23615 2 0.01% 60.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23808-23871 1 0.00% 60.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24127 1 0.00% 60.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24639 2 0.01% 60.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24895 2 0.01% 60.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25088-25151 2 0.01% 60.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25216-25279 1 0.00% 60.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25344-25407 2 0.01% 60.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25663 1 0.00% 60.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25664-25727 1 0.00% 60.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25792-25855 1 0.00% 60.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26175 1 0.00% 60.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26240-26303 1 0.00% 60.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26431 2 0.01% 60.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26687 1 0.00% 60.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26880-26943 2 0.01% 60.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27455 1 0.00% 60.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27711 3 0.01% 60.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28735 2 0.01% 60.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28991 2 0.01% 60.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29247 1 0.00% 60.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29312-29375 1 0.00% 60.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29503 1 0.00% 60.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29632-29695 1 0.00% 60.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29759 2 0.01% 60.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30272-30335 1 0.00% 60.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30527 1 0.00% 60.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30783 4 0.01% 60.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30848-30911 1 0.00% 60.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31424-31487 1 0.00% 60.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31551 1 0.00% 60.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31807 3 0.01% 60.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32319 1 0.00% 60.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32575 1 0.00% 60.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32831 2 0.01% 60.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33087 16 0.04% 60.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33088-33151 1 0.00% 60.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33152-33215 24 0.06% 60.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33343 16 0.04% 60.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33855 1 0.00% 60.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34879 1 0.00% 60.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35072-35135 1 0.00% 60.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36927 1 0.00% 60.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37951 1 0.00% 60.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39168-39231 1 0.00% 60.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39487 1 0.00% 60.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40704-40767 1 0.00% 60.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-41023 1 0.00% 60.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-42047 2 0.01% 60.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42559 1 0.00% 60.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42815 1 0.00% 60.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43071 1 0.00% 60.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43327 1 0.00% 60.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44095 1 0.00% 60.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44992-45055 1 0.00% 60.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47167 2 0.01% 60.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47679 1 0.00% 60.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48191 1 0.00% 60.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49215 1 0.00% 60.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49920-49983 1 0.00% 60.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50176-50239 1 0.00% 60.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50432-50495 1 0.00% 60.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51200-51263 2 0.01% 60.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51456-51519 1 0.00% 60.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52736-52799 1 0.00% 60.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::54272-54335 1 0.00% 60.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::55296-55359 1 0.00% 60.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::56320-56383 2 0.01% 60.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::59392-59455 1 0.00% 60.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::62464-62527 1 0.00% 60.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::64000-64063 1 0.00% 60.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::64768-64831 1 0.00% 60.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65024-65087 19 0.05% 60.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65088-65151 6 0.02% 60.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65152-65215 2 0.01% 60.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65280-65343 6 0.02% 60.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65344-65407 6 0.02% 60.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65408-65471 14 0.04% 60.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65472-65535 6 0.02% 60.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65536-65599 14794 38.44% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::71360-71423 1 0.00% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::76928-76991 1 0.00% 99.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::81536-81599 1 0.00% 99.05% # Bytes accessed per row activation system.physmem.bytesPerActivate::85504-85567 1 0.00% 99.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::93120-93183 1 0.00% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::97152-97215 1 0.00% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::97408-97471 1 0.00% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::95680-95743 1 0.00% 99.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::96064-96127 1 0.00% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::98880-98943 1 0.00% 99.06% # Bytes accessed per row activation system.physmem.bytesPerActivate::100672-100735 1 0.00% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::103680-103743 1 0.00% 99.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::104768-104831 1 0.00% 99.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::106432-106495 1 0.00% 99.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::109760-109823 1 0.00% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::103488-103551 1 0.00% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::106240-106303 1 0.00% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::106624-106687 1 0.00% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::109440-109503 1 0.00% 99.07% # Bytes accessed per row activation system.physmem.bytesPerActivate::110848-110911 1 0.00% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::110912-110975 1 0.00% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::114240-114303 1 0.00% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::115328-115391 1 0.00% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::116992-117055 1 0.00% 99.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::120320-120383 1 0.00% 99.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::111232-111295 1 0.00% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::114048-114111 1 0.00% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::117184-117247 1 0.00% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::118272-118335 1 0.00% 99.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::120000-120063 1 0.00% 99.09% # Bytes accessed per row activation system.physmem.bytesPerActivate::121408-121471 1 0.00% 99.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::121472-121535 1 0.00% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::124416-124479 1 0.00% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::127552-127615 1 0.00% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128640-128703 1 0.00% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::130176-130239 1 0.00% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::121792-121855 1 0.00% 99.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::124608-124671 1 0.00% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::125696-125759 1 0.00% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128832-128895 1 0.00% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::130176-130239 1 0.00% 99.10% # Bytes accessed per row activation system.physmem.bytesPerActivate::130368-130431 1 0.00% 99.11% # Bytes accessed per row activation system.physmem.bytesPerActivate::130432-130495 1 0.00% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::130496-130559 1 0.00% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::130624-130687 1 0.00% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::130560-130623 1 0.00% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::130624-130687 1 0.00% 99.11% # Bytes accessed per row activation system.physmem.bytesPerActivate::130688-130751 1 0.00% 99.12% # Bytes accessed per row activation system.physmem.bytesPerActivate::130880-130943 1 0.00% 99.12% # Bytes accessed per row activation system.physmem.bytesPerActivate::131072-131135 328 0.85% 99.97% # Bytes accessed per row activation system.physmem.bytesPerActivate::131200-131263 1 0.00% 99.97% # Bytes accessed per row activation system.physmem.bytesPerActivate::132096-132159 3 0.01% 99.98% # Bytes accessed per row activation system.physmem.bytesPerActivate::136576-136639 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::161408-161471 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::190336-190399 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::196032-196095 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::156992-157055 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::193280-193343 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::196096-196159 1 0.00% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::196608-196671 2 0.01% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::420352-420415 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 38567 # Bytes accessed per row activation -system.physmem.totQLat 306544443250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 400266823250 # Sum of mem lat for all requests -system.physmem.totBusLat 77472300000 # Total cycles spent in databus access -system.physmem.totBankLat 16250080000 # Total cycles spent in bank access -system.physmem.avgQLat 19784.13 # Average queueing delay per request -system.physmem.avgBankLat 1048.77 # Average bank access latency per request +system.physmem.bytesPerActivate::total 38488 # Bytes accessed per row activation +system.physmem.totQLat 303199099750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 396944112250 # Sum of mem lat for all requests +system.physmem.totBusLat 77472355000 # Total cycles spent in databus access +system.physmem.totBankLat 16272657500 # Total cycles spent in bank access +system.physmem.avgQLat 19568.21 # Average queueing delay per request +system.physmem.avgBankLat 1050.22 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25832.90 # Average memory access latency -system.physmem.avgRdBW 379.13 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 25618.44 # Average memory access latency +system.physmem.avgRdBW 379.12 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 19.87 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 50.65 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 2.57 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.12 # Data bus utilization in percentage system.physmem.avgRdQLen 0.15 # Average read queue length over time -system.physmem.avgWrQLen 10.80 # Average write queue length over time -system.physmem.readRowHits 15469403 # Number of row buffer hits during reads -system.physmem.writeRowHits 798459 # Number of row buffer hits during writes +system.physmem.avgWrQLen 10.84 # Average write queue length over time +system.physmem.readRowHits 15469547 # Number of row buffer hits during reads +system.physmem.writeRowHits 798405 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.84 # Row buffer hit rate for reads system.physmem.writeRowHitRate 98.33 # Row buffer hit rate for writes -system.physmem.avgGap 160401.00 # Average gap between requests +system.physmem.avgGap 160407.65 # Average gap between requests system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -485,59 +504,59 @@ system.realview.nvmem.bw_inst_read::cpu.inst 8 system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54138467 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16546589 # Transaction distribution -system.membus.trans_dist::ReadResp 16546589 # Transaction distribution +system.membus.throughput 54136540 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16546595 # Transaction distribution +system.membus.trans_dist::ReadResp 16546595 # Transaction distribution system.membus.trans_dist::WriteReq 763368 # Transaction distribution system.membus.trans_dist::WriteResp 763368 # Transaction distribution -system.membus.trans_dist::Writeback 57965 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4516 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4516 # Transaction distribution -system.membus.trans_dist::ReadExReq 132246 # Transaction distribution -system.membus.trans_dist::ReadExResp 132246 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382986 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::Writeback 57971 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4515 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4515 # Transaction distribution +system.membus.trans_dist::ReadExReq 132250 # Transaction distribution +system.membus.trans_dist::ReadExResp 132250 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382988 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1893707 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1893729 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3850 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4280555 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4280579 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30670848 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30670848 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.bridge.slave 2382986 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.bridge.slave 2382988 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 32564555 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 32564577 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.realview.gic.pio 3850 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34951403 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390389 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 34951427 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390393 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16524280 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16525240 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7700 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 18922393 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 18923357 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 122683392 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 122683392 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.bridge.slave 2390389 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.bridge.slave 2390393 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 139207672 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 139208632 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::system.realview.gic.pio 7700 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 141605785 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 141605785 # Total data (bytes) +system.membus.tot_pkt_size::total 141606749 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 141606749 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1206150500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1206151500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 17904777500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 17903854000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.7 # Layer utilization (%) system.membus.reqLayer3.occupancy 3613000 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) system.membus.reqLayer5.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 4945376509 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4944443675 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 34635651750 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 34633310000 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -545,13 +564,13 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 47817981 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16518751 # Transaction distribution -system.iobus.trans_dist::ReadResp 16518751 # Transaction distribution +system.iobus.throughput 47815955 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16518752 # Transaction distribution +system.iobus.trans_dist::ReadResp 16518752 # Transaction distribution system.iobus.trans_dist::WriteReq 8166 # Transaction distribution system.iobus.trans_dist::WriteResp 8166 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7944 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7946 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 534 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -573,11 +592,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382986 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382988 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 30670848 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.realview_io.pio 7944 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.realview_io.pio 7946 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.timer0.pio 534 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -600,9 +619,9 @@ system.iobus.pkt_count::system.realview.aaci_fake.pio 16 system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 33053834 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 33053836 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15892 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1068 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -624,11 +643,11 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390389 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390393 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 122683392 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.realview_io.pio 15888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.realview_io.pio 15892 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.timer0.pio 1068 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -651,11 +670,11 @@ system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 125073781 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 125073781 # Total data (bytes) +system.iobus.tot_pkt_size::total 125073785 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 125073785 # Total data (bytes) system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3977000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3978000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 534000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -701,32 +720,32 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 15335424000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374820000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374822000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 30670848000 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 1.2 # Layer utilization (%) +system.iobus.respLayer1.occupancy 42022039000 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 14996055 # DTB read hits -system.cpu.dtb.read_misses 7342 # DTB read misses -system.cpu.dtb.write_hits 11230429 # DTB write hits -system.cpu.dtb.write_misses 2216 # DTB write misses +system.cpu.dtb.read_hits 14996132 # DTB read hits +system.cpu.dtb.read_misses 7340 # DTB read misses +system.cpu.dtb.write_hits 11230462 # DTB write hits +system.cpu.dtb.write_misses 2218 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_entries 3506 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 192 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 194 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 15003397 # DTB read accesses -system.cpu.dtb.write_accesses 11232645 # DTB write accesses +system.cpu.dtb.read_accesses 15003472 # DTB read accesses +system.cpu.dtb.write_accesses 11232680 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 26226484 # DTB hits +system.cpu.dtb.hits 26226594 # DTB hits system.cpu.dtb.misses 9558 # DTB misses -system.cpu.dtb.accesses 26236042 # DTB accesses -system.cpu.itb.inst_hits 61492425 # ITB inst hits +system.cpu.dtb.accesses 26236152 # DTB accesses +system.cpu.itb.inst_hits 61492700 # ITB inst hits system.cpu.itb.inst_misses 4471 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -743,79 +762,79 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 61496896 # ITB inst accesses -system.cpu.itb.hits 61492425 # DTB hits +system.cpu.itb.inst_accesses 61497171 # ITB inst accesses +system.cpu.itb.hits 61492700 # DTB hits system.cpu.itb.misses 4471 # DTB misses -system.cpu.itb.accesses 61496896 # DTB accesses -system.cpu.numCycles 5231244768 # number of cpu cycles simulated +system.cpu.itb.accesses 61497171 # DTB accesses +system.cpu.numCycles 5231466570 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60198587 # Number of instructions committed -system.cpu.committedOps 76605405 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 68872209 # Number of integer alu accesses +system.cpu.committedInsts 60198861 # Number of instructions committed +system.cpu.committedOps 76605713 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 68872503 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses -system.cpu.num_func_calls 2140451 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7948368 # number of instructions that are conditional controls -system.cpu.num_int_insts 68872209 # number of integer instructions +system.cpu.num_func_calls 2140458 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7948408 # number of instructions that are conditional controls +system.cpu.num_int_insts 68872503 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions -system.cpu.num_int_register_reads 394776354 # number of times the integer registers were read -system.cpu.num_int_register_writes 74181797 # number of times the integer registers were written +system.cpu.num_int_register_reads 394778081 # number of times the integer registers were read +system.cpu.num_int_register_writes 74182147 # number of times the integer registers were written system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written -system.cpu.num_mem_refs 27393915 # number of memory refs -system.cpu.num_load_insts 15660071 # Number of load instructions -system.cpu.num_store_insts 11733844 # Number of store instructions -system.cpu.num_idle_cycles 4582065338.612248 # Number of idle cycles -system.cpu.num_busy_cycles 649179429.387752 # Number of busy cycles -system.cpu.not_idle_fraction 0.124097 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.875903 # Percentage of idle cycles +system.cpu.num_mem_refs 27394052 # number of memory refs +system.cpu.num_load_insts 15660178 # Number of load instructions +system.cpu.num_store_insts 11733874 # Number of store instructions +system.cpu.num_idle_cycles 4581968820.612248 # Number of idle cycles +system.cpu.num_busy_cycles 649497749.387752 # Number of busy cycles +system.cpu.not_idle_fraction 0.124152 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.875848 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 83018 # number of quiesce instructions executed -system.cpu.icache.replacements 856250 # number of replacements -system.cpu.icache.tagsinuse 510.885364 # Cycle average of tags in use -system.cpu.icache.total_refs 60635663 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 856762 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 70.773054 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 19768699000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.885364 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.997823 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.997823 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 60635663 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 60635663 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 60635663 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 60635663 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 60635663 # number of overall hits -system.cpu.icache.overall_hits::total 60635663 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 856762 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 856762 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 856762 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 856762 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 856762 # number of overall misses -system.cpu.icache.overall_misses::total 856762 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11759087500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11759087500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11759087500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11759087500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11759087500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11759087500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 61492425 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 61492425 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 61492425 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 61492425 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 61492425 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 61492425 # number of overall (read+write) accesses +system.cpu.icache.tags.replacements 856294 # number of replacements +system.cpu.icache.tags.tagsinuse 510.881133 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 60635894 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 856806 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 70.769689 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 19815360250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.881133 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997815 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997815 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 60635894 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 60635894 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 60635894 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 60635894 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 60635894 # number of overall hits +system.cpu.icache.overall_hits::total 60635894 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 856806 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 856806 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 856806 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 856806 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 856806 # number of overall misses +system.cpu.icache.overall_misses::total 856806 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11768628750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11768628750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11768628750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11768628750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11768628750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11768628750 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 61492700 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 61492700 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 61492700 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 61492700 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 61492700 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 61492700 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013933 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.013933 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.013933 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.013933 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.013933 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.013933 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13725.033907 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13725.033907 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13725.033907 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13725.033907 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13725.033907 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13725.033907 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13735.464913 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13735.464913 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13735.464913 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13735.464913 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13735.464913 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13735.464913 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -824,174 +843,174 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856762 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 856762 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 856762 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 856762 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 856762 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 856762 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10045563500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 10045563500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10045563500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 10045563500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10045563500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 10045563500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 429084500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 429084500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 429084500 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 429084500 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856806 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 856806 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 856806 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 856806 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 856806 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 856806 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10049829250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 10049829250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10049829250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 10049829250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10049829250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 10049829250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 430705250 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 430705250 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 430705250 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 430705250 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013933 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.013933 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.013933 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11725.033907 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11725.033907 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11725.033907 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11725.033907 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11725.033907 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11725.033907 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11729.410450 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11729.410450 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11729.410450 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11729.410450 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11729.410450 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11729.410450 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 62577 # number of replacements -system.cpu.l2cache.tagsinuse 50733.086800 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1684914 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 128011 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 13.162259 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 2564823166000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 37695.331461 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.dtb.walker 3.884612 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000689 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 6997.589035 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 6036.281004 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.575185 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.106775 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.092106 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.774125 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8724 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3533 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 844523 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 369967 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1226747 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 595512 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 595512 # number of Writeback hits +system.cpu.l2cache.tags.replacements 62586 # number of replacements +system.cpu.l2cache.tags.tagsinuse 50732.763816 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1683068 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 127970 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 13.152051 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 2564920911000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 37695.858347 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.884553 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000692 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 6997.437473 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 6035.582751 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.575193 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.106772 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.092096 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.774121 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8720 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3535 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 844565 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 370151 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1226971 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 595786 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 595786 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 113491 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 113491 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 8724 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 3533 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 844523 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 483458 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1340238 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 8724 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 3533 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 844523 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 483458 # number of overall hits -system.cpu.l2cache.overall_hits::total 1340238 # number of overall hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 113434 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 113434 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 8720 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 3535 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 844565 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 483585 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1340405 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 8720 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 3535 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 844565 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 483585 # number of overall hits +system.cpu.l2cache.overall_hits::total 1340405 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 10599 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 9833 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 20439 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 2885 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2885 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 133877 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133877 # number of ReadExReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 10600 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 9837 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 20444 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 2872 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 2872 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 133893 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 133893 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 10599 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 143710 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 154316 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 10600 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 143730 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 154337 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 5 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 10599 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 143710 # number of overall misses -system.cpu.l2cache.overall_misses::total 154316 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 468000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 122000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 741931500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 698335500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1440857000 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 460000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 460000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8582435500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 8582435500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 468000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 122000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 741931500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9280771000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 10023292500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 468000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 122000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 741931500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9280771000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 10023292500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8729 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3535 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 855122 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 379800 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1247186 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 595512 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 595512 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2911 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2911 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 247368 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 247368 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 8729 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 3535 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 855122 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 627168 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1494554 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 8729 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 3535 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 855122 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 627168 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1494554 # number of overall (read+write) accesses +system.cpu.l2cache.overall_misses::cpu.inst 10600 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 143730 # number of overall misses +system.cpu.l2cache.overall_misses::total 154337 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 390500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 122500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 745731750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 700197500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1446442250 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 469980 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 469980 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8609650357 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 8609650357 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 390500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 122500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 745731750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9309847857 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 10056092607 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 390500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 122500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 745731750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9309847857 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 10056092607 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8725 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3537 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 855165 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 379988 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1247415 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 595786 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 595786 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2898 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2898 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 247327 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 247327 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 8725 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 3537 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 855165 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 627315 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1494742 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 8725 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 3537 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 855165 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 627315 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1494742 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000573 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000566 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000565 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012395 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025890 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.016388 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991068 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991068 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541206 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.541206 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025888 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.016389 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991028 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991028 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541360 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.541360 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000573 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000566 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000565 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012395 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.229141 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.103252 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.229119 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.103253 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000573 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000566 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000565 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012395 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.229141 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.103252 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 93600 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 61000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70000.141523 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71019.576935 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 70495.474338 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 159.445407 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 159.445407 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 64106.870486 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 64106.870486 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 93600 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 61000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70000.141523 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 64579.855264 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 64953.034682 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 93600 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 61000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70000.141523 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 64579.855264 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 64953.034682 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.229119 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.103253 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 78100 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 61250 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70352.051887 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71179.983735 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70751.430738 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 163.642061 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 163.642061 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 64302.468068 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 64302.468068 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 78100 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 61250 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70352.051887 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 64773.170925 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 65156.719432 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 78100 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 61250 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70352.051887 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 64773.170925 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 65156.719432 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1000,92 +1019,92 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 57965 # number of writebacks -system.cpu.l2cache.writebacks::total 57965 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 57971 # number of writebacks +system.cpu.l2cache.writebacks::total 57971 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 5 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10599 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 9833 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 20439 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2885 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 2885 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133877 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 133877 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10600 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 9837 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 20444 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2872 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 2872 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133893 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 133893 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 5 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 10599 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 143710 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 154316 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 10600 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 143730 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 154337 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 5 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 10599 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 143710 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 154316 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 404750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.inst 10600 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 143730 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 154337 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 326500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 97500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 611089500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 576558000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1188149750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 28854885 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 28854885 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6940085381 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6940085381 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 404750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 612276250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 575969500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1188669750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 28722872 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 28722872 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6933953143 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6933953143 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 326500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 97500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 611089500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7516643381 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 8128235131 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 404750 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 612276250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7509922643 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 8122622893 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 326500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 97500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 611089500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7516643381 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 8128235131 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 339371500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166657063250 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166996434750 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 16701843725 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 16701843725 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 339371500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 183358906975 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 183698278475 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 612276250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7509922643 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 8122622893 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 339357750 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166657272750 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166996630500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 16702868810 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 16702868810 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 339357750 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 183360141560 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 183699499310 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000573 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000566 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000565 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012395 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025890 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016388 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991068 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991068 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541206 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541206 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025888 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016389 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991028 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991028 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541360 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541360 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000573 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000566 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000565 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012395 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229141 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.103252 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229119 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.103253 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000573 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000566 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000565 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012395 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229141 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.103252 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 80950 # average ReadReq mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229119 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.103253 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 65300 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 48750 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57655.392018 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58635.004576 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58131.501052 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001.693241 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.693241 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 51839.265751 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 51839.265751 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 80950 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57761.910377 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58551.336790 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58142.719135 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 51787.271500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 51787.271500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 65300 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 48750 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57655.392018 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52304.247311 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52672.666029 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 80950 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57761.910377 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52250.209720 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52629.135548 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 65300 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 48750 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57655.392018 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52304.247311 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52672.666029 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57761.910377 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52250.209720 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52629.135548 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1095,79 +1114,79 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 626656 # number of replacements -system.cpu.dcache.tagsinuse 511.879114 # Cycle average of tags in use -system.cpu.dcache.total_refs 23655617 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 627168 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 37.718150 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 650249000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.879114 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999764 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999764 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13195840 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13195840 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 9972724 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 9972724 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 236345 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 236345 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247797 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247797 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 23168564 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 23168564 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 23168564 # number of overall hits -system.cpu.dcache.overall_hits::total 23168564 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 368347 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 368347 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 250279 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 250279 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 11453 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 11453 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 618626 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 618626 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 618626 # number of overall misses -system.cpu.dcache.overall_misses::total 618626 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5378545500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5378545500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10531910500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10531910500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 158860000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 158860000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 15910456000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 15910456000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 15910456000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 15910456000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13564187 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13564187 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10223003 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10223003 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247798 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 247798 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 247797 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 247797 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 23787190 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 23787190 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 23787190 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 23787190 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027156 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.027156 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024482 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.024482 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046219 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046219 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.026007 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.026007 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.026007 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.026007 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14601.844185 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14601.844185 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42080.679961 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 42080.679961 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13870.601589 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13870.601589 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 25719.022479 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 25719.022479 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 25719.022479 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 25719.022479 # average overall miss latency +system.cpu.dcache.tags.replacements 626803 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.877792 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 23655579 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 627315 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37.709251 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 657281250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.877792 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999761 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999761 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 13195771 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13195771 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 9972807 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 9972807 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 236302 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 236302 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247801 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247801 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 23168578 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 23168578 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 23168578 # number of overall hits +system.cpu.dcache.overall_hits::total 23168578 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 368488 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 368488 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 250225 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 250225 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 11500 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 11500 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 618713 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 618713 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 618713 # number of overall misses +system.cpu.dcache.overall_misses::total 618713 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5386574000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5386574000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10624198015 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10624198015 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 159892750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 159892750 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 16010772015 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16010772015 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 16010772015 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16010772015 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13564259 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13564259 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10223032 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10223032 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247802 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 247802 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247801 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247801 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 23787291 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 23787291 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 23787291 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 23787291 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027166 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.027166 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024477 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.024477 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046408 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046408 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.026010 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.026010 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.026010 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.026010 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14618.044550 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14618.044550 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42458.579339 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 42458.579339 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13903.717391 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13903.717391 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 25877.542601 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 25877.542601 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 25877.542601 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 25877.542601 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1176,54 +1195,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 595512 # number of writebacks -system.cpu.dcache.writebacks::total 595512 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368347 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 368347 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250279 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 250279 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11453 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 11453 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 618626 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 618626 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 618626 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 618626 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4641851500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4641851500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10031352500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10031352500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 135954000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 135954000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14673204000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 14673204000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14673204000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 14673204000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182050723500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182050723500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26234076500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26234076500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208284800000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 208284800000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027156 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027156 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024482 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024482 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046219 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046219 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026007 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.026007 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026007 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.026007 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12601.844185 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12601.844185 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40080.679961 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40080.679961 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11870.601589 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11870.601589 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23719.022479 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23719.022479 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23719.022479 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23719.022479 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 595786 # number of writebacks +system.cpu.dcache.writebacks::total 595786 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368488 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 368488 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250225 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 250225 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11500 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 11500 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 618713 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 618713 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 618713 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 618713 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4644879500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4644879500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10059088985 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10059088985 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 136816250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 136816250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14703968485 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 14703968485 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14703968485 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 14703968485 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182050953750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182050953750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26234980190 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26234980190 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208285933940 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 208285933940 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027166 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027166 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024477 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024477 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046408 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046408 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026010 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.026010 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026010 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.026010 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12605.239519 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12605.239519 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40200.175782 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40200.175782 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11897.065217 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11897.065217 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23765.410594 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23765.410594 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23765.410594 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23765.410594 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1231,44 +1250,44 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 53002965 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2454953 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2454953 # Transaction distribution +system.cpu.toL2Bus.throughput 53012095 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2455185 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2455185 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 763368 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 763368 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 595512 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2911 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2911 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 247368 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 247368 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1725126 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 5750616 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma 12461 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma 27468 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 7515671 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 54754292 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 83665829 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma 14140 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma 34916 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 138469177 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 138469177 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 166564 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3009252000 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::Writeback 595786 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2898 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2898 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 247327 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 247327 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1725213 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 5751160 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma 12463 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma 27463 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 7516299 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 54757044 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 83692777 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma 14148 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma 34900 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 138498869 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 138498869 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 166632 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3009752500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1291764000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1296058500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2507996500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2542947575 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 8926000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 8926500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 18739000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 18739250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.replacements 0 # number of replacements -system.iocache.tagsinuse 0 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.avg_refs nan # Average number of references to valid blocks. -system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.iocache.tags.replacements 0 # number of replacements +system.iocache.tags.tagsinuse 0 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs nan # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1277,10 +1296,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1470128900250 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1470128900250 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1470128900250 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1470128900250 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1466807214000 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1466807214000 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1466807214000 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1466807214000 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt index 35b3a08bb..b5f8111f8 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt @@ -223,27 +223,27 @@ system.realview.nvmem.bw_total::total 9 # To system.membus.throughput 55969561 # Throughput (bytes/s) system.membus.data_through_bus 130566366 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.l2c.replacements 62242 # number of replacements -system.l2c.tagsinuse 50006.300222 # Cycle average of tags in use -system.l2c.total_refs 1678485 # Total number of references to valid blocks. -system.l2c.sampled_refs 127627 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.151488 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2316901489000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 36900.571453 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 0.993823 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.993931 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4917.298419 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 3152.525311 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 2097.421525 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 2936.495759 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.563058 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.075032 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.048104 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.032004 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.044807 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.763036 # Average percentage of cache occupancy +system.l2c.tags.replacements 62242 # number of replacements +system.l2c.tags.tagsinuse 50006.300222 # Cycle average of tags in use +system.l2c.tags.total_refs 1678485 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 127627 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.151488 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2316901489000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 36900.571453 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.993823 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.993931 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4917.298419 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3152.525311 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2097.421525 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2936.495759 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.563058 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.075032 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.048104 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.032004 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.044807 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.763036 # Average percentage of cache occupancy system.l2c.ReadReq_hits::cpu0.dtb.walker 9005 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 3277 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.inst 473134 # number of ReadReq hits @@ -456,17 +456,17 @@ system.cpu0.not_idle_fraction 0.959732 # Pe system.cpu0.idle_fraction 0.040268 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 82795 # number of quiesce instructions executed -system.cpu0.icache.replacements 850590 # number of replacements -system.cpu0.icache.tagsinuse 511.678593 # Cycle average of tags in use -system.cpu0.icache.total_refs 60583498 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 851102 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 71.182418 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 5709383000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 444.510252 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 67.168341 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.868184 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.131188 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.999372 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 850590 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.678593 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 60583498 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 851102 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 71.182418 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 5709383000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 444.510252 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 67.168341 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.868184 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.131188 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999372 # Average percentage of cache occupancy system.cpu0.icache.ReadReq_hits::cpu0.inst 32064735 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::cpu1.inst 28518763 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 60583498 # number of ReadReq hits @@ -512,17 +512,17 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 623334 # number of replacements -system.cpu0.dcache.tagsinuse 511.997031 # Cycle average of tags in use -system.cpu0.dcache.total_refs 23628284 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 623846 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 37.875187 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 21763000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 451.298938 # Average occupied blocks per requestor -system.cpu0.dcache.occ_blocks::cpu1.data 60.698093 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.881443 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::cpu1.data 0.118551 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 623334 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.997031 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 23628284 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 623846 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 37.875187 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 21763000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 451.298938 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 60.698093 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.881443 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.118551 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu0.dcache.ReadReq_hits::cpu0.data 6995590 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::cpu1.data 6184430 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 13180020 # number of ReadReq hits @@ -666,12 +666,12 @@ system.cpu1.not_idle_fraction -0.942843 # Pe system.cpu1.idle_fraction 1.942843 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.iocache.replacements 0 # number of replacements -system.iocache.tagsinuse 0 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.avg_refs nan # Average number of references to valid blocks. -system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.iocache.tags.replacements 0 # number of replacements +system.iocache.tags.tagsinuse 0 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs nan # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index 3eb24dda0..56bd99bdd 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -1,51 +1,51 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.112100 # Number of seconds simulated -sim_ticks 5112099860500 # Number of ticks simulated -final_tick 5112099860500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.112102 # Number of seconds simulated +sim_ticks 5112102211000 # Number of ticks simulated +final_tick 5112102211000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 794426 # Simulator instruction rate (inst/s) -host_op_rate 1626557 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 20315509625 # Simulator tick rate (ticks/s) -host_mem_usage 586244 # Number of bytes of host memory used -host_seconds 251.64 # Real time elapsed on the host -sim_insts 199905607 # Number of instructions simulated -sim_ops 409299132 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2420928 # Number of bytes read from this memory +host_inst_rate 878832 # Simulator instruction rate (inst/s) +host_op_rate 1799374 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 22473674513 # Simulator tick rate (ticks/s) +host_mem_usage 586256 # Number of bytes of host memory used +host_seconds 227.47 # Real time elapsed on the host +sim_insts 199908396 # Number of instructions simulated +sim_ops 409304707 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2421056 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 852736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10605184 # Number of bytes read from this memory -system.physmem.bytes_read::total 13879296 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10605120 # Number of bytes read from this memory +system.physmem.bytes_read::total 13879360 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 852736 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 852736 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9264448 # Number of bytes written to this memory -system.physmem.bytes_written::total 9264448 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 37827 # Number of read requests responded to by this memory +system.physmem.bytes_written::writebacks 9264512 # Number of bytes written to this memory +system.physmem.bytes_written::total 9264512 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 37829 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 2 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 13324 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 165706 # Number of read requests responded to by this memory -system.physmem.num_reads::total 216864 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 144757 # Number of write requests responded to by this memory -system.physmem.num_writes::total 144757 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 473568 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu.data 165705 # Number of read requests responded to by this memory +system.physmem.num_reads::total 216865 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 144758 # Number of write requests responded to by this memory +system.physmem.num_writes::total 144758 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 473593 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 25 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 166807 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2074526 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2714989 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2074513 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2715000 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 166807 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 166807 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1812259 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1812259 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1812259 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 473568 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 1812270 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1812270 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1812270 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 473593 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 25 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 166807 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2074526 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4527248 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2074513 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4527271 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 0 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady @@ -192,34 +192,34 @@ system.physmem.writeRowHits 0 # Nu system.physmem.readRowHitRate nan # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap nan # Average gap between requests -system.membus.throughput 9632717 # Throughput (bytes/s) -system.membus.data_through_bus 49243411 # Total data (bytes) +system.membus.throughput 9632725 # Throughput (bytes/s) +system.membus.data_through_bus 49243475 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.iocache.replacements 47568 # number of replacements -system.iocache.tagsinuse 0.042441 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47584 # Sample count of references to valid blocks. -system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 4994822603059 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.042441 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.002653 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.002653 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 903 # number of ReadReq misses -system.iocache.ReadReq_misses::total 903 # number of ReadReq misses +system.iocache.tags.replacements 47569 # number of replacements +system.iocache.tags.tagsinuse 0.042449 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 47585 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 4994822663009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042449 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.002653 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.002653 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses +system.iocache.ReadReq_misses::total 904 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47623 # number of demand (read+write) misses -system.iocache.demand_misses::total 47623 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47623 # number of overall misses -system.iocache.overall_misses::total 47623 # number of overall misses -system.iocache.ReadReq_accesses::pc.south_bridge.ide 903 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 903 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47624 # number of demand (read+write) misses +system.iocache.demand_misses::total 47624 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47624 # number of overall misses +system.iocache.overall_misses::total 47624 # number of overall misses +system.iocache.ReadReq_accesses::pc.south_bridge.ide 904 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 904 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47623 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47623 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47623 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47623 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47624 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47624 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47624 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47624 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -241,7 +241,7 @@ system.iocache.writebacks::total 46667 # nu system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. @@ -252,58 +252,58 @@ system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. system.iobus.throughput 2555194 # Throughput (bytes/s) -system.iobus.data_through_bus 13062406 # Total data (bytes) -system.cpu.numCycles 10224199744 # number of cpu cycles simulated +system.iobus.data_through_bus 13062414 # Total data (bytes) +system.cpu.numCycles 10224204444 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 199905607 # Number of instructions committed -system.cpu.committedOps 409299132 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 374462047 # Number of integer alu accesses +system.cpu.committedInsts 199908396 # Number of instructions committed +system.cpu.committedOps 409304707 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 374467605 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 2307315 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 39972114 # number of instructions that are conditional controls -system.cpu.num_int_insts 374462047 # number of integer instructions +system.cpu.num_func_calls 2307395 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 39972475 # number of instructions that are conditional controls +system.cpu.num_int_insts 374467605 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 915890300 # number of times the integer registers were read -system.cpu.num_int_register_writes 480542889 # number of times the integer registers were written +system.cpu.num_int_register_reads 915905592 # number of times the integer registers were read +system.cpu.num_int_register_writes 480549431 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 35654170 # number of memory refs -system.cpu.num_load_insts 27234345 # Number of load instructions -system.cpu.num_store_insts 8419825 # Number of store instructions -system.cpu.num_idle_cycles 9770518400.401503 # Number of idle cycles -system.cpu.num_busy_cycles 453681343.598497 # Number of busy cycles -system.cpu.not_idle_fraction 0.044373 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.955627 # Percentage of idle cycles +system.cpu.num_mem_refs 35655576 # number of memory refs +system.cpu.num_load_insts 27235236 # Number of load instructions +system.cpu.num_store_insts 8420340 # Number of store instructions +system.cpu.num_idle_cycles 9770516372.735863 # Number of idle cycles +system.cpu.num_busy_cycles 453688071.264138 # Number of busy cycles +system.cpu.not_idle_fraction 0.044374 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.955626 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.icache.replacements 790584 # number of replacements -system.cpu.icache.tagsinuse 510.666660 # Cycle average of tags in use -system.cpu.icache.total_refs 243492014 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 791096 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 307.790728 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 148824778500 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.666660 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.997396 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.997396 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 243492014 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 243492014 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 243492014 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 243492014 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 243492014 # number of overall hits -system.cpu.icache.overall_hits::total 243492014 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 791103 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 791103 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 791103 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 791103 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 791103 # number of overall misses -system.cpu.icache.overall_misses::total 791103 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 244283117 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 244283117 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 244283117 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 244283117 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 244283117 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 244283117 # number of overall (read+write) accesses +system.cpu.icache.tags.replacements 790522 # number of replacements +system.cpu.icache.tags.tagsinuse 510.666660 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 243495984 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 791034 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 307.819871 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 148824778500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.666660 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997396 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997396 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 243495984 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 243495984 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 243495984 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 243495984 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 243495984 # number of overall hits +system.cpu.icache.overall_hits::total 243495984 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 791041 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 791041 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 791041 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 791041 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 791041 # number of overall misses +system.cpu.icache.overall_misses::total 791041 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 244287025 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 244287025 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 244287025 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 244287025 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 244287025 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 244287025 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003238 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.003238 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.003238 # miss rate for demand accesses @@ -319,15 +319,15 @@ system.cpu.icache.avg_blocked_cycles::no_targets nan system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 3477 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 3.026333 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 7886 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 3489 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 2.260246 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5102064745500 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.026333 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.189146 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.189146 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.replacements 3477 # number of replacements +system.cpu.itb_walker_cache.tags.tagsinuse 3.026296 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.total_refs 7886 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.tags.sampled_refs 3489 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.tags.avg_refs 2.260246 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.tags.warmup_cycle 5102094222000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026296 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.189143 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_percent::total 0.189143 # Average percentage of cache occupancy system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7887 # number of ReadReq hits system.cpu.itb_walker_cache.ReadReq_hits::total 7887 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits @@ -367,39 +367,39 @@ system.cpu.itb_walker_cache.cache_copies 0 # nu system.cpu.itb_walker_cache.writebacks::writebacks 526 # number of writebacks system.cpu.itb_walker_cache.writebacks::total 526 # number of writebacks system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 7629 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 5.014191 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 12947 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 7641 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.694412 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5100425401500 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.014191 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.313387 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.313387 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12955 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 12955 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12955 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 12955 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12955 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 12955 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8819 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 8819 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8819 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 8819 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8819 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 8819 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21774 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 21774 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21774 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 21774 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21774 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 21774 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.405024 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.405024 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.405024 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.405024 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.405024 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.405024 # miss rate for overall accesses +system.cpu.dtb_walker_cache.tags.replacements 7632 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 5.014181 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 12948 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 7644 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.693878 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 5100438909500 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.014181 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313386 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.313386 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12956 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 12956 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12956 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 12956 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12956 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 12956 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8822 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 8822 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8822 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 8822 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8822 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 8822 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21778 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 21778 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21778 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 21778 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21778 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 21778 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.405088 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.405088 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.405088 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.405088 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.405088 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.405088 # miss rate for overall accesses system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -411,47 +411,47 @@ system.cpu.dtb_walker_cache.cache_copies 0 # nu system.cpu.dtb_walker_cache.writebacks::writebacks 2413 # number of writebacks system.cpu.dtb_walker_cache.writebacks::total 2413 # number of writebacks system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1621960 # number of replacements -system.cpu.dcache.tagsinuse 511.999425 # Cycle average of tags in use -system.cpu.dcache.total_refs 20168705 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1622472 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.430849 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.999425 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999999 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 12073185 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 12073185 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8093252 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8093252 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 20166437 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20166437 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20166437 # number of overall hits -system.cpu.dcache.overall_hits::total 20166437 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1308369 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1308369 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 316387 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 316387 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1624756 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1624756 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1624756 # number of overall misses -system.cpu.dcache.overall_misses::total 1624756 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 13381554 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13381554 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8409639 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8409639 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21791193 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21791193 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21791193 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21791193 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097774 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.097774 # miss rate for ReadReq accesses +system.cpu.dcache.tags.replacements 1622027 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.999424 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 20170040 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1622539 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.431159 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.999424 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 12074025 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 12074025 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8093747 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8093747 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 20167772 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20167772 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20167772 # number of overall hits +system.cpu.dcache.overall_hits::total 20167772 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1308420 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1308420 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 316403 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 316403 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1624823 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1624823 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1624823 # number of overall misses +system.cpu.dcache.overall_misses::total 1624823 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 13382445 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13382445 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8410150 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8410150 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21792595 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21792595 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21792595 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21792595 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097771 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.097771 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037622 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.037622 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.074560 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.074560 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.074560 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.074560 # miss rate for overall accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.074558 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.074558 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.074558 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.074558 # miss rate for overall accesses system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -460,50 +460,50 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1535700 # number of writebacks -system.cpu.dcache.writebacks::total 1535700 # number of writebacks +system.cpu.dcache.writebacks::writebacks 1535756 # number of writebacks +system.cpu.dcache.writebacks::total 1535756 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 54622198 # Throughput (bytes/s) -system.cpu.toL2Bus.data_through_bus 279208723 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 25408 # Total snoop data (bytes) -system.cpu.l2cache.replacements 105930 # number of replacements -system.cpu.l2cache.tagsinuse 64819.953901 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3456506 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 170058 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 20.325454 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 51906.788145 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.dtb.walker 0.004959 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.132241 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2490.593013 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 10422.435543 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.792035 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.038003 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.159034 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.989074 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6501 # number of ReadReq hits +system.cpu.toL2Bus.throughput 54622987 # Throughput (bytes/s) +system.cpu.toL2Bus.data_through_bus 279212819 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 25472 # Total snoop data (bytes) +system.cpu.l2cache.tags.replacements 105931 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64819.947299 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3456551 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 170059 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 20.325599 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 51906.795355 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.004959 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.132237 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2490.582004 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 10422.432745 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.792035 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.038003 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.159034 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.989074 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6502 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2802 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 777765 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1275491 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2062559 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1538639 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1538639 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 777703 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1275544 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2062551 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1538695 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1538695 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 20 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 20 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 179721 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 179721 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 6501 # number of demand (read+write) hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 179738 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 179738 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 6502 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.itb.walker 2802 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 777765 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1455212 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2242280 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 6501 # number of overall hits +system.cpu.l2cache.demand_hits::cpu.inst 777703 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1455282 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2242289 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 6502 # number of overall hits system.cpu.l2cache.overall_hits::cpu.itb.walker 2802 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 777765 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1455212 # number of overall hits -system.cpu.l2cache.overall_hits::total 2242280 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 777703 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1455282 # number of overall hits +system.cpu.l2cache.overall_hits::total 2242289 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 2 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.inst 13325 # number of ReadReq misses @@ -511,58 +511,58 @@ system.cpu.l2cache.ReadReq_misses::cpu.data 32246 # system.cpu.l2cache.ReadReq_misses::total 45578 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 1803 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 1803 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 134393 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 134393 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 134392 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 134392 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 2 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.inst 13325 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 166639 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 179971 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 166638 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 179970 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 2 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses system.cpu.l2cache.overall_misses::cpu.inst 13325 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 166639 # number of overall misses -system.cpu.l2cache.overall_misses::total 179971 # number of overall misses -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6503 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::cpu.data 166638 # number of overall misses +system.cpu.l2cache.overall_misses::total 179970 # number of overall misses +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6504 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2807 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 791090 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1307737 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2108137 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1538639 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1538639 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 791028 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1307790 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2108129 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1538695 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1538695 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1823 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 1823 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 314114 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 314114 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6503 # number of demand (read+write) accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 314130 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 314130 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6504 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.itb.walker 2807 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 791090 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1621851 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2422251 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6503 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 791028 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1621920 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2422259 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6504 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.itb.walker 2807 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 791090 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1621851 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2422251 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 791028 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1621920 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2422259 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000308 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001781 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016844 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024658 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016845 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024657 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.021620 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989029 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989029 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.427848 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.427848 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.427823 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.427823 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000308 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001781 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016844 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.102746 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.074299 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016845 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.102741 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.074298 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000308 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001781 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016844 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.102746 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.074299 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016845 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.102741 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.074298 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -571,8 +571,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 98090 # number of writebacks -system.cpu.l2cache.writebacks::total 98090 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 98091 # number of writebacks +system.cpu.l2cache.writebacks::total 98091 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index 3847513ea..bb1dca70a 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -1,130 +1,130 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.196145 # Number of seconds simulated -sim_ticks 5196144770000 # Number of ticks simulated -final_tick 5196144770000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.196173 # Number of seconds simulated +sim_ticks 5196173457000 # Number of ticks simulated +final_tick 5196173457000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 471788 # Simulator instruction rate (inst/s) -host_op_rate 909467 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 19106715414 # Simulator tick rate (ticks/s) -host_mem_usage 586268 # Number of bytes of host memory used -host_seconds 271.95 # Real time elapsed on the host -sim_insts 128304418 # Number of instructions simulated -sim_ops 247333117 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2891776 # Number of bytes read from this memory +host_inst_rate 766970 # Simulator instruction rate (inst/s) +host_op_rate 1478526 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 31067837744 # Simulator tick rate (ticks/s) +host_mem_usage 586132 # Number of bytes of host memory used +host_seconds 167.25 # Real time elapsed on the host +sim_insts 128277551 # Number of instructions simulated +sim_ops 247287193 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2879808 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 823744 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8961408 # Number of bytes read from this memory -system.physmem.bytes_read::total 12677312 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 823744 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 823744 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8105792 # Number of bytes written to this memory -system.physmem.bytes_written::total 8105792 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 45184 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu.inst 826368 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8990464 # Number of bytes read from this memory +system.physmem.bytes_read::total 12697024 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 826368 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 826368 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8117888 # Number of bytes written to this memory +system.physmem.bytes_written::total 8117888 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 44997 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12871 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 140022 # Number of read requests responded to by this memory -system.physmem.num_reads::total 198083 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 126653 # Number of write requests responded to by this memory -system.physmem.num_writes::total 126653 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 556523 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu.inst 12912 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 140476 # Number of read requests responded to by this memory +system.physmem.num_reads::total 198391 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 126842 # Number of write requests responded to by this memory +system.physmem.num_writes::total 126842 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 554217 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 12 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 158530 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1724626 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2439753 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 158530 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 158530 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1559963 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1559963 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1559963 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 556523 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 159034 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1730209 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2443534 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 159034 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 159034 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1562282 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1562282 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1562282 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 554217 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 12 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 158530 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1724626 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3999716 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 198083 # Total number of read requests seen -system.physmem.writeReqs 126653 # Total number of write requests seen -system.physmem.cpureqs 326336 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 12677312 # Total number of bytes read from memory -system.physmem.bytesWritten 8105792 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 12677312 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 8105792 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 70 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 1597 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 12388 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 12465 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 13064 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 12742 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 12822 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 12061 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 12170 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 12418 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 11780 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 11808 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 12169 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 12505 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 12558 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 12789 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 12227 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 12047 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7920 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 8110 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 8533 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 8387 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 8388 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7744 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7664 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7959 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7196 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7383 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7714 # Track writes on a per bank basis +system.physmem.bw_total::cpu.inst 159034 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1730209 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4005815 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 198391 # Total number of read requests seen +system.physmem.writeReqs 126842 # Total number of write requests seen +system.physmem.cpureqs 326873 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 12697024 # Total number of bytes read from memory +system.physmem.bytesWritten 8117888 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 12697024 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 8117888 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 80 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 1638 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 12755 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 12192 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 12372 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 12296 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 12564 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 12318 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 12219 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 12027 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 12046 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 12112 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 12490 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 12561 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 12978 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 12970 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 12385 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 12026 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 8334 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7768 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7804 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7872 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 8132 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7928 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7689 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7630 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7475 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7683 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 8127 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 7959 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 8157 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 8159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7876 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7504 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 8470 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 8471 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7991 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7509 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 3 # Number of times wr buffer was full causing retry -system.physmem.totGap 5196144706500 # Total gap between requests +system.physmem.numWrRetry 2 # Number of times wr buffer was full causing retry +system.physmem.totGap 5196173392500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 198083 # Categorize read packet sizes +system.physmem.readPktSize::6 198391 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 126653 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 154572 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 13375 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 7517 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3048 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2915 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2517 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1489 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1349 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1265 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1181 # What read queue length does an incoming req see +system.physmem.writePktSize::6 126842 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 155016 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 13333 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 7466 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2991 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2873 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2490 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1473 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1327 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1269 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1177 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 1109 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 1086 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1032 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1095 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1162 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1135 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 924 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 646 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 350 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 220 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1030 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1124 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1206 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1161 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 914 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 651 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 362 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 223 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 30 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -136,200 +136,201 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4307 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4302 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 4658 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 5438 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5493 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5496 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5500 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5502 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5502 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5506 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5506 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5506 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5506 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5506 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5506 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5506 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5506 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 849 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 45242 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 458.910923 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 168.789921 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1568.289191 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 18577 41.06% 41.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 7110 15.72% 56.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 4218 9.32% 66.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 2889 6.39% 72.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 2001 4.42% 76.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 1601 3.54% 80.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 1275 2.82% 83.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 961 2.12% 85.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 799 1.77% 87.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 633 1.40% 88.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 499 1.10% 89.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 460 1.02% 90.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 337 0.74% 91.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 345 0.76% 92.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 215 0.48% 92.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 394 0.87% 93.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 170 0.38% 93.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 159 0.35% 94.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 128 0.28% 94.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 109 0.24% 94.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 88 0.19% 94.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 127 0.28% 95.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 644 1.42% 96.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 160 0.35% 97.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 109 0.24% 97.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 90 0.20% 97.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 61 0.13% 97.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 44 0.10% 97.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 17 0.04% 97.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 21 0.05% 97.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 12 0.03% 97.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 37 0.08% 97.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 16 0.04% 97.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 11 0.02% 97.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 14 0.03% 97.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 9 0.02% 98.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 7 0.02% 98.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 9 0.02% 98.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 6 0.01% 98.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 11 0.02% 98.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 4 0.01% 98.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 2 0.00% 98.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 7 0.02% 98.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 3 0.01% 98.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 3 0.01% 98.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 4 0.01% 98.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 2 0.00% 98.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 5 0.01% 98.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 3 0.01% 98.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 2 0.00% 98.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 2 0.00% 98.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 3 0.01% 98.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 3 0.01% 98.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 10 0.02% 98.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 1 0.00% 98.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 1 0.00% 98.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 4 0.01% 98.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3715 5 0.01% 98.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 11 0.02% 98.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 2 0.00% 98.25% # Bytes accessed per row activation +system.physmem.wrQLenPdf::2 5452 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5504 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5510 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5511 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5512 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5513 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5515 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5515 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5515 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5515 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5515 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5515 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5515 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5515 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5515 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5515 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5515 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5514 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5514 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5514 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 857 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 2 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 45212 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 459.873662 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 169.351443 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1570.406469 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 18373 40.64% 40.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 7212 15.95% 56.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 4299 9.51% 66.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 2899 6.41% 72.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 2036 4.50% 77.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 1645 3.64% 80.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 1210 2.68% 83.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 976 2.16% 85.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 783 1.73% 87.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 608 1.34% 88.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 508 1.12% 89.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 473 1.05% 90.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 299 0.66% 91.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 322 0.71% 92.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 227 0.50% 92.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 394 0.87% 93.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 154 0.34% 93.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 143 0.32% 94.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 136 0.30% 94.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 125 0.28% 94.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 123 0.27% 94.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 132 0.29% 95.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 601 1.33% 96.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 193 0.43% 97.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 92 0.20% 97.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 79 0.17% 97.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 66 0.15% 97.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 49 0.11% 97.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 20 0.04% 97.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 25 0.06% 97.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 17 0.04% 97.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 28 0.06% 97.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 17 0.04% 97.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 13 0.03% 97.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 13 0.03% 97.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 10 0.02% 97.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 13 0.03% 98.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 7 0.02% 98.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 10 0.02% 98.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 19 0.04% 98.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 4 0.01% 98.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 2 0.00% 98.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2755 5 0.01% 98.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 2 0.00% 98.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 2 0.00% 98.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 3 0.01% 98.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 6 0.01% 98.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 4 0.01% 98.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 5 0.01% 98.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3203 3 0.01% 98.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3331 2 0.00% 98.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3395 2 0.00% 98.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 8 0.02% 98.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3651 1 0.00% 98.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3715 2 0.00% 98.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3779 15 0.03% 98.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3907 3 0.01% 98.24% # Bytes accessed per row activation system.physmem.bytesPerActivate::3968-3971 1 0.00% 98.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 3 0.01% 98.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 14 0.03% 98.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4163 6 0.01% 98.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 2 0.00% 98.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4291 2 0.00% 98.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 4 0.01% 98.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 2 0.00% 98.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4035 2 0.00% 98.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4099 13 0.03% 98.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4163 6 0.01% 98.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4227 3 0.01% 98.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4291 2 0.00% 98.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4355 4 0.01% 98.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4419 3 0.01% 98.32% # Bytes accessed per row activation system.physmem.bytesPerActivate::4480-4483 3 0.01% 98.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4547 2 0.00% 98.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4611 2 0.00% 98.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4547 3 0.01% 98.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4611 1 0.00% 98.33% # Bytes accessed per row activation system.physmem.bytesPerActivate::4672-4675 1 0.00% 98.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4803 2 0.00% 98.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 1 0.00% 98.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4995 2 0.00% 98.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4803 2 0.00% 98.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4931 2 0.00% 98.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4995 1 0.00% 98.35% # Bytes accessed per row activation system.physmem.bytesPerActivate::5056-5059 4 0.01% 98.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5123 2 0.00% 98.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5187 2 0.00% 98.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5251 1 0.00% 98.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5315 1 0.00% 98.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5123 3 0.01% 98.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5187 1 0.00% 98.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5251 3 0.01% 98.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5315 1 0.00% 98.37% # Bytes accessed per row activation system.physmem.bytesPerActivate::5376-5379 1 0.00% 98.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5443 2 0.00% 98.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5507 2 0.00% 98.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5635 1 0.00% 98.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5443 1 0.00% 98.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5507 3 0.01% 98.39% # Bytes accessed per row activation system.physmem.bytesPerActivate::5696-5699 1 0.00% 98.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5763 2 0.00% 98.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5827 1 0.00% 98.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5763 2 0.00% 98.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5827 1 0.00% 98.39% # Bytes accessed per row activation system.physmem.bytesPerActivate::5888-5891 1 0.00% 98.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6019 1 0.00% 98.40% # Bytes accessed per row activation system.physmem.bytesPerActivate::6080-6083 2 0.00% 98.40% # Bytes accessed per row activation system.physmem.bytesPerActivate::6144-6147 1 0.00% 98.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6339 1 0.00% 98.41% # Bytes accessed per row activation system.physmem.bytesPerActivate::6400-6403 1 0.00% 98.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6595 2 0.00% 98.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6659 1 0.00% 98.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6723 4 0.01% 98.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6851 12 0.03% 98.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6531 1 0.00% 98.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6595 2 0.00% 98.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6723 5 0.01% 98.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6787 1 0.00% 98.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6851 8 0.02% 98.45% # Bytes accessed per row activation system.physmem.bytesPerActivate::6912-6915 2 0.00% 98.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6979 1 0.00% 98.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7043 2 0.00% 98.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7107 1 0.00% 98.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 7 0.02% 98.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7235 2 0.00% 98.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7427 2 0.00% 98.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7555 2 0.00% 98.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7619 1 0.00% 98.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7683 1 0.00% 98.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7939 1 0.00% 98.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8067 2 0.00% 98.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8131 1 0.00% 98.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 340 0.75% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8451 1 0.00% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8579 2 0.00% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8640-8643 1 0.00% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8768-8771 1 0.00% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8832-8835 1 0.00% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8963 1 0.00% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9219 7 0.02% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9280-9283 1 0.00% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9536-9539 1 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9600-9603 1 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9664-9667 1 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12224-12227 1 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12352-12355 1 0.00% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12608-12611 1 0.00% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12803 1 0.00% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13059 1 0.00% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13632-13635 1 0.00% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14083 1 0.00% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14144-14147 1 0.00% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14211 2 0.00% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14912-14915 8 0.02% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7043 4 0.01% 98.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7171 4 0.01% 98.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7427 2 0.00% 98.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7555 2 0.00% 98.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7619 1 0.00% 98.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7683 1 0.00% 98.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7939 1 0.00% 98.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8067 2 0.00% 98.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8131 1 0.00% 98.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8195 342 0.76% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8320-8323 2 0.00% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8384-8387 3 0.01% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8451 2 0.00% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8512-8515 2 0.00% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8896-8899 1 0.00% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9219 5 0.01% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9280-9283 1 0.00% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9408-9411 2 0.00% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9475 1 0.00% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9664-9667 1 0.00% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9731 1 0.00% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9792-9795 1 0.00% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10112-10115 1 0.00% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11779 1 0.00% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13120-13123 1 0.00% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13504-13507 1 0.00% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13696-13699 1 0.00% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13888-13891 2 0.00% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13952-13955 1 0.00% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14400-14403 1 0.00% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14464-14467 1 0.00% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14595 2 0.00% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14720-14723 1 0.00% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14915 6 0.01% 99.35% # Bytes accessed per row activation system.physmem.bytesPerActivate::14976-14979 1 0.00% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15107 1 0.00% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 10 0.02% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15488-15491 1 0.00% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15808-15811 1 0.00% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16320-16323 1 0.00% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 237 0.52% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16448-16451 13 0.03% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16512-16515 17 0.04% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16576-16579 3 0.01% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16643 5 0.01% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16704-16707 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16960-16963 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17280-17283 2 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17600-17603 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17856-17859 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 45242 # Bytes accessed per row activation -system.physmem.totQLat 3435518998 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 7067756498 # Sum of mem lat for all requests -system.physmem.totBusLat 990065000 # Total cycles spent in databus access -system.physmem.totBankLat 2642172500 # Total cycles spent in bank access -system.physmem.avgQLat 17349.97 # Average queueing delay per request -system.physmem.avgBankLat 13343.43 # Average bank access latency per request +system.physmem.bytesPerActivate::15040-15043 2 0.00% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15107 2 0.00% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15296-15299 1 0.00% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 5 0.01% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16064-16067 1 0.00% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 241 0.53% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16448-16451 16 0.04% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16512-16515 8 0.02% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16576-16579 3 0.01% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16643 6 0.01% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16704-16707 4 0.01% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16768-16771 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16832-16835 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17024-17027 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17411 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17472-17475 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17667 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 45212 # Bytes accessed per row activation +system.physmem.totQLat 3446222750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 7081229000 # Sum of mem lat for all requests +system.physmem.totBusLat 991555000 # Total cycles spent in databus access +system.physmem.totBankLat 2643451250 # Total cycles spent in bank access +system.physmem.avgQLat 17377.87 # Average queueing delay per request +system.physmem.avgBankLat 13329.83 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 35693.40 # Average memory access latency +system.physmem.avgMemAccLat 35707.70 # Average memory access latency system.physmem.avgRdBW 2.44 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 2.44 # Average consumed read bandwidth in MB/s @@ -337,99 +338,99 @@ system.physmem.avgConsumedWrBW 1.56 # Av system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 9.35 # Average write queue length over time -system.physmem.readRowHits 181015 # Number of row buffer hits during reads -system.physmem.writeRowHits 98394 # Number of row buffer hits during writes -system.physmem.readRowHitRate 91.42 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 77.69 # Row buffer hit rate for writes -system.physmem.avgGap 16001135.40 # Average gap between requests -system.membus.throughput 4358895 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 623371 # Transaction distribution -system.membus.trans_dist::ReadResp 623371 # Transaction distribution -system.membus.trans_dist::WriteReq 13727 # Transaction distribution -system.membus.trans_dist::WriteResp 13727 # Transaction distribution -system.membus.trans_dist::Writeback 126653 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2147 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1615 # Transaction distribution -system.membus.trans_dist::ReadExReq 159120 # Transaction distribution -system.membus.trans_dist::ReadExResp 159120 # Transaction distribution -system.membus.trans_dist::MessageReq 1656 # Transaction distribution -system.membus.trans_dist::MessageResp 1656 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3312 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3312 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 390174 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 480118 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710116 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1580408 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 139407 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 139407 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 529581 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.bridge.slave 480118 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.cpu.interrupts.pio 710116 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.cpu.interrupts.int_slave 3312 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1723127 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6624 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::total 6624 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 14904512 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 246342 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420229 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 16571083 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5878592 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 5878592 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 20783104 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.bridge.slave 246342 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.cpu.interrupts.pio 1420229 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.cpu.interrupts.int_slave 6624 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 22456299 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 22456299 # Total data (bytes) -system.membus.snoop_data_through_bus 193152 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1348670998 # Layer occupancy (ticks) +system.physmem.avgWrQLen 12.20 # Average write queue length over time +system.physmem.readRowHits 181450 # Number of row buffer hits during reads +system.physmem.writeRowHits 98471 # Number of row buffer hits during writes +system.physmem.readRowHitRate 91.50 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 77.63 # Row buffer hit rate for writes +system.physmem.avgGap 15976771.71 # Average gap between requests +system.membus.throughput 4367376 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 623405 # Transaction distribution +system.membus.trans_dist::ReadResp 623405 # Transaction distribution +system.membus.trans_dist::WriteReq 13711 # Transaction distribution +system.membus.trans_dist::WriteResp 13711 # Transaction distribution +system.membus.trans_dist::Writeback 126842 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2139 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1656 # Transaction distribution +system.membus.trans_dist::ReadExReq 159580 # Transaction distribution +system.membus.trans_dist::ReadExResp 159580 # Transaction distribution +system.membus.trans_dist::MessageReq 1655 # Transaction distribution +system.membus.trans_dist::MessageResp 1655 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3310 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3310 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 391390 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 480072 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710114 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1581576 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 139223 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 139223 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 530613 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.bridge.slave 480072 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.cpu.interrupts.pio 710114 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.cpu.interrupts.int_slave 3310 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1724109 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6620 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::total 6620 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 14948416 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 246316 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420225 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 16614957 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5866496 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 5866496 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 20814912 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.bridge.slave 246316 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.cpu.interrupts.pio 1420225 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.cpu.interrupts.int_slave 6620 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 22488073 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 22488073 # Total data (bytes) +system.membus.snoop_data_through_bus 205568 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 1351024000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 256617500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 256571500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 359320000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 359320500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 3312000 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 3310000 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1656000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1655000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 2607874799 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 2612485256 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer4.occupancy 428809000 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 428859500 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.replacements 47501 # number of replacements -system.iocache.tagsinuse 0.169264 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47517 # Sample count of references to valid blocks. -system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 5049524013000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.169264 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.010579 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.010579 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 834 # number of ReadReq misses -system.iocache.ReadReq_misses::total 834 # number of ReadReq misses +system.iocache.tags.replacements 47504 # number of replacements +system.iocache.tags.tagsinuse 0.125284 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 47520 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 5049571138000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.125284 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007830 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.007830 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 839 # number of ReadReq misses +system.iocache.ReadReq_misses::total 839 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47554 # number of demand (read+write) misses -system.iocache.demand_misses::total 47554 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47554 # number of overall misses -system.iocache.overall_misses::total 47554 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 142703185 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 142703185 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10862337325 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10862337325 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 11005040510 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 11005040510 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 11005040510 # number of overall miss cycles -system.iocache.overall_miss_latency::total 11005040510 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 834 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 834 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47559 # number of demand (read+write) misses +system.iocache.demand_misses::total 47559 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47559 # number of overall misses +system.iocache.overall_misses::total 47559 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 142400936 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 142400936 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10875044083 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10875044083 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 11017445019 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 11017445019 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 11017445019 # number of overall miss cycles +system.iocache.overall_miss_latency::total 11017445019 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 839 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 839 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47554 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47554 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47554 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47554 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47559 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47559 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47559 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47559 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -438,40 +439,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 171106.936451 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 171106.936451 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 232498.658497 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 232498.658497 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 231421.973125 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 231421.973125 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 231421.973125 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 231421.973125 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 174194 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 169726.979738 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 169726.979738 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 232770.635338 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 232770.635338 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 231658.466726 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 231658.466726 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 231658.466726 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 231658.466726 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 178608 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 16040 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 16401 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.859975 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.890068 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 46669 # number of writebacks -system.iocache.writebacks::total 46669 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 834 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 834 # number of ReadReq MSHR misses +system.iocache.writebacks::writebacks 46667 # number of writebacks +system.iocache.writebacks::total 46667 # number of writebacks +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 839 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 839 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47554 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47554 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47554 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47554 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 99319185 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 99319185 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8432090325 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8432090325 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8531409510 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8531409510 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8531409510 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8531409510 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47559 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47559 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47559 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47559 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 98742936 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 98742936 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8443977083 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8443977083 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8542720019 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8542720019 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8542720019 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8542720019 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -480,14 +481,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 119087.751799 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 119087.751799 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 180481.385381 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 180481.385381 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 179404.666484 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 179404.666484 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 179404.666484 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 179404.666484 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 117691.222884 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 117691.222884 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 180735.810852 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 180735.810852 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 179623.625791 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 179623.625791 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 179623.625791 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 179623.625791 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -501,16 +502,16 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.throughput 631272 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 230083 # Transaction distribution -system.iobus.trans_dist::ReadResp 230083 # Transaction distribution -system.iobus.trans_dist::WriteReq 57530 # Transaction distribution -system.iobus.trans_dist::WriteResp 57530 # Transaction distribution -system.iobus.trans_dist::MessageReq 1656 # Transaction distribution -system.iobus.trans_dist::MessageResp 1656 # Transaction distribution +system.iobus.throughput 631271 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 230080 # Transaction distribution +system.iobus.trans_dist::ReadResp 230080 # Transaction distribution +system.iobus.trans_dist::WriteReq 57515 # Transaction distribution +system.iobus.trans_dist::WriteResp 57515 # Transaction distribution +system.iobus.trans_dist::MessageReq 1655 # Transaction distribution +system.iobus.trans_dist::MessageResp 1655 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) @@ -526,15 +527,15 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 480118 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95108 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95108 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3312 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3312 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.apicbridge.slave 3312 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 480072 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95118 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95118 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3310 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3310 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.apicbridge.slave 3310 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) @@ -549,12 +550,12 @@ system.iobus.pkt_count::system.pc.fake_com_2.pio 12 system.iobus.pkt_count::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.iocache.cpu_side 95108 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.iocache.cpu_side 95118 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 578538 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 578500 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) @@ -570,15 +571,15 @@ system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 246342 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027216 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027216 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6624 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6624 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.apicbridge.slave 6624 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 246316 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6620 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6620 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.apicbridge.slave 6620 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) @@ -593,17 +594,17 @@ system.iobus.tot_pkt_size::system.pc.fake_com_2.pio 6 system.iobus.tot_pkt_size::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.iocache.cpu_side 3027216 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.iocache.cpu_side 3027256 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 3280182 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 3280182 # Total data (bytes) -system.iobus.reqLayer0.occupancy 3949664 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::total 3280192 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 3280192 # Total data (bytes) +system.iobus.reqLayer0.occupancy 3949164 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 8851000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 8813000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -633,85 +634,85 @@ system.iobus.reqLayer16.occupancy 9000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 424330510 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 424368519 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 469308000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 469277000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 52196000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 53493500 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1656000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1655000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.numCycles 10392289540 # number of cpu cycles simulated +system.cpu.numCycles 10392346914 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 128304418 # Number of instructions committed -system.cpu.committedOps 247333117 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 232067207 # Number of integer alu accesses +system.cpu.committedInsts 128277551 # Number of instructions committed +system.cpu.committedOps 247287193 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 232021751 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 2300061 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 23160261 # number of instructions that are conditional controls -system.cpu.num_int_insts 232067207 # number of integer instructions +system.cpu.num_func_calls 2299501 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 23156792 # number of instructions that are conditional controls +system.cpu.num_int_insts 232021751 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 567198543 # number of times the integer registers were read -system.cpu.num_int_register_writes 293301890 # number of times the integer registers were written +system.cpu.num_int_register_reads 567075946 # number of times the integer registers were read +system.cpu.num_int_register_writes 293251743 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 22245318 # number of memory refs -system.cpu.num_load_insts 13878816 # Number of load instructions -system.cpu.num_store_insts 8366502 # Number of store instructions -system.cpu.num_idle_cycles 9785692797.998116 # Number of idle cycles -system.cpu.num_busy_cycles 606596742.001883 # Number of busy cycles -system.cpu.not_idle_fraction 0.058370 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.941630 # Percentage of idle cycles +system.cpu.num_mem_refs 22231243 # number of memory refs +system.cpu.num_load_insts 13871494 # Number of load instructions +system.cpu.num_store_insts 8359749 # Number of store instructions +system.cpu.num_idle_cycles 9785544869.998116 # Number of idle cycles +system.cpu.num_busy_cycles 606802044.001883 # Number of busy cycles +system.cpu.not_idle_fraction 0.058389 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.941611 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.icache.replacements 791404 # number of replacements -system.cpu.icache.tagsinuse 510.366672 # Cycle average of tags in use -system.cpu.icache.total_refs 144533937 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 791916 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 182.511702 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 161113577000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.366672 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996810 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996810 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 144533937 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 144533937 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 144533937 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 144533937 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 144533937 # number of overall hits -system.cpu.icache.overall_hits::total 144533937 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 791923 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 791923 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 791923 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 791923 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 791923 # number of overall misses -system.cpu.icache.overall_misses::total 791923 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11177158500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11177158500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11177158500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11177158500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11177158500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11177158500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 145325860 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 145325860 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 145325860 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 145325860 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 145325860 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 145325860 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005449 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.005449 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.005449 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.005449 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.005449 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.005449 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14113.946053 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14113.946053 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14113.946053 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14113.946053 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14113.946053 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14113.946053 # average overall miss latency +system.cpu.icache.tags.replacements 791620 # number of replacements +system.cpu.icache.tags.tagsinuse 510.364411 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 144498695 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 792132 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 182.417444 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 161170792250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.364411 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996805 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996805 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 144498695 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 144498695 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 144498695 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 144498695 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 144498695 # number of overall hits +system.cpu.icache.overall_hits::total 144498695 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 792139 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 792139 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 792139 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 792139 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 792139 # number of overall misses +system.cpu.icache.overall_misses::total 792139 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11198521009 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11198521009 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11198521009 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11198521009 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11198521009 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11198521009 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 145290834 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 145290834 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 145290834 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 145290834 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 145290834 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 145290834 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005452 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.005452 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.005452 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.005452 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.005452 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.005452 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14137.065602 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14137.065602 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14137.065602 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14137.065602 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14137.065602 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14137.065602 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -720,80 +721,80 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 791923 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 791923 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 791923 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 791923 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 791923 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 791923 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9593312500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9593312500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9593312500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9593312500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9593312500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9593312500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005449 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005449 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005449 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.005449 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005449 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.005449 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12113.946053 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12113.946053 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12113.946053 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12113.946053 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12113.946053 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12113.946053 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 792139 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 792139 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 792139 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 792139 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 792139 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 792139 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9607971991 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9607971991 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9607971991 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9607971991 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9607971991 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9607971991 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005452 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005452 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005452 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.005452 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005452 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.005452 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12129.149039 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12129.149039 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12129.149039 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12129.149039 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12129.149039 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12129.149039 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 3530 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 3.075423 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 7811 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 3541 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 2.205874 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5166918586000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.075423 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.192214 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.192214 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7833 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 7833 # number of ReadReq hits +system.cpu.itb_walker_cache.tags.replacements 3473 # number of replacements +system.cpu.itb_walker_cache.tags.tagsinuse 3.080805 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.total_refs 7889 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.tags.sampled_refs 3486 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.tags.avg_refs 2.263052 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.tags.warmup_cycle 5163044300000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.080805 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.192550 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_percent::total 0.192550 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7889 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 7889 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7835 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 7835 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7835 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 7835 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4388 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 4388 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4388 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 4388 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4388 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 4388 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 43163000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 43163000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 43163000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 43163000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 43163000 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 43163000 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12221 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 12221 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7891 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 7891 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7891 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 7891 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4335 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 4335 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4335 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 4335 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4335 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 4335 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 44091250 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 44091250 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 44091250 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 44091250 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 44091250 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 44091250 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12224 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 12224 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12223 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 12223 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12223 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 12223 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.359054 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.359054 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.358995 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.358995 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.358995 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.358995 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 9836.599818 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 9836.599818 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 9836.599818 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9836.599818 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9836.599818 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9836.599818 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12226 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 12226 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12226 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 12226 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.354630 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.354630 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.354572 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.354572 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.354572 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.354572 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10170.991926 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10170.991926 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10170.991926 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10170.991926 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10170.991926 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10170.991926 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -802,78 +803,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 619 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 619 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4388 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4388 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4388 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 4388 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4388 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 4388 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 34387000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 34387000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 34387000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 34387000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 34387000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 34387000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.359054 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.359054 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.358995 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.358995 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.358995 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.358995 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 7836.599818 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 7836.599818 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 7836.599818 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7836.599818 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7836.599818 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7836.599818 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 892 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 892 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4335 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4335 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4335 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 4335 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4335 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 4335 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 35418750 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 35418750 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 35418750 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 35418750 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 35418750 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 35418750 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.354630 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.354630 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.354572 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.354572 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.354572 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.354572 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8170.415225 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8170.415225 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8170.415225 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8170.415225 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8170.415225 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8170.415225 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 7412 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 5.056524 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 13351 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 7427 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.797630 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5162997491000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.056524 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.316033 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.316033 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13351 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 13351 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13351 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 13351 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13351 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 13351 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8618 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 8618 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8618 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 8618 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8618 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 8618 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 90576000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 90576000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 90576000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 90576000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 90576000 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 90576000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21969 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 21969 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21969 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 21969 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21969 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 21969 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.392280 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.392280 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.392280 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.392280 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.392280 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.392280 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10510.095150 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10510.095150 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10510.095150 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10510.095150 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10510.095150 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10510.095150 # average overall miss latency +system.cpu.dtb_walker_cache.tags.replacements 7524 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 5.060120 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 13176 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 7539 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.747712 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 5163729602000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.060120 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.316258 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.316258 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13177 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 13177 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13177 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 13177 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13177 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 13177 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8707 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 8707 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8707 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 8707 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8707 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 8707 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 93129000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 93129000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 93129000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 93129000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 93129000 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 93129000 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21884 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 21884 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21884 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 21884 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21884 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 21884 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.397871 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.397871 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.397871 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.397871 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.397871 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.397871 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10695.876881 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10695.876881 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10695.876881 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10695.876881 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10695.876881 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10695.876881 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -882,90 +883,90 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 2749 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 2749 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8618 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8618 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8618 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 8618 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8618 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 8618 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 73340000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 73340000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 73340000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 73340000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 73340000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 73340000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.392280 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.392280 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.392280 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.392280 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.392280 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.392280 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8510.095150 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8510.095150 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8510.095150 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8510.095150 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8510.095150 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8510.095150 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 3011 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 3011 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8707 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8707 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8707 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 8707 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8707 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 8707 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 75714500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 75714500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 75714500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 75714500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 75714500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 75714500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.397871 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.397871 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.397871 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.397871 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.397871 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.397871 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8695.819456 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8695.819456 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8695.819456 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8695.819456 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8695.819456 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8695.819456 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1622441 # number of replacements -system.cpu.dcache.tagsinuse 511.992388 # Cycle average of tags in use -system.cpu.dcache.total_refs 20034872 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1622953 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.344703 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 48929000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.992388 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999985 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999985 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 11992680 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11992680 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8039994 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8039994 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 20032674 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20032674 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20032674 # number of overall hits -system.cpu.dcache.overall_hits::total 20032674 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1308966 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1308966 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 316237 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 316237 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1625203 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1625203 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1625203 # number of overall misses -system.cpu.dcache.overall_misses::total 1625203 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 18848048000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 18848048000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10644655000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10644655000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 29492703000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 29492703000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 29492703000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 29492703000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13301646 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13301646 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8356231 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8356231 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21657877 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21657877 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21657877 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21657877 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098406 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.098406 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037844 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037844 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.075040 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.075040 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.075040 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.075040 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14399.188367 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14399.188367 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33660.371810 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33660.371810 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 18147.088702 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 18147.088702 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 18147.088702 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 18147.088702 # average overall miss latency +system.cpu.dcache.tags.replacements 1620395 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.997299 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 20022949 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1620907 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.352929 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 49459250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.997299 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999995 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 11985789 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11985789 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8034970 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8034970 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 20020759 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20020759 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20020759 # number of overall hits +system.cpu.dcache.overall_hits::total 20020759 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1308577 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1308577 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 314536 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 314536 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1623113 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1623113 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1623113 # number of overall misses +system.cpu.dcache.overall_misses::total 1623113 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 18867836541 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 18867836541 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10715308194 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10715308194 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 29583144735 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 29583144735 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 29583144735 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 29583144735 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13294366 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13294366 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8349506 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8349506 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21643872 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21643872 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21643872 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21643872 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098431 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.098431 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037671 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037671 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.074992 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.074992 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.074992 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.074992 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14418.590989 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14418.590989 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34067.032689 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34067.032689 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 18226.176942 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 18226.176942 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 18226.176942 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 18226.176942 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -974,46 +975,46 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1539801 # number of writebacks -system.cpu.dcache.writebacks::total 1539801 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1308966 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1308966 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 316237 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 316237 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1625203 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1625203 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1625203 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1625203 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16230116000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 16230116000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10012181000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10012181000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26242297000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26242297000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26242297000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26242297000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94201595500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94201595500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2525692000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2525692000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96727287500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 96727287500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098406 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098406 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037844 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037844 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.075040 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.075040 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.075040 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.075040 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12399.188367 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12399.188367 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31660.371810 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31660.371810 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16147.088702 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 16147.088702 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16147.088702 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16147.088702 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1537197 # number of writebacks +system.cpu.dcache.writebacks::total 1537197 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1308577 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1308577 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 314536 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 314536 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1623113 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1623113 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1623113 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1623113 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16237300459 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 16237300459 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10031005806 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10031005806 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26268306265 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26268306265 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26268306265 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26268306265 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94200368500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94200368500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2523287500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2523287500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96723656000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 96723656000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098431 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098431 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037671 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037671 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074992 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.074992 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074992 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.074992 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12408.364551 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12408.364551 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31891.439473 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31891.439473 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16183.904796 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 16183.904796 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16183.904796 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16183.904796 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1021,175 +1022,175 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 49236259 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2696119 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2695598 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 13727 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 13727 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1543169 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2198 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2198 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 360759 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 314063 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1583833 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 5979450 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side 7815 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side 17592 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 7588690 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 50682240 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 204056779 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side 219328 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side 574336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 255532683 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 255511115 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 327616 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3834241500 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 49187749 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2695979 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2695445 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 13711 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 13711 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1541100 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2190 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2190 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 359066 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 312361 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1584265 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 5972620 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side 8122 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side 18187 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 7583194 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 50696064 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 203753837 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side 242368 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side 606720 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 255298989 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 255278509 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 309568 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3830199000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 505500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 480000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1187884500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1191344009 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3023860000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3055023235 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 6582000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 6503750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 12927000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 13060750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.l2cache.replacements 86618 # number of replacements -system.cpu.l2cache.tagsinuse 64735.286295 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3491811 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 151264 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 23.084217 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 49971.529408 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.dtb.walker 0.027392 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.141401 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 3486.795305 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 11276.792789 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.762505 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.053204 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.172070 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.987782 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6224 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2803 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 779038 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1279905 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2067970 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1543169 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1543169 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 330 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 330 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 201356 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 201356 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 6224 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 2803 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 779038 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1481261 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2269326 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 6224 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 2803 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 779038 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1481261 # number of overall hits -system.cpu.l2cache.overall_hits::total 2269326 # number of overall hits +system.cpu.l2cache.tags.replacements 86901 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64732.450740 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3488744 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 151586 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 23.014949 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 50263.095698 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.027390 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.141416 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3383.648694 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 11085.537541 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.766954 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.051630 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.169152 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.987739 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6468 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2890 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 779213 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1279490 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2068061 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1541100 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1541100 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 295 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 295 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 199238 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 199238 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 6468 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 2890 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 779213 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1478728 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2267299 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 6468 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 2890 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 779213 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1478728 # number of overall hits +system.cpu.l2cache.overall_hits::total 2267299 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 1 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 12872 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 28269 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 41147 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 1336 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 1336 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 112679 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 112679 # number of ReadExReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 12913 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 28265 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 41184 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 1412 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 1412 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 113104 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 113104 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 12872 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 140948 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 153826 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 12913 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 141369 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 154288 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 12872 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 140948 # number of overall misses -system.cpu.l2cache.overall_misses::total 153826 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 89000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 389000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1010996500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2121306500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 3132781000 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 15904000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 15904000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7647596500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 7647596500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 89000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 389000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1010996500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9768903000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 10780377500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 89000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 389000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1010996500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9768903000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 10780377500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6225 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2808 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 791910 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1308174 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2109117 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1543169 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1543169 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1666 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 1666 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 314035 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 314035 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6225 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 2808 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 791910 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1622209 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2423152 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6225 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 2808 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 791910 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1622209 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2423152 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000161 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001781 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016254 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021610 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.019509 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.801921 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.801921 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.358810 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.358810 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000161 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001781 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016254 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.086886 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.063482 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000161 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001781 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016254 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.086886 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.063482 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 89000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 77800 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 78542.301119 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75040.026177 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 76136.316135 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11904.191617 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11904.191617 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67870.645817 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67870.645817 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 89000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 77800 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78542.301119 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69308.560604 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70081.634444 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 89000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 77800 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78542.301119 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69308.560604 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70081.634444 # average overall miss latency +system.cpu.l2cache.overall_misses::cpu.inst 12913 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 141369 # number of overall misses +system.cpu.l2cache.overall_misses::total 154288 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 89250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 743250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1023689491 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2132999959 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 3157521950 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 16111372 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 16111372 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7687296700 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 7687296700 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 89250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 743250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1023689491 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9820296659 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 10844818650 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 89250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 743250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1023689491 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9820296659 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 10844818650 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6469 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2895 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 792126 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1307755 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2109245 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1541100 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1541100 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1707 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 1707 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 312342 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 312342 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6469 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 2895 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 792126 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1620097 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2421587 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6469 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 2895 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 792126 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1620097 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2421587 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000155 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001727 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016302 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021613 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.019525 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.827182 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.827182 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.362116 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.362116 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000155 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001727 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016302 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.087260 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.063714 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000155 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001727 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016302 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.087260 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.063714 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 89250 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 148650 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79275.884070 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75464.353759 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 76668.656517 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11410.320113 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11410.320113 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67966.620986 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67966.620986 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 89250 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 148650 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79275.884070 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69465.700818 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70289.449925 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 89250 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 148650 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79275.884070 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69465.700818 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70289.449925 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1198,90 +1199,90 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 79984 # number of writebacks -system.cpu.l2cache.writebacks::total 79984 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 80175 # number of writebacks +system.cpu.l2cache.writebacks::total 80175 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 1 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12872 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 28269 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 41147 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1336 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 1336 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 112679 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 112679 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12913 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 28265 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 41184 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1412 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 1412 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 113104 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 113104 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 1 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 12872 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 140948 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 153826 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 12913 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 141369 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 154288 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 1 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 12872 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 140948 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 153826 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 12913 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 141369 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 154288 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 76250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 326250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 851715758 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1771468289 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2623586547 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14290818 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14290818 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6265697836 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6265697836 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 679250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 860763509 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1776510041 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2638029050 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 15111394 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 15111394 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6272468800 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6272468800 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 76250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 326250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 851715758 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8037166125 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 8889284383 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 679250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 860763509 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8048978841 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 8910497850 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 76250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 326250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 851715758 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8037166125 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 8889284383 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86643520000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86643520000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2359628500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2359628500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 89003148500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 89003148500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000161 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001781 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016254 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021610 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019509 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.801921 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.801921 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.358810 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.358810 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000161 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001781 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016254 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.086886 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.063482 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000161 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001781 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016254 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.086886 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.063482 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 679250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 860763509 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8048978841 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 8910497850 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86642397000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86642397000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2357413500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2357413500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 88999810500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 88999810500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000155 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001727 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016302 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021613 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019525 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.827182 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.827182 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.362116 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.362116 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000155 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001727 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016302 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087260 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.063714 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000155 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001727 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016302 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087260 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.063714 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 65250 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66168.098042 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62664.695921 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63761.308163 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10696.720060 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10696.720060 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55606.615572 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55606.615572 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 135850 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66658.677999 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62851.938475 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64054.706925 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10702.120397 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10702.120397 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55457.532890 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55457.532890 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 65250 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66168.098042 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57022.207658 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57787.918707 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 135850 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66658.677999 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56935.953717 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57752.371215 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 65250 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66168.098042 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57022.207658 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57787.918707 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 135850 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66658.677999 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56935.953717 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57752.371215 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency |