x86, regressions: updates stats

This is due to op class, function call, walker patches.

2 files changed, 69 insertions, 69 deletions

diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
index c125666af..81ef154d3 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
@@ -1,16 +1,16 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  5.112100                       # Number of seconds simulated
-sim_ticks                                5112099861500                       # Number of ticks simulated
-final_tick                               5112099861500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                5112099860500                       # Number of ticks simulated
+final_tick                               5112099860500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1058684                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2167614                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            27073251373                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 628224                       # Number of bytes of host memory used
-host_seconds                                   188.82                       # Real time elapsed on the host
+host_inst_rate                                1019592                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2087576                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            26073588986                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 631672                       # Number of bytes of host memory used
+host_seconds                                   196.06                       # Real time elapsed on the host
 sim_insts                                   199905607                       # Number of instructions simulated
-sim_ops                                     409299164                       # Number of ops (including micro ops) simulated
+sim_ops                                     409299132                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::pc.south_bridge.ide      2420928                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.dtb.walker          128                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker          320                       # Number of bytes read from this memory
@@ -194,7 +194,7 @@ system.iocache.tagsinuse                     0.042441                       # Cy
 system.iocache.total_refs                           0                       # Total number of references to valid blocks.
 system.iocache.sampled_refs                     47584                       # Sample count of references to valid blocks.
 system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
-system.iocache.warmup_cycle              4994822604059                       # Cycle when the warmup percentage was hit.
+system.iocache.warmup_cycle              4994822603059                       # Cycle when the warmup percentage was hit.
 system.iocache.occ_blocks::pc.south_bridge.ide     0.042441                       # Average occupied blocks per requestor
 system.iocache.occ_percent::pc.south_bridge.ide     0.002653                       # Average percentage of cache occupancy
 system.iocache.occ_percent::total            0.002653                       # Average percentage of cache occupancy
@@ -245,57 +245,57 @@ system.pc.south_bridge.ide.disks1.dma_read_txs            0
 system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
-system.cpu.numCycles                      10224199746                       # number of cpu cycles simulated
+system.cpu.numCycles                      10224199744                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   199905607                       # Number of instructions committed
-system.cpu.committedOps                     409299164                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             374462077                       # Number of integer alu accesses
+system.cpu.committedOps                     409299132                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses             374462047                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
-system.cpu.num_func_calls                           0                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     39972120                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    374462077                       # number of integer instructions
+system.cpu.num_func_calls                     2307315                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     39972114                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    374462047                       # number of integer instructions
 system.cpu.num_fp_insts                             0                       # number of float instructions
-system.cpu.num_int_register_reads           915890450                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          480542967                       # number of times the integer registers were written
+system.cpu.num_int_register_reads           915890300                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          480542889                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
 system.cpu.num_mem_refs                      35654170                       # number of memory refs
 system.cpu.num_load_insts                    27234345                       # Number of load instructions
 system.cpu.num_store_insts                    8419825                       # Number of store instructions
-system.cpu.num_idle_cycles               9770518373.401503                       # Number of idle cycles
-system.cpu.num_busy_cycles               453681372.598497                       # Number of busy cycles
+system.cpu.num_idle_cycles               9770518400.401503                       # Number of idle cycles
+system.cpu.num_busy_cycles               453681343.598497                       # Number of busy cycles
 system.cpu.not_idle_fraction                 0.044373                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                     0.955627                       # Percentage of idle cycles
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
 system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed
 system.cpu.icache.replacements                 790584                       # number of replacements
 system.cpu.icache.tagsinuse                510.666660                       # Cycle average of tags in use
-system.cpu.icache.total_refs                243492011                       # Total number of references to valid blocks.
+system.cpu.icache.total_refs                243492014                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                 791096                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                 307.790725                       # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle           148824779500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.avg_refs                 307.790728                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle           148824778500                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.occ_blocks::cpu.inst     510.666660                       # Average occupied blocks per requestor
 system.cpu.icache.occ_percent::cpu.inst      0.997396                       # Average percentage of cache occupancy
 system.cpu.icache.occ_percent::total         0.997396                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst    243492011                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       243492011                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     243492011                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        243492011                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    243492011                       # number of overall hits
-system.cpu.icache.overall_hits::total       243492011                       # number of overall hits
+system.cpu.icache.ReadReq_hits::cpu.inst    243492014                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       243492014                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     243492014                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        243492014                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    243492014                       # number of overall hits
+system.cpu.icache.overall_hits::total       243492014                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst       791103                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total        791103                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst       791103                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total         791103                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst       791103                       # number of overall misses
 system.cpu.icache.overall_misses::total        791103                       # number of overall misses
-system.cpu.icache.ReadReq_accesses::cpu.inst    244283114                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    244283114                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    244283114                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    244283114                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    244283114                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    244283114                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_accesses::cpu.inst    244283117                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    244283117                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    244283117                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    244283117                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    244283117                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    244283117                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.003238                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.003238                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.003238                       # miss rate for demand accesses
@@ -316,7 +316,7 @@ system.cpu.itb_walker_cache.tagsinuse        3.026333                       # Cy
 system.cpu.itb_walker_cache.total_refs           7886                       # Total number of references to valid blocks.
 system.cpu.itb_walker_cache.sampled_refs         3489                       # Sample count of references to valid blocks.
 system.cpu.itb_walker_cache.avg_refs         2.260246                       # Average number of references to valid blocks.
-system.cpu.itb_walker_cache.warmup_cycle 5102064746500                       # Cycle when the warmup percentage was hit.
+system.cpu.itb_walker_cache.warmup_cycle 5102064745500                       # Cycle when the warmup percentage was hit.
 system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker     3.026333                       # Average occupied blocks per requestor
 system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker     0.189146                       # Average percentage of cache occupancy
 system.cpu.itb_walker_cache.occ_percent::total     0.189146                       # Average percentage of cache occupancy
@@ -364,7 +364,7 @@ system.cpu.dtb_walker_cache.tagsinuse        5.014191                       # Cy
 system.cpu.dtb_walker_cache.total_refs          12947                       # Total number of references to valid blocks.
 system.cpu.dtb_walker_cache.sampled_refs         7641                       # Sample count of references to valid blocks.
 system.cpu.dtb_walker_cache.avg_refs         1.694412                       # Average number of references to valid blocks.
-system.cpu.dtb_walker_cache.warmup_cycle 5100425402500                       # Cycle when the warmup percentage was hit.
+system.cpu.dtb_walker_cache.warmup_cycle 5100425401500                       # Cycle when the warmup percentage was hit.
 system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker     5.014191                       # Average occupied blocks per requestor
 system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker     0.313387                       # Average percentage of cache occupancy
 system.cpu.dtb_walker_cache.occ_percent::total     0.313387                       # Average percentage of cache occupancy
@@ -408,22 +408,22 @@ system.cpu.dcache.tagsinuse                511.999425                       # Cy
 system.cpu.dcache.total_refs                 20168705                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                1622472                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                  12.430849                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle                7550500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.warmup_cycle                7549500                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.occ_blocks::cpu.data     511.999425                       # Average occupied blocks per requestor
 system.cpu.dcache.occ_percent::cpu.data      0.999999                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_percent::total         0.999999                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data     12073184                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        12073184                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      8093253                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        8093253                       # number of WriteReq hits
+system.cpu.dcache.ReadReq_hits::cpu.data     12073185                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        12073185                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      8093252                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        8093252                       # number of WriteReq hits
 system.cpu.dcache.demand_hits::cpu.data      20166437                       # number of demand (read+write) hits
 system.cpu.dcache.demand_hits::total         20166437                       # number of demand (read+write) hits
 system.cpu.dcache.overall_hits::cpu.data     20166437                       # number of overall hits
 system.cpu.dcache.overall_hits::total        20166437                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1308370                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1308370                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       316386                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       316386                       # number of WriteReq misses
+system.cpu.dcache.ReadReq_misses::cpu.data      1308369                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1308369                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       316387                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       316387                       # number of WriteReq misses
 system.cpu.dcache.demand_misses::cpu.data      1624756                       # number of demand (read+write) misses
 system.cpu.dcache.demand_misses::total        1624756                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data      1624756                       # number of overall misses
@@ -456,16 +456,16 @@ system.cpu.dcache.writebacks::writebacks      1535700                       # nu
 system.cpu.dcache.writebacks::total           1535700                       # number of writebacks
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                105930                       # number of replacements
-system.cpu.l2cache.tagsinuse             64819.953894                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                 3456507                       # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse             64819.953901                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 3456506                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                170058                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                 20.325460                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                 20.325454                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 51906.788142                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::writebacks 51906.788145                       # Average occupied blocks per requestor
 system.cpu.l2cache.occ_blocks::cpu.dtb.walker     0.004959                       # Average occupied blocks per requestor
 system.cpu.l2cache.occ_blocks::cpu.itb.walker     0.132241                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst   2490.593014                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data  10422.435538                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst   2490.593013                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data  10422.435543                       # Average occupied blocks per requestor
 system.cpu.l2cache.occ_percent::writebacks     0.792035                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::cpu.dtb.walker     0.000000                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::cpu.itb.walker     0.000002                       # Average percentage of cache occupancy
@@ -475,14 +475,14 @@ system.cpu.l2cache.occ_percent::total        0.989074                       # Av
 system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker         6501                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         2802                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.inst       777765                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data      1275492                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        2062560                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data      1275491                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        2062559                       # number of ReadReq hits
 system.cpu.l2cache.Writeback_hits::writebacks      1538639                       # number of Writeback hits
 system.cpu.l2cache.Writeback_hits::total      1538639                       # number of Writeback hits
 system.cpu.l2cache.UpgradeReq_hits::cpu.data           20                       # number of UpgradeReq hits
 system.cpu.l2cache.UpgradeReq_hits::total           20                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       179720                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       179720                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       179721                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       179721                       # number of ReadExReq hits
 system.cpu.l2cache.demand_hits::cpu.dtb.walker         6501                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.itb.walker         2802                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.inst       777765                       # number of demand (read+write) hits
@@ -515,14 +515,14 @@ system.cpu.l2cache.overall_misses::total       179971                       # nu
 system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker         6503                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         2807                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.inst       791090                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      1307738                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      2108138                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      1307737                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      2108137                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses::writebacks      1538639                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses::total      1538639                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::cpu.data         1823                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::total         1823                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       314113                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       314113                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       314114                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       314114                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses::cpu.dtb.walker         6503                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.itb.walker         2807                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.inst       791090                       # number of demand (read+write) accesses
@@ -540,8 +540,8 @@ system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.024658
 system.cpu.l2cache.ReadReq_miss_rate::total     0.021620                       # miss rate for ReadReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.989029                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::total     0.989029                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.427849                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.427849                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.427848                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.427848                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000308                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.001781                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016844                       # miss rate for demand accesses
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
index fe64538c7..452558553 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
@@ -4,13 +4,13 @@ sim_seconds                                  5.187336                       # Nu
 sim_ticks                                5187335906000                       # Number of ticks simulated
 final_tick                               5187335906000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 632480                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1219228                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            25568906299                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 629256                       # Number of bytes of host memory used
-host_seconds                                   202.88                       # Real time elapsed on the host
+host_inst_rate                                 633010                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1220249                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            25590316667                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 632708                       # Number of bytes of host memory used
+host_seconds                                   202.71                       # Real time elapsed on the host
 sim_insts                                   128315489                       # Number of instructions simulated
-sim_ops                                     247353050                       # Number of ops (including micro ops) simulated
+sim_ops                                     247353048                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::pc.south_bridge.ide      2850304                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker          320                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.inst            824512                       # Number of bytes read from this memory
@@ -293,10 +293,10 @@ system.cpu.numCycles                      10374671812                       # nu
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   128315489                       # Number of instructions committed
-system.cpu.committedOps                     247353050                       # Number of ops (including micro ops) committed
+system.cpu.committedOps                     247353048                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses             232087369                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
-system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_func_calls                     2299349                       # number of times a function call or return occured
 system.cpu.num_conditional_control_insts     23166071                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                    232087369                       # number of integer instructions
 system.cpu.num_fp_insts                             0                       # number of float instructions