diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-09-18 10:30:04 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-09-18 10:30:04 -0400 |
| commit | d2b57a7473768e8aff3707916b40b264cab6821c (patch) | |
| tree | f4e64db0a8bb23dd26a1c8f1ec5b887be346f625 /tests/quick/fs/10.linux-boot/ref | |
| parent | 7c55464aac2bcab15699e563f18a7d3d565d949a (diff) | |
| download | gem5-d2b57a7473768e8aff3707916b40b264cab6821c.tar.xz | |
Stats: Update stats to reflect SimpleMemory bandwidth
This patch simply bumps the stats to reflect the introduction of a
bandwidth limit of 12.8GB/s for SimpleMemory.
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref')
4 files changed, 2060 insertions, 2060 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index de241166d..181c5df24 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,218 +1,218 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.962054 # Number of seconds simulated -sim_ticks 1962054431000 # Number of ticks simulated -final_tick 1962054431000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.962058 # Number of seconds simulated +sim_ticks 1962057812000 # Number of ticks simulated +final_tick 1962057812000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2014980 # Simulator instruction rate (inst/s) -host_op_rate 2014979 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 66592137800 # Simulator tick rate (ticks/s) -host_mem_usage 297124 # Number of bytes of host memory used -host_seconds 29.46 # Real time elapsed on the host -sim_insts 59368818 # Number of instructions simulated -sim_ops 59368818 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 834816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24594240 # Number of bytes read from this memory +host_inst_rate 1235183 # Simulator instruction rate (inst/s) +host_op_rate 1235183 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 40819911602 # Simulator tick rate (ticks/s) +host_mem_usage 297060 # Number of bytes of host memory used +host_seconds 48.07 # Real time elapsed on the host +sim_insts 59370518 # Number of instructions simulated +sim_ops 59370518 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 834432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24593280 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 29056 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 572928 # Number of bytes read from this memory -system.physmem.bytes_read::total 28681856 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 834816 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 29056 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 863872 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7716416 # Number of bytes written to this memory -system.physmem.bytes_written::total 7716416 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13044 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 384285 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu1.inst 29312 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 572992 # Number of bytes read from this memory +system.physmem.bytes_read::total 28680832 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 834432 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 29312 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 863744 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7715456 # Number of bytes written to this memory +system.physmem.bytes_written::total 7715456 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13038 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 384270 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41419 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 454 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 8952 # Number of read requests responded to by this memory -system.physmem.num_reads::total 448154 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 120569 # Number of write requests responded to by this memory -system.physmem.num_writes::total 120569 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 425481 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12534943 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1351041 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 14809 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 292004 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14618277 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 425481 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 14809 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 440290 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3932825 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3932825 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3932825 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 425481 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12534943 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1351041 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 14809 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 292004 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18551102 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 341254 # number of replacements -system.l2c.tagsinuse 65290.172220 # Cycle average of tags in use -system.l2c.total_refs 2492312 # Total number of references to valid blocks. -system.l2c.sampled_refs 406269 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.134635 # Average number of references to valid blocks. +system.physmem.num_reads::cpu1.inst 458 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 8953 # Number of read requests responded to by this memory +system.physmem.num_reads::total 448138 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 120554 # Number of write requests responded to by this memory +system.physmem.num_writes::total 120554 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 425284 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12534432 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1351039 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 14939 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 292036 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14617730 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 425284 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 14939 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 440224 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3932329 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3932329 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3932329 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 425284 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12534432 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1351039 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 14939 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 292036 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18550059 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 341238 # number of replacements +system.l2c.tagsinuse 65290.171288 # Cycle average of tags in use +system.l2c.total_refs 2492514 # Total number of references to valid blocks. +system.l2c.sampled_refs 406253 # Sample count of references to valid blocks. +system.l2c.avg_refs 6.135374 # Average number of references to valid blocks. system.l2c.warmup_cycle 7854344000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 55481.040218 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4824.761707 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 4855.330442 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 116.015324 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 13.024529 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.846573 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.073620 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 55481.148199 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4824.640956 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 4855.323185 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 116.032373 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 13.026576 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.846575 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.073618 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.data 0.074086 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.001770 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.001771 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.data 0.000199 # Average percentage of cache occupancy system.l2c.occ_percent::total 0.996249 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 902302 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 773944 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 86739 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 31910 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1794895 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 820354 # number of Writeback hits -system.l2c.Writeback_hits::total 820354 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 162 # number of UpgradeReq hits +system.l2c.ReadReq_hits::cpu0.inst 902430 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 773977 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 86748 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 31919 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1795074 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 820361 # number of Writeback hits +system.l2c.Writeback_hits::total 820361 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 161 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 57 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 219 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 23 # number of SCUpgradeReq hits +system.l2c.UpgradeReq_hits::total 218 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 21 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.data 21 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 44 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 172408 # number of ReadExReq hits +system.l2c.SCUpgradeReq_hits::total 42 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 172410 # number of ReadExReq hits system.l2c.ReadExReq_hits::cpu1.data 12341 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 184749 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 902302 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 946352 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 86739 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 44251 # number of demand (read+write) hits -system.l2c.demand_hits::total 1979644 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 902302 # number of overall hits -system.l2c.overall_hits::cpu0.data 946352 # number of overall hits -system.l2c.overall_hits::cpu1.inst 86739 # number of overall hits -system.l2c.overall_hits::cpu1.data 44251 # number of overall hits -system.l2c.overall_hits::total 1979644 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 13044 # number of ReadReq misses +system.l2c.ReadExReq_hits::total 184751 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 902430 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 946387 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 86748 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 44260 # number of demand (read+write) hits +system.l2c.demand_hits::total 1979825 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 902430 # number of overall hits +system.l2c.overall_hits::cpu0.data 946387 # number of overall hits +system.l2c.overall_hits::cpu1.inst 86748 # number of overall hits +system.l2c.overall_hits::cpu1.data 44260 # number of overall hits +system.l2c.overall_hits::total 1979825 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 13038 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.data 271462 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 465 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 325 # number of ReadReq misses -system.l2c.ReadReq_misses::total 285296 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2436 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 489 # number of UpgradeReq misses +system.l2c.ReadReq_misses::cpu1.inst 469 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 326 # number of ReadReq misses +system.l2c.ReadReq_misses::total 285295 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 2435 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 490 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 2925 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 35 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 34 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 73 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 108 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 113191 # number of ReadExReq misses +system.l2c.SCUpgradeReq_misses::total 107 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 113176 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 8669 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 121860 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 13044 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 384653 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 465 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 8994 # number of demand (read+write) misses -system.l2c.demand_misses::total 407156 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 13044 # number of overall misses -system.l2c.overall_misses::cpu0.data 384653 # number of overall misses -system.l2c.overall_misses::cpu1.inst 465 # number of overall misses -system.l2c.overall_misses::cpu1.data 8994 # number of overall misses -system.l2c.overall_misses::total 407156 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 678900500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 14120860000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 24120000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 17316000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 14841196500 # number of ReadReq miss cycles +system.l2c.ReadExReq_misses::total 121845 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.inst 13038 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 384638 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 469 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 8995 # number of demand (read+write) misses +system.l2c.demand_misses::total 407140 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 13038 # number of overall misses +system.l2c.overall_misses::cpu0.data 384638 # number of overall misses +system.l2c.overall_misses::cpu1.inst 469 # number of overall misses +system.l2c.overall_misses::cpu1.data 8995 # number of overall misses +system.l2c.overall_misses::total 407140 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.inst 678189500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 14120883000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 24328000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 17368000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 14840768500 # number of ReadReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu0.data 1412000 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu1.data 1560000 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::total 2972000 # number of UpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::cpu0.data 156000 # number of SCUpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::cpu1.data 208000 # number of SCUpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::total 364000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 5886266000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 5885512000 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu1.data 450808000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6337074000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 678900500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 20007126000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 24120000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 468124000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 21178270500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 678900500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 20007126000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 24120000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 468124000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 21178270500 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 915346 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 1045406 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 87204 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 32235 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2080191 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 820354 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 820354 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 2598 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 546 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 3144 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 58 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_miss_latency::total 6336320000 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 678189500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 20006395000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 24328000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 468176000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 21177088500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 678189500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 20006395000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 24328000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 468176000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 21177088500 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.inst 915468 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 1045439 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 87217 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 32245 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2080369 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 820361 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 820361 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 2596 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 547 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 3143 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 55 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu1.data 94 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 152 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 285599 # number of ReadExReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 149 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 285586 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.data 21010 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 306609 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 915346 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1331005 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 87204 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 53245 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2386800 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 915346 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1331005 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 87204 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 53245 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2386800 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.014250 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.259671 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.005332 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.010082 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.137149 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.937644 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.895604 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.930344 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.603448 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_accesses::total 306596 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 915468 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1331025 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 87217 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 53255 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2386965 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 915468 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1331025 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 87217 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 53255 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2386965 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.014242 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.259663 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.005377 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.010110 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.137137 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.937982 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.895795 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.930640 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.618182 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.776596 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.710526 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.396328 # miss rate for ReadExReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.718121 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.396294 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 0.412613 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.397444 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.014250 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.288994 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.005332 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.168917 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.170587 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.014250 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.288994 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.005332 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.168917 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.170587 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52046.956455 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 52017.814648 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51870.967742 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 53280 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52020.345536 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 579.638752 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3190.184049 # average UpgradeReq miss latency +system.l2c.ReadExReq_miss_rate::total 0.397412 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.014242 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.288979 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.005377 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.168904 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.170568 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.014242 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.288979 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.005377 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.168904 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.170568 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52016.375211 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 52017.899374 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51872.068230 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 53276.073620 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52019.027673 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 579.876797 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3183.673469 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total 1016.068376 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 4457.142857 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 4588.235294 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2849.315068 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 3370.370370 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52002.950765 # average ReadExReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 3401.869159 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52003.180886 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52002.307071 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52002.904973 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 52046.956455 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 52013.440686 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 51870.967742 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 52048.476762 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52015.125652 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 52046.956455 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 52013.440686 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 51870.967742 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 52048.476762 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52015.125652 # average overall miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52003.118716 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 52016.375211 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 52013.568602 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 51872.068230 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 52048.471373 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52014.266591 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 52016.375211 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 52013.568602 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 51872.068230 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 52048.471373 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52014.266591 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -221,119 +221,119 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 79049 # number of writebacks -system.l2c.writebacks::total 79049 # number of writebacks +system.l2c.writebacks::writebacks 79034 # number of writebacks +system.l2c.writebacks::total 79034 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu1.inst 11 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu1.inst 11 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu1.inst 11 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.inst 13044 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 13038 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.data 271462 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 454 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 325 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 285285 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 2436 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 489 # number of UpgradeReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 458 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 326 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 285284 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 2435 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 490 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::total 2925 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 35 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 34 # number of SCUpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 73 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 108 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 113191 # number of ReadExReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 107 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 113176 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu1.data 8669 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 121860 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 13044 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 384653 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 454 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 8994 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 407145 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 13044 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 384653 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 454 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 8994 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 407145 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 522369000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 10863316000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 18183000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 13416000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 11417284000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 97500000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 19560000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 117060000 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 1400000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_misses::total 121845 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 13038 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 384638 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 458 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 8995 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 407129 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 13038 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 384638 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 458 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 8995 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 407129 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 521730000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 10863339000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 18343000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 13456000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 11416868000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 97460000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 19615000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 117075000 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 1360000 # number of SCUpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 2920000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 4320000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4527974000 # number of ReadExReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 4280000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4527400000 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 346780000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 4874754000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 522369000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 15391290000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 18183000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 360196000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 16292038000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 522369000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 15391290000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 18183000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 360196000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 16292038000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1370658000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadExReq_mshr_miss_latency::total 4874180000 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 521730000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 15390739000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 18343000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 360236000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 16291048000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 521730000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 15390739000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 18343000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 360236000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 16291048000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1369455000 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 19250000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 1389908000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1967340000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 505194000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 2472534000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3337998000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 524444000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 3862442000 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014250 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.259671 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.005206 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.010082 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.137144 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.937644 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.895604 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.930344 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.603448 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadReq_mshr_uncacheable_latency::total 1388705000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1966544000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 505236000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2471780000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3335999000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 524486000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 3860485000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014242 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.259663 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.005251 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.010110 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.137131 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.937982 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.895795 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.930640 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.618182 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.776596 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.710526 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.396328 # mshr miss rate for ReadExReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.718121 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.396294 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.412613 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.397444 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014250 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.288994 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005206 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.168917 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.170582 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014250 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.288994 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005206 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.168917 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.170582 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40046.688132 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40017.814648 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40050.660793 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 41280 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40020.624989 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40024.630542 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40020.512821 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_mshr_miss_rate::total 0.397412 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014242 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.288979 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005251 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.168904 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.170563 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014242 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.288979 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005251 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.168904 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.170563 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40016.106765 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40017.899374 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40050.218341 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 41276.073620 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40019.307076 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40024.640657 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40030.612245 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40025.641026 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40002.950765 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40003.180886 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40002.307071 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40002.904973 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40046.688132 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40013.440686 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40050.660793 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40048.476762 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40015.321323 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40046.688132 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40013.440686 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40050.660793 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40048.476762 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40015.321323 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40003.118716 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40016.106765 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40013.568602 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40050.218341 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40048.471373 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40014.462247 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40016.106765 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40013.568602 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40050.218341 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40048.471373 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40014.462247 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -345,14 +345,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41698 # number of replacements -system.iocache.tagsinuse 0.566768 # Cycle average of tags in use +system.iocache.tagsinuse 0.566822 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41714 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. system.iocache.warmup_cycle 1754521474000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 0.566768 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.035423 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.035423 # Average percentage of cache occupancy +system.iocache.occ_blocks::tsunami.ide 0.566822 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.035426 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.035426 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 178 # number of ReadReq misses system.iocache.ReadReq_misses::total 178 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -363,12 +363,12 @@ system.iocache.overall_misses::tsunami.ide 41730 # system.iocache.overall_misses::total 41730 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 21239998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 21239998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 7628774806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 7628774806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 7650014804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 7650014804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 7650014804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 7650014804 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 11448106806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 11448106806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 11469346804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 11469346804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 11469346804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 11469346804 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 178 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 178 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -387,17 +387,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119325.831461 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 119325.831461 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183595.851126 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 183595.851126 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 183321.706302 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 183321.706302 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 183321.706302 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 183321.706302 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 7551000 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 275512.774499 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 275512.774499 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 274846.556530 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 274846.556530 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 274846.556530 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 274846.556530 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 199371000 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7072 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 24657 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 1067.731900 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8085.776858 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -413,12 +413,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41730 system.iocache.overall_mshr_misses::total 41730 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11983000 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 11983000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 5467915000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 5467915000 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 5479898000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 5479898000 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 5479898000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 5479898000 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9287247000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 9287247000 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 9299230000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9299230000 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 9299230000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9299230000 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -429,12 +429,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67320.224719 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 67320.224719 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131592.101463 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 131592.101463 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131317.948718 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 131317.948718 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131317.948718 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 131317.948718 # average overall mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 223509.024836 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 223509.024836 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 222842.798946 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 222842.798946 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 222842.798946 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 222842.798946 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -452,22 +452,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 8658373 # DTB read hits +system.cpu0.dtb.read_hits 8658368 # DTB read hits system.cpu0.dtb.read_misses 7687 # DTB read misses system.cpu0.dtb.read_acv 174 # DTB read access violations system.cpu0.dtb.read_accesses 524201 # DTB read accesses -system.cpu0.dtb.write_hits 6036768 # DTB write hits +system.cpu0.dtb.write_hits 6036843 # DTB write hits system.cpu0.dtb.write_misses 798 # DTB write misses system.cpu0.dtb.write_acv 115 # DTB write access violations system.cpu0.dtb.write_accesses 195659 # DTB write accesses -system.cpu0.dtb.data_hits 14695141 # DTB hits +system.cpu0.dtb.data_hits 14695211 # DTB hits system.cpu0.dtb.data_misses 8485 # DTB misses system.cpu0.dtb.data_acv 289 # DTB access violations system.cpu0.dtb.data_accesses 719860 # DTB accesses -system.cpu0.itb.fetch_hits 3948342 # ITB hits +system.cpu0.itb.fetch_hits 3948323 # ITB hits system.cpu0.itb.fetch_misses 3841 # ITB misses system.cpu0.itb.fetch_acv 143 # ITB acv -system.cpu0.itb.fetch_accesses 3952183 # ITB accesses +system.cpu0.itb.fetch_accesses 3952164 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -480,55 +480,55 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3924108862 # number of cpu cycles simulated +system.cpu0.numCycles 3924115624 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 54115388 # Number of instructions committed -system.cpu0.committedOps 54115388 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 50086021 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 302769 # Number of float alu accesses -system.cpu0.num_func_calls 1426994 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 6243543 # number of instructions that are conditional controls -system.cpu0.num_int_insts 50086021 # number of integer instructions -system.cpu0.num_fp_insts 302769 # number of float instructions -system.cpu0.num_int_register_reads 68608752 # number of times the integer registers were read -system.cpu0.num_int_register_writes 37121526 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 149232 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 152287 # number of times the floating registers were written -system.cpu0.num_mem_refs 14741011 # number of memory refs -system.cpu0.num_load_insts 8689642 # Number of load instructions -system.cpu0.num_store_insts 6051369 # Number of store instructions -system.cpu0.num_idle_cycles 3676810844.998126 # Number of idle cycles -system.cpu0.num_busy_cycles 247298017.001874 # Number of busy cycles +system.cpu0.committedInsts 54116505 # Number of instructions committed +system.cpu0.committedOps 54116505 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 50087098 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 302903 # Number of float alu accesses +system.cpu0.num_func_calls 1426970 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 6243728 # number of instructions that are conditional controls +system.cpu0.num_int_insts 50087098 # number of integer instructions +system.cpu0.num_fp_insts 302903 # number of float instructions +system.cpu0.num_int_register_reads 68610814 # number of times the integer registers were read +system.cpu0.num_int_register_writes 37122288 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 149298 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 152355 # number of times the floating registers were written +system.cpu0.num_mem_refs 14741096 # number of memory refs +system.cpu0.num_load_insts 8689646 # Number of load instructions +system.cpu0.num_store_insts 6051450 # Number of store instructions +system.cpu0.num_idle_cycles 3676817171.998126 # Number of idle cycles +system.cpu0.num_busy_cycles 247298452.001874 # Number of busy cycles system.cpu0.not_idle_fraction 0.063020 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.936980 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6365 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 202758 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 72603 40.61% 40.61% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 134 0.07% 40.69% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 6366 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 202757 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 72604 40.61% 40.61% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.07% 40.69% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1979 1.11% 41.79% # number of times we switched to this ipl system.cpu0.kern.ipl_count::30 6 0.00% 41.80% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 104051 58.20% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 178773 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 71234 49.27% 49.27% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 134 0.09% 49.36% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::31 104050 58.20% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 178770 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 71235 49.27% 49.27% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.09% 49.36% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1979 1.37% 50.73% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::30 6 0.00% 50.73% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 71230 49.27% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 144583 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1900684456500 96.87% 96.87% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 103099000 0.01% 96.88% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 795217500 0.04% 96.92% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_good::31 71229 49.27% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 144580 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1900688314000 96.87% 96.87% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 102511500 0.01% 96.88% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 795126500 0.04% 96.92% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::30 5572000 0.00% 96.92% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 60465248000 3.08% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1962053593000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 60465450000 3.08% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1962056974000 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.981144 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.684568 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.808752 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.684565 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.808749 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 6 2.68% 2.68% # number of syscalls executed system.cpu0.kern.syscall::3 19 8.48% 11.16% # number of syscalls executed system.cpu0.kern.syscall::4 3 1.34% 12.50% # number of syscalls executed @@ -565,33 +565,33 @@ system.cpu0.kern.callpal::wripir 91 0.05% 0.05% # nu system.cpu0.kern.callpal::wrmces 1 0.00% 0.05% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.05% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3870 2.06% 2.11% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3872 2.06% 2.11% # number of callpals executed system.cpu0.kern.callpal::tbi 44 0.02% 2.13% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.14% # number of callpals executed -system.cpu0.kern.callpal::swpipl 171949 91.52% 93.66% # number of callpals executed +system.cpu0.kern.callpal::swpipl 171948 91.52% 93.66% # number of callpals executed system.cpu0.kern.callpal::rdps 6691 3.56% 97.22% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 97.22% # number of callpals executed system.cpu0.kern.callpal::wrusp 4 0.00% 97.22% # number of callpals executed system.cpu0.kern.callpal::rdusp 7 0.00% 97.23% # number of callpals executed system.cpu0.kern.callpal::whami 2 0.00% 97.23% # number of callpals executed -system.cpu0.kern.callpal::rti 4706 2.50% 99.73% # number of callpals executed +system.cpu0.kern.callpal::rti 4705 2.50% 99.73% # number of callpals executed system.cpu0.kern.callpal::callsys 356 0.19% 99.92% # number of callpals executed system.cpu0.kern.callpal::imb 149 0.08% 100.00% # number of callpals executed system.cpu0.kern.callpal::total 187881 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7232 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1230 # number of protection mode switches +system.cpu0.kern.mode_switch::kernel 7233 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1235 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1229 -system.cpu0.kern.mode_good::user 1230 +system.cpu0.kern.mode_good::kernel 1234 +system.cpu0.kern.mode_good::user 1235 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.169939 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.170607 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.290593 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1958392751000 99.81% 99.81% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3660835000 0.19% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.291568 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1958395542000 99.81% 99.81% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3661425000 0.19% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3871 # number of times the context was actually changed +system.cpu0.kern.swap_context 3873 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -623,51 +623,51 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 914730 # number of replacements -system.cpu0.icache.tagsinuse 508.781983 # Cycle average of tags in use -system.cpu0.icache.total_refs 53208794 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 915241 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 58.136375 # Average number of references to valid blocks. +system.cpu0.icache.replacements 914851 # number of replacements +system.cpu0.icache.tagsinuse 508.781994 # Cycle average of tags in use +system.cpu0.icache.total_refs 53209789 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 915362 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 58.129777 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 36528993000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 508.781983 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu0.inst 508.781994 # Average occupied blocks per requestor system.cpu0.icache.occ_percent::cpu0.inst 0.993715 # Average percentage of cache occupancy system.cpu0.icache.occ_percent::total 0.993715 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 53208794 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 53208794 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 53208794 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 53208794 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 53208794 # number of overall hits -system.cpu0.icache.overall_hits::total 53208794 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 915369 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 915369 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 915369 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 915369 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 915369 # number of overall misses -system.cpu0.icache.overall_misses::total 915369 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13645389000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 13645389000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 13645389000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 13645389000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 13645389000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 13645389000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 54124163 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 54124163 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 54124163 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 54124163 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 54124163 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 54124163 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016912 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.016912 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016912 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.016912 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016912 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.016912 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14906.981775 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14906.981775 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14906.981775 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14906.981775 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14906.981775 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14906.981775 # average overall miss latency +system.cpu0.icache.ReadReq_hits::cpu0.inst 53209789 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 53209789 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 53209789 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 53209789 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 53209789 # number of overall hits +system.cpu0.icache.overall_hits::total 53209789 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 915491 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 915491 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 915491 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 915491 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 915491 # number of overall misses +system.cpu0.icache.overall_misses::total 915491 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13646549000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 13646549000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 13646549000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 13646549000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 13646549000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 13646549000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 54125280 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 54125280 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 54125280 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 54125280 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 54125280 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 54125280 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016914 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.016914 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016914 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.016914 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016914 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.016914 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14906.262323 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14906.262323 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14906.262323 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14906.262323 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14906.262323 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14906.262323 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -676,112 +676,112 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 915369 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 915369 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 915369 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 915369 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 915369 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 915369 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10898588000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 10898588000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10898588000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 10898588000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10898588000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 10898588000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.016912 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.016912 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.016912 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.016912 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.016912 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.016912 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11906.223610 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11906.223610 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11906.223610 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11906.223610 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11906.223610 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11906.223610 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 915491 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 915491 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 915491 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 915491 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 915491 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 915491 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10899382500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 10899382500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10899382500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 10899382500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10899382500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 10899382500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.016914 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.016914 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.016914 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.016914 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.016914 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.016914 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11905.504806 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11905.504806 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11905.504806 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11905.504806 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11905.504806 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11905.504806 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1337806 # number of replacements -system.cpu0.dcache.tagsinuse 506.531092 # Cycle average of tags in use -system.cpu0.dcache.total_refs 13370025 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1338318 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 9.990170 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 1337819 # number of replacements +system.cpu0.dcache.tagsinuse 506.532892 # Cycle average of tags in use +system.cpu0.dcache.total_refs 13370103 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1338331 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 9.990132 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 101834000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 506.531092 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.989319 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.989319 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 7444474 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7444474 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5554839 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5554839 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 175825 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 175825 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 191178 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 191178 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 12999313 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12999313 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 12999313 # number of overall hits -system.cpu0.dcache.overall_hits::total 12999313 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1037616 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1037616 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 289306 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 289306 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16762 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 16762 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 448 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 448 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1326922 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1326922 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1326922 # number of overall misses -system.cpu0.dcache.overall_misses::total 1326922 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 26113316000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 26113316000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 8963970000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 8963970000 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 238512000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 238512000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4951000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4951000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 35077286000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 35077286000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 35077286000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 35077286000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8482090 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8482090 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5844145 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5844145 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 192587 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 192587 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 191626 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 191626 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 14326235 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 14326235 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 14326235 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 14326235 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.122330 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.122330 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049504 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.049504 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.087036 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.087036 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.002338 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.002338 # miss rate for StoreCondReq accesses +system.cpu0.dcache.occ_blocks::cpu0.data 506.532892 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.989322 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.989322 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 7444463 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7444463 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5554933 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5554933 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 175817 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 175817 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 191182 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 191182 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 12999396 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12999396 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 12999396 # number of overall hits +system.cpu0.dcache.overall_hits::total 12999396 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1037635 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1037635 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 289296 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 289296 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16772 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 16772 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 445 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 445 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1326931 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1326931 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1326931 # number of overall misses +system.cpu0.dcache.overall_misses::total 1326931 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 26113637000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 26113637000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 8963228000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 8963228000 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 238633000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 238633000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4867000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4867000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 35076865000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 35076865000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 35076865000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 35076865000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8482098 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8482098 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5844229 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5844229 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 192589 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 192589 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 191627 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 191627 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 14326327 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 14326327 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 14326327 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 14326327 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.122332 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.122332 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049501 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.049501 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.087087 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.087087 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.002322 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.002322 # miss rate for StoreCondReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.092622 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total 0.092622 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.092622 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.092622 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25166.647392 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 25166.647392 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30984.390230 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 30984.390230 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14229.328242 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14229.328242 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 11051.339286 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 11051.339286 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26435.077570 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 26435.077570 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26435.077570 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 26435.077570 # average overall miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25166.495926 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 25166.495926 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30982.896411 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 30982.896411 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14228.058669 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14228.058669 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 10937.078652 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 10937.078652 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26434.580999 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 26434.580999 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26434.580999 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 26434.580999 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -790,62 +790,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 785164 # number of writebacks -system.cpu0.dcache.writebacks::total 785164 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1037616 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1037616 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 289306 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 289306 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16762 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16762 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 448 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 448 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1326922 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1326922 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1326922 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1326922 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 23000405022 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 23000405022 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8096051001 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8096051001 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 188226000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 188226000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3606001 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3606001 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 31096456023 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 31096456023 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 31096456023 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 31096456023 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1463096000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1463096000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2089087000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2089087000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3552183000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3552183000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122330 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.122330 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049504 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049504 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.087036 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.087036 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.002338 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.002338 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.writebacks::writebacks 785166 # number of writebacks +system.cpu0.dcache.writebacks::total 785166 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1037635 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 1037635 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 289296 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 289296 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16772 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16772 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 445 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 445 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1326931 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1326931 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1326931 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1326931 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 23000669022 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 23000669022 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8095339001 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8095339001 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 188317000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 188317000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3531001 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3531001 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 31096008023 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 31096008023 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 31096008023 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 31096008023 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1461823000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1461823000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2088243000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2088243000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3550066000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3550066000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122332 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.122332 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049501 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049501 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.087087 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.087087 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.002322 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.002322 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092622 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total 0.092622 # mshr miss rate for demand accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092622 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.092622 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 22166.586697 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 22166.586697 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27984.386777 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27984.386777 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11229.328242 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11229.328242 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 8049.109375 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 8049.109375 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23435.029356 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23435.029356 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23435.029356 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23435.029356 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 22166.435232 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 22166.435232 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27982.892957 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27982.892957 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11228.058669 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11228.058669 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7934.833708 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 7934.833708 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23434.532785 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23434.532785 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23434.532785 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23434.532785 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -857,22 +857,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1027490 # DTB read hits +system.cpu1.dtb.read_hits 1027530 # DTB read hits system.cpu1.dtb.read_misses 2750 # DTB read misses system.cpu1.dtb.read_acv 36 # DTB read access violations system.cpu1.dtb.read_accesses 205838 # DTB read accesses -system.cpu1.dtb.write_hits 663174 # DTB write hits +system.cpu1.dtb.write_hits 663193 # DTB write hits system.cpu1.dtb.write_misses 356 # DTB write misses system.cpu1.dtb.write_acv 48 # DTB write access violations system.cpu1.dtb.write_accesses 97040 # DTB write accesses -system.cpu1.dtb.data_hits 1690664 # DTB hits +system.cpu1.dtb.data_hits 1690723 # DTB hits system.cpu1.dtb.data_misses 3106 # DTB misses system.cpu1.dtb.data_acv 84 # DTB access violations system.cpu1.dtb.data_accesses 302878 # DTB accesses -system.cpu1.itb.fetch_hits 1394882 # ITB hits +system.cpu1.itb.fetch_hits 1394871 # ITB hits system.cpu1.itb.fetch_misses 1246 # ITB misses system.cpu1.itb.fetch_acv 41 # ITB acv -system.cpu1.itb.fetch_accesses 1396128 # ITB accesses +system.cpu1.itb.fetch_accesses 1396117 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -885,51 +885,51 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3923836450 # number of cpu cycles simulated +system.cpu1.numCycles 3923836552 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 5253430 # Number of instructions committed -system.cpu1.committedOps 5253430 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 4920456 # Number of integer alu accesses +system.cpu1.committedInsts 5254013 # Number of instructions committed +system.cpu1.committedOps 5254013 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 4921025 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 25430 # Number of float alu accesses -system.cpu1.num_func_calls 157592 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 506756 # number of instructions that are conditional controls -system.cpu1.num_int_insts 4920456 # number of integer instructions +system.cpu1.num_func_calls 157600 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 506865 # number of instructions that are conditional controls +system.cpu1.num_int_insts 4921025 # number of integer instructions system.cpu1.num_fp_insts 25430 # number of float instructions -system.cpu1.num_int_register_reads 6826440 # number of times the integer registers were read -system.cpu1.num_int_register_writes 3699681 # number of times the integer registers were written +system.cpu1.num_int_register_reads 6827399 # number of times the integer registers were read +system.cpu1.num_int_register_writes 3700117 # number of times the integer registers were written system.cpu1.num_fp_register_reads 16282 # number of times the floating registers were read system.cpu1.num_fp_register_writes 16129 # number of times the floating registers were written -system.cpu1.num_mem_refs 1700289 # number of memory refs -system.cpu1.num_load_insts 1033544 # Number of load instructions -system.cpu1.num_store_insts 666745 # Number of store instructions -system.cpu1.num_idle_cycles 3903109824.944130 # Number of idle cycles -system.cpu1.num_busy_cycles 20726625.055870 # Number of busy cycles -system.cpu1.not_idle_fraction 0.005282 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.994718 # Percentage of idle cycles +system.cpu1.num_mem_refs 1700348 # number of memory refs +system.cpu1.num_load_insts 1033584 # Number of load instructions +system.cpu1.num_store_insts 666764 # Number of store instructions +system.cpu1.num_idle_cycles 3903107404.303190 # Number of idle cycles +system.cpu1.num_busy_cycles 20729147.696810 # Number of busy cycles +system.cpu1.not_idle_fraction 0.005283 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.994717 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 2331 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 35943 # number of hwrei instructions executed +system.cpu1.kern.inst.hwrei 35942 # number of hwrei instructions executed system.cpu1.kern.ipl_count::0 9143 31.85% 31.85% # number of times we switched to this ipl system.cpu1.kern.ipl_count::22 1973 6.87% 38.72% # number of times we switched to this ipl system.cpu1.kern.ipl_count::30 91 0.32% 39.04% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 17500 60.96% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 28707 # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 17499 60.96% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 28706 # number of times we switched to this ipl system.cpu1.kern.ipl_good::0 9135 45.13% 45.13% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::22 1973 9.75% 54.87% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::30 91 0.45% 55.32% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::31 9044 44.68% 100.00% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::total 20243 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1920768070500 97.90% 97.90% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 725778000 0.04% 97.94% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 67189500 0.00% 97.94% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 40357157000 2.06% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1961918195000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::0 1920766593500 97.90% 97.90% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 726074500 0.04% 97.94% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 67017000 0.00% 97.94% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 40358561000 2.06% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1961918246000 # number of cycles we spent at this ipl system.cpu1.kern.ipl_used::0 0.999125 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.516800 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.705159 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.516830 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.705184 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::2 2 1.96% 1.96% # number of syscalls executed system.cpu1.kern.syscall::3 11 10.78% 12.75% # number of syscalls executed system.cpu1.kern.syscall::4 1 0.98% 13.73% # number of syscalls executed @@ -959,7 +959,7 @@ system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # nu system.cpu1.kern.callpal::swpctx 365 1.24% 1.27% # number of callpals executed system.cpu1.kern.callpal::tbi 10 0.03% 1.31% # number of callpals executed system.cpu1.kern.callpal::wrent 7 0.02% 1.33% # number of callpals executed -system.cpu1.kern.callpal::swpipl 24055 81.82% 83.15% # number of callpals executed +system.cpu1.kern.callpal::swpipl 24054 81.82% 83.15% # number of callpals executed system.cpu1.kern.callpal::rdps 2165 7.36% 90.51% # number of callpals executed system.cpu1.kern.callpal::wrkgp 1 0.00% 90.52% # number of callpals executed system.cpu1.kern.callpal::wrusp 3 0.01% 90.53% # number of callpals executed @@ -969,66 +969,66 @@ system.cpu1.kern.callpal::rti 2587 8.80% 99.34% # nu system.cpu1.kern.callpal::callsys 161 0.55% 99.89% # number of callpals executed system.cpu1.kern.callpal::imb 31 0.11% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 29400 # number of callpals executed +system.cpu1.kern.callpal::total 29399 # number of callpals executed system.cpu1.kern.mode_switch::kernel 879 # number of protection mode switches -system.cpu1.kern.mode_switch::user 516 # number of protection mode switches +system.cpu1.kern.mode_switch::user 515 # number of protection mode switches system.cpu1.kern.mode_switch::idle 2075 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 532 -system.cpu1.kern.mode_good::user 516 +system.cpu1.kern.mode_good::kernel 531 +system.cpu1.kern.mode_good::user 515 system.cpu1.kern.mode_good::idle 16 -system.cpu1.kern.mode_switch_good::kernel 0.605233 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::kernel 0.604096 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::idle 0.007711 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.306628 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 4074736000 0.21% 0.21% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1594048000 0.08% 0.29% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1955463610000 99.71% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_switch_good::total 0.306140 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 4075179000 0.21% 0.21% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1593973000 0.08% 0.29% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1955466537000 99.71% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 366 # number of times the context was actually changed -system.cpu1.icache.replacements 86665 # number of replacements -system.cpu1.icache.tagsinuse 419.761966 # Cycle average of tags in use -system.cpu1.icache.total_refs 5169415 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 87177 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 59.297923 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1958459766000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 419.761966 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.819848 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.819848 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 5169415 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 5169415 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 5169415 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 5169415 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 5169415 # number of overall hits -system.cpu1.icache.overall_hits::total 5169415 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 87205 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 87205 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 87205 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 87205 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 87205 # number of overall misses -system.cpu1.icache.overall_misses::total 87205 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1314538500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 1314538500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 1314538500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 1314538500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 1314538500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 1314538500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 5256620 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 5256620 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 5256620 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 5256620 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 5256620 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 5256620 # number of overall (read+write) accesses +system.cpu1.icache.replacements 86678 # number of replacements +system.cpu1.icache.tagsinuse 419.761864 # Cycle average of tags in use +system.cpu1.icache.total_refs 5169985 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 87190 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 59.295619 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1958463060000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 419.761864 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.819847 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.819847 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 5169985 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 5169985 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 5169985 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 5169985 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 5169985 # number of overall hits +system.cpu1.icache.overall_hits::total 5169985 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 87218 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 87218 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 87218 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 87218 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 87218 # number of overall misses +system.cpu1.icache.overall_misses::total 87218 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1315004000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 1315004000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 1315004000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 1315004000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 1315004000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 1315004000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 5257203 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 5257203 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 5257203 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 5257203 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 5257203 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 5257203 # number of overall (read+write) accesses system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.016590 # miss rate for ReadReq accesses system.cpu1.icache.ReadReq_miss_rate::total 0.016590 # miss rate for ReadReq accesses system.cpu1.icache.demand_miss_rate::cpu1.inst 0.016590 # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::total 0.016590 # miss rate for demand accesses system.cpu1.icache.overall_miss_rate::cpu1.inst 0.016590 # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::total 0.016590 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15074.118457 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 15074.118457 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15074.118457 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 15074.118457 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15074.118457 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 15074.118457 # average overall miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15077.208833 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 15077.208833 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15077.208833 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 15077.208833 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15077.208833 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 15077.208833 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1037,112 +1037,112 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 87205 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 87205 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 87205 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 87205 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 87205 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 87205 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 1052891500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 1052891500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1052891500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 1052891500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1052891500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 1052891500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 87218 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 87218 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 87218 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 87218 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 87218 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 87218 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 1053316500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 1053316500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1053316500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 1053316500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1053316500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 1053316500 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016590 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.016590 # mshr miss rate for ReadReq accesses system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.016590 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::total 0.016590 # mshr miss rate for demand accesses system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.016590 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total 0.016590 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12073.751505 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12073.751505 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12073.751505 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 12073.751505 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12073.751505 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 12073.751505 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12076.824738 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12076.824738 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12076.824738 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 12076.824738 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12076.824738 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 12076.824738 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 53525 # number of replacements -system.cpu1.dcache.tagsinuse 416.811918 # Cycle average of tags in use -system.cpu1.dcache.total_refs 1627176 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 53933 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 30.170322 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 1941569697000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 416.811918 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.814086 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.814086 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 982724 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 982724 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 626457 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 626457 # number of WriteReq hits +system.cpu1.dcache.replacements 53530 # number of replacements +system.cpu1.dcache.tagsinuse 416.811223 # Cycle average of tags in use +system.cpu1.dcache.total_refs 1627239 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 53938 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 30.168694 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 1941569871000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 416.811223 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.814084 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.814084 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 982758 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 982758 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 626472 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 626472 # number of WriteReq hits system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 11310 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_hits::total 11310 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 11708 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 11708 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 1609181 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 1609181 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 1609181 # number of overall hits -system.cpu1.dcache.overall_hits::total 1609181 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 35620 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 35620 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 22610 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 22610 # number of WriteReq misses +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 11707 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 11707 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 1609230 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 1609230 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 1609230 # number of overall hits +system.cpu1.dcache.overall_hits::total 1609230 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 35626 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 35626 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 22614 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 22614 # number of WriteReq misses system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1003 # number of LoadLockedReq misses system.cpu1.dcache.LoadLockedReq_misses::total 1003 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 543 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 543 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 58230 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 58230 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 58230 # number of overall misses -system.cpu1.dcache.overall_misses::total 58230 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 484449000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 484449000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 694363000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 694363000 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 12193000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 12193000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 7082000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 7082000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 1178812000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 1178812000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 1178812000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 1178812000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 1018344 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1018344 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 649067 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 649067 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 544 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 544 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 58240 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 58240 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 58240 # number of overall misses +system.cpu1.dcache.overall_misses::total 58240 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 484494000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 484494000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 694414000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 694414000 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 12192000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 12192000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 7087000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 7087000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 1178908000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 1178908000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 1178908000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 1178908000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 1018384 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1018384 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 649086 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 649086 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 12313 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::total 12313 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 12251 # number of StoreCondReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::total 12251 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 1667411 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 1667411 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 1667411 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 1667411 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.034978 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.034978 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034835 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.034835 # miss rate for WriteReq accesses +system.cpu1.dcache.demand_accesses::cpu1.data 1667470 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 1667470 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 1667470 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 1667470 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.034983 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.034983 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034840 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.034840 # miss rate for WriteReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.081459 # miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.081459 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.044323 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.044323 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.034922 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.034922 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.034922 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.034922 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13600.477260 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 13600.477260 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 30710.437859 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 30710.437859 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12156.530409 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12156.530409 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13042.357274 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 13042.357274 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20244.066632 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 20244.066632 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20244.066632 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 20244.066632 # average overall miss latency +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.044405 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.044405 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.034927 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.034927 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.034927 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.034927 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13599.449840 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13599.449840 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 30707.260989 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 30707.260989 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12155.533400 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12155.533400 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13027.573529 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 13027.573529 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20242.239011 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 20242.239011 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20242.239011 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 20242.239011 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1151,62 +1151,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 35190 # number of writebacks -system.cpu1.dcache.writebacks::total 35190 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 35620 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 35620 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 22610 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 22610 # number of WriteReq MSHR misses +system.cpu1.dcache.writebacks::writebacks 35195 # number of writebacks +system.cpu1.dcache.writebacks::total 35195 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 35626 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 35626 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 22614 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 22614 # number of WriteReq MSHR misses system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 1003 # number of LoadLockedReq MSHR misses system.cpu1.dcache.LoadLockedReq_mshr_misses::total 1003 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 543 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 543 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 58230 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 58230 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 58230 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 58230 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 377581004 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 377581004 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 626529004 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 626529004 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 9184000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 9184000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5453000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5453000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1004110008 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 1004110008 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1004110008 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 1004110008 # number of overall MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 544 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 544 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 58240 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 58240 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 58240 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 58240 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 377607005 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 377607005 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 626568004 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 626568004 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 9183000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 9183000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5455000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5455000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1004175009 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 1004175009 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1004175009 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 1004175009 # number of overall MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 20565000 # number of ReadReq MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 20565000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 534607500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 534607500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 555172500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 555172500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.034978 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.034978 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034835 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034835 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 534647000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 534647000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 555212000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 555212000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.034983 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.034983 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034840 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034840 # mshr miss rate for WriteReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.081459 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.081459 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.044323 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.044323 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.034922 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.034922 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034922 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.034922 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10600.252779 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10600.252779 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27710.261123 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27710.261123 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9156.530409 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9156.530409 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 10042.357274 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 10042.357274 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17243.860690 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17243.860690 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17243.860690 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17243.860690 # average overall mshr miss latency +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.044405 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.044405 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.034927 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.034927 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034927 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.034927 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10599.197356 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10599.197356 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27707.084284 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27707.084284 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9155.533400 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9155.533400 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 10027.573529 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 10027.573529 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17242.015951 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17242.015951 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17242.015951 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17242.015951 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 9ccbe5ddb..c82eab488 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,138 +1,138 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.921792 # Number of seconds simulated -sim_ticks 1921792488000 # Number of ticks simulated -final_tick 1921792488000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.920895 # Number of seconds simulated +sim_ticks 1920895294000 # Number of ticks simulated +final_tick 1920895294000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1964765 # Simulator instruction rate (inst/s) -host_op_rate 1964764 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 67191639126 # Simulator tick rate (ticks/s) -host_mem_usage 295072 # Number of bytes of host memory used -host_seconds 28.60 # Real time elapsed on the host -sim_insts 56195476 # Number of instructions simulated -sim_ops 56195476 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 850624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24858752 # Number of bytes read from this memory +host_inst_rate 1271848 # Simulator instruction rate (inst/s) +host_op_rate 1271848 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43474553061 # Simulator tick rate (ticks/s) +host_mem_usage 295012 # Number of bytes of host memory used +host_seconds 44.18 # Real time elapsed on the host +sim_insts 56195754 # Number of instructions simulated +sim_ops 56195754 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 850496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24859968 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory -system.physmem.bytes_read::total 28361728 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 850624 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 850624 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7403520 # Number of bytes written to this memory -system.physmem.bytes_written::total 7403520 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 13291 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388418 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 28362816 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 850496 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 850496 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7404288 # Number of bytes written to this memory +system.physmem.bytes_written::total 7404288 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13289 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388437 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 443152 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115680 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115680 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 442620 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12935191 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1380145 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14757955 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 442620 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 442620 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3852403 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3852403 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3852403 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 442620 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12935191 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1380145 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18610359 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 336240 # number of replacements -system.l2c.tagsinuse 65308.066862 # Cycle average of tags in use -system.l2c.total_refs 2448422 # Total number of references to valid blocks. -system.l2c.sampled_refs 401402 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.099676 # Average number of references to valid blocks. +system.physmem.num_reads::total 443169 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115692 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115692 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 442760 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12941865 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1380789 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14765415 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 442760 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 442760 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3854603 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3854603 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3854603 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 442760 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12941865 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1380789 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18620018 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 336257 # number of replacements +system.l2c.tagsinuse 65308.063316 # Cycle average of tags in use +system.l2c.total_refs 2448454 # Total number of references to valid blocks. +system.l2c.sampled_refs 401419 # Sample count of references to valid blocks. +system.l2c.avg_refs 6.099497 # Average number of references to valid blocks. system.l2c.warmup_cycle 6040304000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 55651.693971 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 4767.859045 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 4888.513847 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.849177 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.072752 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.074593 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 55656.590733 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 4765.137084 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 4886.335499 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.849252 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.inst 0.072710 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.074560 # Average percentage of cache occupancy system.l2c.occ_percent::total 0.996522 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.inst 916493 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 814973 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1731466 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 835196 # number of Writeback hits -system.l2c.Writeback_hits::total 835196 # number of Writeback hits +system.l2c.ReadReq_hits::cpu.inst 916463 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 814985 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1731448 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 835257 # number of Writeback hits +system.l2c.Writeback_hits::total 835257 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 4 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 187534 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 187534 # number of ReadExReq hits -system.l2c.demand_hits::cpu.inst 916493 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 1002507 # number of demand (read+write) hits -system.l2c.demand_hits::total 1919000 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.inst 916493 # number of overall hits -system.l2c.overall_hits::cpu.data 1002507 # number of overall hits -system.l2c.overall_hits::total 1919000 # number of overall hits -system.l2c.ReadReq_misses::cpu.inst 13291 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 271963 # number of ReadReq misses -system.l2c.ReadReq_misses::total 285254 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 14 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 14 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 116845 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 116845 # number of ReadExReq misses -system.l2c.demand_misses::cpu.inst 13291 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 388808 # number of demand (read+write) misses -system.l2c.demand_misses::total 402099 # number of demand (read+write) misses -system.l2c.overall_misses::cpu.inst 13291 # number of overall misses -system.l2c.overall_misses::cpu.data 388808 # number of overall misses -system.l2c.overall_misses::total 402099 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu.inst 691744000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.data 14147302000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 14839046000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu.data 320000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 320000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu.data 6076563000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6076563000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu.inst 691744000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.data 20223865000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 20915609000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu.inst 691744000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.data 20223865000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 20915609000 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu.inst 929784 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 1086936 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2016720 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 835196 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 835196 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu.data 18 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 18 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu.data 304379 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 304379 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu.inst 929784 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 1391315 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2321099 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu.inst 929784 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 1391315 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2321099 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.014295 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.250211 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.141445 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu.data 0.777778 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.777778 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.383880 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.383880 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.inst 0.014295 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.279454 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.173236 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.inst 0.014295 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.279454 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.173236 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu.inst 52046.046197 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.data 52019.215849 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52020.465971 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu.data 22857.142857 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 22857.142857 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu.data 52005.331850 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52005.331850 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu.inst 52046.046197 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.data 52015.043415 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52016.068182 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.inst 52046.046197 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.data 52015.043415 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52016.068182 # average overall miss latency +system.l2c.ReadExReq_hits::cpu.data 187565 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 187565 # number of ReadExReq hits +system.l2c.demand_hits::cpu.inst 916463 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 1002550 # number of demand (read+write) hits +system.l2c.demand_hits::total 1919013 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.inst 916463 # number of overall hits +system.l2c.overall_hits::cpu.data 1002550 # number of overall hits +system.l2c.overall_hits::total 1919013 # number of overall hits +system.l2c.ReadReq_misses::cpu.inst 13289 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 271966 # number of ReadReq misses +system.l2c.ReadReq_misses::total 285255 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu.data 13 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 13 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu.data 116861 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 116861 # number of ReadExReq misses +system.l2c.demand_misses::cpu.inst 13289 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 388827 # number of demand (read+write) misses +system.l2c.demand_misses::total 402116 # number of demand (read+write) misses +system.l2c.overall_misses::cpu.inst 13289 # number of overall misses +system.l2c.overall_misses::cpu.data 388827 # number of overall misses +system.l2c.overall_misses::total 402116 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu.inst 691205000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.data 14147611000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 14838816000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu.data 248000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 248000 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu.data 6077413000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 6077413000 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu.inst 691205000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.data 20225024000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 20916229000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu.inst 691205000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.data 20225024000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 20916229000 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu.inst 929752 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 1086951 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2016703 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 835257 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 835257 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu.data 304426 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 304426 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu.inst 929752 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 1391377 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2321129 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu.inst 929752 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.data 1391377 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2321129 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu.inst 0.014293 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.250210 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.141446 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu.data 0.764706 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.764706 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu.data 0.383873 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.383873 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu.inst 0.014293 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.279455 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.173242 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.inst 0.014293 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.279455 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.173242 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu.inst 52013.319287 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.data 52019.778208 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52019.477310 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu.data 19076.923077 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 19076.923077 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu.data 52005.485149 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52005.485149 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu.inst 52013.319287 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.data 52015.482464 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52015.410976 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.inst 52013.319287 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.data 52015.482464 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52015.410976 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -141,66 +141,66 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 74168 # number of writebacks -system.l2c.writebacks::total 74168 # number of writebacks -system.l2c.ReadReq_mshr_misses::cpu.inst 13291 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.data 271963 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 285254 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu.data 14 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 14 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu.data 116845 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 116845 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu.inst 13291 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.data 388808 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 402099 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu.inst 13291 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.data 388808 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 402099 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu.inst 532249000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.data 10883746000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 11415995000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 620000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 620000 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4674423000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 4674423000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.inst 532249000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.data 15558169000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 16090418000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.inst 532249000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.data 15558169000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 16090418000 # number of overall MSHR miss cycles +system.l2c.writebacks::writebacks 74180 # number of writebacks +system.l2c.writebacks::total 74180 # number of writebacks +system.l2c.ReadReq_mshr_misses::cpu.inst 13289 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.data 271966 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 285255 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu.data 116861 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 116861 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu.inst 13289 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.data 388827 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 402116 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu.inst 13289 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.data 388827 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 402116 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu.inst 531734000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.data 10884019000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 11415753000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 560000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 560000 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4675081000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 4675081000 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.inst 531734000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.data 15559100000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 16090834000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.inst 531734000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.data 15559100000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 16090834000 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 1331550000 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::total 1331550000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1893145000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1893145000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu.data 3224695000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 3224695000 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.014295 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.250211 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.141445 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.777778 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.777778 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.383880 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.383880 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu.inst 0.014295 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.data 0.279454 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.173236 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu.inst 0.014295 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.data 0.279454 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.173236 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40045.820480 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40019.215849 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40020.455454 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 44285.714286 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 44285.714286 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40005.331850 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40005.331850 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40045.820480 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40015.043415 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40016.060721 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40045.820480 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40015.043415 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40016.060721 # average overall mshr miss latency +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1892958000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1892958000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.data 3224508000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 3224508000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.014293 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.250210 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.141446 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.383873 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.383873 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.014293 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.279455 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.173242 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.014293 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.279455 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.173242 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40013.093536 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40019.778208 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40019.466793 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 43076.923077 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 43076.923077 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40005.485149 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40005.485149 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40013.093536 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40015.482464 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40015.403515 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40013.093536 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40015.482464 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40015.403515 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -209,14 +209,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.355427 # Cycle average of tags in use +system.iocache.tagsinuse 1.347775 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. system.iocache.warmup_cycle 1754498131000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.355427 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.084714 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.084714 # Average percentage of cache occupancy +system.iocache.occ_blocks::tsunami.ide 1.347775 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.084236 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.084236 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -227,12 +227,12 @@ system.iocache.overall_misses::tsunami.ide 41725 # system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 20672998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 20672998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 7634106806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 7634106806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 7654779804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 7654779804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 7654779804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 7654779804 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 11448538806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 11448538806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 11469211804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 11469211804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 11469211804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 11469211804 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -251,17 +251,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119497.098266 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 119497.098266 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183724.172266 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 183724.172266 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 183457.874272 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 183457.874272 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 183457.874272 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 183457.874272 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 7454000 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 275523.171111 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 275523.171111 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 274876.256537 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 274876.256537 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 274876.256537 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 274876.256537 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 199147000 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7097 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 24626 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 1050.302945 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8086.859417 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -277,12 +277,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41725 system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11676000 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 11676000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 5473252000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 5473252000 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 5484928000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 5484928000 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 5484928000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 5484928000 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9287684000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 9287684000 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 9299360000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9299360000 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 9299360000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9299360000 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -293,12 +293,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67491.329480 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 67491.329480 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131720.542934 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 131720.542934 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131454.236070 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 131454.236070 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131454.236070 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 131454.236070 # average overall mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 223519.541779 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 223519.541779 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 222872.618334 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 222872.618334 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 222872.618334 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 222872.618334 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -316,22 +316,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9066933 # DTB read hits +system.cpu.dtb.read_hits 9066995 # DTB read hits system.cpu.dtb.read_misses 10329 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations system.cpu.dtb.read_accesses 728856 # DTB read accesses -system.cpu.dtb.write_hits 6357519 # DTB write hits +system.cpu.dtb.write_hits 6357563 # DTB write hits system.cpu.dtb.write_misses 1142 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations system.cpu.dtb.write_accesses 291931 # DTB write accesses -system.cpu.dtb.data_hits 15424452 # DTB hits +system.cpu.dtb.data_hits 15424558 # DTB hits system.cpu.dtb.data_misses 11471 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations system.cpu.dtb.data_accesses 1020787 # DTB accesses -system.cpu.itb.fetch_hits 4975863 # ITB hits +system.cpu.itb.fetch_hits 4975749 # ITB hits system.cpu.itb.fetch_misses 5006 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4980869 # ITB accesses +system.cpu.itb.fetch_accesses 4980755 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -344,51 +344,51 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3843584976 # number of cpu cycles simulated +system.cpu.numCycles 3841790588 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56195476 # Number of instructions committed -system.cpu.committedOps 56195476 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 52066692 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 324259 # Number of float alu accesses -system.cpu.num_func_calls 1483822 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 6469666 # number of instructions that are conditional controls -system.cpu.num_int_insts 52066692 # number of integer instructions -system.cpu.num_fp_insts 324259 # number of float instructions -system.cpu.num_int_register_reads 71339619 # number of times the integer registers were read -system.cpu.num_int_register_writes 38530592 # number of times the integer registers were written -system.cpu.num_fp_register_reads 163543 # number of times the floating registers were read -system.cpu.num_fp_register_writes 166418 # number of times the floating registers were written -system.cpu.num_mem_refs 15477059 # number of memory refs -system.cpu.num_load_insts 9103780 # Number of load instructions -system.cpu.num_store_insts 6373279 # Number of store instructions -system.cpu.num_idle_cycles 3588655153.998133 # Number of idle cycles -system.cpu.num_busy_cycles 254929822.001867 # Number of busy cycles -system.cpu.not_idle_fraction 0.066326 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.933674 # Percentage of idle cycles +system.cpu.committedInsts 56195754 # Number of instructions committed +system.cpu.committedOps 56195754 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 52066962 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 324393 # Number of float alu accesses +system.cpu.num_func_calls 1483816 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 6469707 # number of instructions that are conditional controls +system.cpu.num_int_insts 52066962 # number of integer instructions +system.cpu.num_fp_insts 324393 # number of float instructions +system.cpu.num_int_register_reads 71340235 # number of times the integer registers were read +system.cpu.num_int_register_writes 38530699 # number of times the integer registers were written +system.cpu.num_fp_register_reads 163609 # number of times the floating registers were read +system.cpu.num_fp_register_writes 166486 # number of times the floating registers were written +system.cpu.num_mem_refs 15477180 # number of memory refs +system.cpu.num_load_insts 9103852 # Number of load instructions +system.cpu.num_store_insts 6373328 # Number of store instructions +system.cpu.num_idle_cycles 3586858626.998133 # Number of idle cycles +system.cpu.num_busy_cycles 254931961.001867 # Number of busy cycles +system.cpu.not_idle_fraction 0.066358 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.933642 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6374 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 212119 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74932 40.88% 40.88% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 212106 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74929 40.88% 40.88% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 40.95% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1937 1.06% 42.01% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 106298 57.99% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183298 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73565 49.31% 49.31% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::21 131 0.09% 49.39% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1937 1.30% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73565 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149198 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1861046523500 96.84% 96.84% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 104284500 0.01% 96.84% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 779455000 0.04% 96.89% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 59861392000 3.11% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1921791655000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981757 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_count::22 1936 1.06% 42.01% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 106288 57.99% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183284 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73562 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::22 1936 1.30% 50.69% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73562 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149191 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1860148981000 96.84% 96.84% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 104328000 0.01% 96.84% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 779009000 0.04% 96.88% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 59862143000 3.12% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1920894461000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981756 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.692064 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.813964 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.692101 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.813988 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -424,33 +424,33 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4174 2.16% 2.16% # number of callpals executed +system.cpu.kern.callpal::swpctx 4176 2.16% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 176067 91.22% 93.41% # number of callpals executed -system.cpu.kern.callpal::rdps 6838 3.54% 96.96% # number of callpals executed +system.cpu.kern.callpal::swpipl 176055 91.22% 93.41% # number of callpals executed +system.cpu.kern.callpal::rdps 6837 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal::rti 5162 2.67% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5161 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 193021 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5905 # number of protection mode switches -system.cpu.kern.mode_switch::user 1740 # number of protection mode switches +system.cpu.kern.callpal::total 193009 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5906 # number of protection mode switches +system.cpu.kern.mode_switch::user 1739 # number of protection mode switches system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches system.cpu.kern.mode_good::kernel 1909 -system.cpu.kern.mode_good::user 1740 -system.cpu.kern.mode_good::idle 169 -system.cpu.kern.mode_switch_good::kernel 0.323285 # fraction of useful protection mode switches +system.cpu.kern.mode_good::user 1739 +system.cpu.kern.mode_good::idle 170 +system.cpu.kern.mode_switch_good::kernel 0.323231 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080591 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::total 0.391911 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 46687559000 2.43% 2.43% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5260775000 0.27% 2.70% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1869843314000 97.30% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4175 # number of times the context was actually changed +system.cpu.kern.mode_ticks::kernel 46683787000 2.43% 2.43% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5260006000 0.27% 2.70% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1868950661000 97.30% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4177 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -482,51 +482,51 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 929133 # number of replacements -system.cpu.icache.tagsinuse 508.706285 # Cycle average of tags in use -system.cpu.icache.total_refs 55277511 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 929644 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 59.460945 # Average number of references to valid blocks. +system.cpu.icache.replacements 929101 # number of replacements +system.cpu.icache.tagsinuse 508.704776 # Cycle average of tags in use +system.cpu.icache.total_refs 55277821 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 929612 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 59.463326 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 36213864000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 508.706285 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.993567 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.993567 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 55277511 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 55277511 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 55277511 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 55277511 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 55277511 # number of overall hits -system.cpu.icache.overall_hits::total 55277511 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 929804 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 929804 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 929804 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 929804 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 929804 # number of overall misses -system.cpu.icache.overall_misses::total 929804 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13857748000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13857748000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13857748000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13857748000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13857748000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13857748000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 56207315 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 56207315 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 56207315 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 56207315 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 56207315 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 56207315 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 508.704776 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.993564 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.993564 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 55277821 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 55277821 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 55277821 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 55277821 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 55277821 # number of overall hits +system.cpu.icache.overall_hits::total 55277821 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 929772 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 929772 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 929772 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 929772 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 929772 # number of overall misses +system.cpu.icache.overall_misses::total 929772 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13856924500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13856924500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13856924500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13856924500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13856924500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13856924500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 56207593 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 56207593 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 56207593 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 56207593 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 56207593 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 56207593 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016542 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.016542 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.016542 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.016542 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.016542 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.016542 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14903.945348 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14903.945348 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14903.945348 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14903.945348 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14903.945348 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14903.945348 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14903.572596 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14903.572596 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14903.572596 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14903.572596 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14903.572596 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14903.572596 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -535,104 +535,104 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929804 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 929804 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 929804 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 929804 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 929804 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 929804 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11067649000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11067649000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11067649000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11067649000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11067649000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11067649000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929772 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 929772 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 929772 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 929772 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 929772 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 929772 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11066921000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11066921000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11066921000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11066921000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11066921000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11066921000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016542 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016542 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016542 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.016542 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016542 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.016542 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11903.206482 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11903.206482 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11903.206482 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11903.206482 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11903.206482 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11903.206482 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11902.833168 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11902.833168 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11902.833168 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11902.833168 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11902.833168 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11902.833168 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1390802 # number of replacements -system.cpu.dcache.tagsinuse 511.979761 # Cycle average of tags in use -system.cpu.dcache.total_refs 14052158 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1391314 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 10.099918 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1390864 # number of replacements +system.cpu.dcache.tagsinuse 511.979749 # Cycle average of tags in use +system.cpu.dcache.total_refs 14052220 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1391376 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 10.099513 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 101905000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.979761 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 511.979749 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999960 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999960 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 7816348 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7816348 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5853489 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5853489 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 183027 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183027 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 199276 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 199276 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13669837 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13669837 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13669837 # number of overall hits -system.cpu.dcache.overall_hits::total 13669837 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1069663 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1069663 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 304397 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 304397 # number of WriteReq misses +system.cpu.dcache.ReadReq_hits::cpu.data 7816402 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7816402 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5853491 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5853491 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183030 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183030 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199280 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 199280 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13669893 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13669893 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13669893 # number of overall hits +system.cpu.dcache.overall_hits::total 13669893 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1069678 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1069678 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304443 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304443 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 17273 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 17273 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1374060 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1374060 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1374060 # number of overall misses -system.cpu.dcache.overall_misses::total 1374060 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 26660030000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 26660030000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9238691000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9238691000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 247715000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 247715000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35898721000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35898721000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35898721000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35898721000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 8886011 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 8886011 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6157886 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6157886 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200300 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200300 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 199276 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 199276 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15043897 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15043897 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15043897 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15043897 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120376 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.120376 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049432 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.049432 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086236 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086236 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.091337 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.091337 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.091337 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.091337 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24923.765709 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24923.765709 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30350.795179 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30350.795179 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14341.168297 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14341.168297 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 26126.021426 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 26126.021426 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 26126.021426 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 26126.021426 # average overall miss latency +system.cpu.dcache.demand_misses::cpu.data 1374121 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1374121 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1374121 # number of overall misses +system.cpu.dcache.overall_misses::total 1374121 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 26660570000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 26660570000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9239957000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9239957000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 247721000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 247721000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35900527000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35900527000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35900527000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35900527000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 8886080 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 8886080 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6157934 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6157934 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200303 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199280 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199280 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15044014 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15044014 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15044014 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15044014 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120377 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120377 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049439 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049439 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086234 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086234 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.091340 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.091340 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.091340 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.091340 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24923.921030 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24923.921030 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30350.367721 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30350.367721 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14341.515660 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14341.515660 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26126.175934 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26126.175934 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26126.175934 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26126.175934 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -641,54 +641,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 835196 # number of writebacks -system.cpu.dcache.writebacks::total 835196 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069663 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1069663 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304397 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304397 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 835257 # number of writebacks +system.cpu.dcache.writebacks::total 835257 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069678 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1069678 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304443 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 304443 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17273 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 17273 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1374060 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1374060 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1374060 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1374060 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23450996000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 23450996000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8325500000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8325500000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 195896000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 195896000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31776496000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 31776496000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31776496000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 31776496000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 1374121 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1374121 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1374121 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1374121 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23451491000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23451491000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8326628000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8326628000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 195902000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 195902000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31778119000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 31778119000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31778119000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 31778119000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1421708000 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1421708000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011005000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011005000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3432713000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3432713000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120376 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120376 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049432 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049432 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086236 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086236 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091337 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091337 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091337 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091337 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21923.723640 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21923.723640 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27350.795179 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27350.795179 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11341.168297 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11341.168297 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23125.988676 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23125.988676 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23125.988676 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23125.988676 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2010806000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2010806000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3432514000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3432514000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120377 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120377 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049439 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049439 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086234 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086234 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091340 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091340 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091340 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091340 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21923.878962 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21923.878962 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27350.367721 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27350.367721 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11341.515660 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11341.515660 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23126.143185 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23126.143185 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23126.143185 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23126.143185 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index a84f458bf..ef29d389c 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.207291 # Nu sim_ticks 1207290627000 # Number of ticks simulated final_tick 1207290627000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1000042 # Simulator instruction rate (inst/s) -host_op_rate 1274494 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 19638848032 # Simulator tick rate (ticks/s) -host_mem_usage 383956 # Number of bytes of host memory used -host_seconds 61.47 # Real time elapsed on the host +host_inst_rate 965295 # Simulator instruction rate (inst/s) +host_op_rate 1230212 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 18956490102 # Simulator tick rate (ticks/s) +host_mem_usage 382720 # Number of bytes of host memory used +host_seconds 63.69 # Real time elapsed on the host sim_insts 61477134 # Number of instructions simulated sim_ops 78349023 # Number of ops (including micro ops) simulated system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory @@ -89,20 +89,20 @@ system.physmem.bw_total::cpu1.inst 267624 # To system.physmem.bw_total::cpu1.data 6461987 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 57984106 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 69267 # number of replacements -system.l2c.tagsinuse 52917.687187 # Cycle average of tags in use +system.l2c.tagsinuse 52917.687101 # Cycle average of tags in use system.l2c.total_refs 1645693 # Total number of references to valid blocks. system.l2c.sampled_refs 134464 # Sample count of references to valid blocks. system.l2c.avg_refs 12.238912 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 40124.661939 # Average occupied blocks per requestor +system.l2c.occ_blocks::writebacks 40124.661917 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.dtb.walker 0.000403 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.itb.walker 0.001466 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 3720.854168 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 4213.259552 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 3720.854167 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 4213.259554 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu1.dtb.walker 2.746626 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu1.itb.walker 0.001732 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 2800.295642 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 2055.865658 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 2800.295591 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 2055.865645 # Average occupied blocks per requestor system.l2c.occ_percent::writebacks 0.612254 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy @@ -189,40 +189,40 @@ system.l2c.overall_misses::cpu1.data 75979 # nu system.l2c.overall_misses::total 161841 # number of overall misses system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 52000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.itb.walker 104000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 298918500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 409688500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 298939500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 409670500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 208500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.itb.walker 52500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 263122000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 189491500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1161637500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 30055000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 27347000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 57402000 # number of UpgradeReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 263172000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 189494500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1161693500 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 30053000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 27343000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 57396000 # number of UpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::cpu0.data 3692000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 6038000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 9730000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 3494564965 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 3764669994 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7259234959 # number of ReadExReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 6036000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 9728000 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 3494513965 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 3764719994 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7259233959 # number of ReadExReq miss cycles system.l2c.demand_miss_latency::cpu0.dtb.walker 52000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.itb.walker 104000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 298918500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 3904253465 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 298939500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 3904184465 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.dtb.walker 208500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.itb.walker 52500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 263122000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 3954161494 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 8420872459 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 263172000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 3954214494 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 8420927459 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu0.dtb.walker 52000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.itb.walker 104000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 298918500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 3904253465 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 298939500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 3904184465 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.dtb.walker 208500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.itb.walker 52500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 263122000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 3954161494 # number of overall miss cycles -system.l2c.overall_miss_latency::total 8420872459 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 263172000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 3954214494 # number of overall miss cycles +system.l2c.overall_miss_latency::total 8420927459 # number of overall miss cycles system.l2c.ReadReq_accesses::cpu0.dtb.walker 4115 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.itb.walker 1843 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.inst 408051 # number of ReadReq accesses(hits+misses) @@ -299,40 +299,40 @@ system.l2c.overall_miss_rate::cpu1.data 0.278223 # mi system.l2c.overall_miss_rate::total 0.108804 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52000 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 52000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52040.128830 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 52030.543561 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52043.784819 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 52028.257557 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52125 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 52500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52175.689074 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 52072.410003 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52072.686928 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6389.243197 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 7630.301339 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 6925.916988 # average UpgradeReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52185.603807 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 52073.234405 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52075.197239 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6388.818027 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 7629.185268 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 6925.193050 # average UpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6488.576450 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 12449.484536 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 9231.499051 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52007.872323 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52041.332513 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52025.219547 # average ReadExReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 12445.360825 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 9229.601518 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52007.113315 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52042.023694 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52025.212380 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52000 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.itb.walker 52000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 52040.128830 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 52010.250376 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 52043.784819 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 52009.331197 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52125 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.itb.walker 52500 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 52175.689074 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 52042.820964 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52031.762403 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 52185.603807 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 52043.518525 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52032.102242 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52000 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 52000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 52040.128830 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 52010.250376 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 52043.784819 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 52009.331197 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52125 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.itb.walker 52500 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 52175.689074 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 52042.820964 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52031.762403 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 52185.603807 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 52043.518525 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52032.102242 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -387,53 +387,53 @@ system.l2c.overall_mshr_misses::cpu1.data 75979 # n system.l2c.overall_mshr_misses::total 161840 # number of overall MSHR misses system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 40000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 80000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 229974000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 315198000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 229995000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 315180000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 160000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 40000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 202602000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 145821000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 893915000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 188555000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 143675000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 332230000 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 22768000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 19442000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 42210000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2688204000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2896575000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5584779000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 202652000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 145824000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 893971000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 188550000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 143713000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 332263000 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 22778000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 19436000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 42214000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2688153000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2896625000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5584778000 # number of ReadExReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 40000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 80000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 229974000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 3003402000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 229995000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 3003333000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 160000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 40000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 202602000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 3042396000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 6478694000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 202652000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 3042449000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 6478749000 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 40000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 80000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 229974000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 3003402000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 229995000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 3003333000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 160000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 40000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 202602000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 3042396000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 6478694000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 202652000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 3042449000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 6478749000 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 265520000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12448668498 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12448669498 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3961000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154365734497 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 167083883995 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154365762499 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 167083912997 # number of ReadReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1128303000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 30843793500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 31972096500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 30843801500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 31972104500 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 265520000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13576971498 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13576972498 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3961000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 185209527997 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 199055980495 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 185209563999 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 199056017497 # number of overall MSHR uncacheable cycles system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000243 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001085 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014074 # mshr miss rate for ReadReq accesses @@ -472,40 +472,40 @@ system.l2c.overall_mshr_miss_rate::cpu1.data 0.278223 system.l2c.overall_mshr_miss_rate::total 0.108803 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40044.227756 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40030.226060 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40047.884381 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40027.940056 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40174.895895 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40071.723001 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40073.295378 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40083.971088 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40087.890625 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40085.666023 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40014.059754 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40086.597938 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40047.438330 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40007.203131 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40041.125242 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40024.789835 # average ReadExReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40184.810629 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40072.547403 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40075.805801 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40082.908163 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40098.493304 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40089.647683 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40031.634446 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40074.226804 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40051.233397 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40006.444124 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40041.816422 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40024.782668 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40044.227756 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40009.618075 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40047.884381 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40008.698896 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40174.895895 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40042.590716 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40031.475531 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40184.810629 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40043.288277 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40031.815373 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40044.227756 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40009.618075 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40047.884381 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40008.698896 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40174.895895 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40042.590716 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40031.475531 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40184.810629 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40043.288277 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40031.815373 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -586,8 +586,8 @@ system.cpu0.num_fp_register_writes 840 # nu system.cpu0.num_mem_refs 13404188 # number of memory refs system.cpu0.num_load_insts 7413537 # Number of load instructions system.cpu0.num_store_insts 5990651 # Number of store instructions -system.cpu0.num_idle_cycles 2267023722.330122 # Number of idle cycles -system.cpu0.num_busy_cycles 147557531.669878 # Number of busy cycles +system.cpu0.num_idle_cycles 2267023582.330122 # Number of idle cycles +system.cpu0.num_busy_cycles 147557671.669878 # Number of busy cycles system.cpu0.not_idle_fraction 0.061111 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.938889 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed @@ -613,12 +613,12 @@ system.cpu0.icache.demand_misses::cpu0.inst 408647 # system.cpu0.icache.demand_misses::total 408647 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 408647 # number of overall misses system.cpu0.icache.overall_misses::total 408647 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6096214000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6096214000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 6096214000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6096214000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 6096214000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6096214000 # number of overall miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6096279000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 6096279000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 6096279000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 6096279000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 6096279000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 6096279000 # number of overall miss cycles system.cpu0.icache.ReadReq_accesses::cpu0.inst 29574638 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::total 29574638 # number of ReadReq accesses(hits+misses) system.cpu0.icache.demand_accesses::cpu0.inst 29574638 # number of demand (read+write) accesses @@ -631,12 +631,12 @@ system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013817 system.cpu0.icache.demand_miss_rate::total 0.013817 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013817 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.013817 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14918.044180 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14918.044180 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14918.044180 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14918.044180 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14918.044180 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14918.044180 # average overall miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14918.203241 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14918.203241 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14918.203241 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14918.203241 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14918.203241 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14918.203241 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -651,12 +651,12 @@ system.cpu0.icache.demand_mshr_misses::cpu0.inst 408647 system.cpu0.icache.demand_mshr_misses::total 408647 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 408647 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 408647 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4869428500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4869428500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4869428500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4869428500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4869428500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4869428500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4869493500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4869493500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4869493500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4869493500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4869493500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4869493500 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 351814000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 351814000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 351814000 # number of overall MSHR uncacheable cycles @@ -667,24 +667,24 @@ system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013817 system.cpu0.icache.demand_mshr_miss_rate::total 0.013817 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013817 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.013817 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11915.977604 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11915.977604 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11915.977604 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11915.977604 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11915.977604 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11915.977604 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11916.136666 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11916.136666 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11916.136666 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11916.136666 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11916.136666 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11916.136666 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 330734 # number of replacements -system.cpu0.dcache.tagsinuse 459.649704 # Cycle average of tags in use +system.cpu0.dcache.tagsinuse 459.649702 # Cycle average of tags in use system.cpu0.dcache.total_refs 12280871 # Total number of references to valid blocks. system.cpu0.dcache.sampled_refs 331246 # Sample count of references to valid blocks. system.cpu0.dcache.avg_refs 37.074775 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 664264000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 459.649704 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu0.data 459.649702 # Average occupied blocks per requestor system.cpu0.dcache.occ_percent::cpu0.data 0.897753 # Average percentage of cache occupancy system.cpu0.dcache.occ_percent::total 0.897753 # Average percentage of cache occupancy system.cpu0.dcache.ReadReq_hits::cpu0.data 6605687 # number of ReadReq hits @@ -711,18 +711,18 @@ system.cpu0.dcache.demand_misses::cpu0.data 369775 # system.cpu0.dcache.demand_misses::total 369775 # number of demand (read+write) misses system.cpu0.dcache.overall_misses::cpu0.data 369775 # number of overall misses system.cpu0.dcache.overall_misses::total 369775 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3443053000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 3443053000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4918745500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 4918745500 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 100903000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 100903000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 74598000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 74598000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 8361798500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 8361798500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 8361798500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 8361798500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3443058000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 3443058000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4918727500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 4918727500 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 100897000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 100897000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 74611000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 74611000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 8361785500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 8361785500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 8361785500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 8361785500 # number of overall miss cycles system.cpu0.dcache.ReadReq_accesses::cpu0.data 6833740 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 6833740 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 5496942 # number of WriteReq accesses(hits+misses) @@ -747,18 +747,18 @@ system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029988 system.cpu0.dcache.demand_miss_rate::total 0.029988 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029988 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.029988 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15097.600119 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15097.600119 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34707.000325 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 34707.000325 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10820.697051 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10820.697051 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9950.380152 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9950.380152 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 22613.206680 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 22613.206680 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 22613.206680 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 22613.206680 # average overall miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15097.622044 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15097.622044 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34706.873315 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 34706.873315 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10820.053619 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10820.053619 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9952.114179 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9952.114179 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 22613.171523 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 22613.171523 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 22613.171523 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 22613.171523 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -781,26 +781,26 @@ system.cpu0.dcache.demand_mshr_misses::cpu0.data 369775 system.cpu0.dcache.demand_mshr_misses::total 369775 # number of demand (read+write) MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu0.data 369775 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 369775 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2758299641 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2758299641 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4493384071 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4493384071 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 72902006 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 72902006 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 52119015 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 52119015 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2758303642 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2758303642 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4493366071 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4493366071 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 72896006 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 72896006 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 52131016 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 52131016 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1001 # number of StoreCondFailReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1001 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7251683712 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 7251683712 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7251683712 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 7251683712 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13559859000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13559859000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1253198500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1253198500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14813057500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14813057500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7251669713 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 7251669713 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7251669713 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 7251669713 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13559876000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13559876000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1253192500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1253192500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14813068500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14813068500 # number of overall MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033372 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033372 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025782 # mshr miss rate for WriteReq accesses @@ -813,20 +813,20 @@ system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029988 system.cpu0.dcache.demand_mshr_miss_rate::total 0.029988 # mshr miss rate for demand accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029988 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.029988 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12094.993887 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12094.993887 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31705.621364 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31705.621364 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7817.909491 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7817.909491 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6959.409133 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6959.409133 # average StoreCondReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12095.011432 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12095.011432 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31705.494355 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31705.494355 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7817.266059 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7817.266059 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6961.011617 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6961.011617 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19611.070819 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19611.070819 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19611.070819 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19611.070819 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19611.032961 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19611.032961 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19611.032961 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19611.032961 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -894,8 +894,8 @@ system.cpu1.num_fp_register_writes 2260 # nu system.cpu1.num_mem_refs 14689113 # number of memory refs system.cpu1.num_load_insts 8640454 # Number of load instructions system.cpu1.num_store_insts 6048659 # Number of store instructions -system.cpu1.num_idle_cycles 1863361909.381196 # Number of idle cycles -system.cpu1.num_busy_cycles 549721128.618804 # Number of busy cycles +system.cpu1.num_idle_cycles 1863361359.722463 # Number of idle cycles +system.cpu1.num_busy_cycles 549721678.277537 # Number of busy cycles system.cpu1.not_idle_fraction 0.227809 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.772191 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed @@ -921,12 +921,12 @@ system.cpu1.icache.demand_misses::cpu1.inst 455583 # system.cpu1.icache.demand_misses::total 455583 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 455583 # number of overall misses system.cpu1.icache.overall_misses::total 455583 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6728267000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 6728267000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 6728267000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 6728267000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 6728267000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 6728267000 # number of overall miss cycles +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6728250000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 6728250000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 6728250000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 6728250000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 6728250000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 6728250000 # number of overall miss cycles system.cpu1.icache.ReadReq_accesses::cpu1.inst 33211062 # number of ReadReq accesses(hits+misses) system.cpu1.icache.ReadReq_accesses::total 33211062 # number of ReadReq accesses(hits+misses) system.cpu1.icache.demand_accesses::cpu1.inst 33211062 # number of demand (read+write) accesses @@ -939,12 +939,12 @@ system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013718 system.cpu1.icache.demand_miss_rate::total 0.013718 # miss rate for demand accesses system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013718 # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::total 0.013718 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14768.476875 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 14768.476875 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14768.476875 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 14768.476875 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14768.476875 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 14768.476875 # average overall miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14768.439560 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 14768.439560 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14768.439560 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 14768.439560 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14768.439560 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 14768.439560 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -959,12 +959,12 @@ system.cpu1.icache.demand_mshr_misses::cpu1.inst 455583 system.cpu1.icache.demand_mshr_misses::total 455583 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 455583 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 455583 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5360614000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5360614000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5360614000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5360614000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5360614000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5360614000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5360597500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5360597500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5360597500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5360597500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5360597500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5360597500 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5250000 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5250000 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5250000 # number of overall MSHR uncacheable cycles @@ -975,24 +975,24 @@ system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013718 system.cpu1.icache.demand_mshr_miss_rate::total 0.013718 # mshr miss rate for demand accesses system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013718 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total 0.013718 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11766.492604 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11766.492604 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11766.492604 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11766.492604 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11766.492604 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11766.492604 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11766.456387 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11766.456387 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11766.456387 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11766.456387 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11766.456387 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11766.456387 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 292605 # number of replacements -system.cpu1.dcache.tagsinuse 473.034253 # Cycle average of tags in use +system.cpu1.dcache.tagsinuse 473.034237 # Cycle average of tags in use system.cpu1.dcache.total_refs 11973075 # Total number of references to valid blocks. system.cpu1.dcache.sampled_refs 292945 # Sample count of references to valid blocks. system.cpu1.dcache.avg_refs 40.871409 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 85130110000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 473.034253 # Average occupied blocks per requestor +system.cpu1.dcache.occ_blocks::cpu1.data 473.034237 # Average occupied blocks per requestor system.cpu1.dcache.occ_percent::cpu1.data 0.923895 # Average percentage of cache occupancy system.cpu1.dcache.occ_percent::total 0.923895 # Average percentage of cache occupancy system.cpu1.dcache.ReadReq_hits::cpu1.data 6952995 # number of ReadReq hits @@ -1019,18 +1019,18 @@ system.cpu1.dcache.demand_misses::cpu1.data 321159 # system.cpu1.dcache.demand_misses::total 321159 # number of demand (read+write) misses system.cpu1.dcache.overall_misses::cpu1.data 321159 # number of overall misses system.cpu1.dcache.overall_misses::total 321159 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2374183000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2374183000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5137653000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 5137653000 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 106350500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 106350500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 87844000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 87844000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 7511836000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 7511836000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 7511836000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 7511836000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2374362000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2374362000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5137708000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 5137708000 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 106370500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 106370500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 87843000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 87843000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 7512070000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 7512070000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 7512070000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 7512070000 # number of overall miss cycles system.cpu1.dcache.ReadReq_accesses::cpu1.data 7123983 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_accesses::total 7123983 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::cpu1.data 4982126 # number of WriteReq accesses(hits+misses) @@ -1055,18 +1055,18 @@ system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026529 system.cpu1.dcache.demand_miss_rate::total 0.026529 # miss rate for demand accesses system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026529 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total 0.026529 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13885.085503 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 13885.085503 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34212.018299 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 34212.018299 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9563.033900 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9563.033900 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8716.411987 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8716.411987 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23389.772667 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 23389.772667 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23389.772667 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 23389.772667 # average overall miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13886.132360 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13886.132360 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34212.384548 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 34212.384548 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9564.832299 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9564.832299 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8716.312760 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8716.312760 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23390.501278 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 23390.501278 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23390.501278 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 23390.501278 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1089,24 +1089,24 @@ system.cpu1.dcache.demand_mshr_misses::cpu1.data 321159 system.cpu1.dcache.demand_mshr_misses::total 321159 # number of demand (read+write) MSHR misses system.cpu1.dcache.overall_mshr_misses::cpu1.data 321159 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_misses::total 321159 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1860610613 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1860610613 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4686894192 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4686894192 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 72963005 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 72963005 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 57623011 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 57623011 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6547504805 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 6547504805 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6547504805 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 6547504805 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168686172000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168686172000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 39932194000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 39932194000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 208618366000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 208618366000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1860790612 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1860790612 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4686951190 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4686951190 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 72983005 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 72983005 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 57622011 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 57622011 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6547741802 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 6547741802 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6547741802 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 6547741802 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168686201000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168686201000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 39932204000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 39932204000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 208618405000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 208618405000 # number of overall MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024002 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.024002 # mshr miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030142 # mshr miss rate for WriteReq accesses @@ -1119,18 +1119,18 @@ system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026529 system.cpu1.dcache.demand_mshr_miss_rate::total 0.026529 # mshr miss rate for demand accesses system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026529 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total 0.026529 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10881.527435 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10881.527435 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31210.381445 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31210.381445 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6560.831310 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6560.831310 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5722.245382 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5722.245382 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20387.112941 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20387.112941 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20387.112941 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20387.112941 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10882.580134 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10882.580134 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31210.760999 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31210.760999 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6562.629710 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6562.629710 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5722.146077 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5722.146077 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20387.850884 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20387.850884 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20387.850884 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20387.850884 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1152,10 +1152,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 574301885796 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 574301885796 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 574301885796 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 574301885796 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 574279130811 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 574279130811 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 574279130811 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 574279130811 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index 5fafbec2b..1b5c0ec90 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -1,168 +1,168 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.196043 # Number of seconds simulated -sim_ticks 5196043137000 # Number of ticks simulated -final_tick 5196043137000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.196023 # Number of seconds simulated +sim_ticks 5196022575000 # Number of ticks simulated +final_tick 5196022575000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 682761 # Simulator instruction rate (inst/s) -host_op_rate 1316197 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 27664981075 # Simulator tick rate (ticks/s) -host_mem_usage 397336 # Number of bytes of host memory used -host_seconds 187.82 # Real time elapsed on the host -sim_insts 128236332 # Number of instructions simulated -sim_ops 247208442 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2881344 # Number of bytes read from this memory +host_inst_rate 1315892 # Simulator instruction rate (inst/s) +host_op_rate 2536713 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 53344387183 # Simulator tick rate (ticks/s) +host_mem_usage 354072 # Number of bytes of host memory used +host_seconds 97.41 # Real time elapsed on the host +sim_insts 128174734 # Number of instructions simulated +sim_ops 247089109 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2880320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 824320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8950528 # Number of bytes read from this memory -system.physmem.bytes_read::total 12656512 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 824320 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 824320 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8081152 # Number of bytes written to this memory -system.physmem.bytes_written::total 8081152 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 45021 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu.inst 824192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8956288 # Number of bytes read from this memory +system.physmem.bytes_read::total 12661120 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 824192 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 824192 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8085888 # Number of bytes written to this memory +system.physmem.bytes_written::total 8085888 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 45005 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12880 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 139852 # Number of read requests responded to by this memory -system.physmem.num_reads::total 197758 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 126268 # Number of write requests responded to by this memory -system.physmem.num_writes::total 126268 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 554527 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu.inst 12878 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 139942 # Number of read requests responded to by this memory +system.physmem.num_reads::total 197830 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 126342 # Number of write requests responded to by this memory +system.physmem.num_writes::total 126342 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 554332 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 158644 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1722566 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2435798 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 158644 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 158644 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1555251 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1555251 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1555251 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 554527 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 158620 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1723682 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2436695 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 158620 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 158620 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1556169 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1556169 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1556169 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 554332 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 158644 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1722566 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3991049 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 86291 # number of replacements -system.l2c.tagsinuse 64759.780052 # Cycle average of tags in use -system.l2c.total_refs 3494113 # Total number of references to valid blocks. -system.l2c.sampled_refs 150981 # Sample count of references to valid blocks. -system.l2c.avg_refs 23.142733 # Average number of references to valid blocks. +system.physmem.bw_total::cpu.inst 158620 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1723682 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3992863 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 86330 # number of replacements +system.l2c.tagsinuse 64759.737076 # Cycle average of tags in use +system.l2c.total_refs 3491284 # Total number of references to valid blocks. +system.l2c.sampled_refs 151054 # Sample count of references to valid blocks. +system.l2c.avg_refs 23.112821 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 50071.847750 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.itb.walker 0.141309 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 3396.359734 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 11291.431260 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.764036 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 50074.264340 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.itb.walker 0.140725 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 3394.913598 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 11290.418413 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.764073 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.051824 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.172294 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.988156 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 6458 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 2811 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 779608 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 1280721 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2069598 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 1543757 # number of Writeback hits -system.l2c.Writeback_hits::total 1543757 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu.data 305 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 305 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 200867 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 200867 # number of ReadExReq hits -system.l2c.demand_hits::cpu.dtb.walker 6458 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.itb.walker 2811 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.inst 779608 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 1481588 # number of demand (read+write) hits -system.l2c.demand_hits::total 2270465 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.dtb.walker 6458 # number of overall hits -system.l2c.overall_hits::cpu.itb.walker 2811 # number of overall hits -system.l2c.overall_hits::cpu.inst 779608 # number of overall hits -system.l2c.overall_hits::cpu.data 1481588 # number of overall hits -system.l2c.overall_hits::total 2270465 # number of overall hits +system.l2c.occ_percent::cpu.inst 0.051802 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.172278 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.988155 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 6719 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.itb.walker 2994 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.inst 778172 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 1280323 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2068208 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 1543462 # number of Writeback hits +system.l2c.Writeback_hits::total 1543462 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu.data 302 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 302 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu.data 200678 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 200678 # number of ReadExReq hits +system.l2c.demand_hits::cpu.dtb.walker 6719 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.itb.walker 2994 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.inst 778172 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 1481001 # number of demand (read+write) hits +system.l2c.demand_hits::total 2268886 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.dtb.walker 6719 # number of overall hits +system.l2c.overall_hits::cpu.itb.walker 2994 # number of overall hits +system.l2c.overall_hits::cpu.inst 778172 # number of overall hits +system.l2c.overall_hits::cpu.data 1481001 # number of overall hits +system.l2c.overall_hits::total 2268886 # number of overall hits system.l2c.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.inst 12881 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 28319 # number of ReadReq misses -system.l2c.ReadReq_misses::total 41205 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 1371 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1371 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 112462 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 112462 # number of ReadExReq misses +system.l2c.ReadReq_misses::cpu.inst 12879 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 28353 # number of ReadReq misses +system.l2c.ReadReq_misses::total 41237 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu.data 1338 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 1338 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu.data 112514 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 112514 # number of ReadExReq misses system.l2c.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.inst 12881 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 140781 # number of demand (read+write) misses -system.l2c.demand_misses::total 153667 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.inst 12879 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 140867 # number of demand (read+write) misses +system.l2c.demand_misses::total 153751 # number of demand (read+write) misses system.l2c.overall_misses::cpu.itb.walker 5 # number of overall misses -system.l2c.overall_misses::cpu.inst 12881 # number of overall misses -system.l2c.overall_misses::cpu.data 140781 # number of overall misses -system.l2c.overall_misses::total 153667 # number of overall misses +system.l2c.overall_misses::cpu.inst 12879 # number of overall misses +system.l2c.overall_misses::cpu.data 140867 # number of overall misses +system.l2c.overall_misses::total 153751 # number of overall misses system.l2c.ReadReq_miss_latency::cpu.itb.walker 260000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.inst 670242000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.data 1486972500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 2157474500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu.data 34071000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 34071000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu.data 5850445000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 5850445000 # number of ReadExReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.inst 670083000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.data 1488776500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 2159119500 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu.data 33785000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 33785000 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu.data 5852520000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 5852520000 # number of ReadExReq miss cycles system.l2c.demand_miss_latency::cpu.itb.walker 260000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.inst 670242000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.data 7337417500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 8007919500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.inst 670083000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.data 7341296500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 8011639500 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu.itb.walker 260000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.inst 670242000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.data 7337417500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 8007919500 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu.dtb.walker 6458 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.itb.walker 2816 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.inst 792489 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 1309040 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2110803 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 1543757 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1543757 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu.data 1676 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 1676 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu.data 313329 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 313329 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu.dtb.walker 6458 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.itb.walker 2816 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.inst 792489 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 1622369 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2424132 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu.dtb.walker 6458 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.itb.walker 2816 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.inst 792489 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 1622369 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2424132 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001776 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.016254 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.021633 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.019521 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu.data 0.818019 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.818019 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.358926 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.358926 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.itb.walker 0.001776 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.inst 0.016254 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.086775 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.063391 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.itb.walker 0.001776 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.inst 0.016254 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.086775 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.063391 # miss rate for overall accesses +system.l2c.overall_miss_latency::cpu.inst 670083000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.data 7341296500 # number of overall miss cycles +system.l2c.overall_miss_latency::total 8011639500 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu.dtb.walker 6719 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.itb.walker 2999 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.inst 791051 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 1308676 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2109445 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 1543462 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 1543462 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu.data 1640 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 1640 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu.data 313192 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 313192 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu.dtb.walker 6719 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.itb.walker 2999 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.inst 791051 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 1621868 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2422637 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu.dtb.walker 6719 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.itb.walker 2999 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.inst 791051 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.data 1621868 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2422637 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001667 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.inst 0.016281 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.021665 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.019549 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu.data 0.815854 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.815854 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu.data 0.359249 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.359249 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu.itb.walker 0.001667 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.inst 0.016281 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.086855 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.063464 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.itb.walker 0.001667 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.inst 0.016281 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.086855 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.063464 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.inst 52033.382501 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.data 52507.945196 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52359.531610 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu.data 24851.203501 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 24851.203501 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu.data 52021.527271 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52021.527271 # average ReadExReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.inst 52029.117167 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.data 52508.605791 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52358.791862 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu.data 25250.373692 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 25250.373692 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu.data 52015.926907 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52015.926907 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.inst 52033.382501 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.data 52119.373353 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52112.161362 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.inst 52029.117167 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.data 52115.090830 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52107.885477 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.inst 52033.382501 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.data 52119.373353 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52112.161362 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.inst 52029.117167 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.data 52115.090830 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52107.885477 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -171,78 +171,78 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 79601 # number of writebacks -system.l2c.writebacks::total 79601 # number of writebacks +system.l2c.writebacks::writebacks 79675 # number of writebacks +system.l2c.writebacks::total 79675 # number of writebacks system.l2c.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.inst 12881 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.data 28319 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 41205 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu.data 1371 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 1371 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu.data 112462 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 112462 # number of ReadExReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.inst 12879 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.data 28353 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 41237 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu.data 1338 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 1338 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu.data 112514 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 112514 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.inst 12881 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.data 140781 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 153667 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.inst 12879 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.data 140867 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 153751 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.inst 12881 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.data 140781 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 153667 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.inst 12879 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.data 140867 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 153751 # number of overall MSHR misses system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 200000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.inst 515661000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.data 1147140000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1663001000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 55229000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 55229000 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4500898000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 4500898000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.inst 515526000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.data 1148536000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1664262000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 53936000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 53936000 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4502349000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 4502349000 # number of ReadExReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu.itb.walker 200000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.inst 515661000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.data 5648038000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 6163899000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.inst 515526000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.data 5650885000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 6166611000 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu.itb.walker 200000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.inst 515661000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.data 5648038000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 6163899000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.inst 515526000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.data 5650885000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 6166611000 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 86117450000 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::total 86117450000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 2306140000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 2306140000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu.data 88423590000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 88423590000 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001776 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.016254 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.021633 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.019521 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.818019 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.818019 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.358926 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.358926 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.001776 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.inst 0.016254 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.data 0.086775 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.063391 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.001776 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.inst 0.016254 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.data 0.086775 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.063391 # mshr miss rate for overall accesses +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 2306155000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2306155000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.data 88423605000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 88423605000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001667 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.016281 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.021665 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.019549 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.815854 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.815854 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.359249 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.359249 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.001667 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.016281 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.086855 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.063464 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.001667 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.016281 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.086855 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.063464 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40032.683798 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40507.786292 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40359.203980 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40283.734500 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40283.734500 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40021.500596 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40021.500596 # average ReadExReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40028.418355 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40508.447078 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40358.464486 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40310.911809 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40310.911809 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40015.900244 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40015.900244 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40032.683798 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40119.320079 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40112.053987 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40028.418355 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40115.037589 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40107.778161 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40032.683798 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40119.320079 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40112.053987 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40028.418355 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40115.037589 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40107.778161 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -251,14 +251,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 47503 # number of replacements -system.iocache.tagsinuse 0.108785 # Cycle average of tags in use +system.iocache.tagsinuse 0.108744 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 47519 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. system.iocache.warmup_cycle 5053216388000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.108785 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.006799 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.006799 # Average percentage of cache occupancy +system.iocache.occ_blocks::pc.south_bridge.ide 0.108744 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.006796 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.006796 # Average percentage of cache occupancy system.iocache.ReadReq_misses::pc.south_bridge.ide 838 # number of ReadReq misses system.iocache.ReadReq_misses::total 838 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses @@ -267,14 +267,14 @@ system.iocache.demand_misses::pc.south_bridge.ide 47558 system.iocache.demand_misses::total 47558 # number of demand (read+write) misses system.iocache.overall_misses::pc.south_bridge.ide 47558 # number of overall misses system.iocache.overall_misses::total 47558 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 128838932 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 128838932 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 7147789160 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 7147789160 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 7276628092 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 7276628092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 7276628092 # number of overall miss cycles -system.iocache.overall_miss_latency::total 7276628092 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 129993932 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 129993932 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10714208160 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10714208160 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 10844202092 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10844202092 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 10844202092 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10844202092 # number of overall miss cycles system.iocache.ReadReq_accesses::pc.south_bridge.ide 838 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 838 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) @@ -291,19 +291,19 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 153745.742243 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 153745.742243 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 152992.062500 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 152992.062500 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 153005.342781 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 153005.342781 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 153005.342781 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 153005.342781 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 372008 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 155124.023866 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 155124.023866 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 229328.085616 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 229328.085616 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 228020.566298 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 228020.566298 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 228020.566298 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 228020.566298 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 89624012 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 38 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10977 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9789.684211 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8164.709119 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -317,14 +317,14 @@ system.iocache.demand_mshr_misses::pc.south_bridge.ide 47558 system.iocache.demand_mshr_misses::total 47558 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::pc.south_bridge.ide 47558 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 47558 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 85232000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 85232000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 4718093984 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 4718093984 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4803325984 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 4803325984 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4803325984 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 4803325984 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 86387000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 86387000 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8284511992 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8284511992 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8370898992 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8370898992 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8370898992 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8370898992 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -333,14 +333,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 101708.830549 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 101708.830549 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 100986.600685 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 100986.600685 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 100999.326801 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 100999.326801 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 100999.326801 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 100999.326801 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 103087.112172 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 103087.112172 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 177322.602568 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 177322.602568 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 176014.529459 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 176014.529459 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 176014.529459 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 176014.529459 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -354,75 +354,75 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 10392086274 # number of cpu cycles simulated +system.cpu.numCycles 10392045150 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 128236332 # Number of instructions committed -system.cpu.committedOps 247208442 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 231946757 # Number of integer alu accesses +system.cpu.committedInsts 128174734 # Number of instructions committed +system.cpu.committedOps 247089109 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 231827885 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 23151326 # number of instructions that are conditional controls -system.cpu.num_int_insts 231946757 # number of integer instructions +system.cpu.num_conditional_control_insts 23138722 # number of instructions that are conditional controls +system.cpu.num_int_insts 231827885 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 566912178 # number of times the integer registers were read -system.cpu.num_int_register_writes 293147449 # number of times the integer registers were written +system.cpu.num_int_register_reads 566609561 # number of times the integer registers were read +system.cpu.num_int_register_writes 292994515 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 22230275 # number of memory refs -system.cpu.num_load_insts 13869948 # Number of load instructions -system.cpu.num_store_insts 8360327 # Number of store instructions -system.cpu.num_idle_cycles 9776409858.670118 # Number of idle cycles -system.cpu.num_busy_cycles 615676415.329882 # Number of busy cycles -system.cpu.not_idle_fraction 0.059245 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.940755 # Percentage of idle cycles +system.cpu.num_mem_refs 22210252 # number of memory refs +system.cpu.num_load_insts 13855140 # Number of load instructions +system.cpu.num_store_insts 8355112 # Number of store instructions +system.cpu.num_idle_cycles 9776628704.958118 # Number of idle cycles +system.cpu.num_busy_cycles 615416445.041882 # Number of busy cycles +system.cpu.not_idle_fraction 0.059220 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.940780 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.icache.replacements 791983 # number of replacements -system.cpu.icache.tagsinuse 510.339207 # Cycle average of tags in use -system.cpu.icache.total_refs 144447737 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 792495 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 182.269588 # Average number of references to valid blocks. +system.cpu.icache.replacements 790545 # number of replacements +system.cpu.icache.tagsinuse 510.338891 # Cycle average of tags in use +system.cpu.icache.total_refs 144363546 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 791057 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 182.494493 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 160970951000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.339207 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 510.338891 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.996756 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.996756 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 144447737 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 144447737 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 144447737 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 144447737 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 144447737 # number of overall hits -system.cpu.icache.overall_hits::total 144447737 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 792502 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 792502 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 792502 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 792502 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 792502 # number of overall misses -system.cpu.icache.overall_misses::total 792502 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11813272500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11813272500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11813272500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11813272500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11813272500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11813272500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 145240239 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 145240239 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 145240239 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 145240239 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 145240239 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 145240239 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005456 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.005456 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.005456 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.005456 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.005456 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.005456 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14906.299921 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14906.299921 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14906.299921 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14906.299921 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14906.299921 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14906.299921 # average overall miss latency +system.cpu.icache.ReadReq_hits::cpu.inst 144363546 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 144363546 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 144363546 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 144363546 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 144363546 # number of overall hits +system.cpu.icache.overall_hits::total 144363546 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 791064 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 791064 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 791064 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 791064 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 791064 # number of overall misses +system.cpu.icache.overall_misses::total 791064 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11792673000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11792673000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11792673000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11792673000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11792673000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11792673000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 145154610 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 145154610 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 145154610 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 145154610 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 145154610 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 145154610 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005450 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.005450 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.005450 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.005450 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.005450 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.005450 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14907.356421 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14907.356421 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14907.356421 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14907.356421 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14907.356421 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14907.356421 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -431,80 +431,80 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 792502 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 792502 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 792502 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 792502 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 792502 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 792502 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9434751000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9434751000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9434751000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9434751000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9434751000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9434751000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005456 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005456 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005456 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.005456 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005456 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.005456 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11905.018536 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11905.018536 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11905.018536 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11905.018536 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11905.018536 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11905.018536 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 791064 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 791064 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 791064 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 791064 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 791064 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 791064 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9418462000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9418462000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9418462000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9418462000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9418462000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9418462000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005450 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005450 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005450 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.005450 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005450 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.005450 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11906.068283 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11906.068283 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11906.068283 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11906.068283 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11906.068283 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11906.068283 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 3538 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 3.068811 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 7893 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 3550 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 2.223380 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5169410055000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.068811 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.191801 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.191801 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7916 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 7916 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 3550 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 3.065778 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 7809 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 3562 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 2.192308 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5171078849000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.065778 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.191611 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.191611 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7809 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 7809 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7918 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 7918 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7918 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 7918 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4398 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 4398 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4398 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 4398 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4398 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 4398 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 51351000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 51351000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 51351000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 51351000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 51351000 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 51351000 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12314 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 12314 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7811 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 7811 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7811 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 7811 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4415 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 4415 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4415 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 4415 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4415 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 4415 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 53239000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 53239000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 53239000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 53239000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 53239000 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 53239000 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12224 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 12224 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12316 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 12316 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12316 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 12316 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.357154 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.357154 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.357096 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.357096 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.357096 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.357096 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11675.989086 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11675.989086 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11675.989086 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11675.989086 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11675.989086 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11675.989086 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12226 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 12226 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12226 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 12226 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.361175 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.361175 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.361116 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.361116 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.361116 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.361116 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 12058.663647 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 12058.663647 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 12058.663647 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 12058.663647 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 12058.663647 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 12058.663647 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -513,78 +513,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 656 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 656 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4398 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4398 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4398 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 4398 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4398 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 4398 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 38157000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 38157000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 38157000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 38157000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 38157000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 38157000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.357154 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.357154 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.357096 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.357096 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.357096 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.357096 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8675.989086 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8675.989086 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8675.989086 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8675.989086 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8675.989086 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8675.989086 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 830 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 830 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4415 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4415 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4415 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 4415 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4415 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 4415 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 39994000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 39994000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 39994000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 39994000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 39994000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 39994000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.361175 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.361175 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.361116 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.361116 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.361116 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.361116 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9058.663647 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9058.663647 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9058.663647 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9058.663647 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9058.663647 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9058.663647 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 7615 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 5.050606 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 13416 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 7630 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.758322 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5165509990000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.050606 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.315663 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.315663 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13416 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 13416 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13416 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 13416 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13416 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 13416 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8830 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 8830 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8830 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 8830 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8830 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 8830 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 114790500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 114790500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 114790500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 114790500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 114790500 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 114790500 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22246 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 22246 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22246 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 22246 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22246 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 22246 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.396925 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.396925 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.396925 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.396925 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.396925 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.396925 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 13000.056625 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 13000.056625 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 13000.056625 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 13000.056625 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 13000.056625 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 13000.056625 # average overall miss latency +system.cpu.dtb_walker_cache.replacements 7810 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 5.052392 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 12921 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 7826 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.651035 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5166488673000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.052392 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.315774 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.315774 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12921 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 12921 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12921 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 12921 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12921 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 12921 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 9010 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 9010 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 9010 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 9010 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 9010 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 9010 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 118862500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 118862500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 118862500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 118862500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 118862500 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 118862500 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21931 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 21931 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21931 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 21931 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21931 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 21931 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.410834 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.410834 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.410834 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.410834 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.410834 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.410834 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 13192.286349 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 13192.286349 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 13192.286349 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 13192.286349 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 13192.286349 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 13192.286349 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -593,90 +593,90 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 3005 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 3005 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8830 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8830 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8830 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 8830 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8830 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 8830 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 88300000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 88300000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 88300000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 88300000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 88300000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 88300000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.396925 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.396925 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.396925 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.396925 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.396925 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.396925 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10000 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10000 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10000 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10000 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10000 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10000 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 3142 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 3142 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 9010 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 9010 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 9010 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 9010 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 9010 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 9010 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 91832000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 91832000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 91832000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 91832000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 91832000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 91832000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.410834 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.410834 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.410834 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.410834 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.410834 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.410834 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10192.230855 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10192.230855 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10192.230855 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10192.230855 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10192.230855 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10192.230855 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1622589 # number of replacements -system.cpu.dcache.tagsinuse 511.997330 # Cycle average of tags in use -system.cpu.dcache.total_refs 20023565 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1623101 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.336611 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1622132 # number of replacements +system.cpu.dcache.tagsinuse 511.997396 # Cycle average of tags in use +system.cpu.dcache.total_refs 20004026 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1622644 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12.328044 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 45838000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.997330 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 511.997396 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999995 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 11986605 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11986605 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8034775 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8034775 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 20021380 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20021380 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20021380 # number of overall hits -system.cpu.dcache.overall_hits::total 20021380 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1309816 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1309816 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 315519 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 315519 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1625335 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1625335 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1625335 # number of overall misses -system.cpu.dcache.overall_misses::total 1625335 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 19889195500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 19889195500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9348149500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9348149500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 29237345000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 29237345000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 29237345000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 29237345000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13296421 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13296421 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8350294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8350294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21646715 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21646715 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21646715 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21646715 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098509 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.098509 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037785 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037785 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.075085 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.075085 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.075085 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.075085 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15184.724801 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15184.724801 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29627.849670 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 29627.849670 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 17988.503908 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 17988.503908 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 17988.503908 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 17988.503908 # average overall miss latency +system.cpu.dcache.ReadReq_hits::cpu.data 11972131 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11972131 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8029723 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8029723 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 20001854 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20001854 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20001854 # number of overall hits +system.cpu.dcache.overall_hits::total 20001854 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1309489 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1309489 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 315369 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 315369 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1624858 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1624858 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1624858 # number of overall misses +system.cpu.dcache.overall_misses::total 1624858 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 19885711500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 19885711500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9346101000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9346101000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 29231812500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 29231812500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 29231812500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 29231812500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13281620 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13281620 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8345092 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8345092 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21626712 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21626712 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21626712 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21626712 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098594 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.098594 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037791 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037791 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.075132 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.075132 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.075132 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.075132 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15185.856086 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15185.856086 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29635.446096 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 29635.446096 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 17990.379775 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 17990.379775 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 17990.379775 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 17990.379775 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -685,46 +685,46 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1540096 # number of writebacks -system.cpu.dcache.writebacks::total 1540096 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1309816 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1309816 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315519 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 315519 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1625335 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1625335 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1625335 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1625335 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15959698500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 15959698500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8401590001 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8401590001 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24361288501 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 24361288501 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24361288501 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 24361288501 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 1539490 # number of writebacks +system.cpu.dcache.writebacks::total 1539490 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1309489 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1309489 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315369 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 315369 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1624858 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1624858 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1624858 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1624858 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15957199501 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 15957199501 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8399992000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8399992000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24357191501 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 24357191501 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24357191501 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 24357191501 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 93628676500 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 93628676500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2467826500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2467826500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96096503000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 96096503000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098509 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098509 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037785 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037785 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.075085 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.075085 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.075085 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.075085 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12184.687391 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12184.687391 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26627.841750 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26627.841750 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14988.472223 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 14988.472223 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14988.472223 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 14988.472223 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2467841500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2467841500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96096518000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 96096518000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098594 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098594 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037791 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037791 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.075132 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.075132 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.075132 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.075132 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12185.821722 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12185.821722 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26635.439755 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26635.439755 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14990.350850 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 14990.350850 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14990.350850 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 14990.350850 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency |