diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-09-10 11:57:37 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-09-10 11:57:37 -0400 |
| commit | d6283445744d5be2a9ac33f0adbc729d48e22c40 (patch) | |
| tree | 67910602fd144f50fa86b1c8a90e0e4f0e66ee90 /tests/quick/fs/10.linux-boot/ref | |
| parent | cf5935445f23d0ba2f41debc50952fe45d7c9f4a (diff) | |
| download | gem5-d6283445744d5be2a9ac33f0adbc729d48e22c40.tar.xz | |
Device: Update stats for PIO and PCI latency change
This patch merely updates the regression stats to reflect the change
in PIO and PCI latency.
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref')
5 files changed, 3340 insertions, 3310 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index 19b49bfc4..de241166d 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,218 +1,218 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.954210 # Number of seconds simulated -sim_ticks 1954209529000 # Number of ticks simulated -final_tick 1954209529000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.962054 # Number of seconds simulated +sim_ticks 1962054431000 # Number of ticks simulated +final_tick 1962054431000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1320479 # Simulator instruction rate (inst/s) -host_op_rate 1320478 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 43430338961 # Simulator tick rate (ticks/s) -host_mem_usage 301360 # Number of bytes of host memory used -host_seconds 45.00 # Real time elapsed on the host -sim_insts 59416773 # Number of instructions simulated -sim_ops 59416773 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 717056 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 23797184 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2649344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 145856 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1424768 # Number of bytes read from this memory -system.physmem.bytes_read::total 28734208 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 717056 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 145856 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 862912 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7745216 # Number of bytes written to this memory -system.physmem.bytes_written::total 7745216 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 11204 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 371831 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41396 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2279 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 22262 # Number of read requests responded to by this memory -system.physmem.num_reads::total 448972 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 121019 # Number of write requests responded to by this memory -system.physmem.num_writes::total 121019 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 366929 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12177396 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1355711 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 74637 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 729076 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14703750 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 366929 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 74637 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 441566 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3963350 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3963350 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3963350 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 366929 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12177396 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1355711 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 74637 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 729076 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18667100 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 342059 # number of replacements -system.l2c.tagsinuse 65268.160318 # Cycle average of tags in use -system.l2c.total_refs 2559182 # Total number of references to valid blocks. -system.l2c.sampled_refs 407064 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.286928 # Average number of references to valid blocks. -system.l2c.warmup_cycle 7752825000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 55637.634903 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 3742.497316 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 4175.530834 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 1176.828105 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 535.669160 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.848963 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.057106 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.063714 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.017957 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.008174 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.995913 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 478624 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 342590 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 511938 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 491329 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1824481 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 858650 # number of Writeback hits -system.l2c.Writeback_hits::total 858650 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 133 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 95 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 228 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 22 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 24 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 46 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 101497 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 99318 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 200815 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 478624 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 444087 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 511938 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 590647 # number of demand (read+write) hits -system.l2c.demand_hits::total 2025296 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 478624 # number of overall hits -system.l2c.overall_hits::cpu0.data 444087 # number of overall hits -system.l2c.overall_hits::cpu1.inst 511938 # number of overall hits -system.l2c.overall_hits::cpu1.data 590647 # number of overall hits -system.l2c.overall_hits::total 2025296 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 11204 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 270589 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 2290 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1211 # number of ReadReq misses -system.l2c.ReadReq_misses::total 285294 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2582 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 476 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3058 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 85 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 88 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 173 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 101602 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 21093 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 122695 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 11204 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 372191 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 2290 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 22304 # number of demand (read+write) misses -system.l2c.demand_misses::total 407989 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 11204 # number of overall misses -system.l2c.overall_misses::cpu0.data 372191 # number of overall misses -system.l2c.overall_misses::cpu1.inst 2290 # number of overall misses -system.l2c.overall_misses::cpu1.data 22304 # number of overall misses -system.l2c.overall_misses::total 407989 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 582910000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 14075669000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 119002000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 63420000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 14841001000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 1144000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 1924000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 3068000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 695000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 156000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 851000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 5283582000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 1096874000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6380456000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 582910000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 19359251000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 119002000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 1160294000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 21221457000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 582910000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 19359251000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 119002000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 1160294000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 21221457000 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 489828 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 613179 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 514228 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 492540 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2109775 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 858650 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 858650 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 2715 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 571 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 3286 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 107 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 112 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 219 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 203099 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 120411 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 323510 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 489828 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 816278 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 514228 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 612951 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2433285 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 489828 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 816278 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 514228 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 612951 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2433285 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.022873 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.441289 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.004453 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.002459 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.135225 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.951013 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.833625 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.930615 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.794393 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.785714 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.789954 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.500258 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.175175 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.379262 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.022873 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.455961 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.004453 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.036388 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.167670 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.022873 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.455961 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.004453 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.036388 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.167670 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52026.954659 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 52018.629730 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51965.938865 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 52369.942197 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52020.024957 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 443.067390 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4042.016807 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 1003.270111 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 8176.470588 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1772.727273 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 4919.075145 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52002.736167 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52001.801546 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52002.575492 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 52026.954659 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 52014.291049 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 51965.938865 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 52021.789813 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52014.777359 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 52026.954659 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 52014.291049 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 51965.938865 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 52021.789813 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52014.777359 # average overall miss latency +host_inst_rate 2014980 # Simulator instruction rate (inst/s) +host_op_rate 2014979 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 66592137800 # Simulator tick rate (ticks/s) +host_mem_usage 297124 # Number of bytes of host memory used +host_seconds 29.46 # Real time elapsed on the host +sim_insts 59368818 # Number of instructions simulated +sim_ops 59368818 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 834816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24594240 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 29056 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 572928 # Number of bytes read from this memory +system.physmem.bytes_read::total 28681856 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 834816 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 29056 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 863872 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7716416 # Number of bytes written to this memory +system.physmem.bytes_written::total 7716416 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13044 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 384285 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41419 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 454 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 8952 # Number of read requests responded to by this memory +system.physmem.num_reads::total 448154 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 120569 # Number of write requests responded to by this memory +system.physmem.num_writes::total 120569 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 425481 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12534943 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1351041 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 14809 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 292004 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14618277 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 425481 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 14809 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 440290 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3932825 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3932825 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3932825 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 425481 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12534943 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1351041 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 14809 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 292004 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18551102 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 341254 # number of replacements +system.l2c.tagsinuse 65290.172220 # Cycle average of tags in use +system.l2c.total_refs 2492312 # Total number of references to valid blocks. +system.l2c.sampled_refs 406269 # Sample count of references to valid blocks. +system.l2c.avg_refs 6.134635 # Average number of references to valid blocks. +system.l2c.warmup_cycle 7854344000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 55481.040218 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4824.761707 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 4855.330442 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 116.015324 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 13.024529 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.846573 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.073620 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.074086 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.001770 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.000199 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.996249 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 902302 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 773944 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 86739 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 31910 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1794895 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 820354 # number of Writeback hits +system.l2c.Writeback_hits::total 820354 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 162 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 57 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 219 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 23 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 21 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 44 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 172408 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 12341 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 184749 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 902302 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 946352 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 86739 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 44251 # number of demand (read+write) hits +system.l2c.demand_hits::total 1979644 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 902302 # number of overall hits +system.l2c.overall_hits::cpu0.data 946352 # number of overall hits +system.l2c.overall_hits::cpu1.inst 86739 # number of overall hits +system.l2c.overall_hits::cpu1.data 44251 # number of overall hits +system.l2c.overall_hits::total 1979644 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 13044 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 271462 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 465 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 325 # number of ReadReq misses +system.l2c.ReadReq_misses::total 285296 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 2436 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 489 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2925 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 35 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 73 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 108 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 113191 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 8669 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 121860 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.inst 13044 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 384653 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 465 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 8994 # number of demand (read+write) misses +system.l2c.demand_misses::total 407156 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 13044 # number of overall misses +system.l2c.overall_misses::cpu0.data 384653 # number of overall misses +system.l2c.overall_misses::cpu1.inst 465 # number of overall misses +system.l2c.overall_misses::cpu1.data 8994 # number of overall misses +system.l2c.overall_misses::total 407156 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.inst 678900500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 14120860000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 24120000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 17316000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 14841196500 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 1412000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 1560000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 2972000 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 156000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 208000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 364000 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 5886266000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 450808000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 6337074000 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 678900500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 20007126000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 24120000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 468124000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 21178270500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 678900500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 20007126000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 24120000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 468124000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 21178270500 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.inst 915346 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 1045406 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 87204 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 32235 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2080191 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 820354 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 820354 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 2598 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 546 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 3144 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 58 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 94 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 152 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 285599 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 21010 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 306609 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 915346 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1331005 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 87204 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 53245 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2386800 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 915346 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1331005 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 87204 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 53245 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2386800 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.014250 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.259671 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.005332 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.010082 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.137149 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.937644 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.895604 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.930344 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.603448 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.776596 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.710526 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.396328 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.412613 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.397444 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.014250 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.288994 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.005332 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.168917 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.170587 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.014250 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.288994 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.005332 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.168917 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.170587 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52046.956455 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 52017.814648 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51870.967742 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 53280 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52020.345536 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 579.638752 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3190.184049 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 1016.068376 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 4457.142857 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2849.315068 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 3370.370370 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52002.950765 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52002.307071 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52002.904973 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 52046.956455 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 52013.440686 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 51870.967742 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 52048.476762 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52015.125652 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 52046.956455 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 52013.440686 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 51870.967742 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 52048.476762 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52015.125652 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -221,119 +221,119 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 79488 # number of writebacks -system.l2c.writebacks::total 79488 # number of writebacks +system.l2c.writebacks::writebacks 79049 # number of writebacks +system.l2c.writebacks::total 79049 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu1.inst 11 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu1.inst 11 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu1.inst 11 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.inst 11204 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 270589 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 2279 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 1211 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 285283 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 2582 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 476 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 3058 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 85 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 88 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 173 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 101602 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 21093 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 122695 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 11204 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 372191 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 2279 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 22304 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 407978 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 11204 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 372191 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 2279 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 22304 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 407978 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 448459000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 10828601000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 91164000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 48888000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 11417112000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 103374000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 19058000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 122432000 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 3419000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 3520000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 6939000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4064358000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 843758000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 4908116000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 448459000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 14892959000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 91164000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 892646000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 16325228000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 448459000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 14892959000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 91164000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 892646000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 16325228000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 538312030 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 264188000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 802500030 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 914384000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 465175000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1379559000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 1452696030 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 729363000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 2182059030 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.022873 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.441289 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.004432 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.002459 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.135220 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.951013 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.833625 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.930615 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.794393 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.785714 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.789954 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.500258 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.175175 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.379262 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.022873 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.455961 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.004432 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.036388 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.167666 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.022873 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.455961 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.004432 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.036388 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.167666 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40026.686898 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40018.629730 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40001.755156 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40369.942197 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40020.302647 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40036.405887 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40037.815126 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40036.625245 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40223.529412 # average SCUpgradeReq mshr miss latency +system.l2c.ReadReq_mshr_misses::cpu0.inst 13044 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 271462 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 454 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 325 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 285285 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 2436 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 489 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 2925 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 35 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 73 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 108 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 113191 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 8669 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 121860 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 13044 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 384653 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 454 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 8994 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 407145 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 13044 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 384653 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 454 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 8994 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 407145 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 522369000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 10863316000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 18183000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 13416000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 11417284000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 97500000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 19560000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 117060000 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 1400000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 2920000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 4320000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4527974000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 346780000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 4874754000 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 522369000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 15391290000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 18183000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 360196000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 16292038000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 522369000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 15391290000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 18183000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 360196000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 16292038000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1370658000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 19250000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1389908000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1967340000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 505194000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2472534000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3337998000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 524444000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 3862442000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014250 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.259671 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.005206 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.010082 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.137144 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.937644 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.895604 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.930344 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.603448 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.776596 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.710526 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.396328 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.412613 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.397444 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014250 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.288994 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005206 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.168917 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.170582 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014250 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.288994 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005206 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.168917 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.170582 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40046.688132 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40017.814648 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40050.660793 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 41280 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40020.624989 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40024.630542 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40020.512821 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40109.826590 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40002.736167 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40001.801546 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40002.575492 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40026.686898 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40014.291049 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40001.755156 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40021.789813 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40014.971396 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40026.686898 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40014.291049 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40001.755156 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40021.789813 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40014.971396 # average overall mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40002.950765 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40002.307071 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40002.904973 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40046.688132 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40013.440686 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40050.660793 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40048.476762 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40015.321323 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40046.688132 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40013.440686 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40050.660793 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40048.476762 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40015.321323 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -344,39 +344,39 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 41707 # number of replacements -system.iocache.tagsinuse 1.261563 # Cycle average of tags in use +system.iocache.replacements 41698 # number of replacements +system.iocache.tagsinuse 0.566768 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 41723 # Sample count of references to valid blocks. +system.iocache.sampled_refs 41714 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1747651126000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.261563 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.078848 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.078848 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::tsunami.ide 176 # number of ReadReq misses -system.iocache.ReadReq_misses::total 176 # number of ReadReq misses +system.iocache.warmup_cycle 1754521474000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 0.566768 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.035423 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.035423 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::tsunami.ide 178 # number of ReadReq misses +system.iocache.ReadReq_misses::total 178 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.demand_misses::tsunami.ide 41728 # number of demand (read+write) misses -system.iocache.demand_misses::total 41728 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41728 # number of overall misses -system.iocache.overall_misses::total 41728 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21013998 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21013998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 7626285806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 7626285806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 7647299804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 7647299804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 7647299804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 7647299804 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 41730 # number of demand (read+write) misses +system.iocache.demand_misses::total 41730 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 41730 # number of overall misses +system.iocache.overall_misses::total 41730 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 21239998 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21239998 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 7628774806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 7628774806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 7650014804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 7650014804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 7650014804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 7650014804 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 178 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 178 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41728 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41728 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41728 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41728 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41730 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41730 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41730 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41730 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses @@ -385,40 +385,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119397.715909 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 119397.715909 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183535.950279 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 183535.950279 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 183265.428585 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 183265.428585 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 183265.428585 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 183265.428585 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 7316000 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119325.831461 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 119325.831461 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183595.851126 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 183595.851126 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 183321.706302 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 183321.706302 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 183321.706302 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 183321.706302 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 7551000 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7050 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7072 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 1037.730496 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 1067.731900 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 41531 # number of writebacks -system.iocache.writebacks::total 41531 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses +system.iocache.writebacks::writebacks 41520 # number of writebacks +system.iocache.writebacks::total 41520 # number of writebacks +system.iocache.ReadReq_mshr_misses::tsunami.ide 178 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 178 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41728 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41728 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41728 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41728 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11861000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 11861000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 5465428000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 5465428000 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 5477289000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 5477289000 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 5477289000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 5477289000 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 41730 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41730 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41730 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41730 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11983000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 11983000 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 5467915000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 5467915000 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 5479898000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 5479898000 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 5479898000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 5479898000 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -427,14 +427,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67392.045455 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 67392.045455 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131532.248749 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 131532.248749 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131261.718750 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 131261.718750 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131261.718750 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 131261.718750 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67320.224719 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 67320.224719 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131592.101463 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 131592.101463 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131317.948718 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 131317.948718 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131317.948718 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 131317.948718 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -452,22 +452,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 5733461 # DTB read hits +system.cpu0.dtb.read_hits 8658373 # DTB read hits system.cpu0.dtb.read_misses 7687 # DTB read misses system.cpu0.dtb.read_acv 174 # DTB read access violations system.cpu0.dtb.read_accesses 524201 # DTB read accesses -system.cpu0.dtb.write_hits 3961949 # DTB write hits +system.cpu0.dtb.write_hits 6036768 # DTB write hits system.cpu0.dtb.write_misses 798 # DTB write misses system.cpu0.dtb.write_acv 115 # DTB write access violations system.cpu0.dtb.write_accesses 195659 # DTB write accesses -system.cpu0.dtb.data_hits 9695410 # DTB hits +system.cpu0.dtb.data_hits 14695141 # DTB hits system.cpu0.dtb.data_misses 8485 # DTB misses system.cpu0.dtb.data_acv 289 # DTB access violations system.cpu0.dtb.data_accesses 719860 # DTB accesses -system.cpu0.itb.fetch_hits 3214179 # ITB hits +system.cpu0.itb.fetch_hits 3948342 # ITB hits system.cpu0.itb.fetch_misses 3841 # ITB misses system.cpu0.itb.fetch_acv 143 # ITB acv -system.cpu0.itb.fetch_accesses 3218020 # ITB accesses +system.cpu0.itb.fetch_accesses 3952183 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -480,55 +480,55 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3908419058 # number of cpu cycles simulated +system.cpu0.numCycles 3924108862 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 36160769 # Number of instructions committed -system.cpu0.committedOps 36160769 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 33648309 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 143029 # Number of float alu accesses -system.cpu0.num_func_calls 874750 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4239273 # number of instructions that are conditional controls -system.cpu0.num_int_insts 33648309 # number of integer instructions -system.cpu0.num_fp_insts 143029 # number of float instructions -system.cpu0.num_int_register_reads 46246517 # number of times the integer registers were read -system.cpu0.num_int_register_writes 25142738 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 70823 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 71471 # number of times the floating registers were written -system.cpu0.num_mem_refs 9725994 # number of memory refs -system.cpu0.num_load_insts 5755174 # Number of load instructions -system.cpu0.num_store_insts 3970820 # Number of store instructions -system.cpu0.num_idle_cycles 3741414636.998085 # Number of idle cycles -system.cpu0.num_busy_cycles 167004421.001915 # Number of busy cycles -system.cpu0.not_idle_fraction 0.042729 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.957271 # Percentage of idle cycles +system.cpu0.committedInsts 54115388 # Number of instructions committed +system.cpu0.committedOps 54115388 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 50086021 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 302769 # Number of float alu accesses +system.cpu0.num_func_calls 1426994 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 6243543 # number of instructions that are conditional controls +system.cpu0.num_int_insts 50086021 # number of integer instructions +system.cpu0.num_fp_insts 302769 # number of float instructions +system.cpu0.num_int_register_reads 68608752 # number of times the integer registers were read +system.cpu0.num_int_register_writes 37121526 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 149232 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 152287 # number of times the floating registers were written +system.cpu0.num_mem_refs 14741011 # number of memory refs +system.cpu0.num_load_insts 8689642 # Number of load instructions +system.cpu0.num_store_insts 6051369 # Number of store instructions +system.cpu0.num_idle_cycles 3676810844.998126 # Number of idle cycles +system.cpu0.num_busy_cycles 247298017.001874 # Number of busy cycles +system.cpu0.not_idle_fraction 0.063020 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.936980 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 4839 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 129053 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 41012 38.31% 38.31% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.12% 38.43% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1971 1.84% 40.27% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 17 0.02% 40.29% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 63919 59.71% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 107050 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 40581 48.74% 48.74% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.16% 48.90% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1971 2.37% 51.26% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 17 0.02% 51.28% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 40564 48.72% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 83264 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1905788612000 97.52% 97.52% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 88224500 0.00% 97.53% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 590412500 0.03% 97.56% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 12827000 0.00% 97.56% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 47728597000 2.44% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1954208673000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.989491 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6365 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 202758 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 72603 40.61% 40.61% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 134 0.07% 40.69% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1979 1.11% 41.79% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 6 0.00% 41.80% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 104051 58.20% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 178773 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 71234 49.27% 49.27% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 134 0.09% 49.36% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1979 1.37% 50.73% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 6 0.00% 50.73% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 71230 49.27% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 144583 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1900684456500 96.87% 96.87% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 103099000 0.01% 96.88% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 795217500 0.04% 96.92% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 5572000 0.00% 96.92% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 60465248000 3.08% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1962053593000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.981144 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.634616 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.777805 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.684568 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.808752 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 6 2.68% 2.68% # number of syscalls executed system.cpu0.kern.syscall::3 19 8.48% 11.16% # number of syscalls executed system.cpu0.kern.syscall::4 3 1.34% 12.50% # number of syscalls executed @@ -561,37 +561,37 @@ system.cpu0.kern.syscall::144 1 0.45% 99.11% # nu system.cpu0.kern.syscall::147 2 0.89% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 224 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 91 0.08% 0.08% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.08% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.08% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.08% # number of callpals executed -system.cpu0.kern.callpal::swpctx 1959 1.72% 1.80% # number of callpals executed -system.cpu0.kern.callpal::tbi 44 0.04% 1.84% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.01% 1.84% # number of callpals executed -system.cpu0.kern.callpal::swpipl 101152 88.59% 90.44% # number of callpals executed -system.cpu0.kern.callpal::rdps 6620 5.80% 96.24% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.24% # number of callpals executed -system.cpu0.kern.callpal::wrusp 4 0.00% 96.24% # number of callpals executed -system.cpu0.kern.callpal::rdusp 7 0.01% 96.25% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.25% # number of callpals executed -system.cpu0.kern.callpal::rti 3778 3.31% 99.56% # number of callpals executed -system.cpu0.kern.callpal::callsys 356 0.31% 99.87% # number of callpals executed -system.cpu0.kern.callpal::imb 149 0.13% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 114174 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 5323 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1231 # number of protection mode switches +system.cpu0.kern.callpal::wripir 91 0.05% 0.05% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.05% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.05% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.05% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3870 2.06% 2.11% # number of callpals executed +system.cpu0.kern.callpal::tbi 44 0.02% 2.13% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.14% # number of callpals executed +system.cpu0.kern.callpal::swpipl 171949 91.52% 93.66% # number of callpals executed +system.cpu0.kern.callpal::rdps 6691 3.56% 97.22% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 97.22% # number of callpals executed +system.cpu0.kern.callpal::wrusp 4 0.00% 97.22% # number of callpals executed +system.cpu0.kern.callpal::rdusp 7 0.00% 97.23% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 97.23% # number of callpals executed +system.cpu0.kern.callpal::rti 4706 2.50% 99.73% # number of callpals executed +system.cpu0.kern.callpal::callsys 356 0.19% 99.92% # number of callpals executed +system.cpu0.kern.callpal::imb 149 0.08% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 187881 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7232 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1230 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1230 -system.cpu0.kern.mode_good::user 1231 +system.cpu0.kern.mode_good::kernel 1229 +system.cpu0.kern.mode_good::user 1230 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.231073 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.169939 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.375496 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1950522760000 99.81% 99.81% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3685906000 0.19% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.290593 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1958392751000 99.81% 99.81% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3660835000 0.19% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 1960 # number of times the context was actually changed +system.cpu0.kern.swap_context 3871 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -623,51 +623,51 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 489206 # number of replacements -system.cpu0.icache.tagsinuse 508.795620 # Cycle average of tags in use -system.cpu0.icache.total_refs 35679696 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 489718 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 72.857636 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 36113258000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 508.795620 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.993741 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.993741 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 35679696 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 35679696 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 35679696 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 35679696 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 35679696 # number of overall hits -system.cpu0.icache.overall_hits::total 35679696 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 489848 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 489848 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 489848 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 489848 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 489848 # number of overall misses -system.cpu0.icache.overall_misses::total 489848 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7462315000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 7462315000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 7462315000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 7462315000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 7462315000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 7462315000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 36169544 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 36169544 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 36169544 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 36169544 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 36169544 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 36169544 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013543 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.013543 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013543 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.013543 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013543 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.013543 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15233.939916 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 15233.939916 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15233.939916 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 15233.939916 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15233.939916 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 15233.939916 # average overall miss latency +system.cpu0.icache.replacements 914730 # number of replacements +system.cpu0.icache.tagsinuse 508.781983 # Cycle average of tags in use +system.cpu0.icache.total_refs 53208794 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 915241 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 58.136375 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 36528993000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 508.781983 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.993715 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.993715 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 53208794 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 53208794 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 53208794 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 53208794 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 53208794 # number of overall hits +system.cpu0.icache.overall_hits::total 53208794 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 915369 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 915369 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 915369 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 915369 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 915369 # number of overall misses +system.cpu0.icache.overall_misses::total 915369 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13645389000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 13645389000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 13645389000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 13645389000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 13645389000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 13645389000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 54124163 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 54124163 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 54124163 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 54124163 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 54124163 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 54124163 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016912 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.016912 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016912 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.016912 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016912 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.016912 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14906.981775 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14906.981775 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14906.981775 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14906.981775 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14906.981775 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14906.981775 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -676,112 +676,112 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 489848 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 489848 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 489848 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 489848 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 489848 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 489848 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5992109500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 5992109500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5992109500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 5992109500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5992109500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 5992109500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013543 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013543 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013543 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.013543 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013543 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.013543 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12232.589497 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12232.589497 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12232.589497 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12232.589497 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12232.589497 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12232.589497 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 915369 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 915369 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 915369 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 915369 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 915369 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 915369 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10898588000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 10898588000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10898588000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 10898588000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10898588000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 10898588000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.016912 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.016912 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.016912 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.016912 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.016912 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.016912 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11906.223610 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11906.223610 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11906.223610 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11906.223610 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11906.223610 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11906.223610 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 817819 # number of replacements -system.cpu0.dcache.tagsinuse 479.881496 # Cycle average of tags in use -system.cpu0.dcache.total_refs 8879648 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 818331 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 10.850925 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 85697000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 479.881496 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.937269 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.937269 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 5008276 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5008276 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3627744 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3627744 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 117045 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 117045 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 122538 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 122538 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 8636020 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 8636020 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 8636020 # number of overall hits -system.cpu0.dcache.overall_hits::total 8636020 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 610602 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 610602 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 207036 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 207036 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6562 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 6562 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 580 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 580 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 817638 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 817638 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 817638 # number of overall misses -system.cpu0.dcache.overall_misses::total 817638 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 19940652000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 19940652000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7284412000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 7284412000 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 92857000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 92857000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 8303000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 8303000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 27225064000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 27225064000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 27225064000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 27225064000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 5618878 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 5618878 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 3834780 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 3834780 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 123607 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 123607 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 123118 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 123118 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 9453658 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 9453658 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 9453658 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 9453658 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.108670 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.108670 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.053989 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.053989 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.053088 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.053088 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.004711 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.004711 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.086489 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.086489 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.086489 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.086489 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 32657.364372 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 32657.364372 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35184.277131 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 35184.277131 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14150.716245 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14150.716245 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 14315.517241 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14315.517241 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33297.209768 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33297.209768 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33297.209768 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33297.209768 # average overall miss latency +system.cpu0.dcache.replacements 1337806 # number of replacements +system.cpu0.dcache.tagsinuse 506.531092 # Cycle average of tags in use +system.cpu0.dcache.total_refs 13370025 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1338318 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 9.990170 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 101834000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 506.531092 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.989319 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.989319 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 7444474 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7444474 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5554839 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5554839 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 175825 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 175825 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 191178 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 191178 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 12999313 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12999313 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 12999313 # number of overall hits +system.cpu0.dcache.overall_hits::total 12999313 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1037616 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1037616 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 289306 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 289306 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16762 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 16762 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 448 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 448 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1326922 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1326922 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1326922 # number of overall misses +system.cpu0.dcache.overall_misses::total 1326922 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 26113316000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 26113316000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 8963970000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 8963970000 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 238512000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 238512000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4951000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4951000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 35077286000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 35077286000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 35077286000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 35077286000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8482090 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8482090 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5844145 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5844145 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 192587 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 192587 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 191626 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 191626 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 14326235 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 14326235 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 14326235 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 14326235 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.122330 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.122330 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049504 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.049504 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.087036 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.087036 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.002338 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.002338 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.092622 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.092622 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.092622 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.092622 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25166.647392 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 25166.647392 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30984.390230 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 30984.390230 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14229.328242 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14229.328242 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 11051.339286 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 11051.339286 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26435.077570 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 26435.077570 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26435.077570 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 26435.077570 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -790,62 +790,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 359687 # number of writebacks -system.cpu0.dcache.writebacks::total 359687 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 610602 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 610602 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 207036 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 207036 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6562 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6562 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 580 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 580 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 817638 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 817638 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 817638 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 817638 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 18108780524 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 18108780524 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6663302002 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6663302002 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 73171000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 73171000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 6563000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 6563000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 24772082526 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 24772082526 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 24772082526 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 24772082526 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 601210500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 601210500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1014423500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1014423500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1615634000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1615634000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.108670 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.108670 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.053989 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.053989 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.053088 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.053088 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.004711 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.004711 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.086489 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.086489 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.086489 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.086489 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29657.257140 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29657.257140 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32184.267480 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32184.267480 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11150.716245 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11150.716245 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11315.517241 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11315.517241 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30297.127245 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30297.127245 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30297.127245 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30297.127245 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 785164 # number of writebacks +system.cpu0.dcache.writebacks::total 785164 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1037616 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 1037616 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 289306 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 289306 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16762 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16762 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 448 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 448 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1326922 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1326922 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1326922 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1326922 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 23000405022 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 23000405022 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8096051001 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8096051001 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 188226000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 188226000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3606001 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3606001 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 31096456023 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 31096456023 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 31096456023 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 31096456023 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1463096000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1463096000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2089087000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2089087000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3552183000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3552183000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122330 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.122330 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049504 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049504 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.087036 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.087036 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.002338 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.002338 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092622 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.092622 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092622 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.092622 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 22166.586697 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 22166.586697 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27984.386777 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27984.386777 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11229.328242 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11229.328242 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 8049.109375 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 8049.109375 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23435.029356 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23435.029356 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23435.029356 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23435.029356 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -857,22 +857,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 3958078 # DTB read hits +system.cpu1.dtb.read_hits 1027490 # DTB read hits system.cpu1.dtb.read_misses 2750 # DTB read misses system.cpu1.dtb.read_acv 36 # DTB read access violations system.cpu1.dtb.read_accesses 205838 # DTB read accesses -system.cpu1.dtb.write_hits 2742847 # DTB write hits +system.cpu1.dtb.write_hits 663174 # DTB write hits system.cpu1.dtb.write_misses 356 # DTB write misses system.cpu1.dtb.write_acv 48 # DTB write access violations system.cpu1.dtb.write_accesses 97040 # DTB write accesses -system.cpu1.dtb.data_hits 6700925 # DTB hits +system.cpu1.dtb.data_hits 1690664 # DTB hits system.cpu1.dtb.data_misses 3106 # DTB misses system.cpu1.dtb.data_acv 84 # DTB access violations system.cpu1.dtb.data_accesses 302878 # DTB accesses -system.cpu1.itb.fetch_hits 2128502 # ITB hits +system.cpu1.itb.fetch_hits 1394882 # ITB hits system.cpu1.itb.fetch_misses 1246 # ITB misses system.cpu1.itb.fetch_acv 41 # ITB acv -system.cpu1.itb.fetch_accesses 2129748 # ITB accesses +system.cpu1.itb.fetch_accesses 1396128 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -885,51 +885,51 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3908222400 # number of cpu cycles simulated +system.cpu1.numCycles 3923836450 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 23256004 # Number of instructions committed -system.cpu1.committedOps 23256004 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 21401422 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 186242 # Number of float alu accesses -system.cpu1.num_func_calls 709842 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 2519926 # number of instructions that are conditional controls -system.cpu1.num_int_insts 21401422 # number of integer instructions -system.cpu1.num_fp_insts 186242 # number of float instructions -system.cpu1.num_int_register_reads 29248159 # number of times the integer registers were read -system.cpu1.num_int_register_writes 15707401 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 95219 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 97489 # number of times the floating registers were written -system.cpu1.num_mem_refs 6725970 # number of memory refs -system.cpu1.num_load_insts 3973767 # Number of load instructions -system.cpu1.num_store_insts 2752203 # Number of store instructions -system.cpu1.num_idle_cycles 3808683702.691761 # Number of idle cycles -system.cpu1.num_busy_cycles 99538697.308239 # Number of busy cycles -system.cpu1.not_idle_fraction 0.025469 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.974531 # Percentage of idle cycles +system.cpu1.committedInsts 5253430 # Number of instructions committed +system.cpu1.committedOps 5253430 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 4920456 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 25430 # Number of float alu accesses +system.cpu1.num_func_calls 157592 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 506756 # number of instructions that are conditional controls +system.cpu1.num_int_insts 4920456 # number of integer instructions +system.cpu1.num_fp_insts 25430 # number of float instructions +system.cpu1.num_int_register_reads 6826440 # number of times the integer registers were read +system.cpu1.num_int_register_writes 3699681 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 16282 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 16129 # number of times the floating registers were written +system.cpu1.num_mem_refs 1700289 # number of memory refs +system.cpu1.num_load_insts 1033544 # Number of load instructions +system.cpu1.num_store_insts 666745 # Number of store instructions +system.cpu1.num_idle_cycles 3903109824.944130 # Number of idle cycles +system.cpu1.num_busy_cycles 20726625.055870 # Number of busy cycles +system.cpu1.not_idle_fraction 0.005282 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.994718 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 3849 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 109556 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 40729 40.60% 40.60% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1966 1.96% 42.56% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 91 0.09% 42.65% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 57540 57.35% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 100326 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 39783 48.79% 48.79% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1966 2.41% 51.21% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 91 0.11% 51.32% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 39692 48.68% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 81532 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1901560916500 97.31% 97.31% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 537337500 0.03% 97.34% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 59036000 0.00% 97.34% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 51953880000 2.66% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1954111170000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.976773 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2331 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 35943 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 9143 31.85% 31.85% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1973 6.87% 38.72% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 91 0.32% 39.04% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 17500 60.96% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 28707 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 9135 45.13% 45.13% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1973 9.75% 54.87% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 91 0.45% 55.32% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 9044 44.68% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 20243 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1920768070500 97.90% 97.90% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 725778000 0.04% 97.94% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 67189500 0.00% 97.94% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 40357157000 2.06% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1961918195000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.999125 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.689816 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.812671 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.516800 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.705159 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::2 2 1.96% 1.96% # number of syscalls executed system.cpu1.kern.syscall::3 11 10.78% 12.75% # number of syscalls executed system.cpu1.kern.syscall::4 1 0.98% 13.73% # number of syscalls executed @@ -953,82 +953,82 @@ system.cpu1.kern.syscall::132 2 1.96% 99.02% # nu system.cpu1.kern.syscall::144 1 0.98% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 102 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 17 0.02% 0.02% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.02% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.02% # number of callpals executed -system.cpu1.kern.callpal::swpctx 2292 2.22% 2.24% # number of callpals executed -system.cpu1.kern.callpal::tbi 10 0.01% 2.25% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 2.26% # number of callpals executed -system.cpu1.kern.callpal::swpipl 94758 91.98% 94.24% # number of callpals executed -system.cpu1.kern.callpal::rdps 2221 2.16% 96.40% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 96.40% # number of callpals executed -system.cpu1.kern.callpal::wrusp 3 0.00% 96.40% # number of callpals executed -system.cpu1.kern.callpal::rdusp 2 0.00% 96.40% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 96.41% # number of callpals executed -system.cpu1.kern.callpal::rti 3510 3.41% 99.81% # number of callpals executed -system.cpu1.kern.callpal::callsys 161 0.16% 99.97% # number of callpals executed -system.cpu1.kern.callpal::imb 31 0.03% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 6 0.02% 0.02% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal::swpctx 365 1.24% 1.27% # number of callpals executed +system.cpu1.kern.callpal::tbi 10 0.03% 1.31% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.02% 1.33% # number of callpals executed +system.cpu1.kern.callpal::swpipl 24055 81.82% 83.15% # number of callpals executed +system.cpu1.kern.callpal::rdps 2165 7.36% 90.51% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 90.52% # number of callpals executed +system.cpu1.kern.callpal::wrusp 3 0.01% 90.53% # number of callpals executed +system.cpu1.kern.callpal::rdusp 2 0.01% 90.53% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 90.54% # number of callpals executed +system.cpu1.kern.callpal::rti 2587 8.80% 99.34% # number of callpals executed +system.cpu1.kern.callpal::callsys 161 0.55% 99.89% # number of callpals executed +system.cpu1.kern.callpal::imb 31 0.11% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 103020 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 2836 # number of protection mode switches -system.cpu1.kern.mode_switch::user 515 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2038 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 568 -system.cpu1.kern.mode_good::user 515 -system.cpu1.kern.mode_good::idle 53 -system.cpu1.kern.mode_switch_good::kernel 0.200282 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 29400 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 879 # number of protection mode switches +system.cpu1.kern.mode_switch::user 516 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2075 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 532 +system.cpu1.kern.mode_good::user 516 +system.cpu1.kern.mode_good::idle 16 +system.cpu1.kern.mode_switch_good::kernel 0.605233 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.026006 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.210800 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 72317077000 3.70% 3.70% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1608073000 0.08% 3.78% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1879348652000 96.22% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 2293 # number of times the context was actually changed -system.cpu1.icache.replacements 513692 # number of replacements -system.cpu1.icache.tagsinuse 501.294138 # Cycle average of tags in use -system.cpu1.icache.total_refs 22744965 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 514204 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 44.233349 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 96225204000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 501.294138 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.979090 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.979090 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 22744965 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 22744965 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 22744965 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 22744965 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 22744965 # number of overall hits -system.cpu1.icache.overall_hits::total 22744965 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 514229 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 514229 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 514229 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 514229 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 514229 # number of overall misses -system.cpu1.icache.overall_misses::total 514229 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7551928500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 7551928500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 7551928500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 7551928500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 7551928500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 7551928500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 23259194 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 23259194 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 23259194 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 23259194 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 23259194 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 23259194 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.022109 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.022109 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.022109 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.022109 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.022109 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.022109 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14685.924948 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 14685.924948 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14685.924948 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 14685.924948 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14685.924948 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 14685.924948 # average overall miss latency +system.cpu1.kern.mode_switch_good::idle 0.007711 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.306628 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 4074736000 0.21% 0.21% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1594048000 0.08% 0.29% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1955463610000 99.71% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 366 # number of times the context was actually changed +system.cpu1.icache.replacements 86665 # number of replacements +system.cpu1.icache.tagsinuse 419.761966 # Cycle average of tags in use +system.cpu1.icache.total_refs 5169415 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 87177 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 59.297923 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1958459766000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 419.761966 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.819848 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.819848 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 5169415 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 5169415 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 5169415 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 5169415 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 5169415 # number of overall hits +system.cpu1.icache.overall_hits::total 5169415 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 87205 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 87205 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 87205 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 87205 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 87205 # number of overall misses +system.cpu1.icache.overall_misses::total 87205 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1314538500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 1314538500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 1314538500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 1314538500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 1314538500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 1314538500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 5256620 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 5256620 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 5256620 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 5256620 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 5256620 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 5256620 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.016590 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.016590 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.016590 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.016590 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.016590 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.016590 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15074.118457 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 15074.118457 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15074.118457 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 15074.118457 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15074.118457 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 15074.118457 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1037,112 +1037,112 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 514229 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 514229 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 514229 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 514229 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 514229 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 514229 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6009175500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 6009175500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6009175500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 6009175500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6009175500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 6009175500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.022109 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.022109 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.022109 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.022109 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.022109 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.022109 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11685.796600 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11685.796600 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11685.796600 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11685.796600 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11685.796600 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11685.796600 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 87205 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 87205 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 87205 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 87205 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 87205 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 87205 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 1052891500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 1052891500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1052891500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 1052891500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1052891500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 1052891500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016590 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.016590 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.016590 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.016590 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.016590 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.016590 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12073.751505 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12073.751505 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12073.751505 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 12073.751505 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12073.751505 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 12073.751505 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 642542 # number of replacements -system.cpu1.dcache.tagsinuse 493.349728 # Cycle average of tags in use -system.cpu1.dcache.total_refs 6059289 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 642979 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 9.423774 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 54205321000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 493.349728 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.963574 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.963574 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 3370941 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 3370941 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 2541028 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 2541028 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 71125 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 71125 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 80221 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 80221 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 5911969 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 5911969 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 5911969 # number of overall hits -system.cpu1.dcache.overall_hits::total 5911969 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 513441 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 513441 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 122213 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 122213 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13103 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 13103 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 640 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 640 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 635654 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 635654 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 635654 # number of overall misses -system.cpu1.dcache.overall_misses::total 635654 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 7202554500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 7202554500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2665634000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2665634000 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 183727000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 183727000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 8466000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 8466000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 9868188500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 9868188500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 9868188500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 9868188500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 3884382 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 3884382 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 2663241 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 2663241 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 84228 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 84228 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 80861 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 80861 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 6547623 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 6547623 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 6547623 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 6547623 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.132181 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.132181 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.045889 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.045889 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.155566 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.155566 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.007915 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.007915 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.097082 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.097082 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.097082 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.097082 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14028.008087 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14028.008087 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21811.378495 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 21811.378495 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14021.750744 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14021.750744 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13228.125000 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 13228.125000 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15524.465354 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 15524.465354 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15524.465354 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 15524.465354 # average overall miss latency +system.cpu1.dcache.replacements 53525 # number of replacements +system.cpu1.dcache.tagsinuse 416.811918 # Cycle average of tags in use +system.cpu1.dcache.total_refs 1627176 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 53933 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 30.170322 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 1941569697000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 416.811918 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.814086 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.814086 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 982724 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 982724 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 626457 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 626457 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 11310 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 11310 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 11708 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 11708 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 1609181 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 1609181 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 1609181 # number of overall hits +system.cpu1.dcache.overall_hits::total 1609181 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 35620 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 35620 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 22610 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 22610 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1003 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 1003 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 543 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 543 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 58230 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 58230 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 58230 # number of overall misses +system.cpu1.dcache.overall_misses::total 58230 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 484449000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 484449000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 694363000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 694363000 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 12193000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 12193000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 7082000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 7082000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 1178812000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 1178812000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 1178812000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 1178812000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 1018344 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1018344 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 649067 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 649067 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 12313 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 12313 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 12251 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 12251 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 1667411 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 1667411 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 1667411 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 1667411 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.034978 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.034978 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034835 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.034835 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.081459 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.081459 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.044323 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.044323 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.034922 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.034922 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.034922 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.034922 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13600.477260 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13600.477260 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 30710.437859 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 30710.437859 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12156.530409 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12156.530409 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13042.357274 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 13042.357274 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20244.066632 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 20244.066632 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20244.066632 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 20244.066632 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1151,66 +1151,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 498963 # number of writebacks -system.cpu1.dcache.writebacks::total 498963 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 513441 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 513441 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 122213 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 122213 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 13103 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 13103 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 640 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 640 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 635654 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 635654 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 635654 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 635654 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 5662217009 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 5662217009 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2298995000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2298995000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 144418000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 144418000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 6549000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 6549000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 5000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 5000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7961212009 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 7961212009 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7961212009 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 7961212009 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 295035500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 295035500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 516366500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 516366500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 811402000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 811402000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.132181 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.132181 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.045889 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.045889 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.155566 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.155566 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.007915 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.007915 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.097082 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.097082 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.097082 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.097082 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11027.979863 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11027.979863 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18811.378495 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18811.378495 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11021.750744 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11021.750744 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 10232.812500 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 10232.812500 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12524.442557 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12524.442557 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12524.442557 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12524.442557 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 35190 # number of writebacks +system.cpu1.dcache.writebacks::total 35190 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 35620 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 35620 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 22610 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 22610 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 1003 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 1003 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 543 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 543 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 58230 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 58230 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 58230 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 58230 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 377581004 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 377581004 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 626529004 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 626529004 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 9184000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 9184000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5453000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5453000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1004110008 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 1004110008 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1004110008 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 1004110008 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 20565000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 20565000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 534607500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 534607500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 555172500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 555172500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.034978 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.034978 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034835 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034835 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.081459 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.081459 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.044323 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.044323 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.034922 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.034922 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034922 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.034922 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10600.252779 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10600.252779 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27710.261123 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27710.261123 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9156.530409 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9156.530409 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 10042.357274 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 10042.357274 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17243.860690 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17243.860690 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17243.860690 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17243.860690 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index c7cd1312f..9ccbe5ddb 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,138 +1,138 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.920853 # Number of seconds simulated -sim_ticks 1920853042000 # Number of ticks simulated -final_tick 1920853042000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.921792 # Number of seconds simulated +sim_ticks 1921792488000 # Number of ticks simulated +final_tick 1921792488000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1381815 # Simulator instruction rate (inst/s) -host_op_rate 1381815 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47239093914 # Simulator tick rate (ticks/s) -host_mem_usage 299308 # Number of bytes of host memory used -host_seconds 40.66 # Real time elapsed on the host -sim_insts 56187824 # Number of instructions simulated -sim_ops 56187824 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 850688 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24847552 # Number of bytes read from this memory +host_inst_rate 1964765 # Simulator instruction rate (inst/s) +host_op_rate 1964764 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 67191639126 # Simulator tick rate (ticks/s) +host_mem_usage 295072 # Number of bytes of host memory used +host_seconds 28.60 # Real time elapsed on the host +sim_insts 56195476 # Number of instructions simulated +sim_ops 56195476 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 850624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24858752 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory -system.physmem.bytes_read::total 28350592 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 850688 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 850688 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7389056 # Number of bytes written to this memory -system.physmem.bytes_written::total 7389056 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 13292 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388243 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 28361728 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 850624 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 850624 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7403520 # Number of bytes written to this memory +system.physmem.bytes_written::total 7403520 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13291 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388418 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 442978 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115454 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115454 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 442870 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12935686 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1380820 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14759376 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 442870 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 442870 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3846758 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3846758 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3846758 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 442870 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12935686 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1380820 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18606133 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 336066 # number of replacements -system.l2c.tagsinuse 65311.806529 # Cycle average of tags in use -system.l2c.total_refs 2448197 # Total number of references to valid blocks. -system.l2c.sampled_refs 401228 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.101760 # Average number of references to valid blocks. -system.l2c.warmup_cycle 5946056000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 55675.727094 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 4768.395922 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 4867.683513 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.849544 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.072760 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.074275 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.996579 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.inst 916208 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 814933 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1731141 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 835149 # number of Writeback hits -system.l2c.Writeback_hits::total 835149 # number of Writeback hits +system.physmem.num_reads::total 443152 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115680 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115680 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 442620 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12935191 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1380145 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14757955 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 442620 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 442620 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3852403 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3852403 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3852403 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 442620 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12935191 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1380145 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18610359 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 336240 # number of replacements +system.l2c.tagsinuse 65308.066862 # Cycle average of tags in use +system.l2c.total_refs 2448422 # Total number of references to valid blocks. +system.l2c.sampled_refs 401402 # Sample count of references to valid blocks. +system.l2c.avg_refs 6.099676 # Average number of references to valid blocks. +system.l2c.warmup_cycle 6040304000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 55651.693971 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 4767.859045 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 4888.513847 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.849177 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.inst 0.072752 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.074593 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.996522 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.inst 916493 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 814973 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1731466 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 835196 # number of Writeback hits +system.l2c.Writeback_hits::total 835196 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 4 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 187605 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 187605 # number of ReadExReq hits -system.l2c.demand_hits::cpu.inst 916208 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 1002538 # number of demand (read+write) hits -system.l2c.demand_hits::total 1918746 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.inst 916208 # number of overall hits -system.l2c.overall_hits::cpu.data 1002538 # number of overall hits -system.l2c.overall_hits::total 1918746 # number of overall hits -system.l2c.ReadReq_misses::cpu.inst 13292 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 271915 # number of ReadReq misses -system.l2c.ReadReq_misses::total 285207 # number of ReadReq misses +system.l2c.ReadExReq_hits::cpu.data 187534 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 187534 # number of ReadExReq hits +system.l2c.demand_hits::cpu.inst 916493 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 1002507 # number of demand (read+write) hits +system.l2c.demand_hits::total 1919000 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.inst 916493 # number of overall hits +system.l2c.overall_hits::cpu.data 1002507 # number of overall hits +system.l2c.overall_hits::total 1919000 # number of overall hits +system.l2c.ReadReq_misses::cpu.inst 13291 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 271963 # number of ReadReq misses +system.l2c.ReadReq_misses::total 285254 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu.data 14 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 14 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 116718 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 116718 # number of ReadExReq misses -system.l2c.demand_misses::cpu.inst 13292 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 388633 # number of demand (read+write) misses -system.l2c.demand_misses::total 401925 # number of demand (read+write) misses -system.l2c.overall_misses::cpu.inst 13292 # number of overall misses -system.l2c.overall_misses::cpu.data 388633 # number of overall misses -system.l2c.overall_misses::total 401925 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu.inst 691773000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.data 14144855000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 14836628000 # number of ReadReq miss cycles +system.l2c.ReadExReq_misses::cpu.data 116845 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 116845 # number of ReadExReq misses +system.l2c.demand_misses::cpu.inst 13291 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 388808 # number of demand (read+write) misses +system.l2c.demand_misses::total 402099 # number of demand (read+write) misses +system.l2c.overall_misses::cpu.inst 13291 # number of overall misses +system.l2c.overall_misses::cpu.data 388808 # number of overall misses +system.l2c.overall_misses::total 402099 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu.inst 691744000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.data 14147302000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 14839046000 # number of ReadReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu.data 320000 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::total 320000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu.data 6070015000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6070015000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu.inst 691773000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.data 20214870000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 20906643000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu.inst 691773000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.data 20214870000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 20906643000 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu.inst 929500 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 1086848 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2016348 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 835149 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 835149 # number of Writeback accesses(hits+misses) +system.l2c.ReadExReq_miss_latency::cpu.data 6076563000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 6076563000 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu.inst 691744000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.data 20223865000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 20915609000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu.inst 691744000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.data 20223865000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 20915609000 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu.inst 929784 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 1086936 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2016720 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 835196 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 835196 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu.data 18 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 18 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu.data 304323 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 304323 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu.inst 929500 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 1391171 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2320671 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu.inst 929500 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 1391171 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2320671 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.014300 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.250187 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.141447 # miss rate for ReadReq accesses +system.l2c.ReadExReq_accesses::cpu.data 304379 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 304379 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu.inst 929784 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 1391315 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2321099 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu.inst 929784 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.data 1391315 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2321099 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu.inst 0.014295 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.250211 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.141445 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu.data 0.777778 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 0.777778 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.383533 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.383533 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.inst 0.014300 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.279357 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.173193 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.inst 0.014300 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.279357 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.173193 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu.inst 52044.312368 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.data 52019.399445 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52020.560505 # average ReadReq miss latency +system.l2c.ReadExReq_miss_rate::cpu.data 0.383880 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.383880 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu.inst 0.014295 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.279454 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.173236 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.inst 0.014295 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.279454 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.173236 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu.inst 52046.046197 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.data 52019.215849 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52020.465971 # average ReadReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu.data 22857.142857 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total 22857.142857 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu.data 52005.817440 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52005.817440 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu.inst 52044.312368 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.data 52015.320367 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52016.279157 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.inst 52044.312368 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.data 52015.320367 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52016.279157 # average overall miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu.data 52005.331850 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52005.331850 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu.inst 52046.046197 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.data 52015.043415 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52016.068182 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.inst 52046.046197 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.data 52015.043415 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52016.068182 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -141,66 +141,66 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 73942 # number of writebacks -system.l2c.writebacks::total 73942 # number of writebacks -system.l2c.ReadReq_mshr_misses::cpu.inst 13292 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.data 271915 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 285207 # number of ReadReq MSHR misses +system.l2c.writebacks::writebacks 74168 # number of writebacks +system.l2c.writebacks::total 74168 # number of writebacks +system.l2c.ReadReq_mshr_misses::cpu.inst 13291 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.data 271963 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 285254 # number of ReadReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu.data 14 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::total 14 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu.data 116718 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 116718 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu.inst 13292 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.data 388633 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 401925 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu.inst 13292 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.data 388633 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 401925 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu.inst 532266000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.data 10881875000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 11414141000 # number of ReadReq MSHR miss cycles +system.l2c.ReadExReq_mshr_misses::cpu.data 116845 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 116845 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu.inst 13291 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.data 388808 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 402099 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu.inst 13291 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.data 388808 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 402099 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu.inst 532249000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.data 10883746000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 11415995000 # number of ReadReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 620000 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::total 620000 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4669399000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 4669399000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.inst 532266000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.data 15551274000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 16083540000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.inst 532266000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.data 15551274000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 16083540000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 772639030 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 772639030 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1072677000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1072677000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu.data 1845316030 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 1845316030 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.014300 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.250187 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.141447 # mshr miss rate for ReadReq accesses +system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4674423000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 4674423000 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.inst 532249000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.data 15558169000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 16090418000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.inst 532249000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.data 15558169000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 16090418000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 1331550000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1331550000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1893145000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1893145000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.data 3224695000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 3224695000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.014295 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.250211 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.141445 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.777778 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total 0.777778 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.383533 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.383533 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu.inst 0.014300 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.data 0.279357 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.173193 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu.inst 0.014300 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.data 0.279357 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.173193 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40044.086669 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40019.399445 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40020.549987 # average ReadReq mshr miss latency +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.383880 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.383880 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.014295 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.279454 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.173236 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.014295 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.279454 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.173236 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40045.820480 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40019.215849 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40020.455454 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 44285.714286 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::total 44285.714286 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40005.817440 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40005.817440 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40044.086669 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40015.320367 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40016.271692 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40044.086669 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40015.320367 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40016.271692 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40005.331850 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40005.331850 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40045.820480 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40015.043415 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40016.060721 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40045.820480 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40015.043415 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40016.060721 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -209,14 +209,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.356968 # Cycle average of tags in use +system.iocache.tagsinuse 1.355427 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1753491316000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.356968 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.084811 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.084811 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1754498131000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.355427 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.084714 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.084714 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -227,12 +227,12 @@ system.iocache.overall_misses::tsunami.ide 41725 # system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 20672998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 20672998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 7638105806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 7638105806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 7658778804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 7658778804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 7658778804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 7658778804 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 7634106806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 7634106806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 7654779804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 7654779804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 7654779804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 7654779804 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -251,17 +251,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119497.098266 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 119497.098266 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183820.413121 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 183820.413121 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 183553.716093 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 183553.716093 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 183553.716093 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 183553.716093 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 7453000 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183724.172266 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 183724.172266 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 183457.874272 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 183457.874272 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 183457.874272 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 183457.874272 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 7454000 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7118 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7097 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 1047.063782 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 1050.302945 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -277,12 +277,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41725 system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11676000 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 11676000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 5477251000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 5477251000 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 5488927000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 5488927000 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 5488927000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 5488927000 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 5473252000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 5473252000 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 5484928000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 5484928000 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 5484928000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 5484928000 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -293,12 +293,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67491.329480 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 67491.329480 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131816.783789 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 131816.783789 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131550.077891 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 131550.077891 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131550.077891 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 131550.077891 # average overall mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131720.542934 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 131720.542934 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131454.236070 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 131454.236070 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131454.236070 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 131454.236070 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -316,22 +316,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9065773 # DTB read hits +system.cpu.dtb.read_hits 9066933 # DTB read hits system.cpu.dtb.read_misses 10329 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations system.cpu.dtb.read_accesses 728856 # DTB read accesses -system.cpu.dtb.write_hits 6357048 # DTB write hits +system.cpu.dtb.write_hits 6357519 # DTB write hits system.cpu.dtb.write_misses 1142 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations system.cpu.dtb.write_accesses 291931 # DTB write accesses -system.cpu.dtb.data_hits 15422821 # DTB hits +system.cpu.dtb.data_hits 15424452 # DTB hits system.cpu.dtb.data_misses 11471 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations system.cpu.dtb.data_accesses 1020787 # DTB accesses -system.cpu.itb.fetch_hits 4975760 # ITB hits +system.cpu.itb.fetch_hits 4975863 # ITB hits system.cpu.itb.fetch_misses 5006 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4980766 # ITB accesses +system.cpu.itb.fetch_accesses 4980869 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -344,51 +344,51 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3841706084 # number of cpu cycles simulated +system.cpu.numCycles 3843584976 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56187824 # Number of instructions committed -system.cpu.committedOps 56187824 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 52059470 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses -system.cpu.num_func_calls 1483670 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 6469221 # number of instructions that are conditional controls -system.cpu.num_int_insts 52059470 # number of integer instructions -system.cpu.num_fp_insts 324460 # number of float instructions -system.cpu.num_int_register_reads 71329755 # number of times the integer registers were read -system.cpu.num_int_register_writes 38524240 # number of times the integer registers were written -system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read -system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written -system.cpu.num_mem_refs 15475451 # number of memory refs -system.cpu.num_load_insts 9102635 # Number of load instructions -system.cpu.num_store_insts 6372816 # Number of store instructions -system.cpu.num_idle_cycles 3589579952.998131 # Number of idle cycles -system.cpu.num_busy_cycles 252126131.001869 # Number of busy cycles -system.cpu.not_idle_fraction 0.065629 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.934371 # Percentage of idle cycles +system.cpu.committedInsts 56195476 # Number of instructions committed +system.cpu.committedOps 56195476 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 52066692 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 324259 # Number of float alu accesses +system.cpu.num_func_calls 1483822 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 6469666 # number of instructions that are conditional controls +system.cpu.num_int_insts 52066692 # number of integer instructions +system.cpu.num_fp_insts 324259 # number of float instructions +system.cpu.num_int_register_reads 71339619 # number of times the integer registers were read +system.cpu.num_int_register_writes 38530592 # number of times the integer registers were written +system.cpu.num_fp_register_reads 163543 # number of times the floating registers were read +system.cpu.num_fp_register_writes 166418 # number of times the floating registers were written +system.cpu.num_mem_refs 15477059 # number of memory refs +system.cpu.num_load_insts 9103780 # Number of load instructions +system.cpu.num_store_insts 6373279 # Number of store instructions +system.cpu.num_idle_cycles 3588655153.998133 # Number of idle cycles +system.cpu.num_busy_cycles 254929822.001867 # Number of busy cycles +system.cpu.not_idle_fraction 0.066326 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.933674 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 212104 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74929 40.88% 40.88% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6374 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 212119 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74932 40.88% 40.88% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 40.95% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1936 1.06% 42.01% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 106285 57.99% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183281 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73562 49.31% 49.31% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1936 1.30% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73562 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149191 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1861395652500 96.90% 96.90% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 90398000 0.00% 96.91% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 587366500 0.03% 96.94% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 58778792000 3.06% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1920852209000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981756 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_count::22 1937 1.06% 42.01% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 106298 57.99% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183298 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73565 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::21 131 0.09% 49.39% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::22 1937 1.30% 50.69% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73565 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149198 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1861046523500 96.84% 96.84% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 104284500 0.01% 96.84% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 779455000 0.04% 96.89% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 59861392000 3.11% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1921791655000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981757 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.692120 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814001 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.692064 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.813964 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -424,33 +424,33 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4177 2.16% 2.17% # number of callpals executed +system.cpu.kern.callpal::swpctx 4174 2.16% 2.16% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 176052 91.22% 93.41% # number of callpals executed -system.cpu.kern.callpal::rdps 6837 3.54% 96.96% # number of callpals executed +system.cpu.kern.callpal::swpipl 176067 91.22% 93.41% # number of callpals executed +system.cpu.kern.callpal::rdps 6838 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal::rti 5161 2.67% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5162 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 193007 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5906 # number of protection mode switches -system.cpu.kern.mode_switch::user 1738 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2098 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1908 -system.cpu.kern.mode_good::user 1738 -system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.323061 # fraction of useful protection mode switches +system.cpu.kern.callpal::total 193021 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5905 # number of protection mode switches +system.cpu.kern.mode_switch::user 1740 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1909 +system.cpu.kern.mode_good::user 1740 +system.cpu.kern.mode_good::idle 169 +system.cpu.kern.mode_switch_good::kernel 0.323285 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081030 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.391706 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 46234707000 2.41% 2.41% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5259387000 0.27% 2.68% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1869358108000 97.32% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4178 # number of times the context was actually changed +system.cpu.kern.mode_switch_good::idle 0.080591 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.391911 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 46687559000 2.43% 2.43% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5260775000 0.27% 2.70% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1869843314000 97.30% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4175 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -482,51 +482,51 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 928849 # number of replacements -system.cpu.icache.tagsinuse 508.732123 # Cycle average of tags in use -system.cpu.icache.total_refs 55270143 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 929360 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 59.471188 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 35877190000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 508.732123 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.993617 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.993617 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 55270143 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 55270143 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 55270143 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 55270143 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 55270143 # number of overall hits -system.cpu.icache.overall_hits::total 55270143 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 929520 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 929520 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 929520 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 929520 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 929520 # number of overall misses -system.cpu.icache.overall_misses::total 929520 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13854449500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13854449500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13854449500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13854449500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13854449500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13854449500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 56199663 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 56199663 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 56199663 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 56199663 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 56199663 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 56199663 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016540 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.016540 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.016540 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.016540 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.016540 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.016540 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14904.950405 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14904.950405 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14904.950405 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14904.950405 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14904.950405 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14904.950405 # average overall miss latency +system.cpu.icache.replacements 929133 # number of replacements +system.cpu.icache.tagsinuse 508.706285 # Cycle average of tags in use +system.cpu.icache.total_refs 55277511 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 929644 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 59.460945 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 36213864000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 508.706285 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.993567 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.993567 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 55277511 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 55277511 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 55277511 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 55277511 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 55277511 # number of overall hits +system.cpu.icache.overall_hits::total 55277511 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 929804 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 929804 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 929804 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 929804 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 929804 # number of overall misses +system.cpu.icache.overall_misses::total 929804 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13857748000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13857748000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13857748000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13857748000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13857748000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13857748000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 56207315 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 56207315 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 56207315 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 56207315 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 56207315 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 56207315 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016542 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.016542 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.016542 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.016542 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.016542 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.016542 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14903.945348 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14903.945348 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14903.945348 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14903.945348 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14903.945348 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14903.945348 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -535,104 +535,104 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929520 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 929520 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 929520 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 929520 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 929520 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 929520 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11065203000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11065203000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11065203000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11065203000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11065203000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11065203000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016540 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.016540 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.016540 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11904.211851 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11904.211851 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11904.211851 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11904.211851 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11904.211851 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11904.211851 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929804 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 929804 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 929804 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 929804 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 929804 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 929804 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11067649000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11067649000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11067649000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11067649000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11067649000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11067649000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016542 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016542 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016542 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.016542 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016542 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.016542 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11903.206482 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11903.206482 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11903.206482 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11903.206482 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11903.206482 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11903.206482 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1390657 # number of replacements -system.cpu.dcache.tagsinuse 511.983813 # Cycle average of tags in use -system.cpu.dcache.total_refs 14050696 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1391169 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 10.099920 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 85768000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.983813 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999968 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999968 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 7815339 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7815339 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5853076 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5853076 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 182979 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 182979 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 199284 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 199284 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13668415 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13668415 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13668415 # number of overall hits -system.cpu.dcache.overall_hits::total 13668415 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1069522 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1069522 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 304341 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 304341 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17326 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17326 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1373863 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1373863 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1373863 # number of overall misses -system.cpu.dcache.overall_misses::total 1373863 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 26656014000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 26656014000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9232792000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9232792000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 248493000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 248493000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35888806000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35888806000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35888806000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35888806000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 8884861 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 8884861 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6157417 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6157417 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200305 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200305 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 199284 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 199284 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15042278 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15042278 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15042278 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15042278 # number of overall (read+write) accesses +system.cpu.dcache.replacements 1390802 # number of replacements +system.cpu.dcache.tagsinuse 511.979761 # Cycle average of tags in use +system.cpu.dcache.total_refs 14052158 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1391314 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 10.099918 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 101905000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.979761 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999960 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999960 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 7816348 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7816348 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5853489 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5853489 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183027 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183027 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199276 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 199276 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13669837 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13669837 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13669837 # number of overall hits +system.cpu.dcache.overall_hits::total 13669837 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1069663 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1069663 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304397 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304397 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17273 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17273 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1374060 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1374060 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1374060 # number of overall misses +system.cpu.dcache.overall_misses::total 1374060 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 26660030000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 26660030000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9238691000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9238691000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 247715000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 247715000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35898721000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35898721000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35898721000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35898721000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 8886011 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 8886011 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6157886 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6157886 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200300 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200300 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199276 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199276 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15043897 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15043897 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15043897 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15043897 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120376 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.120376 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049427 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.049427 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086498 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086498 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.091333 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.091333 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.091333 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.091333 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24923.296575 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24923.296575 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30336.996987 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30336.996987 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14342.202470 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14342.202470 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 26122.550793 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 26122.550793 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 26122.550793 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 26122.550793 # average overall miss latency +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049432 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049432 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086236 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086236 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.091337 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.091337 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.091337 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.091337 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24923.765709 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24923.765709 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30350.795179 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30350.795179 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14341.168297 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14341.168297 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26126.021426 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26126.021426 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26126.021426 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26126.021426 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -641,54 +641,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 835149 # number of writebacks -system.cpu.dcache.writebacks::total 835149 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069522 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1069522 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304341 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304341 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17326 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17326 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1373863 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1373863 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1373863 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1373863 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23447403000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 23447403000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8319769000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8319769000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 196515000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 196515000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31767172000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 31767172000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31767172000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 31767172000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 862831000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 862831000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1190523500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1190523500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 2053354500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 2053354500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.writebacks::writebacks 835196 # number of writebacks +system.cpu.dcache.writebacks::total 835196 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069663 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1069663 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304397 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 304397 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17273 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17273 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1374060 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1374060 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1374060 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1374060 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23450996000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23450996000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8325500000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8325500000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 195896000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 195896000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31776496000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 31776496000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31776496000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 31776496000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1421708000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1421708000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011005000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011005000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3432713000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3432713000 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120376 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120376 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049427 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049427 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086498 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086498 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091333 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091333 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091333 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091333 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21923.254501 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21923.254501 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27336.996987 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27336.996987 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11342.202470 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11342.202470 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23122.518039 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23122.518039 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23122.518039 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23122.518039 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049432 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049432 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086236 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086236 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091337 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091337 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091337 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091337 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21923.723640 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21923.723640 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27350.795179 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27350.795179 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11341.168297 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11341.168297 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23125.988676 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23125.988676 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23125.988676 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23125.988676 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 2693ffabe..a84f458bf 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,71 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.172545 # Number of seconds simulated -sim_ticks 1172544977000 # Number of ticks simulated -final_tick 1172544977000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.207291 # Number of seconds simulated +sim_ticks 1207290627000 # Number of ticks simulated +final_tick 1207290627000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 706392 # Simulator instruction rate (inst/s) -host_op_rate 900233 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 13469238975 # Simulator tick rate (ticks/s) -host_mem_usage 389548 # Number of bytes of host memory used -host_seconds 87.05 # Real time elapsed on the host -sim_insts 61493926 # Number of instructions simulated -sim_ops 78368454 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::realview.clcd 50331648 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 394788 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4717236 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 322588 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4794736 # Number of bytes read from this memory -system.physmem.bytes_read::total 60561444 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 394788 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 322588 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 717376 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4107264 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7134608 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 6291456 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 12387 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 73779 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 5122 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 74944 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6457695 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 64176 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 821012 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 42925132 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 55 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 109 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 336693 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 4023075 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 218 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 275118 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4089170 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51649570 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 336693 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 275118 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 611811 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3502863 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 14498 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2567359 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6084720 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3502863 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 42925132 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 55 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 109 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 336693 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 4037573 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 218 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 275118 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 6656529 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 57734290 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 1000042 # Simulator instruction rate (inst/s) +host_op_rate 1274494 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 19638848032 # Simulator tick rate (ticks/s) +host_mem_usage 383956 # Number of bytes of host memory used +host_seconds 61.47 # Real time elapsed on the host +sim_insts 61477134 # Number of instructions simulated +sim_ops 78349023 # Number of ops (including micro ops) simulated system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -76,245 +21,318 @@ system.realview.nvmem.num_reads::cpu0.inst 5 # system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 41 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 58 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 40 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 56 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 41 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 58 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 40 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 56 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 41 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 58 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 69301 # number of replacements -system.l2c.tagsinuse 52667.431766 # Cycle average of tags in use -system.l2c.total_refs 1645571 # Total number of references to valid blocks. -system.l2c.sampled_refs 134500 # Sample count of references to valid blocks. -system.l2c.avg_refs 12.234729 # Average number of references to valid blocks. +system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 56 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::realview.clcd 52642784 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 394084 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4718772 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 323100 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4791152 # Number of bytes read from this memory +system.physmem.bytes_read::total 62870404 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 394084 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 323100 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 717184 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4105920 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory +system.physmem.bytes_written::total 7133264 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 6580348 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 12376 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 73803 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 5130 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 74888 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6746553 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 64155 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory +system.physmem.num_writes::total 820991 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43604069 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 53 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 106 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 326420 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3908563 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 212 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 53 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 267624 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 3968516 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52075617 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 326420 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 267624 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 594044 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3400938 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 14081 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2493471 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 5908490 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3400938 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43604069 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 53 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 106 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 326420 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3922645 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 212 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 53 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 267624 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 6461987 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 57984106 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 69267 # number of replacements +system.l2c.tagsinuse 52917.687187 # Cycle average of tags in use +system.l2c.total_refs 1645693 # Total number of references to valid blocks. +system.l2c.sampled_refs 134464 # Sample count of references to valid blocks. +system.l2c.avg_refs 12.238912 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 39900.139395 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 0.000282 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.001242 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 3730.644795 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 4216.663550 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 2.734150 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 2763.076938 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 2054.171414 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.608828 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 40124.661939 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 0.000403 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 0.001466 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 3720.854168 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 4213.259552 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 2.746626 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.itb.walker 0.001732 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 2800.295642 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 2055.865658 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.612254 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.056925 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.064341 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.056776 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.064289 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.042161 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.031344 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.803641 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 4102 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 1845 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 402958 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 205810 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 5738 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1962 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 449307 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 144268 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1215990 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 572486 # number of Writeback hits -system.l2c.Writeback_hits::total 572486 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1132 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 588 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1720 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 206 # number of SCUpgradeReq hits +system.l2c.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.042729 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.031370 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.807460 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 4114 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 1841 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 402307 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 205875 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 5723 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 1959 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 449970 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 144091 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1215880 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 572580 # number of Writeback hits +system.l2c.Writeback_hits::total 572580 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 1130 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 572 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1702 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 212 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.data 104 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 310 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 56781 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 53046 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 109827 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 4102 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 1845 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 402958 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 262591 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 5738 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 1962 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 449307 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 197314 # number of demand (read+write) hits -system.l2c.demand_hits::total 1325817 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 4102 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 1845 # number of overall hits -system.l2c.overall_hits::cpu0.inst 402958 # number of overall hits -system.l2c.overall_hits::cpu0.data 262591 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 5738 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 1962 # number of overall hits -system.l2c.overall_hits::cpu1.inst 449307 # number of overall hits -system.l2c.overall_hits::cpu1.data 197314 # number of overall hits -system.l2c.overall_hits::total 1325817 # number of overall hits +system.l2c.SCUpgradeReq_hits::total 316 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 56723 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 53017 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 109740 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 4114 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 1841 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 402307 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 262598 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 5723 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 1959 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 449970 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 197108 # number of demand (read+write) hits +system.l2c.demand_hits::total 1325620 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 4114 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 1841 # number of overall hits +system.l2c.overall_hits::cpu0.inst 402307 # number of overall hits +system.l2c.overall_hits::cpu0.data 262598 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 5723 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 1959 # number of overall hits +system.l2c.overall_hits::cpu1.inst 449970 # number of overall hits +system.l2c.overall_hits::cpu1.data 197108 # number of overall hits +system.l2c.overall_hits::total 1325620 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 5755 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 7866 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 5744 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 7874 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 4 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 5035 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 3646 # number of ReadReq misses -system.l2c.ReadReq_misses::total 22309 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 4696 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 3601 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 8297 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 568 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 498 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1066 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 67165 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 72394 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 139559 # number of ReadExReq misses +system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 5043 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 3639 # number of ReadReq misses +system.l2c.ReadReq_misses::total 22308 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 4704 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 3584 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 8288 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 569 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 485 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1054 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 67193 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 72340 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 139533 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 5755 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 75031 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 5744 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 75067 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 4 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 5035 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 76040 # number of demand (read+write) misses -system.l2c.demand_misses::total 161868 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 5043 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 75979 # number of demand (read+write) misses +system.l2c.demand_misses::total 161841 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 5755 # number of overall misses -system.l2c.overall_misses::cpu0.data 75031 # number of overall misses +system.l2c.overall_misses::cpu0.inst 5744 # number of overall misses +system.l2c.overall_misses::cpu0.data 75067 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 4 # number of overall misses -system.l2c.overall_misses::cpu1.inst 5035 # number of overall misses -system.l2c.overall_misses::cpu1.data 76040 # number of overall misses -system.l2c.overall_misses::total 161868 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses +system.l2c.overall_misses::cpu1.inst 5043 # number of overall misses +system.l2c.overall_misses::cpu1.data 75979 # number of overall misses +system.l2c.overall_misses::total 161841 # number of overall misses system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 52000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.itb.walker 104000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 299823500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 409333998 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 298918500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 409688500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 208500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 262768000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 190087500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1162377498 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 29968997 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 27317000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 57285997 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 3654000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 6100000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 9754000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 3493697466 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 3769025494 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7262722960 # number of ReadExReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.itb.walker 52500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 263122000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 189491500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1161637500 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 30055000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 27347000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 57402000 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 3692000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 6038000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 9730000 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 3494564965 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 3764669994 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7259234959 # number of ReadExReq miss cycles system.l2c.demand_miss_latency::cpu0.dtb.walker 52000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.itb.walker 104000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 299823500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 3903031464 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 298918500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 3904253465 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.dtb.walker 208500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 262768000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 3959112994 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 8425100458 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 52500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 263122000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 3954161494 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 8420872459 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu0.dtb.walker 52000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.itb.walker 104000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 299823500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 3903031464 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 298918500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 3904253465 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.dtb.walker 208500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 262768000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 3959112994 # number of overall miss cycles -system.l2c.overall_miss_latency::total 8425100458 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 4103 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 1847 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 408713 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 213676 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 5742 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 1962 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 454342 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 147914 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1238299 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 572486 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 572486 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 5828 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 4189 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 10017 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 774 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 602 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1376 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 123946 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 125440 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 249386 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 4103 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 1847 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 408713 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 337622 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 5742 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 1962 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 454342 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 273354 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1487685 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 4103 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 1847 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 408713 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 337622 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 5742 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 1962 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 454342 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 273354 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1487685 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000244 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001083 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.014081 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.036813 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000697 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.011082 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.024649 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.018016 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.805765 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.859632 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.828292 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.733850 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.827243 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.774709 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.541889 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.577121 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.559610 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000244 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.001083 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.014081 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.222234 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000697 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.011082 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.278174 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.108805 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000244 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.001083 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.014081 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.222234 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000697 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.011082 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.278174 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.108805 # miss rate for overall accesses +system.l2c.overall_miss_latency::cpu1.itb.walker 52500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 263122000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 3954161494 # number of overall miss cycles +system.l2c.overall_miss_latency::total 8420872459 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 4115 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 1843 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 408051 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 213749 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 5727 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 1960 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 455013 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 147730 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1238188 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 572580 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 572580 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 5834 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 4156 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 9990 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 781 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 589 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1370 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 123916 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 125357 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 249273 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 4115 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 1843 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 408051 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 337665 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 5727 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 1960 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 455013 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 273087 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1487461 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 4115 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 1843 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 408051 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 337665 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 5727 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 1960 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 455013 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 273087 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1487461 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000243 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001085 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.014077 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.036838 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000698 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000510 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.011083 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.024633 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.018017 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.806308 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.862368 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.829630 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.728553 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.823430 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.769343 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.542246 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.577072 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.559760 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000243 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.001085 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.014077 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.222312 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000698 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.000510 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.011083 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.278223 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.108804 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000243 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.001085 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.014077 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.222312 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000698 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.000510 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.011083 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.278223 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.108804 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52000 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 52000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52097.914857 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 52038.392830 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52040.128830 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 52030.543561 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52125 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52188.282026 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 52135.902359 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52103.523152 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6381.813671 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 7585.948348 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 6904.422924 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6433.098592 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 12248.995984 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 9150.093809 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52016.637624 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52062.677763 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52040.520210 # average ReadExReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 52500 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52175.689074 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 52072.410003 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52072.686928 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6389.243197 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 7630.301339 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 6925.916988 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6488.576450 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 12449.484536 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 9231.499051 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52007.872323 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52041.332513 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52025.219547 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52000 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.itb.walker 52000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 52097.914857 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 52018.918367 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 52040.128830 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 52010.250376 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52125 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 52188.282026 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 52066.188769 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52049.203413 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.itb.walker 52500 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 52175.689074 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 52042.820964 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52031.762403 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52000 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 52000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 52097.914857 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 52018.918367 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 52040.128830 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 52010.250376 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52125 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 52188.282026 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 52066.188769 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52049.203413 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.itb.walker 52500 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 52175.689074 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 52042.820964 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52031.762403 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -323,8 +341,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 64176 # number of writebacks -system.l2c.writebacks::total 64176 # number of writebacks +system.l2c.writebacks::writebacks 64155 # number of writebacks +system.l2c.writebacks::total 64155 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits @@ -333,149 +351,161 @@ system.l2c.overall_mshr_hits::cpu0.inst 1 # nu system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 5754 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 7866 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 5743 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 7874 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 4 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 5035 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 3646 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 22308 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 4696 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 3601 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 8297 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 568 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 498 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1066 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 67165 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 72394 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 139559 # number of ReadExReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 5043 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 3639 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 22307 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 4704 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 3584 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 8288 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 569 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 485 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1054 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 67193 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 72340 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 139533 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu0.dtb.walker 1 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 5754 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 75031 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 5743 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 75067 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.dtb.walker 4 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 5035 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 76040 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 161867 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 5043 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 75979 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 161840 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0.dtb.walker 1 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 5754 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 75031 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 5743 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 75067 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.dtb.walker 4 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 5035 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 76040 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 161867 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 5043 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 75979 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 161840 # number of overall MSHR misses system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 40000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 80000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 230747000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 314937000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 229974000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 315198000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 160000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 202344000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 146333000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 894641000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 187986000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 144285000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 332271000 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 22750000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 19953000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 42703000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2687673000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2900282000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5587955000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 40000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 202602000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 145821000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 893915000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 188555000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 143675000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 332230000 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 22768000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 19442000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 42210000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2688204000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2896575000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5584779000 # number of ReadExReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 40000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 80000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 230747000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 3002610000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 229974000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 3003402000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 160000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 202344000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 3046615000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 6482596000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 40000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 202602000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 3042396000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 6478694000 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 40000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 80000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 230747000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 3002610000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 229974000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 3003402000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 160000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 202344000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 3046615000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 6482596000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 40000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 202602000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 3042396000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 6478694000 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 265520000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 9314941499 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12448668498 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3961000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 122157234000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 131741656499 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 694839000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 30621237500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 31316076500 # number of WriteReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154365734497 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 167083883995 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1128303000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 30843793500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 31972096500 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 265520000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10009780499 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13576971498 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3961000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 152778471500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 163057732999 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000244 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001083 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014078 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036813 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000697 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.011082 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.024649 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.018015 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.805765 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.859632 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.828292 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.733850 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.827243 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.774709 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.541889 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.577121 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.559610 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000244 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001083 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014078 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.222234 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000697 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011082 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.278174 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.108805 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000244 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001083 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014078 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.222234 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000697 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011082 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.278174 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.108805 # mshr miss rate for overall accesses +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 185209527997 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 199055980495 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000243 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001085 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014074 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036838 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000698 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000510 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.011083 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.024633 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.018016 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.806308 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.862368 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.829630 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.728553 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.823430 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.769343 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.542246 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.577072 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.559760 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000243 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001085 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014074 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.222312 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000698 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000510 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011083 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.278223 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.108803 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000243 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001085 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014074 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.222312 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000698 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000510 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011083 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.278223 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.108803 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40102.015989 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40037.757437 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40044.227756 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40030.226060 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40187.487587 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40135.216676 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40104.043393 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40031.090290 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40068.036656 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40047.125467 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40052.816901 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40066.265060 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40059.099437 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40015.975583 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40062.463740 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40040.090571 # average ReadExReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40174.895895 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40071.723001 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40073.295378 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40083.971088 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40087.890625 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40085.666023 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40014.059754 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40086.597938 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40047.438330 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40007.203131 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40041.125242 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40024.789835 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40102.015989 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40018.259120 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40044.227756 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40009.618075 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40187.487587 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40065.952130 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40048.904347 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40174.895895 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40042.590716 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40031.475531 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40102.015989 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40018.259120 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40044.227756 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40009.618075 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40187.487587 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40065.952130 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40048.904347 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40174.895895 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40042.590716 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40031.475531 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -498,26 +528,26 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7082876 # DTB read hits -system.cpu0.dtb.read_misses 3736 # DTB read misses -system.cpu0.dtb.write_hits 5665319 # DTB write hits +system.cpu0.dtb.read_hits 7076084 # DTB read hits +system.cpu0.dtb.read_misses 3743 # DTB read misses +system.cpu0.dtb.write_hits 5660386 # DTB write hits system.cpu0.dtb.write_misses 804 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1790 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 1791 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.dtb.prefetch_faults 141 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7086612 # DTB read accesses -system.cpu0.dtb.write_accesses 5666123 # DTB write accesses +system.cpu0.dtb.read_accesses 7079827 # DTB read accesses +system.cpu0.dtb.write_accesses 5661190 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12748195 # DTB hits -system.cpu0.dtb.misses 4540 # DTB misses -system.cpu0.dtb.accesses 12752735 # DTB accesses -system.cpu0.itb.inst_hits 29606138 # ITB inst hits +system.cpu0.dtb.hits 12736470 # DTB hits +system.cpu0.dtb.misses 4547 # DTB misses +system.cpu0.dtb.accesses 12741017 # DTB accesses +system.cpu0.itb.inst_hits 29574655 # ITB inst hits system.cpu0.itb.inst_misses 2205 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -534,79 +564,79 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 29608343 # ITB inst accesses -system.cpu0.itb.hits 29606138 # DTB hits +system.cpu0.itb.inst_accesses 29576860 # ITB inst accesses +system.cpu0.itb.hits 29574655 # DTB hits system.cpu0.itb.misses 2205 # DTB misses -system.cpu0.itb.accesses 29608343 # DTB accesses -system.cpu0.numCycles 2345089954 # number of cpu cycles simulated +system.cpu0.itb.accesses 29576860 # DTB accesses +system.cpu0.numCycles 2414581254 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 28907917 # Number of instructions committed -system.cpu0.committedOps 37265600 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 33149705 # Number of integer alu accesses +system.cpu0.committedInsts 28876799 # Number of instructions committed +system.cpu0.committedOps 37228975 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 33114839 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses -system.cpu0.num_func_calls 1243107 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4358822 # number of instructions that are conditional controls -system.cpu0.num_int_insts 33149705 # number of integer instructions +system.cpu0.num_func_calls 1241592 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4354316 # number of instructions that are conditional controls +system.cpu0.num_int_insts 33114839 # number of integer instructions system.cpu0.num_fp_insts 3860 # number of float instructions -system.cpu0.num_int_register_reads 190344582 # number of times the integer registers were read -system.cpu0.num_int_register_writes 36275228 # number of times the integer registers were written +system.cpu0.num_int_register_reads 190147140 # number of times the integer registers were read +system.cpu0.num_int_register_writes 36238708 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written -system.cpu0.num_mem_refs 13418689 # number of memory refs -system.cpu0.num_load_insts 7420825 # Number of load instructions -system.cpu0.num_store_insts 5997864 # Number of store instructions -system.cpu0.num_idle_cycles 2204555139.350120 # Number of idle cycles -system.cpu0.num_busy_cycles 140534814.649880 # Number of busy cycles -system.cpu0.not_idle_fraction 0.059927 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.940073 # Percentage of idle cycles +system.cpu0.num_mem_refs 13404188 # number of memory refs +system.cpu0.num_load_insts 7413537 # Number of load instructions +system.cpu0.num_store_insts 5990651 # Number of store instructions +system.cpu0.num_idle_cycles 2267023722.330122 # Number of idle cycles +system.cpu0.num_busy_cycles 147557531.669878 # Number of busy cycles +system.cpu0.not_idle_fraction 0.061111 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.938889 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 46687 # number of quiesce instructions executed -system.cpu0.icache.replacements 408797 # number of replacements -system.cpu0.icache.tagsinuse 509.495989 # Cycle average of tags in use -system.cpu0.icache.total_refs 29196812 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 409309 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 71.331957 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 75128897000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 509.495989 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.995109 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.995109 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 29196812 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 29196812 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 29196812 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 29196812 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 29196812 # number of overall hits -system.cpu0.icache.overall_hits::total 29196812 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 409309 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 409309 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 409309 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 409309 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 409309 # number of overall misses -system.cpu0.icache.overall_misses::total 409309 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6108172000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6108172000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 6108172000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6108172000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 6108172000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6108172000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 29606121 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 29606121 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 29606121 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 29606121 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 29606121 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 29606121 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013825 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.013825 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013825 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.013825 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013825 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.013825 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14923.131424 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14923.131424 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14923.131424 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14923.131424 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14923.131424 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14923.131424 # average overall miss latency +system.cpu0.kern.inst.quiesce 46683 # number of quiesce instructions executed +system.cpu0.icache.replacements 408135 # number of replacements +system.cpu0.icache.tagsinuse 509.469782 # Cycle average of tags in use +system.cpu0.icache.total_refs 29165991 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 408647 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 71.372091 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 75845657000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 509.469782 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.995058 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.995058 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 29165991 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 29165991 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 29165991 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 29165991 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 29165991 # number of overall hits +system.cpu0.icache.overall_hits::total 29165991 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 408647 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 408647 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 408647 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 408647 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 408647 # number of overall misses +system.cpu0.icache.overall_misses::total 408647 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6096214000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 6096214000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 6096214000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 6096214000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 6096214000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 6096214000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 29574638 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 29574638 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 29574638 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 29574638 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 29574638 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 29574638 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013817 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.013817 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013817 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.013817 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013817 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.013817 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14918.044180 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14918.044180 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14918.044180 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14918.044180 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14918.044180 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14918.044180 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -615,120 +645,120 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 409309 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 409309 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 409309 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 409309 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 409309 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 409309 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4879387500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4879387500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4879387500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4879387500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4879387500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4879387500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 408647 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 408647 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 408647 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 408647 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 408647 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 408647 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4869428500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4869428500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4869428500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4869428500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4869428500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4869428500 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 351814000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 351814000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 351814000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 351814000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013825 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013825 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013825 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.013825 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013825 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.013825 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11921.036430 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11921.036430 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11921.036430 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11921.036430 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11921.036430 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11921.036430 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013817 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013817 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013817 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.013817 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013817 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.013817 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11915.977604 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11915.977604 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11915.977604 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11915.977604 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11915.977604 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11915.977604 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 330813 # number of replacements -system.cpu0.dcache.tagsinuse 457.939353 # Cycle average of tags in use -system.cpu0.dcache.total_refs 12292528 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 331325 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 37.101118 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 330734 # number of replacements +system.cpu0.dcache.tagsinuse 459.649704 # Cycle average of tags in use +system.cpu0.dcache.total_refs 12280871 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 331246 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 37.074775 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 664264000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 457.939353 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.894413 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.894413 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6612408 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6612408 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5360091 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5360091 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147992 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 147992 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149726 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 149726 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 11972499 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 11972499 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11972499 # number of overall hits -system.cpu0.dcache.overall_hits::total 11972499 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 228125 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 228125 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 141749 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 141749 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9279 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 9279 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7492 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7492 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 369874 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 369874 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 369874 # number of overall misses -system.cpu0.dcache.overall_misses::total 369874 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3443081500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 3443081500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4917870500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 4917870500 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 100339500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 100339500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 74628000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 74628000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 8360952000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 8360952000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 8360952000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 8360952000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6840533 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6840533 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5501840 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5501840 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157271 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 157271 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157218 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 157218 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12342373 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12342373 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12342373 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12342373 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033349 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.033349 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025764 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.025764 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059000 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059000 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047654 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047654 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029968 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.029968 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029968 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.029968 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15092.960000 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15092.960000 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34694.216538 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 34694.216538 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10813.611381 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10813.611381 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9961.025093 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9961.025093 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 22604.865441 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 22604.865441 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 22604.865441 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 22604.865441 # average overall miss latency +system.cpu0.dcache.occ_blocks::cpu0.data 459.649704 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.897753 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.897753 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6605687 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6605687 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5355220 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5355220 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147939 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 147939 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149683 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 149683 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 11960907 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 11960907 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11960907 # number of overall hits +system.cpu0.dcache.overall_hits::total 11960907 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 228053 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 228053 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 141722 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 141722 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9325 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 9325 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7497 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7497 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 369775 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 369775 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 369775 # number of overall misses +system.cpu0.dcache.overall_misses::total 369775 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3443053000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 3443053000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4918745500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 4918745500 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 100903000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 100903000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 74598000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 74598000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 8361798500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 8361798500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 8361798500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 8361798500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6833740 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6833740 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5496942 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5496942 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157264 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 157264 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157180 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 157180 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12330682 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12330682 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12330682 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12330682 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033372 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.033372 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025782 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.025782 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059295 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059295 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047697 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047697 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029988 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.029988 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029988 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.029988 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15097.600119 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15097.600119 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34707.000325 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 34707.000325 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10820.697051 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10820.697051 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9950.380152 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9950.380152 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 22613.206680 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 22613.206680 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 22613.206680 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 22613.206680 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -737,62 +767,66 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 306322 # number of writebacks -system.cpu0.dcache.writebacks::total 306322 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 228125 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 228125 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141749 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 141749 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9279 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9279 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7485 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7485 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 369874 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 369874 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 369874 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 369874 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2758091164 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2758091164 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4492431566 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4492431566 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 72483506 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 72483506 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 52154019 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 52154019 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7250522730 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 7250522730 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7250522730 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 7250522730 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 10425846000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 10425846000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 819721500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 819721500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11245567500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11245567500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033349 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033349 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025764 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025764 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059000 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059000 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047609 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047609 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029968 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029968 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029968 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.029968 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12090.262637 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12090.262637 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31692.862496 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31692.862496 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7811.564393 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7811.564393 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6967.804810 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6967.804810 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19602.682887 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19602.682887 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19602.682887 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19602.682887 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 306480 # number of writebacks +system.cpu0.dcache.writebacks::total 306480 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 228053 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 228053 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141722 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 141722 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9325 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9325 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7489 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7489 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 369775 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 369775 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 369775 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 369775 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2758299641 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2758299641 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4493384071 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4493384071 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 72902006 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 72902006 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 52119015 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 52119015 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1001 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1001 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7251683712 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 7251683712 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7251683712 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 7251683712 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13559859000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13559859000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1253198500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1253198500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14813057500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14813057500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033372 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033372 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025782 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025782 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059295 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059295 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047646 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047646 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029988 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029988 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029988 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.029988 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12094.993887 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12094.993887 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31705.621364 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31705.621364 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7817.909491 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7817.909491 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6959.409133 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6959.409133 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19611.070819 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19611.070819 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19611.070819 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19611.070819 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -802,26 +836,26 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 8314117 # DTB read hits -system.cpu1.dtb.read_misses 3669 # DTB read misses -system.cpu1.dtb.write_hits 5830380 # DTB write hits -system.cpu1.dtb.write_misses 1436 # DTB write misses +system.cpu1.dtb.read_hits 8318170 # DTB read hits +system.cpu1.dtb.read_misses 3663 # DTB read misses +system.cpu1.dtb.write_hits 5832653 # DTB write hits +system.cpu1.dtb.write_misses 1435 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1967 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1968 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 140 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 142 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 8317786 # DTB read accesses -system.cpu1.dtb.write_accesses 5831816 # DTB write accesses +system.cpu1.dtb.read_accesses 8321833 # DTB read accesses +system.cpu1.dtb.write_accesses 5834088 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 14144497 # DTB hits -system.cpu1.dtb.misses 5105 # DTB misses -system.cpu1.dtb.accesses 14149602 # DTB accesses -system.cpu1.itb.inst_hits 33196626 # ITB inst hits +system.cpu1.dtb.hits 14150823 # DTB hits +system.cpu1.dtb.misses 5098 # DTB misses +system.cpu1.dtb.accesses 14155921 # DTB accesses +system.cpu1.itb.inst_hits 33211066 # ITB inst hits system.cpu1.itb.inst_misses 2171 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -838,79 +872,79 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 33198797 # ITB inst accesses -system.cpu1.itb.hits 33196626 # DTB hits +system.cpu1.itb.inst_accesses 33213237 # ITB inst accesses +system.cpu1.itb.hits 33211066 # DTB hits system.cpu1.itb.misses 2171 # DTB misses -system.cpu1.itb.accesses 33198797 # DTB accesses -system.cpu1.numCycles 2343593518 # number of cpu cycles simulated +system.cpu1.itb.accesses 33213237 # DTB accesses +system.cpu1.numCycles 2413083038 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 32586009 # Number of instructions committed -system.cpu1.committedOps 41102854 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 37326288 # Number of integer alu accesses +system.cpu1.committedInsts 32600335 # Number of instructions committed +system.cpu1.committedOps 41120048 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 37342001 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses -system.cpu1.num_func_calls 962171 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3714570 # number of instructions that are conditional controls -system.cpu1.num_int_insts 37326288 # number of integer instructions +system.cpu1.num_func_calls 963082 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3716244 # number of instructions that are conditional controls +system.cpu1.num_int_insts 37342001 # number of integer instructions system.cpu1.num_fp_insts 6793 # number of float instructions -system.cpu1.num_int_register_reads 213739964 # number of times the integer registers were read -system.cpu1.num_int_register_writes 39466250 # number of times the integer registers were written +system.cpu1.num_int_register_reads 213831809 # number of times the integer registers were read +system.cpu1.num_int_register_writes 39482622 # number of times the integer registers were written system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written -system.cpu1.num_mem_refs 14682267 # number of memory refs -system.cpu1.num_load_insts 8636040 # Number of load instructions -system.cpu1.num_store_insts 6046227 # Number of store instructions -system.cpu1.num_idle_cycles 1858750530.714142 # Number of idle cycles -system.cpu1.num_busy_cycles 484842987.285858 # Number of busy cycles -system.cpu1.not_idle_fraction 0.206880 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.793120 # Percentage of idle cycles +system.cpu1.num_mem_refs 14689113 # number of memory refs +system.cpu1.num_load_insts 8640454 # Number of load instructions +system.cpu1.num_store_insts 6048659 # Number of store instructions +system.cpu1.num_idle_cycles 1863361909.381196 # Number of idle cycles +system.cpu1.num_busy_cycles 549721128.618804 # Number of busy cycles +system.cpu1.not_idle_fraction 0.227809 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.772191 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 43921 # number of quiesce instructions executed -system.cpu1.icache.replacements 454393 # number of replacements -system.cpu1.icache.tagsinuse 478.384673 # Cycle average of tags in use -system.cpu1.icache.total_refs 32741717 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 454905 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 71.974845 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 92994898000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 478.384673 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.934345 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.934345 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 32741717 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 32741717 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 32741717 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 32741717 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 32741717 # number of overall hits -system.cpu1.icache.overall_hits::total 32741717 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 454905 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 454905 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 454905 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 454905 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 454905 # number of overall misses -system.cpu1.icache.overall_misses::total 454905 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6718353500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 6718353500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 6718353500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 6718353500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 6718353500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 6718353500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 33196622 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 33196622 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 33196622 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 33196622 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 33196622 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 33196622 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013703 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.013703 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013703 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.013703 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013703 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.013703 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14768.695662 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 14768.695662 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14768.695662 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 14768.695662 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14768.695662 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 14768.695662 # average overall miss latency +system.cpu1.kern.inst.quiesce 43948 # number of quiesce instructions executed +system.cpu1.icache.replacements 455071 # number of replacements +system.cpu1.icache.tagsinuse 479.019014 # Cycle average of tags in use +system.cpu1.icache.total_refs 32755479 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 455583 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 71.897940 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 94151388000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 479.019014 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.935584 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.935584 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 32755479 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 32755479 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 32755479 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 32755479 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 32755479 # number of overall hits +system.cpu1.icache.overall_hits::total 32755479 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 455583 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 455583 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 455583 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 455583 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 455583 # number of overall misses +system.cpu1.icache.overall_misses::total 455583 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6728267000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 6728267000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 6728267000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 6728267000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 6728267000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 6728267000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 33211062 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 33211062 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 33211062 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 33211062 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 33211062 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 33211062 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013718 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.013718 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013718 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.013718 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013718 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.013718 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14768.476875 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 14768.476875 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14768.476875 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 14768.476875 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14768.476875 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 14768.476875 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -919,120 +953,120 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 454905 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 454905 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 454905 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 454905 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 454905 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 454905 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5352734000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5352734000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5352734000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5352734000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5352734000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5352734000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 455583 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 455583 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 455583 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 455583 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 455583 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 455583 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5360614000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5360614000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5360614000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5360614000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5360614000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5360614000 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5250000 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5250000 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5250000 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 5250000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013703 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013703 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013703 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.013703 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013703 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.013703 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11766.707334 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11766.707334 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11766.707334 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11766.707334 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11766.707334 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11766.707334 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013718 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013718 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013718 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.013718 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013718 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.013718 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11766.492604 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11766.492604 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11766.492604 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11766.492604 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11766.492604 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11766.492604 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 292476 # number of replacements -system.cpu1.dcache.tagsinuse 472.237187 # Cycle average of tags in use -system.cpu1.dcache.total_refs 11966907 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 292816 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 40.868351 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 84138671000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 472.237187 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.922338 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.922338 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 6949314 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 6949314 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4829723 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4829723 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 81817 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 81817 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 82772 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 82772 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 11779037 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 11779037 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 11779037 # number of overall hits -system.cpu1.dcache.overall_hits::total 11779037 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 170766 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 170766 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 150259 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 150259 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11112 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 11112 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10077 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10077 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 321025 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 321025 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 321025 # number of overall misses -system.cpu1.dcache.overall_misses::total 321025 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2375372000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2375372000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5143695000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 5143695000 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 106521500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 106521500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 88394000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 88394000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 7519067000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 7519067000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 7519067000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 7519067000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 7120080 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 7120080 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 4979982 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 4979982 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 92929 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 92929 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92849 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 92849 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 12100062 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 12100062 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 12100062 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 12100062 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023984 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.023984 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030173 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.030173 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119575 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119575 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108531 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108531 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026531 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.026531 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026531 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.026531 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13910.099200 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 13910.099200 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34232.192414 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 34232.192414 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9586.168107 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9586.168107 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8771.856703 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8771.856703 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23422.060587 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 23422.060587 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23422.060587 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 23422.060587 # average overall miss latency +system.cpu1.dcache.replacements 292605 # number of replacements +system.cpu1.dcache.tagsinuse 473.034253 # Cycle average of tags in use +system.cpu1.dcache.total_refs 11973075 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 292945 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 40.871409 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 85130110000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 473.034253 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.923895 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.923895 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 6952995 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 6952995 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4831955 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4831955 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 81928 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 81928 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 82891 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 82891 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 11784950 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 11784950 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 11784950 # number of overall hits +system.cpu1.dcache.overall_hits::total 11784950 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 170988 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 170988 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 150171 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 150171 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11121 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 11121 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10078 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10078 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 321159 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 321159 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 321159 # number of overall misses +system.cpu1.dcache.overall_misses::total 321159 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2374183000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2374183000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5137653000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 5137653000 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 106350500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 106350500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 87844000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 87844000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 7511836000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 7511836000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 7511836000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 7511836000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 7123983 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 7123983 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 4982126 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 4982126 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 93049 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 93049 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92969 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 92969 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 12106109 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 12106109 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 12106109 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 12106109 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.024002 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.024002 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030142 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.030142 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119518 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119518 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108402 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108402 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026529 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.026529 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026529 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.026529 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13885.085503 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13885.085503 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34212.018299 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 34212.018299 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9563.033900 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9563.033900 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8716.411987 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8716.411987 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23389.772667 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 23389.772667 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23389.772667 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 23389.772667 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1041,62 +1075,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 266164 # number of writebacks -system.cpu1.dcache.writebacks::total 266164 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170766 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 170766 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 150259 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 150259 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11112 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11112 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10067 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10067 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 321025 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 321025 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 321025 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 321025 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1862452631 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1862452631 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4692688176 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4692688176 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 73165002 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 73165002 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 58182011 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 58182011 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6555140807 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 6555140807 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6555140807 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 6555140807 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 136477204500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 136477204500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 39709759000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 39709759000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 176186963500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 176186963500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023984 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023984 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030173 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030173 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119575 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119575 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108423 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108423 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026531 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026531 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026531 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026531 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10906.460484 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10906.460484 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31230.662895 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31230.662895 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6584.323434 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6584.323434 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5779.478593 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5779.478593 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20419.409102 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20419.409102 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20419.409102 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20419.409102 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 266100 # number of writebacks +system.cpu1.dcache.writebacks::total 266100 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170988 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 170988 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 150171 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 150171 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11121 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11121 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10070 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10070 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 321159 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 321159 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 321159 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 321159 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1860610613 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1860610613 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4686894192 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4686894192 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 72963005 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 72963005 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 57623011 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 57623011 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6547504805 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 6547504805 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6547504805 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 6547504805 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168686172000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168686172000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 39932194000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 39932194000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 208618366000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 208618366000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024002 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.024002 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030142 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030142 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119518 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119518 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108316 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108316 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026529 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026529 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026529 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026529 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10881.527435 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10881.527435 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31210.381445 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31210.381445 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6560.831310 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6560.831310 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5722.245382 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5722.245382 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20387.112941 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20387.112941 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20387.112941 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20387.112941 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1118,10 +1152,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 550791407487 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 550791407487 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 550791407487 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 550791407487 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 574301885796 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 574301885796 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 574301885796 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 574301885796 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 724af2042..944186571 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,54 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.594328 # Number of seconds simulated -sim_ticks 2594327510000 # Number of ticks simulated -final_tick 2594327510000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.629150 # Number of seconds simulated +sim_ticks 2629149747000 # Number of ticks simulated +final_tick 2629149747000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 600896 # Simulator instruction rate (inst/s) -host_op_rate 764626 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 25897323777 # Simulator tick rate (ticks/s) -host_mem_usage 390576 # Number of bytes of host memory used -host_seconds 100.18 # Real time elapsed on the host -sim_insts 60196191 # Number of instructions simulated -sim_ops 76598245 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 704288 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9067216 # Number of bytes read from this memory -system.physmem.bytes_read::total 132455344 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 704288 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 704288 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3695616 # Number of bytes written to this memory -system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6711688 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 17207 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141709 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15494347 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57744 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811762 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47289092 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 123 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 271472 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3495016 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51055753 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 271472 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 271472 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1424499 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1162564 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2587063 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1424499 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47289092 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 123 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 271472 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4657580 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53642816 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 820445 # Simulator instruction rate (inst/s) +host_op_rate 1044003 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 35827378651 # Simulator tick rate (ticks/s) +host_mem_usage 386004 # Number of bytes of host memory used +host_seconds 73.38 # Real time elapsed on the host +sim_insts 60207390 # Number of instructions simulated +sim_ops 76612873 # Number of ops (including micro ops) simulated system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -61,141 +23,179 @@ system.realview.nvmem.bw_inst_read::cpu.inst 8 system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 62159 # number of replacements -system.l2c.tagsinuse 51417.185894 # Cycle average of tags in use -system.l2c.total_refs 1682923 # Total number of references to valid blocks. -system.l2c.sampled_refs 127542 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.195049 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2544924960000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 38023.288706 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 3.884784 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.itb.walker 0.000558 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 7004.395748 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 6385.616098 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.580189 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy +system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 705696 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9115408 # Number of bytes read from this memory +system.physmem.bytes_read::total 134077744 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 705696 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 705696 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3736256 # Number of bytes written to this memory +system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory +system.physmem.bytes_written::total 6752328 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 15532032 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 4 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 17229 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142462 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15691729 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58379 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory +system.physmem.num_writes::total 812397 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47261004 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 97 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 49 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 268412 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3467055 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50996618 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 268412 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 268412 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1421089 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1147166 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2568255 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1421089 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47261004 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 97 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 268412 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4614222 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53564873 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 62933 # number of replacements +system.l2c.tagsinuse 51862.510726 # Cycle average of tags in use +system.l2c.total_refs 1683379 # Total number of references to valid blocks. +system.l2c.sampled_refs 128318 # Sample count of references to valid blocks. +system.l2c.avg_refs 13.118806 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2576532162000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 38450.903251 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 2.914018 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.itb.walker 0.000670 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 7005.048584 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 6403.644203 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.586714 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.dtb.walker 0.000044 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.106879 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.097437 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.784564 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 8754 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 3544 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 843519 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 370124 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1225941 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 596001 # number of Writeback hits -system.l2c.Writeback_hits::total 596001 # number of Writeback hits +system.l2c.occ_percent::cpu.inst 0.106889 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.097712 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.791359 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 8836 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.itb.walker 3549 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.inst 844195 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 370308 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1226888 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 596416 # number of Writeback hits +system.l2c.Writeback_hits::total 596416 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 114391 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 114391 # number of ReadExReq hits -system.l2c.demand_hits::cpu.dtb.walker 8754 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.itb.walker 3544 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.inst 843519 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 484515 # number of demand (read+write) hits -system.l2c.demand_hits::total 1340332 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.dtb.walker 8754 # number of overall hits -system.l2c.overall_hits::cpu.itb.walker 3544 # number of overall hits -system.l2c.overall_hits::cpu.inst 843519 # number of overall hits -system.l2c.overall_hits::cpu.data 484515 # number of overall hits -system.l2c.overall_hits::total 1340332 # number of overall hits -system.l2c.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses +system.l2c.ReadExReq_hits::cpu.data 113846 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 113846 # number of ReadExReq hits +system.l2c.demand_hits::cpu.dtb.walker 8836 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.itb.walker 3549 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.inst 844195 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 484154 # number of demand (read+write) hits +system.l2c.demand_hits::total 1340734 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.dtb.walker 8836 # number of overall hits +system.l2c.overall_hits::cpu.itb.walker 3549 # number of overall hits +system.l2c.overall_hits::cpu.inst 844195 # number of overall hits +system.l2c.overall_hits::cpu.data 484154 # number of overall hits +system.l2c.overall_hits::total 1340734 # number of overall hits +system.l2c.ReadReq_misses::cpu.dtb.walker 4 # number of ReadReq misses system.l2c.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.inst 10591 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 10247 # number of ReadReq misses -system.l2c.ReadReq_misses::total 20845 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 2879 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2879 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 133059 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133059 # number of ReadExReq misses -system.l2c.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses +system.l2c.ReadReq_misses::cpu.inst 10613 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 10261 # number of ReadReq misses +system.l2c.ReadReq_misses::total 20880 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu.data 2845 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2845 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu.data 133824 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 133824 # number of ReadExReq misses +system.l2c.demand_misses::cpu.dtb.walker 4 # number of demand (read+write) misses system.l2c.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.inst 10591 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 143306 # number of demand (read+write) misses -system.l2c.demand_misses::total 153904 # number of demand (read+write) misses -system.l2c.overall_misses::cpu.dtb.walker 5 # number of overall misses +system.l2c.demand_misses::cpu.inst 10613 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 144085 # number of demand (read+write) misses +system.l2c.demand_misses::total 154704 # number of demand (read+write) misses +system.l2c.overall_misses::cpu.dtb.walker 4 # number of overall misses system.l2c.overall_misses::cpu.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu.inst 10591 # number of overall misses -system.l2c.overall_misses::cpu.data 143306 # number of overall misses -system.l2c.overall_misses::total 153904 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu.dtb.walker 260500 # number of ReadReq miss cycles +system.l2c.overall_misses::cpu.inst 10613 # number of overall misses +system.l2c.overall_misses::cpu.data 144085 # number of overall misses +system.l2c.overall_misses::total 154704 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu.dtb.walker 208000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu.itb.walker 104000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.inst 552260500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.data 533540500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1086165500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.inst 553137500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.data 534185000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1087634500 # number of ReadReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu.data 1040000 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::total 1040000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu.data 6923957000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6923957000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu.dtb.walker 260500 # number of demand (read+write) miss cycles +system.l2c.ReadExReq_miss_latency::cpu.data 6961477000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 6961477000 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu.dtb.walker 208000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu.itb.walker 104000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.inst 552260500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.data 7457497500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 8010122500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu.dtb.walker 260500 # number of overall miss cycles +system.l2c.demand_miss_latency::cpu.inst 553137500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.data 7495662000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 8049111500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu.dtb.walker 208000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu.itb.walker 104000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.inst 552260500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.data 7457497500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 8010122500 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu.dtb.walker 8759 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.itb.walker 3546 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.inst 854110 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 380371 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1246786 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 596001 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 596001 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu.data 2905 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2905 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu.data 247450 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 247450 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu.dtb.walker 8759 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.itb.walker 3546 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.inst 854110 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 627821 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1494236 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu.dtb.walker 8759 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.itb.walker 3546 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.inst 854110 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 627821 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1494236 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000571 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000564 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.012400 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.026939 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.016719 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu.data 0.991050 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.991050 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.537721 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.537721 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.dtb.walker 0.000571 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.itb.walker 0.000564 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.inst 0.012400 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.228259 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.102998 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.dtb.walker 0.000571 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.itb.walker 0.000564 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.inst 0.012400 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.228259 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.102998 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52100 # average ReadReq miss latency +system.l2c.overall_miss_latency::cpu.inst 553137500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.data 7495662000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 8049111500 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu.dtb.walker 8840 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.itb.walker 3551 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.inst 854808 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 380569 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1247768 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 596416 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 596416 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu.data 2871 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2871 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu.data 247670 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 247670 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu.dtb.walker 8840 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.itb.walker 3551 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.inst 854808 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 628239 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1495438 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu.dtb.walker 8840 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.itb.walker 3551 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.inst 854808 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.data 628239 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1495438 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000452 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000563 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.inst 0.012416 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.026962 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.016734 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu.data 0.990944 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.990944 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu.data 0.540332 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.540332 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu.dtb.walker 0.000452 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.itb.walker 0.000563 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.inst 0.012416 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.229347 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.103451 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.dtb.walker 0.000452 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.itb.walker 0.000563 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.inst 0.012416 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.229347 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.103451 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52000 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.inst 52144.320650 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.data 52067.971113 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52106.764212 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu.data 361.236540 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 361.236540 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu.data 52036.743099 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52036.743099 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52100 # average overall miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.inst 52118.863658 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.data 52059.740766 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52089.774904 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu.data 365.553603 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 365.553603 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu.data 52019.645206 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52019.645206 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52000 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.inst 52144.320650 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.data 52038.976037 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52046.226869 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52100 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.inst 52118.863658 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.data 52022.500607 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52029.110430 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52000 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.inst 52144.320650 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.data 52038.976037 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52046.226869 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.inst 52118.863658 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.data 52022.500607 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52029.110430 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -204,92 +204,92 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 57744 # number of writebacks -system.l2c.writebacks::total 57744 # number of writebacks -system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 5 # number of ReadReq MSHR misses +system.l2c.writebacks::writebacks 58379 # number of writebacks +system.l2c.writebacks::total 58379 # number of writebacks +system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 4 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.inst 10591 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.data 10247 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 20845 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu.data 2879 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 2879 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu.data 133059 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 133059 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu.dtb.walker 5 # number of demand (read+write) MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.inst 10613 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.data 10261 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 20880 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu.data 2845 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 2845 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu.data 133824 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 133824 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu.dtb.walker 4 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.inst 10591 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.data 143306 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 153904 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu.dtb.walker 5 # number of overall MSHR misses +system.l2c.demand_mshr_misses::cpu.inst 10613 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.data 144085 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 154704 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu.dtb.walker 4 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.inst 10591 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.data 143306 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 153904 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 200000 # number of ReadReq MSHR miss cycles +system.l2c.overall_mshr_misses::cpu.inst 10613 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.data 144085 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 154704 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 160000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 80000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.inst 425162000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.data 410573000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 836015000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 115365000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 115365000 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5327229000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5327229000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 200000 # number of demand (read+write) MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.inst 425775500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.data 411049000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 837064500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 114083000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 114083000 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5355569000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5355569000 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 160000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu.itb.walker 80000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.inst 425162000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.data 5737802000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 6163244000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 200000 # number of overall MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.inst 425775500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.data 5766618000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 6192633500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 160000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu.itb.walker 80000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.inst 425162000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.data 5737802000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 6163244000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.inst 425775500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.data 5766618000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 6192633500 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 264840000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131435179000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 131700019000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 31197392500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 31197392500 # number of WriteReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 166753837500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 167018677500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 31852864000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 31852864000 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu.inst 264840000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu.data 162632571500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 162897411500 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000571 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000564 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.012400 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.026939 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.016719 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.991050 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.991050 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.537721 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.537721 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000571 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000564 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.inst 0.012400 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.data 0.228259 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.102998 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000571 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000564 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.inst 0.012400 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.data 0.228259 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.102998 # mshr miss rate for overall accesses +system.l2c.overall_mshr_uncacheable_latency::cpu.data 198606701500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 198871541500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000452 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000563 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.012416 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.026962 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.016734 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.990944 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.990944 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.540332 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.540332 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000452 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000563 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.012416 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.229347 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.103451 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000452 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000563 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.012416 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.229347 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.103451 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40143.706921 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40067.629550 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40106.260494 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40071.205280 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40071.205280 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40036.592790 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40036.592790 # average ReadExReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40118.298313 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40059.350940 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40089.295977 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40099.472759 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40099.472759 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40019.495756 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40019.495756 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40143.706921 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40038.812053 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40046.028693 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40118.298313 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40022.334039 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40028.916512 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40143.706921 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40038.812053 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40046.028693 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40118.298313 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40022.334039 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40028.916512 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -307,26 +307,26 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 14995137 # DTB read hits -system.cpu.dtb.read_misses 7357 # DTB read misses -system.cpu.dtb.write_hits 11229787 # DTB write hits -system.cpu.dtb.write_misses 2205 # DTB write misses +system.cpu.dtb.read_hits 14998169 # DTB read hits +system.cpu.dtb.read_misses 7372 # DTB read misses +system.cpu.dtb.write_hits 11231565 # DTB write hits +system.cpu.dtb.write_misses 2270 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3485 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 3524 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 182 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 231 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 15002494 # DTB read accesses -system.cpu.dtb.write_accesses 11231992 # DTB write accesses +system.cpu.dtb.read_accesses 15005541 # DTB read accesses +system.cpu.dtb.write_accesses 11233835 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 26224924 # DTB hits -system.cpu.dtb.misses 9562 # DTB misses -system.cpu.dtb.accesses 26234486 # DTB accesses -system.cpu.itb.inst_hits 61490084 # ITB inst hits +system.cpu.dtb.hits 26229734 # DTB hits +system.cpu.dtb.misses 9642 # DTB misses +system.cpu.dtb.accesses 26239376 # DTB accesses +system.cpu.itb.inst_hits 61501359 # ITB inst hits system.cpu.itb.inst_misses 4471 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -343,79 +343,79 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 61494555 # ITB inst accesses -system.cpu.itb.hits 61490084 # DTB hits +system.cpu.itb.inst_accesses 61505830 # ITB inst accesses +system.cpu.itb.hits 61501359 # DTB hits system.cpu.itb.misses 4471 # DTB misses -system.cpu.itb.accesses 61494555 # DTB accesses -system.cpu.numCycles 5188655020 # number of cpu cycles simulated +system.cpu.itb.accesses 61505830 # DTB accesses +system.cpu.numCycles 5258299494 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60196191 # Number of instructions committed -system.cpu.committedOps 76598245 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 68865648 # Number of integer alu accesses +system.cpu.committedInsts 60207390 # Number of instructions committed +system.cpu.committedOps 76612873 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 68878830 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses -system.cpu.num_func_calls 2139540 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7910583 # number of instructions that are conditional controls -system.cpu.num_int_insts 68865648 # number of integer instructions +system.cpu.num_func_calls 2140176 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7911775 # number of instructions that are conditional controls +system.cpu.num_int_insts 68878830 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions -system.cpu.num_int_register_reads 394743471 # number of times the integer registers were read -system.cpu.num_int_register_writes 74177139 # number of times the integer registers were written +system.cpu.num_int_register_reads 394820534 # number of times the integer registers were read +system.cpu.num_int_register_writes 74191435 # number of times the integer registers were written system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written -system.cpu.num_mem_refs 27392126 # number of memory refs -system.cpu.num_load_insts 15659006 # Number of load instructions -system.cpu.num_store_insts 11733120 # Number of store instructions -system.cpu.num_idle_cycles 4570211154.554238 # Number of idle cycles -system.cpu.num_busy_cycles 618443865.445762 # Number of busy cycles -system.cpu.not_idle_fraction 0.119192 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.880808 # Percentage of idle cycles +system.cpu.num_mem_refs 27397151 # number of memory refs +system.cpu.num_load_insts 15662227 # Number of load instructions +system.cpu.num_store_insts 11734924 # Number of store instructions +system.cpu.num_idle_cycles 4567780450.602262 # Number of idle cycles +system.cpu.num_busy_cycles 690519043.397737 # Number of busy cycles +system.cpu.not_idle_fraction 0.131320 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.868680 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 82989 # number of quiesce instructions executed -system.cpu.icache.replacements 855220 # number of replacements -system.cpu.icache.tagsinuse 510.929118 # Cycle average of tags in use -system.cpu.icache.total_refs 60634352 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 855732 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 70.856707 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 18856022000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.929118 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.997908 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.997908 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 60634352 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 60634352 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 60634352 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 60634352 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 60634352 # number of overall hits -system.cpu.icache.overall_hits::total 60634352 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 855732 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 855732 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 855732 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 855732 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 855732 # number of overall misses -system.cpu.icache.overall_misses::total 855732 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12556184500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12556184500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12556184500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12556184500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12556184500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12556184500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 61490084 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 61490084 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 61490084 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 61490084 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 61490084 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 61490084 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013917 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.013917 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.013917 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.013917 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.013917 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.013917 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14673.033730 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14673.033730 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14673.033730 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14673.033730 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14673.033730 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14673.033730 # average overall miss latency +system.cpu.kern.inst.quiesce 83013 # number of quiesce instructions executed +system.cpu.icache.replacements 855930 # number of replacements +system.cpu.icache.tagsinuse 510.898307 # Cycle average of tags in use +system.cpu.icache.total_refs 60644917 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 856442 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 70.810302 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 19819985000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.898307 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.997848 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.997848 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 60644917 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 60644917 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 60644917 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 60644917 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 60644917 # number of overall hits +system.cpu.icache.overall_hits::total 60644917 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 856442 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 856442 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 856442 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 856442 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 856442 # number of overall misses +system.cpu.icache.overall_misses::total 856442 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12566277500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12566277500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12566277500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12566277500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12566277500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12566277500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 61501359 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 61501359 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 61501359 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 61501359 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 61501359 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 61501359 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013926 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.013926 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.013926 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.013926 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.013926 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.013926 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14672.654424 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14672.654424 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14672.654424 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14672.654424 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14672.654424 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14672.654424 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -424,112 +424,112 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855732 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 855732 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 855732 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 855732 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 855732 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 855732 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9987081500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9987081500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9987081500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9987081500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9987081500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9987081500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856442 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 856442 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 856442 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 856442 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 856442 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 856442 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9995044500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9995044500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9995044500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9995044500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9995044500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9995044500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 350913000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 350913000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 350913000 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 350913000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013917 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013917 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013917 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.013917 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013917 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.013917 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11670.805229 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11670.805229 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11670.805229 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11670.805229 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11670.805229 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11670.805229 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013926 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013926 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013926 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.013926 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013926 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.013926 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11670.427770 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11670.427770 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11670.427770 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11670.427770 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11670.427770 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11670.427770 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 627309 # number of replacements -system.cpu.dcache.tagsinuse 511.875626 # Cycle average of tags in use -system.cpu.dcache.total_refs 23653426 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 627821 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 37.675430 # Average number of references to valid blocks. +system.cpu.dcache.replacements 627727 # number of replacements +system.cpu.dcache.tagsinuse 511.877273 # Cycle average of tags in use +system.cpu.dcache.total_refs 23657788 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 628239 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 37.657306 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 661351000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.875626 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999757 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999757 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13194612 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13194612 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 9972158 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 9972158 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 236094 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 236094 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247657 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247657 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 23166770 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 23166770 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 23166770 # number of overall hits -system.cpu.dcache.overall_hits::total 23166770 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 368807 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 368807 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 250355 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 250355 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 11564 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 11564 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 619162 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 619162 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 619162 # number of overall misses -system.cpu.dcache.overall_misses::total 619162 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5738700500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5738700500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9229453000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9229453000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 171857500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 171857500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 14968153500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 14968153500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 14968153500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 14968153500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13563419 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13563419 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10222513 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10222513 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247658 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 247658 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 247657 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 247657 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 23785932 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 23785932 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 23785932 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 23785932 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027191 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.027191 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024491 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.024491 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046693 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046693 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.026031 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.026031 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.026031 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.026031 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15560.172394 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15560.172394 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36865.463042 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 36865.463042 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14861.423383 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14861.423383 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 24174.858115 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 24174.858115 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 24174.858115 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 24174.858115 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 511.877273 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999760 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999760 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 13196825 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13196825 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 9973191 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 9973191 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 236701 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 236701 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 248200 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 248200 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 23170016 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 23170016 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 23170016 # number of overall hits +system.cpu.dcache.overall_hits::total 23170016 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 369069 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 369069 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 250541 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 250541 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 11500 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 11500 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 619610 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 619610 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 619610 # number of overall misses +system.cpu.dcache.overall_misses::total 619610 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5742174000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5742174000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9260838000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9260838000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 170995500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 170995500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 15003012000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 15003012000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 15003012000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 15003012000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13565894 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13565894 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10223732 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10223732 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 248201 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 248201 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 248200 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 248200 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 23789626 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 23789626 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 23789626 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 23789626 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027206 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.027206 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024506 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.024506 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046333 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046333 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.026045 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.026045 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.026045 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.026045 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15558.537834 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15558.537834 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36963.363282 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 36963.363282 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14869.173913 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14869.173913 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 24213.637611 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 24213.637611 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 24213.637611 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 24213.637611 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -538,54 +538,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 596001 # number of writebacks -system.cpu.dcache.writebacks::total 596001 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368807 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 368807 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250355 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 250355 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11564 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 11564 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 619162 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 619162 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 619162 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 619162 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4631124500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4631124500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8478310000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8478310000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 137164000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 137164000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13109434500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13109434500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13109434500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13109434500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 146832035500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 146832035500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 40357680500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 40357680500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 187189716000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 187189716000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027191 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027191 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024491 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024491 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046693 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046693 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026031 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.026031 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026031 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.026031 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12557.040674 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12557.040674 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33865.151485 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33865.151485 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11861.293670 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11861.293670 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21172.866713 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 21172.866713 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21172.866713 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 21172.866713 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 596416 # number of writebacks +system.cpu.dcache.writebacks::total 596416 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 369069 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 369069 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250541 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 250541 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11500 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 11500 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 619610 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 619610 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 619610 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 619610 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4633803000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4633803000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8509109000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8509109000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 136482000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 136482000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13142912000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13142912000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13142912000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13142912000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182150932500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182150932500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41013343500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41013343500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 223164276000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 223164276000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027206 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027206 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024506 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024506 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046333 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046333 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026045 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.026045 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026045 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.026045 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12555.383953 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12555.383953 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33962.940197 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33962.940197 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11868 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11868 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21211.587934 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 21211.587934 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21211.587934 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 21211.587934 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -607,10 +607,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1342178832750 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1342178832750 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1342178832750 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1342178832750 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1358668189629 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1358668189629 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1358668189629 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1358668189629 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index a4ae62a22..2aa8a86ab 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -1,168 +1,168 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.191766 # Number of seconds simulated -sim_ticks 5191766314000 # Number of ticks simulated -final_tick 5191766314000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.196043 # Number of seconds simulated +sim_ticks 5196043137000 # Number of ticks simulated +final_tick 5196043137000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 787684 # Simulator instruction rate (inst/s) -host_op_rate 1511929 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 29598304712 # Simulator tick rate (ticks/s) -host_mem_usage 358992 # Number of bytes of host memory used -host_seconds 175.41 # Real time elapsed on the host -sim_insts 138165780 # Number of instructions simulated -sim_ops 265203824 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2891072 # Number of bytes read from this memory +host_inst_rate 1241473 # Simulator instruction rate (inst/s) +host_op_rate 2393258 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 50303585789 # Simulator tick rate (ticks/s) +host_mem_usage 354304 # Number of bytes of host memory used +host_seconds 103.29 # Real time elapsed on the host +sim_insts 128236332 # Number of instructions simulated +sim_ops 247208442 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2881344 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 821248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8939328 # Number of bytes read from this memory -system.physmem.bytes_read::total 12651968 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 821248 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 821248 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8080768 # Number of bytes written to this memory -system.physmem.bytes_written::total 8080768 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 45173 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu.inst 824320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8950528 # Number of bytes read from this memory +system.physmem.bytes_read::total 12656512 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 824320 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 824320 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8081152 # Number of bytes written to this memory +system.physmem.bytes_written::total 8081152 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 45021 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12832 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 139677 # Number of read requests responded to by this memory -system.physmem.num_reads::total 197687 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 126262 # Number of write requests responded to by this memory -system.physmem.num_writes::total 126262 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 556857 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu.inst 12880 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 139852 # Number of read requests responded to by this memory +system.physmem.num_reads::total 197758 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 126268 # Number of write requests responded to by this memory +system.physmem.num_writes::total 126268 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 554527 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 158183 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1721828 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2436929 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 158183 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 158183 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1556458 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1556458 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1556458 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 556857 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 158644 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1722566 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2435798 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 158644 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 158644 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1555251 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1555251 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1555251 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 554527 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 158183 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1721828 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3993388 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 86221 # number of replacements -system.l2c.tagsinuse 64766.656127 # Cycle average of tags in use -system.l2c.total_refs 3490237 # Total number of references to valid blocks. -system.l2c.sampled_refs 150947 # Sample count of references to valid blocks. -system.l2c.avg_refs 23.122268 # Average number of references to valid blocks. +system.physmem.bw_total::cpu.inst 158644 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1722566 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3991049 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 86291 # number of replacements +system.l2c.tagsinuse 64759.780052 # Cycle average of tags in use +system.l2c.total_refs 3494113 # Total number of references to valid blocks. +system.l2c.sampled_refs 150981 # Sample count of references to valid blocks. +system.l2c.avg_refs 23.142733 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 50170.355166 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.itb.walker 0.141198 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 3484.481205 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 11111.678558 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.765539 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 50071.847750 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.itb.walker 0.141309 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 3396.359734 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 11291.431260 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.764036 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.053169 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.169551 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.988261 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 6306 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 2757 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 777565 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 1279351 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2065979 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 1541329 # number of Writeback hits -system.l2c.Writeback_hits::total 1541329 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu.data 319 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 319 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 200451 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 200451 # number of ReadExReq hits -system.l2c.demand_hits::cpu.dtb.walker 6306 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.itb.walker 2757 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.inst 777565 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 1479802 # number of demand (read+write) hits -system.l2c.demand_hits::total 2266430 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.dtb.walker 6306 # number of overall hits -system.l2c.overall_hits::cpu.itb.walker 2757 # number of overall hits -system.l2c.overall_hits::cpu.inst 777565 # number of overall hits -system.l2c.overall_hits::cpu.data 1479802 # number of overall hits -system.l2c.overall_hits::total 2266430 # number of overall hits +system.l2c.occ_percent::cpu.inst 0.051824 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.172294 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.988156 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 6458 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.itb.walker 2811 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.inst 779608 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 1280721 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2069598 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 1543757 # number of Writeback hits +system.l2c.Writeback_hits::total 1543757 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu.data 305 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 305 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu.data 200867 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 200867 # number of ReadExReq hits +system.l2c.demand_hits::cpu.dtb.walker 6458 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.itb.walker 2811 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.inst 779608 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 1481588 # number of demand (read+write) hits +system.l2c.demand_hits::total 2270465 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.dtb.walker 6458 # number of overall hits +system.l2c.overall_hits::cpu.itb.walker 2811 # number of overall hits +system.l2c.overall_hits::cpu.inst 779608 # number of overall hits +system.l2c.overall_hits::cpu.data 1481588 # number of overall hits +system.l2c.overall_hits::total 2270465 # number of overall hits system.l2c.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.inst 12833 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 28373 # number of ReadReq misses -system.l2c.ReadReq_misses::total 41211 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 1346 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1346 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 112235 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 112235 # number of ReadExReq misses +system.l2c.ReadReq_misses::cpu.inst 12881 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 28319 # number of ReadReq misses +system.l2c.ReadReq_misses::total 41205 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu.data 1371 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 1371 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu.data 112462 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 112462 # number of ReadExReq misses system.l2c.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.inst 12833 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 140608 # number of demand (read+write) misses -system.l2c.demand_misses::total 153446 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.inst 12881 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 140781 # number of demand (read+write) misses +system.l2c.demand_misses::total 153667 # number of demand (read+write) misses system.l2c.overall_misses::cpu.itb.walker 5 # number of overall misses -system.l2c.overall_misses::cpu.inst 12833 # number of overall misses -system.l2c.overall_misses::cpu.data 140608 # number of overall misses -system.l2c.overall_misses::total 153446 # number of overall misses +system.l2c.overall_misses::cpu.inst 12881 # number of overall misses +system.l2c.overall_misses::cpu.data 140781 # number of overall misses +system.l2c.overall_misses::total 153667 # number of overall misses system.l2c.ReadReq_miss_latency::cpu.itb.walker 260000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.inst 667948500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.data 1489806000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 2158014500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu.data 32975000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 32975000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu.data 5839097000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 5839097000 # number of ReadExReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.inst 670242000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.data 1486972500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 2157474500 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu.data 34071000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 34071000 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu.data 5850445000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 5850445000 # number of ReadExReq miss cycles system.l2c.demand_miss_latency::cpu.itb.walker 260000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.inst 667948500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.data 7328903000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 7997111500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.inst 670242000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.data 7337417500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 8007919500 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu.itb.walker 260000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.inst 667948500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.data 7328903000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 7997111500 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu.dtb.walker 6306 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.itb.walker 2762 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.inst 790398 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 1307724 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2107190 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 1541329 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1541329 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu.data 1665 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 1665 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu.data 312686 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 312686 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu.dtb.walker 6306 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.itb.walker 2762 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.inst 790398 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 1620410 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2419876 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu.dtb.walker 6306 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.itb.walker 2762 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.inst 790398 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 1620410 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2419876 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001810 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.016236 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.021696 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.019557 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu.data 0.808408 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.808408 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.358938 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.358938 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.itb.walker 0.001810 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.inst 0.016236 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.086773 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.063411 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.itb.walker 0.001810 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.inst 0.016236 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.086773 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.063411 # miss rate for overall accesses +system.l2c.overall_miss_latency::cpu.inst 670242000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.data 7337417500 # number of overall miss cycles +system.l2c.overall_miss_latency::total 8007919500 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu.dtb.walker 6458 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.itb.walker 2816 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.inst 792489 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 1309040 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2110803 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 1543757 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 1543757 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu.data 1676 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 1676 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu.data 313329 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 313329 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu.dtb.walker 6458 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.itb.walker 2816 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.inst 792489 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 1622369 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2424132 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu.dtb.walker 6458 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.itb.walker 2816 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.inst 792489 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.data 1622369 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2424132 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001776 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.inst 0.016254 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.021633 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.019521 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu.data 0.818019 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.818019 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu.data 0.358926 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.358926 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu.itb.walker 0.001776 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.inst 0.016254 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.086775 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.063391 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.itb.walker 0.001776 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.inst 0.016254 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.086775 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.063391 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.inst 52049.286994 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.data 52507.877207 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52365.011769 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu.data 24498.514116 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 24498.514116 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu.data 52025.633715 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52025.633715 # average ReadExReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.inst 52033.382501 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.data 52507.945196 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52359.531610 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu.data 24851.203501 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 24851.203501 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu.data 52021.527271 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52021.527271 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.inst 52049.286994 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.data 52122.944640 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52116.780496 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.inst 52033.382501 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.data 52119.373353 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52112.161362 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.inst 52049.286994 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.data 52122.944640 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52116.780496 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.inst 52033.382501 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.data 52119.373353 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52112.161362 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -171,78 +171,78 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 79595 # number of writebacks -system.l2c.writebacks::total 79595 # number of writebacks +system.l2c.writebacks::writebacks 79601 # number of writebacks +system.l2c.writebacks::total 79601 # number of writebacks system.l2c.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.inst 12833 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.data 28373 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 41211 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu.data 1346 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 1346 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu.data 112235 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 112235 # number of ReadExReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.inst 12881 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.data 28319 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 41205 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu.data 1371 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 1371 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu.data 112462 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 112462 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.inst 12833 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.data 140608 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 153446 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.inst 12881 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.data 140781 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 153667 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.inst 12833 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.data 140608 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 153446 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.inst 12881 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.data 140781 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 153667 # number of overall MSHR misses system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 200000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.inst 513944000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.data 1149325000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1663469000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 54216000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 54216000 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4492274000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 4492274000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.inst 515661000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.data 1147140000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1663001000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 55229000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 55229000 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4500898000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 4500898000 # number of ReadExReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu.itb.walker 200000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.inst 513944000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.data 5641599000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 6155743000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.inst 515661000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.data 5648038000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 6163899000 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu.itb.walker 200000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.inst 513944000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.data 5641599000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 6155743000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 56050191064 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 56050191064 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1204378000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1204378000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu.data 57254569064 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 57254569064 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001810 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.016236 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.021696 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.019557 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.808408 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.808408 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.358938 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.358938 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.001810 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.inst 0.016236 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.data 0.086773 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.063411 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.001810 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.inst 0.016236 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.data 0.086773 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.063411 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_latency::cpu.inst 515661000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.data 5648038000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 6163899000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 86117450000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 86117450000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 2306140000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2306140000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.data 88423590000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 88423590000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001776 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.016254 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.021633 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.019521 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.818019 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.818019 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.358926 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.358926 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.001776 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.016254 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.086775 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.063391 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.001776 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.016254 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.086775 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.063391 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40048.624640 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40507.700983 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40364.684186 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40279.346211 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40279.346211 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40025.606985 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40025.606985 # average ReadExReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40032.683798 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40507.786292 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40359.203980 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40283.734500 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40283.734500 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40021.500596 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40021.500596 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40048.624640 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40122.887745 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40116.672966 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40032.683798 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40119.320079 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40112.053987 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40048.624640 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40122.887745 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40116.672966 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40032.683798 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40119.320079 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40112.053987 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -250,39 +250,39 @@ system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 47504 # number of replacements -system.iocache.tagsinuse 0.108710 # Cycle average of tags in use +system.iocache.replacements 47503 # number of replacements +system.iocache.tagsinuse 0.108785 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47520 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47519 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 5048944307000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.108710 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.006794 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.006794 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 839 # number of ReadReq misses -system.iocache.ReadReq_misses::total 839 # number of ReadReq misses +system.iocache.warmup_cycle 5053216388000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::pc.south_bridge.ide 0.108785 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.006799 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.006799 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 838 # number of ReadReq misses +system.iocache.ReadReq_misses::total 838 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47559 # number of demand (read+write) misses -system.iocache.demand_misses::total 47559 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47559 # number of overall misses -system.iocache.overall_misses::total 47559 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 128944932 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 128944932 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 7159405160 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 7159405160 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 7288350092 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 7288350092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 7288350092 # number of overall miss cycles -system.iocache.overall_miss_latency::total 7288350092 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 839 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 839 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47558 # number of demand (read+write) misses +system.iocache.demand_misses::total 47558 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47558 # number of overall misses +system.iocache.overall_misses::total 47558 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 128838932 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 128838932 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 7147789160 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 7147789160 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 7276628092 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 7276628092 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 7276628092 # number of overall miss cycles +system.iocache.overall_miss_latency::total 7276628092 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 838 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 838 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47559 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47559 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47559 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47559 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47558 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47558 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47558 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47558 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -291,14 +291,14 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 153688.834327 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 153688.834327 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 153240.692637 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 153240.692637 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 153248.598415 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 153248.598415 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 153248.598415 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 153248.598415 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 153745.742243 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 153745.742243 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 152992.062500 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 152992.062500 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 153005.342781 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 153005.342781 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 153005.342781 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 153005.342781 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 372008 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 38 # number of cycles access was blocked @@ -309,22 +309,22 @@ system.iocache.fast_writes 0 # nu system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 839 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 839 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 838 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 838 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47559 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47559 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47559 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47559 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 85286000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 85286000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 4729709976 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 4729709976 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4814995976 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 4814995976 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4814995976 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 4814995976 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47558 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47558 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47558 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47558 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 85232000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 85232000 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 4718093984 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 4718093984 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4803325984 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 4803325984 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4803325984 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 4803325984 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -333,14 +333,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 101651.966627 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 101651.966627 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 101235.230651 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 101235.230651 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 101242.582392 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 101242.582392 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 101242.582392 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 101242.582392 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 101708.830549 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 101708.830549 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 100986.600685 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 100986.600685 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 100999.326801 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 100999.326801 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 100999.326801 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 100999.326801 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -354,75 +354,75 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 10383532628 # number of cpu cycles simulated +system.cpu.numCycles 10392086274 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 138165780 # Number of instructions committed -system.cpu.committedOps 265203824 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 249613019 # Number of integer alu accesses +system.cpu.committedInsts 128236332 # Number of instructions committed +system.cpu.committedOps 247208442 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 231946757 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 24887741 # number of instructions that are conditional controls -system.cpu.num_int_insts 249613019 # number of integer instructions +system.cpu.num_conditional_control_insts 23151326 # number of instructions that are conditional controls +system.cpu.num_int_insts 231946757 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 778264795 # number of times the integer registers were read -system.cpu.num_int_register_writes 423017346 # number of times the integer registers were written +system.cpu.num_int_register_reads 720715933 # number of times the integer registers were read +system.cpu.num_int_register_writes 387556667 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 23180616 # number of memory refs -system.cpu.num_load_insts 14822216 # Number of load instructions -system.cpu.num_store_insts 8358400 # Number of store instructions -system.cpu.num_idle_cycles 9771874926.286118 # Number of idle cycles -system.cpu.num_busy_cycles 611657701.713882 # Number of busy cycles -system.cpu.not_idle_fraction 0.058907 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.941093 # Percentage of idle cycles +system.cpu.num_mem_refs 22230275 # number of memory refs +system.cpu.num_load_insts 13869948 # Number of load instructions +system.cpu.num_store_insts 8360327 # Number of store instructions +system.cpu.num_idle_cycles 9776409858.670118 # Number of idle cycles +system.cpu.num_busy_cycles 615676415.329882 # Number of busy cycles +system.cpu.not_idle_fraction 0.059245 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.940755 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.icache.replacements 789892 # number of replacements -system.cpu.icache.tagsinuse 510.351457 # Cycle average of tags in use -system.cpu.icache.total_refs 158472876 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 790404 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 200.496045 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 160421909000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.351457 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996780 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996780 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 158472876 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 158472876 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 158472876 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 158472876 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 158472876 # number of overall hits -system.cpu.icache.overall_hits::total 158472876 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 790411 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 790411 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 790411 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 790411 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 790411 # number of overall misses -system.cpu.icache.overall_misses::total 790411 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11780909500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11780909500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11780909500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11780909500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11780909500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11780909500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 159263287 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 159263287 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 159263287 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 159263287 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 159263287 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 159263287 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.004963 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.004963 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.004963 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.004963 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.004963 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.004963 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14904.789407 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14904.789407 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14904.789407 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14904.789407 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14904.789407 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14904.789407 # average overall miss latency +system.cpu.icache.replacements 791983 # number of replacements +system.cpu.icache.tagsinuse 510.339207 # Cycle average of tags in use +system.cpu.icache.total_refs 144447737 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 792495 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 182.269588 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 160970951000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.339207 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.996756 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.996756 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 144447737 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 144447737 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 144447737 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 144447737 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 144447737 # number of overall hits +system.cpu.icache.overall_hits::total 144447737 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 792502 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 792502 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 792502 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 792502 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 792502 # number of overall misses +system.cpu.icache.overall_misses::total 792502 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11813272500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11813272500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11813272500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11813272500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11813272500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11813272500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 145240239 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 145240239 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 145240239 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 145240239 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 145240239 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 145240239 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005456 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.005456 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.005456 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.005456 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.005456 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.005456 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14906.299921 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14906.299921 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14906.299921 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14906.299921 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14906.299921 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14906.299921 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -431,80 +431,80 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 790411 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 790411 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 790411 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 790411 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 790411 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 790411 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9408658500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9408658500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9408658500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9408658500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9408658500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9408658500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.004963 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.004963 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.004963 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.004963 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.004963 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.004963 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11903.501469 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11903.501469 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11903.501469 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11903.501469 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11903.501469 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11903.501469 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 792502 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 792502 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 792502 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 792502 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 792502 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 792502 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9434751000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9434751000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9434751000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9434751000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9434751000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9434751000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005456 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005456 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005456 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.005456 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005456 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.005456 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11905.018536 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11905.018536 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11905.018536 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11905.018536 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11905.018536 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11905.018536 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 3403 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 3.070913 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 8040 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 3415 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 2.354319 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5164836918000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.070913 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.191932 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.191932 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 8060 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 8060 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 3538 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 3.068811 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 7893 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 3550 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 2.223380 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5169410055000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.068811 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.191801 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.191801 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7916 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 7916 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 8062 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 8062 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 8062 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 8062 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4266 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 4266 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4266 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 4266 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4266 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 4266 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 50418000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 50418000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 50418000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 50418000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 50418000 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 50418000 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12326 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 12326 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7918 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 7918 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7918 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 7918 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4398 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 4398 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4398 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 4398 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4398 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 4398 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 51351000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 51351000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 51351000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 51351000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 51351000 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 51351000 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12314 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 12314 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12328 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 12328 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12328 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 12328 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.346098 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.346098 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.346042 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.346042 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.346042 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.346042 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11818.565401 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11818.565401 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11818.565401 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11818.565401 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11818.565401 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11818.565401 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12316 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 12316 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12316 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 12316 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.357154 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.357154 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.357096 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.357096 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.357096 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.357096 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11675.989086 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11675.989086 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11675.989086 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11675.989086 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11675.989086 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11675.989086 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -513,78 +513,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 726 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 726 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4266 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4266 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4266 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 4266 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4266 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 4266 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 37620000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 37620000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 37620000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 37620000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 37620000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 37620000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.346098 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.346098 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.346042 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.346042 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.346042 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.346042 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8818.565401 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8818.565401 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8818.565401 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8818.565401 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8818.565401 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8818.565401 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 656 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 656 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4398 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4398 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4398 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 4398 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4398 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 4398 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 38157000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 38157000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 38157000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 38157000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 38157000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 38157000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.357154 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.357154 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.357096 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.357096 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.357096 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.357096 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8675.989086 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8675.989086 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8675.989086 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8675.989086 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8675.989086 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8675.989086 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 7529 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 5.053120 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 13331 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 7543 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.767334 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5161009077000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.053120 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.315820 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.315820 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13332 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 13332 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13332 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 13332 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13332 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 13332 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8729 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 8729 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8729 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 8729 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8729 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 8729 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 112265000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 112265000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 112265000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 112265000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 112265000 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 112265000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22061 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 22061 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22061 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 22061 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22061 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 22061 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.395676 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.395676 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.395676 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.395676 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.395676 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.395676 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12861.152480 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12861.152480 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12861.152480 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12861.152480 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12861.152480 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12861.152480 # average overall miss latency +system.cpu.dtb_walker_cache.replacements 7615 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 5.050606 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 13416 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 7630 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.758322 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5165509990000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.050606 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.315663 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.315663 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13416 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 13416 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13416 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 13416 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13416 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 13416 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8830 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 8830 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8830 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 8830 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8830 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 8830 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 114790500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 114790500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 114790500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 114790500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 114790500 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 114790500 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22246 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 22246 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22246 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 22246 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22246 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 22246 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.396925 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.396925 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.396925 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.396925 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.396925 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.396925 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 13000.056625 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 13000.056625 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 13000.056625 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 13000.056625 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 13000.056625 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 13000.056625 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -593,90 +593,90 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 2916 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 2916 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8729 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8729 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8729 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 8729 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8729 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 8729 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 86078000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 86078000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 86078000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 86078000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 86078000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 86078000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.395676 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.395676 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.395676 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.395676 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.395676 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.395676 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 9861.152480 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9861.152480 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 9861.152480 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 9861.152480 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 9861.152480 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 9861.152480 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 3005 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 3005 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8830 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8830 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8830 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 8830 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8830 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 8830 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 88300000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 88300000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 88300000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 88300000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 88300000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 88300000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.396925 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.396925 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.396925 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.396925 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.396925 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.396925 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10000 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10000 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10000 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10000 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10000 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10000 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1620698 # number of replacements -system.cpu.dcache.tagsinuse 511.997463 # Cycle average of tags in use -system.cpu.dcache.total_refs 20024816 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1621210 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.351772 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1622589 # number of replacements +system.cpu.dcache.tagsinuse 511.997330 # Cycle average of tags in use +system.cpu.dcache.total_refs 20023565 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1623101 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12.336611 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 45838000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.997463 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 511.997330 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999995 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 11989143 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11989143 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8033492 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8033492 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 20022635 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20022635 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20022635 # number of overall hits -system.cpu.dcache.overall_hits::total 20022635 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1308550 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1308550 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 314872 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 314872 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1623422 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1623422 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1623422 # number of overall misses -system.cpu.dcache.overall_misses::total 1623422 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 19872663500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 19872663500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9327755500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9327755500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 29200419000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 29200419000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 29200419000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 29200419000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13297693 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13297693 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8348364 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8348364 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21646057 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21646057 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21646057 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21646057 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098404 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.098404 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037717 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037717 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.074999 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.074999 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.074999 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.074999 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15186.781934 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15186.781934 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29623.959895 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 29623.959895 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 17986.955333 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 17986.955333 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 17986.955333 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 17986.955333 # average overall miss latency +system.cpu.dcache.ReadReq_hits::cpu.data 11986605 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11986605 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8034775 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8034775 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 20021380 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20021380 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20021380 # number of overall hits +system.cpu.dcache.overall_hits::total 20021380 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1309816 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1309816 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 315519 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 315519 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1625335 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1625335 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1625335 # number of overall misses +system.cpu.dcache.overall_misses::total 1625335 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 19889195500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 19889195500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9348149500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9348149500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 29237345000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 29237345000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 29237345000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 29237345000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13296421 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13296421 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8350294 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8350294 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21646715 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21646715 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21646715 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21646715 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098509 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.098509 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037785 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037785 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.075085 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.075085 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.075085 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.075085 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15184.724801 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15184.724801 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29627.849670 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 29627.849670 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 17988.503908 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 17988.503908 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 17988.503908 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 17988.503908 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -685,46 +685,46 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1537687 # number of writebacks -system.cpu.dcache.writebacks::total 1537687 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1308550 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1308550 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 314872 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 314872 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1623422 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1623422 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1623422 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1623422 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15946963002 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 15946963002 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8383136001 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8383136001 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24330099003 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 24330099003 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24330099003 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 24330099003 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 75924400500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 75924400500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1366040500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1366040500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 77290441000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 77290441000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098404 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098404 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037717 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037717 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074999 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.074999 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074999 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.074999 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12186.743343 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12186.743343 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26623.948782 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26623.948782 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14986.922071 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 14986.922071 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14986.922071 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 14986.922071 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1540096 # number of writebacks +system.cpu.dcache.writebacks::total 1540096 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1309816 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1309816 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315519 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 315519 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1625335 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1625335 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1625335 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1625335 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15959698500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 15959698500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8401590001 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8401590001 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24361288501 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 24361288501 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24361288501 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 24361288501 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 93628676500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 93628676500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2467826500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2467826500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96096503000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 96096503000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098509 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098509 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037785 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037785 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.075085 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.075085 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.075085 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.075085 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12184.687391 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12184.687391 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26627.841750 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26627.841750 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14988.472223 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 14988.472223 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14988.472223 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 14988.472223 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency |