diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-12-23 09:31:20 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-12-23 09:31:20 -0500 |
| commit | df8df4fd0a95763cb0658cbe77615e7deac391d3 (patch) | |
| tree | 0c8776db2ef482a4f6e5db099133105f9af799d7 /tests/quick/fs/10.linux-boot/ref | |
| parent | b2342c5d9aea0b732f6d5a5b6c9c3961940ed8e7 (diff) | |
| download | gem5-df8df4fd0a95763cb0658cbe77615e7deac391d3.tar.xz | |
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes
Changes due to speculative execution of an unaligned PC, introduction
of TLB stats, changes and re-work of the prefetcher, and the
introduction of rank-wise refresh in the DRAM controller.
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref')
13 files changed, 10219 insertions, 9181 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index 9ca2241e2..7159169af 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,118 +1,118 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.962845 # Number of seconds simulated -sim_ticks 1962844580000 # Number of ticks simulated -final_tick 1962844580000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.962843 # Number of seconds simulated +sim_ticks 1962842856000 # Number of ticks simulated +final_tick 1962842856000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1184099 # Simulator instruction rate (inst/s) -host_op_rate 1184098 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 38148129943 # Simulator tick rate (ticks/s) -host_mem_usage 318172 # Number of bytes of host memory used -host_seconds 51.45 # Real time elapsed on the host -sim_insts 60925667 # Number of instructions simulated -sim_ops 60925667 # Number of ops (including micro ops) simulated +host_inst_rate 1228880 # Simulator instruction rate (inst/s) +host_op_rate 1228880 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 39594262798 # Simulator tick rate (ticks/s) +host_mem_usage 373652 # Number of bytes of host memory used +host_seconds 49.57 # Real time elapsed on the host +sim_insts 60920382 # Number of instructions simulated +sim_ops 60920382 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 823168 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24882816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 41728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 386368 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 823232 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24883392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 41664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 386496 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26135040 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 823168 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 41728 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 26135744 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 823232 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 41664 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 864896 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7758336 # Number of bytes written to this memory -system.physmem.bytes_written::total 7758336 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 12862 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 388794 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 652 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 6037 # Number of read requests responded to by this memory +system.physmem.bytes_written::writebacks 7759040 # Number of bytes written to this memory +system.physmem.bytes_written::total 7759040 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 12863 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 388803 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 651 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 6039 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 408360 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 121224 # Number of write requests responded to by this memory -system.physmem.num_writes::total 121224 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 419375 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12676916 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 21259 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 196841 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 408371 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 121235 # Number of write requests responded to by this memory +system.physmem.num_writes::total 121235 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 419408 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12677221 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 21226 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 196906 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 489 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13314880 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 419375 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 21259 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13315250 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 419408 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 21226 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 440634 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3952598 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3952598 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3952598 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 419375 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12676916 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 21259 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 196841 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 3952960 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3952960 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3952960 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 419408 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12677221 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 21226 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 196906 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 489 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17267478 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 408360 # Number of read requests accepted -system.physmem.writeReqs 162776 # Number of write requests accepted -system.physmem.readBursts 408360 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 162776 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26127936 # Total number of bytes read from DRAM +system.physmem.bw_total::total 17268211 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 408371 # Number of read requests accepted +system.physmem.writeReqs 162787 # Number of write requests accepted +system.physmem.readBursts 408371 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 162787 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26128640 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 7104 # Total number of bytes read from write queue -system.physmem.bytesWritten 10271680 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26135040 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10417664 # Total written bytes from the system interface side +system.physmem.bytesWritten 10277440 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26135744 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10418368 # Total written bytes from the system interface side system.physmem.servicedByWrQ 111 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2254 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 7048 # Number of requests that are neither read nor write +system.physmem.mergedWrBursts 2175 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 7051 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 25705 # Per bank write bursts system.physmem.perBankRdBursts::1 25985 # Per bank write bursts -system.physmem.perBankRdBursts::2 25732 # Per bank write bursts -system.physmem.perBankRdBursts::3 25537 # Per bank write bursts +system.physmem.perBankRdBursts::2 25737 # Per bank write bursts +system.physmem.perBankRdBursts::3 25534 # Per bank write bursts system.physmem.perBankRdBursts::4 24847 # Per bank write bursts -system.physmem.perBankRdBursts::5 24747 # Per bank write bursts +system.physmem.perBankRdBursts::5 24754 # Per bank write bursts system.physmem.perBankRdBursts::6 25534 # Per bank write bursts -system.physmem.perBankRdBursts::7 25495 # Per bank write bursts +system.physmem.perBankRdBursts::7 25489 # Per bank write bursts system.physmem.perBankRdBursts::8 25150 # Per bank write bursts system.physmem.perBankRdBursts::9 25518 # Per bank write bursts system.physmem.perBankRdBursts::10 25462 # Per bank write bursts -system.physmem.perBankRdBursts::11 25292 # Per bank write bursts +system.physmem.perBankRdBursts::11 25296 # Per bank write bursts system.physmem.perBankRdBursts::12 25577 # Per bank write bursts system.physmem.perBankRdBursts::13 25454 # Per bank write bursts system.physmem.perBankRdBursts::14 26241 # Per bank write bursts -system.physmem.perBankRdBursts::15 25973 # Per bank write bursts -system.physmem.perBankWrBursts::0 10613 # Per bank write bursts -system.physmem.perBankWrBursts::1 10753 # Per bank write bursts -system.physmem.perBankWrBursts::2 9796 # Per bank write bursts -system.physmem.perBankWrBursts::3 9387 # Per bank write bursts -system.physmem.perBankWrBursts::4 8893 # Per bank write bursts -system.physmem.perBankWrBursts::5 9110 # Per bank write bursts -system.physmem.perBankWrBursts::6 9958 # Per bank write bursts -system.physmem.perBankWrBursts::7 9669 # Per bank write bursts -system.physmem.perBankWrBursts::8 9689 # Per bank write bursts -system.physmem.perBankWrBursts::9 9901 # Per bank write bursts -system.physmem.perBankWrBursts::10 9876 # Per bank write bursts -system.physmem.perBankWrBursts::11 10215 # Per bank write bursts -system.physmem.perBankWrBursts::12 10815 # Per bank write bursts -system.physmem.perBankWrBursts::13 10652 # Per bank write bursts -system.physmem.perBankWrBursts::14 10531 # Per bank write bursts -system.physmem.perBankWrBursts::15 10637 # Per bank write bursts +system.physmem.perBankRdBursts::15 25977 # Per bank write bursts +system.physmem.perBankWrBursts::0 10598 # Per bank write bursts +system.physmem.perBankWrBursts::1 10761 # Per bank write bursts +system.physmem.perBankWrBursts::2 9727 # Per bank write bursts +system.physmem.perBankWrBursts::3 9433 # Per bank write bursts +system.physmem.perBankWrBursts::4 8910 # Per bank write bursts +system.physmem.perBankWrBursts::5 9140 # Per bank write bursts +system.physmem.perBankWrBursts::6 9908 # Per bank write bursts +system.physmem.perBankWrBursts::7 9771 # Per bank write bursts +system.physmem.perBankWrBursts::8 9710 # Per bank write bursts +system.physmem.perBankWrBursts::9 9867 # Per bank write bursts +system.physmem.perBankWrBursts::10 9923 # Per bank write bursts +system.physmem.perBankWrBursts::11 10306 # Per bank write bursts +system.physmem.perBankWrBursts::12 10733 # Per bank write bursts +system.physmem.perBankWrBursts::13 10678 # Per bank write bursts +system.physmem.perBankWrBursts::14 10553 # Per bank write bursts +system.physmem.perBankWrBursts::15 10567 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1962839541500 # Total gap between requests +system.physmem.totGap 1962837817500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 408360 # Read request sizes (log2) +system.physmem.readPktSize::6 408371 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 162776 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 408168 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 68 # What read queue length does an incoming req see +system.physmem.writePktSize::6 162787 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 408177 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 70 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see @@ -158,173 +158,178 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2297 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4384 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 8312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 9464 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 10119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 10932 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 11465 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 12365 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 11871 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 11907 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10784 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8529 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8090 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6890 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6447 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6307 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 345 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 266 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 227 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4404 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 8320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 9433 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 10077 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 10961 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 11550 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 12406 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 11941 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 12017 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 10895 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10072 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8581 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6888 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6429 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6271 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 272 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 130 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 59 # What write queue length does an incoming req see system.physmem.wrQLenPdf::54 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 26 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 69162 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 526.295017 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 318.923666 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 416.254848 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 16035 23.18% 23.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 12178 17.61% 40.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5186 7.50% 48.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3086 4.46% 52.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3308 4.78% 57.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1800 2.60% 60.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1507 2.18% 62.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1316 1.90% 64.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 24746 35.78% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 69162 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5880 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 69.428401 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2107.963348 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 5875 99.91% 99.91% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 69318 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 525.203843 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 317.866807 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 416.347675 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 16137 23.28% 23.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 12161 17.54% 40.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5284 7.62% 48.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3087 4.45% 52.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3309 4.77% 57.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1757 2.53% 60.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1519 2.19% 62.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1296 1.87% 64.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 24768 35.73% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 69318 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5881 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 69.418466 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2107.784288 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 5876 99.91% 99.91% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-8191 1 0.02% 99.93% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-45055 1 0.02% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-61439 1 0.02% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::73728-77823 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::122880-126975 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5880 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5880 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 27.295068 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.802481 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 33.368634 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4837 82.26% 82.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 186 3.16% 85.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 281 4.78% 90.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 57 0.97% 91.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 98 1.67% 92.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 42 0.71% 93.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 21 0.36% 93.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 12 0.20% 94.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 21 0.36% 94.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 6 0.10% 94.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 10 0.17% 94.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 8 0.14% 94.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 13 0.22% 95.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 5 0.09% 95.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 22 0.37% 95.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 44 0.75% 96.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 23 0.39% 96.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 6 0.10% 96.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 80 1.36% 98.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 40 0.68% 98.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 14 0.24% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 24 0.41% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 14 0.24% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 2 0.03% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 5 0.09% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 1 0.02% 99.86% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 5881 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5881 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 27.305730 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.811619 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 33.369719 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4828 82.09% 82.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 189 3.21% 85.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 283 4.81% 90.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 60 1.02% 91.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 106 1.80% 92.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 43 0.73% 93.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 17 0.29% 93.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 8 0.14% 94.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 22 0.37% 94.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 7 0.12% 94.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 14 0.24% 94.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 3 0.05% 94.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 16 0.27% 95.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 2 0.03% 95.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 15 0.26% 95.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 48 0.82% 96.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 18 0.31% 96.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 12 0.20% 96.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 85 1.45% 98.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 44 0.75% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 9 0.15% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 24 0.41% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 10 0.17% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 3 0.05% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 5 0.09% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 2 0.03% 99.86% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::224-231 2 0.03% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 1 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 4 0.07% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5880 # Writes before turning the bus around for reads -system.physmem.totQLat 2202002500 # Total ticks spent queuing -system.physmem.totMemAccLat 9856671250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2041245000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5393.77 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::232-239 2 0.03% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 3 0.05% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5881 # Writes before turning the bus around for reads +system.physmem.totQLat 2189518000 # Total ticks spent queuing +system.physmem.totMemAccLat 9844393000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2041300000 # Total ticks spent in databus transfers +system.physmem.avgQLat 5363.05 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24143.77 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 24113.05 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.31 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 5.23 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.31 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBW 5.24 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.32 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 5.31 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.11 # Average write queue length when enqueuing -system.physmem.readRowHits 365785 # Number of row buffer hits during reads -system.physmem.writeRowHits 133797 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.60 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 83.35 # Row buffer hit rate for writes -system.physmem.avgGap 3436728.80 # Average gap between requests -system.physmem.pageHitRate 87.84 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1840639787000 # Time in different power states -system.physmem.memoryStateTime::REF 65543660000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 56660375500 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 257115600 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 265749120 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 140291250 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 145002000 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 1587939600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1596402600 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 506599920 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 533407680 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 128203398960 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 128203398960 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 65563204050 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 65997539775 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1120194702750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1119813706500 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1316453252130 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1316555206635 # Total energy per rank (pJ) -system.physmem.averagePower::0 670.686708 # Core power per rank (mW) -system.physmem.averagePower::1 670.738650 # Core power per rank (mW) +system.physmem.avgWrQLen 25.78 # Average write queue length when enqueuing +system.physmem.readRowHits 365775 # Number of row buffer hits during reads +system.physmem.writeRowHits 133752 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.59 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 83.28 # Row buffer hit rate for writes +system.physmem.avgGap 3436593.41 # Average gap between requests +system.physmem.pageHitRate 87.81 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 258098400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 140827500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1587963000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 507047040 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 128202890400 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 65554579665 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1120197596250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1316449002255 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.687203 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1863305388500 # Time in different power states +system.physmem_0.memoryStateTime::REF 65543400000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 33987247750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 265945680 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 145109250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1596465000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 533543760 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 128202890400 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 65970100260 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1119833096250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1316547150600 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.737211 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1862702158750 # Time in different power states +system.physmem_1.memoryStateTime::REF 65543400000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 34590463750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7534386 # DTB read hits +system.cpu0.dtb.read_hits 7535038 # DTB read hits system.cpu0.dtb.read_misses 7765 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations system.cpu0.dtb.read_accesses 524069 # DTB read accesses -system.cpu0.dtb.write_hits 5126601 # DTB write hits +system.cpu0.dtb.write_hits 5127057 # DTB write hits system.cpu0.dtb.write_misses 910 # DTB write misses system.cpu0.dtb.write_acv 133 # DTB write access violations system.cpu0.dtb.write_accesses 202595 # DTB write accesses -system.cpu0.dtb.data_hits 12660987 # DTB hits +system.cpu0.dtb.data_hits 12662095 # DTB hits system.cpu0.dtb.data_misses 8675 # DTB misses system.cpu0.dtb.data_acv 343 # DTB access violations system.cpu0.dtb.data_accesses 726664 # DTB accesses @@ -344,32 +349,32 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3925689160 # number of cpu cycles simulated +system.cpu0.numCycles 3925685712 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 47974635 # Number of instructions committed -system.cpu0.committedOps 47974635 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 44501266 # Number of integer alu accesses +system.cpu0.committedInsts 47981838 # Number of instructions committed +system.cpu0.committedOps 47981838 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 44508329 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 212945 # Number of float alu accesses -system.cpu0.num_func_calls 1202793 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 5632199 # number of instructions that are conditional controls -system.cpu0.num_int_insts 44501266 # number of integer instructions +system.cpu0.num_func_calls 1202945 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 5633344 # number of instructions that are conditional controls +system.cpu0.num_int_insts 44508329 # number of integer instructions system.cpu0.num_fp_insts 212945 # number of float instructions -system.cpu0.num_int_register_reads 61193579 # number of times the integer registers were read -system.cpu0.num_int_register_writes 33138119 # number of times the integer registers were written +system.cpu0.num_int_register_reads 61205329 # number of times the integer registers were read +system.cpu0.num_int_register_writes 33143507 # number of times the integer registers were written system.cpu0.num_fp_register_reads 104073 # number of times the floating registers were read system.cpu0.num_fp_register_writes 105864 # number of times the floating registers were written -system.cpu0.num_mem_refs 12702031 # number of memory refs -system.cpu0.num_load_insts 7562183 # Number of load instructions -system.cpu0.num_store_insts 5139848 # Number of store instructions -system.cpu0.num_idle_cycles 3702096779.998114 # Number of idle cycles -system.cpu0.num_busy_cycles 223592380.001886 # Number of busy cycles +system.cpu0.num_mem_refs 12703139 # number of memory refs +system.cpu0.num_load_insts 7562835 # Number of load instructions +system.cpu0.num_store_insts 5140304 # Number of store instructions +system.cpu0.num_idle_cycles 3702094605.998114 # Number of idle cycles +system.cpu0.num_busy_cycles 223591106.001886 # Number of busy cycles system.cpu0.not_idle_fraction 0.056956 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.943044 # Percentage of idle cycles -system.cpu0.Branches 7223323 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2734296 5.70% 5.70% # Class of executed instruction -system.cpu0.op_class::IntAlu 31541688 65.73% 71.43% # Class of executed instruction -system.cpu0.op_class::IntMult 52334 0.11% 71.54% # Class of executed instruction +system.cpu0.Branches 7224625 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2734428 5.70% 5.70% # Class of executed instruction +system.cpu0.op_class::IntAlu 31547561 65.74% 71.43% # Class of executed instruction +system.cpu0.op_class::IntMult 52422 0.11% 71.54% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 71.54% # Class of executed instruction system.cpu0.op_class::FloatAdd 26783 0.06% 71.60% # Class of executed instruction system.cpu0.op_class::FloatCmp 0 0.00% 71.60% # Class of executed instruction @@ -397,11 +402,11 @@ system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.60% # Cl system.cpu0.op_class::SimdFloatMult 0 0.00% 71.60% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.60% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::MemRead 7738218 16.13% 87.73% # Class of executed instruction -system.cpu0.op_class::MemWrite 5145965 10.72% 98.45% # Class of executed instruction +system.cpu0.op_class::MemRead 7738872 16.13% 87.73% # Class of executed instruction +system.cpu0.op_class::MemWrite 5146421 10.72% 98.45% # Class of executed instruction system.cpu0.op_class::IprAccess 742486 1.55% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 47983653 # Class of executed instruction +system.cpu0.op_class::total 47990856 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 6794 # number of quiesce instructions executed system.cpu0.kern.inst.hwrei 165589 # number of hwrei instructions executed @@ -417,12 +422,12 @@ system.cpu0.kern.ipl_good::22 1976 1.72% 50.92% # nu system.cpu0.kern.ipl_good::30 424 0.37% 51.29% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::31 55969 48.71% 100.00% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::total 114892 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1903342573000 96.97% 96.97% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 94358500 0.00% 96.97% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 767882500 0.04% 97.01% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 314406500 0.02% 97.03% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 58324587500 2.97% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1962843808000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::0 1903333022000 96.97% 96.97% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 94388000 0.00% 96.97% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 768238500 0.04% 97.01% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 314332500 0.02% 97.03% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 58332103000 2.97% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1962842084000 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.990637 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl @@ -487,98 +492,98 @@ system.cpu0.kern.mode_switch_good::kernel 0.195209 # f system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::total 0.326733 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1959059969000 99.81% 99.81% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3783834500 0.19% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::kernel 1959061538500 99.81% 99.81% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3780541000 0.19% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 3098 # number of times the context was actually changed -system.cpu0.dcache.tags.replacements 1190018 # number of replacements -system.cpu0.dcache.tags.tagsinuse 505.199068 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 11465472 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1190530 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.630561 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 1190069 # number of replacements +system.cpu0.dcache.tags.tagsinuse 505.197532 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 11466522 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1190581 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.631031 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 108210250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.199068 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986717 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.986717 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.197532 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986714 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.986714 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 328 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 325 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 51888213 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 51888213 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6450398 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6450398 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4712072 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4712072 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 140773 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 140773 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 148356 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 148356 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 11162470 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 11162470 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11162470 # number of overall hits -system.cpu0.dcache.overall_hits::total 11162470 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 942246 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 942246 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 257610 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 257610 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13707 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13707 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5575 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 5575 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1199856 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1199856 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1199856 # number of overall misses -system.cpu0.dcache.overall_misses::total 1199856 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 27226306250 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 27226306250 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10348541688 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 10348541688 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 149709000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 149709000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 42660894 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 42660894 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 37574847938 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 37574847938 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 37574847938 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 37574847938 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7392644 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7392644 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4969682 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4969682 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 154480 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 154480 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153931 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 153931 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12362326 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12362326 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12362326 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12362326 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127457 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.127457 # miss rate for ReadReq accesses +system.cpu0.dcache.tags.tag_accesses 51892703 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 51892703 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6451021 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6451021 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4712504 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4712504 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 140772 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 140772 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 148353 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 148353 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 11163525 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 11163525 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11163525 # number of overall hits +system.cpu0.dcache.overall_hits::total 11163525 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 942274 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 942274 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 257633 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 257633 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13709 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 13709 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5579 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 5579 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1199907 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1199907 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1199907 # number of overall misses +system.cpu0.dcache.overall_misses::total 1199907 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 27224956000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 27224956000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10342084186 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 10342084186 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 150000000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 150000000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 42703895 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 42703895 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 37567040186 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 37567040186 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 37567040186 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 37567040186 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7393295 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7393295 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4970137 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4970137 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 154481 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 154481 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153932 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 153932 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12363432 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12363432 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12363432 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12363432 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127450 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.127450 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051836 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::total 0.051836 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088730 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088730 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.036218 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.036218 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097057 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.097057 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097057 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.097057 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28895.114705 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 28895.114705 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40171.350833 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 40171.350833 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10922.083607 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10922.083607 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7652.178296 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7652.178296 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31316.131217 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 31316.131217 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31316.131217 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 31316.131217 # average overall miss latency +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088742 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088742 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.036243 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.036243 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097053 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.097053 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097053 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.097053 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28892.823107 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 28892.823107 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40142.699833 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 40142.699833 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10941.717120 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10941.717120 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7654.399534 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7654.399534 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31308.293214 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 31308.293214 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31308.293214 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 31308.293214 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -587,62 +592,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 685854 # number of writebacks -system.cpu0.dcache.writebacks::total 685854 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 942246 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 942246 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 257610 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 257610 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13707 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13707 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5575 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 5575 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1199856 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1199856 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1199856 # 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number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127457 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127457 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.writebacks::writebacks 685914 # number of writebacks +system.cpu0.dcache.writebacks::total 685914 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 942274 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 942274 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 257633 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 257633 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13709 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13709 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5579 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 5579 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1199907 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1199907 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1199907 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1199907 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25214933000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25214933000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9773693814 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9773693814 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 122568000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 122568000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31544105 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31544105 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 34988626814 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 34988626814 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 34988626814 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 34988626814 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1461501000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1461501000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2267119000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2267119000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3728620000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3728620000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127450 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127450 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051836 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051836 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088730 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088730 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.036218 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.036218 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097057 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.097057 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097057 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.097057 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26761.931332 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26761.931332 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37965.045270 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37965.045270 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8921.062231 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8921.062231 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5651.857578 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5651.857578 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29167.248455 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29167.248455 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29167.248455 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29167.248455 # average overall mshr miss latency +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088742 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088742 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.036243 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.036243 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097053 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.097053 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097053 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.097053 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26759.661203 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26759.661203 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37936.498096 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37936.498096 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8940.695893 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8940.695893 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5654.078688 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5654.078688 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29159.448869 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29159.448869 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29159.448869 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29159.448869 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -650,13 +655,13 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 699671 # number of replacements -system.cpu0.icache.tags.tagsinuse 508.391653 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 47283349 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 700182 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 67.530084 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 699791 # number of replacements +system.cpu0.icache.tags.tagsinuse 508.391652 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 47290432 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 700302 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 67.528626 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 40276505250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.391653 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.391652 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992952 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.992952 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id @@ -665,44 +670,44 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 system.cpu0.icache.tags.age_task_id_blocks_1024::2 436 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 48683959 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 48683959 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 47283349 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 47283349 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 47283349 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 47283349 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 47283349 # number of overall hits -system.cpu0.icache.overall_hits::total 47283349 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 700305 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 700305 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 700305 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 700305 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 700305 # number of overall misses -system.cpu0.icache.overall_misses::total 700305 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9967517496 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 9967517496 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 9967517496 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 9967517496 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 9967517496 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 9967517496 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 47983654 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 47983654 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 47983654 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 47983654 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 47983654 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 47983654 # number of overall (read+write) accesses +system.cpu0.icache.tags.tag_accesses 48691282 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 48691282 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 47290432 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 47290432 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 47290432 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 47290432 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 47290432 # number of overall hits +system.cpu0.icache.overall_hits::total 47290432 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 700425 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 700425 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 700425 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 700425 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 700425 # number of overall misses +system.cpu0.icache.overall_misses::total 700425 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9965953746 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 9965953746 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 9965953746 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 9965953746 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 9965953746 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 9965953746 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 47990857 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 47990857 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 47990857 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 47990857 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 47990857 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 47990857 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014595 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::total 0.014595 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014595 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total 0.014595 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014595 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.014595 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14233.109140 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14233.109140 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14233.109140 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14233.109140 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14233.109140 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14233.109140 # average overall miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14228.438085 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14228.438085 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14228.438085 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14228.438085 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14228.438085 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14228.438085 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -711,51 +716,51 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 700305 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 700305 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 700305 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 700305 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 700305 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 700305 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8561918504 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 8561918504 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8561918504 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 8561918504 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8561918504 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 8561918504 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 700425 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 700425 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 700425 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 700425 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 700425 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 700425 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8560109254 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 8560109254 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8560109254 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 8560109254 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8560109254 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 8560109254 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014595 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014595 # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014595 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total 0.014595 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014595 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.014595 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12225.985112 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12225.985112 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12225.985112 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12225.985112 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12225.985112 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12225.985112 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12221.307426 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12221.307426 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12221.307426 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12221.307426 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12221.307426 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12221.307426 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2382379 # DTB read hits +system.cpu1.dtb.read_hits 2381610 # DTB read hits system.cpu1.dtb.read_misses 2620 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations system.cpu1.dtb.read_accesses 205337 # DTB read accesses -system.cpu1.dtb.write_hits 1702197 # DTB write hits +system.cpu1.dtb.write_hits 1701782 # DTB write hits system.cpu1.dtb.write_misses 235 # DTB write misses system.cpu1.dtb.write_acv 24 # DTB write access violations system.cpu1.dtb.write_accesses 89739 # DTB write accesses -system.cpu1.dtb.data_hits 4084576 # DTB hits +system.cpu1.dtb.data_hits 4083392 # DTB hits system.cpu1.dtb.data_misses 2855 # DTB misses system.cpu1.dtb.data_acv 24 # DTB access violations system.cpu1.dtb.data_accesses 295076 # DTB accesses -system.cpu1.itb.fetch_hits 1808740 # ITB hits +system.cpu1.itb.fetch_hits 1808769 # ITB hits system.cpu1.itb.fetch_misses 1064 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1809804 # ITB accesses +system.cpu1.itb.fetch_accesses 1809833 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -768,87 +773,87 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3923834014 # number of cpu cycles simulated +system.cpu1.numCycles 3923834021 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 12951032 # Number of instructions committed -system.cpu1.committedOps 12951032 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 11936898 # Number of integer alu accesses +system.cpu1.committedInsts 12938544 # Number of instructions committed +system.cpu1.committedOps 12938544 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 11924615 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 171199 # Number of float alu accesses -system.cpu1.num_func_calls 411532 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1284277 # number of instructions that are conditional controls -system.cpu1.num_int_insts 11936898 # number of integer instructions +system.cpu1.num_func_calls 411382 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1282019 # number of instructions that are conditional controls +system.cpu1.num_int_insts 11924615 # number of integer instructions system.cpu1.num_fp_insts 171199 # number of float instructions -system.cpu1.num_int_register_reads 16412569 # number of times the integer registers were read -system.cpu1.num_int_register_writes 8783541 # number of times the integer registers were written +system.cpu1.num_int_register_reads 16391744 # number of times the integer registers were read +system.cpu1.num_int_register_writes 8774012 # number of times the integer registers were written system.cpu1.num_fp_register_reads 88996 # number of times the floating registers were read system.cpu1.num_fp_register_writes 90942 # number of times the floating registers were written -system.cpu1.num_mem_refs 4107226 # number of memory refs -system.cpu1.num_load_insts 2395961 # Number of load instructions -system.cpu1.num_store_insts 1711265 # Number of store instructions -system.cpu1.num_idle_cycles 3874307298.691787 # Number of idle cycles -system.cpu1.num_busy_cycles 49526715.308213 # Number of busy cycles -system.cpu1.not_idle_fraction 0.012622 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.987378 # Percentage of idle cycles -system.cpu1.Branches 1849703 # Number of branches fetched -system.cpu1.op_class::No_OpClass 699491 5.40% 5.40% # Class of executed instruction -system.cpu1.op_class::IntAlu 7680347 59.29% 64.69% # Class of executed instruction -system.cpu1.op_class::IntMult 22457 0.17% 64.86% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 64.86% # Class of executed instruction -system.cpu1.op_class::FloatAdd 13113 0.10% 64.96% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 64.96% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 64.96% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 64.96% # Class of executed instruction -system.cpu1.op_class::FloatDiv 1759 0.01% 64.98% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::MemRead 2467292 19.05% 84.02% # Class of executed instruction -system.cpu1.op_class::MemWrite 1712246 13.22% 97.24% # Class of executed instruction -system.cpu1.op_class::IprAccess 357206 2.76% 100.00% # Class of executed instruction +system.cpu1.num_mem_refs 4106042 # number of memory refs +system.cpu1.num_load_insts 2395192 # Number of load instructions +system.cpu1.num_store_insts 1710850 # Number of store instructions +system.cpu1.num_idle_cycles 3874343491.006502 # Number of idle cycles +system.cpu1.num_busy_cycles 49490529.993498 # Number of busy cycles +system.cpu1.not_idle_fraction 0.012613 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.987387 # Percentage of idle cycles +system.cpu1.Branches 1847277 # Number of branches fetched +system.cpu1.op_class::No_OpClass 699299 5.40% 5.40% # Class of executed instruction +system.cpu1.op_class::IntAlu 7669413 59.26% 64.67% # Class of executed instruction +system.cpu1.op_class::IntMult 22263 0.17% 64.84% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 64.84% # Class of executed instruction +system.cpu1.op_class::FloatAdd 13113 0.10% 64.94% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::FloatDiv 1759 0.01% 64.95% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::MemRead 2466523 19.06% 84.01% # Class of executed instruction +system.cpu1.op_class::MemWrite 1711831 13.23% 97.24% # Class of executed instruction +system.cpu1.op_class::IprAccess 357222 2.76% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 12953911 # Class of executed instruction +system.cpu1.op_class::total 12941423 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2765 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 77892 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 26462 38.26% 38.26% # number of times we switched to this ipl +system.cpu1.kern.inst.quiesce 2766 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 77895 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 26463 38.26% 38.26% # number of times we switched to this ipl system.cpu1.kern.ipl_count::22 1970 2.85% 41.11% # number of times we switched to this ipl system.cpu1.kern.ipl_count::30 512 0.74% 41.85% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 40213 58.15% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 69157 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 25618 48.15% 48.15% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_count::31 40215 58.15% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 69160 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 25619 48.15% 48.15% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::22 1970 3.70% 51.85% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::30 512 0.96% 52.81% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 25106 47.19% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 53206 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1910435586500 97.38% 97.38% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 701157000 0.04% 97.41% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 358940000 0.02% 97.43% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 50421293500 2.57% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1961916977000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.968105 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_good::31 25107 47.19% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 53208 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1910451046000 97.38% 97.38% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 701160000 0.04% 97.41% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 358891000 0.02% 97.43% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 50405883500 2.57% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1961916980500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.968106 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.624325 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.769351 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.624319 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.769346 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed @@ -870,7 +875,7 @@ system.cpu1.kern.callpal::wrfen 1 0.00% 0.60% # nu system.cpu1.kern.callpal::swpctx 1967 2.75% 3.35% # number of callpals executed system.cpu1.kern.callpal::tbi 3 0.00% 3.35% # number of callpals executed system.cpu1.kern.callpal::wrent 7 0.01% 3.36% # number of callpals executed -system.cpu1.kern.callpal::swpipl 62982 88.13% 91.49% # number of callpals executed +system.cpu1.kern.callpal::swpipl 62985 88.13% 91.49% # number of callpals executed system.cpu1.kern.callpal::rdps 2216 3.10% 94.59% # number of callpals executed system.cpu1.kern.callpal::wrkgp 1 0.00% 94.60% # number of callpals executed system.cpu1.kern.callpal::wrusp 3 0.00% 94.60% # number of callpals executed @@ -879,108 +884,108 @@ system.cpu1.kern.callpal::rti 3692 5.17% 99.77% # nu system.cpu1.kern.callpal::callsys 121 0.17% 99.94% # number of callpals executed system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 71465 # number of callpals executed +system.cpu1.kern.callpal::total 71468 # number of callpals executed system.cpu1.kern.mode_switch::kernel 1923 # number of protection mode switches -system.cpu1.kern.mode_switch::user 367 # number of protection mode switches +system.cpu1.kern.mode_switch::user 368 # number of protection mode switches system.cpu1.kern.mode_switch::idle 2902 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 803 -system.cpu1.kern.mode_good::user 367 +system.cpu1.kern.mode_good::kernel 804 +system.cpu1.kern.mode_good::user 368 system.cpu1.kern.mode_good::idle 436 -system.cpu1.kern.mode_switch_good::kernel 0.417577 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::kernel 0.418097 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::idle 0.150241 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.309322 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 17997631500 0.92% 0.92% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1494992000 0.08% 0.99% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1941547962000 99.01% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_switch_good::total 0.309648 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 17982324500 0.92% 0.92% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1495094500 0.08% 0.99% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1941563117500 99.01% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 1968 # number of times the context was actually changed -system.cpu1.dcache.tags.replacements 157269 # number of replacements -system.cpu1.dcache.tags.tagsinuse 486.065602 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 3912422 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 157596 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 24.825643 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 1048852145500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.065602 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.949347 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.949347 # Average percentage of cache occupancy +system.cpu1.dcache.tags.replacements 157282 # number of replacements +system.cpu1.dcache.tags.tagsinuse 486.069018 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 3911225 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 157609 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 24.816000 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 1048852201500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.069018 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.949354 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.949354 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 327 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::3 295 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 0.638672 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 16561703 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 16561703 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 2221454 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2221454 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1590675 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1590675 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 47775 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 47775 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50240 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 50240 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 3812129 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 3812129 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 3812129 # number of overall hits -system.cpu1.dcache.overall_hits::total 3812129 # number of overall hits +system.cpu1.dcache.tags.tag_accesses 16556980 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 16556980 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 2220683 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2220683 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1590246 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1590246 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 47776 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 47776 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50237 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 50237 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 3810929 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 3810929 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 3810929 # number of overall hits +system.cpu1.dcache.overall_hits::total 3810929 # number of overall hits system.cpu1.dcache.ReadReq_misses::cpu1.data 115097 # number of ReadReq misses system.cpu1.dcache.ReadReq_misses::total 115097 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 57126 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 57126 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8902 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 8902 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5962 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 5962 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 172223 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 172223 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 172223 # number of overall misses -system.cpu1.dcache.overall_misses::total 172223 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1389994499 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1389994499 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1079772299 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 1079772299 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 80592000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 80592000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 43791416 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 43791416 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 2469766798 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 2469766798 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 2469766798 # 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mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043241 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.043241 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043241 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.043241 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10061.200561 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10061.200561 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16845.789107 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16845.789107 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7051.274851 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7051.274851 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5346.000168 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5346.000168 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12311.949946 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12311.949946 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12311.949946 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12311.949946 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1052,13 +1057,13 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 318302 # number of replacements -system.cpu1.icache.tags.tagsinuse 446.541764 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 12635057 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 318814 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 39.631437 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1956986830500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 446.541764 # Average occupied blocks per requestor +system.cpu1.icache.tags.replacements 318148 # number of replacements +system.cpu1.icache.tags.tagsinuse 446.541580 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 12622723 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 318660 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 39.611884 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1956986313500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 446.541580 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.872152 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.872152 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -1066,44 +1071,44 @@ system.cpu1.icache.tags.age_task_id_blocks_1024::2 72 system.cpu1.icache.tags.age_task_id_blocks_1024::3 439 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 13272765 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 13272765 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 12635057 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 12635057 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 12635057 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 12635057 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 12635057 # number of overall hits -system.cpu1.icache.overall_hits::total 12635057 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 318854 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 318854 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 318854 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 318854 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 318854 # number of overall misses -system.cpu1.icache.overall_misses::total 318854 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4204550742 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4204550742 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4204550742 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4204550742 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4204550742 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4204550742 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 12953911 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 12953911 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 12953911 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 12953911 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 12953911 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 12953911 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024614 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.024614 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024614 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.024614 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024614 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.024614 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13186.445025 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13186.445025 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13186.445025 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13186.445025 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13186.445025 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13186.445025 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 13260123 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 13260123 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 12622723 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 12622723 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 12622723 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 12622723 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 12622723 # number of overall hits +system.cpu1.icache.overall_hits::total 12622723 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 318700 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 318700 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 318700 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 318700 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 318700 # number of overall misses +system.cpu1.icache.overall_misses::total 318700 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4202225742 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4202225742 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4202225742 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4202225742 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4202225742 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4202225742 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 12941423 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 12941423 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 12941423 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 12941423 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 12941423 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 12941423 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024626 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.024626 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024626 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.024626 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024626 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.024626 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13185.521625 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13185.521625 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13185.521625 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13185.521625 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13185.521625 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13185.521625 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1112,30 +1117,30 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 318854 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 318854 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 318854 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 318854 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 318854 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 318854 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3566590258 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3566590258 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3566590258 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3566590258 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3566590258 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3566590258 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024614 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024614 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024614 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.024614 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024614 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.024614 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11185.653177 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11185.653177 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11185.653177 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11185.653177 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11185.653177 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11185.653177 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 318700 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 318700 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 318700 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 318700 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 318700 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 318700 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3564575258 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3564575258 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3564575258 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3564575258 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3564575258 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3564575258 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024626 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024626 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024626 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.024626 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024626 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.024626 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11184.735670 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11184.735670 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11184.735670 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11184.735670 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11184.735670 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11184.735670 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1208,7 +1213,7 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 406206788 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 406213784 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) @@ -1217,14 +1222,14 @@ system.iobus.respLayer0.utilization 0.0 # La system.iobus.respLayer1.occupancy 42016500 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41696 # number of replacements -system.iocache.tags.tagsinuse 0.577792 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.577776 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41712 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1755504938000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.577792 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.036112 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.036112 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1755504098000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.577776 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.036111 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.036111 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1240,8 +1245,8 @@ system.iocache.overall_misses::tsunami.ide 176 # system.iocache.overall_misses::total 176 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 21474383 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 21474383 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13634244905 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 13634244905 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13634467901 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 13634467901 # number of WriteInvalidateReq miss cycles system.iocache.demand_miss_latency::tsunami.ide 21474383 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::total 21474383 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::tsunami.ide 21474383 # number of overall miss cycles @@ -1264,17 +1269,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122013.539773 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 122013.539773 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328124.877383 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 328124.877383 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328130.244056 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 328130.244056 # average WriteInvalidateReq miss latency system.iocache.demand_avg_miss_latency::tsunami.ide 122013.539773 # average overall miss latency system.iocache.demand_avg_miss_latency::total 122013.539773 # average overall miss latency system.iocache.overall_avg_miss_latency::tsunami.ide 122013.539773 # average overall miss latency system.iocache.overall_avg_miss_latency::total 122013.539773 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 206283 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 206274 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 23550 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 23554 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.759363 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.757493 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1290,8 +1295,8 @@ system.iocache.overall_mshr_misses::tsunami.ide 176 system.iocache.overall_mshr_misses::total 176 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12321383 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 12321383 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11473540905 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11473540905 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11473763901 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11473763901 # number of WriteInvalidateReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::tsunami.ide 12321383 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 12321383 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::tsunami.ide 12321383 # number of overall MSHR miss cycles @@ -1306,187 +1311,187 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70007.857955 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 70007.857955 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276124.877383 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276124.877383 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276130.244056 # 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number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 4215286500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.018365 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.288975 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.002043 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.002777 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total 0.138232 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.942057 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.765820 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.867130 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.954109 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.975506 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.964819 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.475999 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.119678 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.417896 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018367 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.328016 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.002045 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.039472 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.173317 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018367 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.328016 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.002045 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.039472 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.173317 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60793.986161 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52556.207467 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60230.828221 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 58242.320819 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 52950.882923 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10053.381548 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10008.588533 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10036.562896 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10035.675615 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10015.192140 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10025.309392 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56475.322591 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61281.194151 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 56699.748311 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60793.986161 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53743.165348 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60230.828221 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61134.555501 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 54084.877339 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60793.986161 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53743.165348 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60230.828221 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61134.555501 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 54084.877339 # average overall mshr miss latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.942939 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.766781 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.867973 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.954158 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.975532 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.964856 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.475985 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.119692 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.417881 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018365 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.328008 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.002043 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.039486 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.173319 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018365 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.328008 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.002043 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.039486 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.173319 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60538.871181 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52550.828390 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59734.254992 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 59817.406143 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 52934.752136 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10053.230223 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10008.575758 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10036.442405 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10037.871508 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10015.176663 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10026.386313 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56413.793892 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61161.826847 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 56635.575673 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60538.871181 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53720.845810 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59734.254992 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61096.974152 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 54054.286512 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60538.871181 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53720.845810 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59734.254992 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61096.974152 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 54054.286512 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1621,96 +1626,96 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 292732 # Transaction distribution -system.membus.trans_dist::ReadResp 292732 # Transaction distribution +system.membus.trans_dist::ReadReq 292731 # Transaction distribution +system.membus.trans_dist::ReadResp 292731 # Transaction distribution system.membus.trans_dist::WriteReq 14079 # Transaction distribution system.membus.trans_dist::WriteResp 14079 # Transaction distribution -system.membus.trans_dist::Writeback 121224 # Transaction distribution +system.membus.trans_dist::Writeback 121235 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 16421 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 11471 # Transaction distribution -system.membus.trans_dist::UpgradeResp 7051 # Transaction distribution -system.membus.trans_dist::ReadExReq 124094 # Transaction distribution -system.membus.trans_dist::ReadExResp 123249 # Transaction distribution +system.membus.trans_dist::UpgradeReq 16420 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 11480 # Transaction distribution +system.membus.trans_dist::UpgradeResp 7054 # Transaction distribution +system.membus.trans_dist::ReadExReq 124107 # Transaction distribution +system.membus.trans_dist::ReadExResp 123261 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42552 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 932442 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 974994 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 932487 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 975039 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124815 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124815 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1099809 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1099854 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 82034 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31235136 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31317170 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31236544 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31318578 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317568 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 5317568 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 36634738 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 22113 # Total snoops (count) -system.membus.snoop_fanout::samples 600297 # Request fanout histogram +system.membus.pkt_size::total 36636146 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 22119 # Total snoops (count) +system.membus.snoop_fanout::samples 600328 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 600297 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 600328 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 600297 # Request fanout histogram -system.membus.reqLayer0.occupancy 40801500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 600328 # Request fanout histogram +system.membus.reqLayer0.occupancy 40794500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1914880000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1915022000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 3840416202 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3840524699 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.membus.respLayer2.occupancy 43136500 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.trans_dist::ReadReq 2106484 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2106469 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 2106481 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2106466 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 14079 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 14079 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 793794 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 793856 # Transaction distribution system.toL2Bus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 16644 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 11537 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 28181 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 298092 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 298092 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1400589 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3132441 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 637707 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 458977 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5629714 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 44818176 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119962112 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20406592 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 16779186 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 201966066 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 99450 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3260906 # Request fanout histogram +system.toL2Bus.trans_dist::UpgradeReq 16639 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 11546 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 28185 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 298132 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 298132 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1400829 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3132611 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 637399 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 458996 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5629835 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 44825856 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119969536 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20396736 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 16779122 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 201971250 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 99473 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3261009 # Request fanout histogram system.toL2Bus.snoop_fanout::mean 3.012796 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.112395 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.112394 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 3219178 98.72% 98.72% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 3219281 98.72% 98.72% # Request fanout histogram system.toL2Bus.snoop_fanout::4 41728 1.28% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3260906 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4802513358 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 3261009 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4802800383 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3153866996 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3154409746 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 5532423832 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 5532665081 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 1434969242 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 1434275242 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 787756714 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 787817718 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 166d29f48..5c3a9c7d0 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,107 +1,107 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.920428 # Number of seconds simulated -sim_ticks 1920427877000 # Number of ticks simulated -final_tick 1920427877000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.920419 # Number of seconds simulated +sim_ticks 1920418772000 # Number of ticks simulated +final_tick 1920418772000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 694902 # Simulator instruction rate (inst/s) -host_op_rate 694902 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 23785763794 # Simulator tick rate (ticks/s) -host_mem_usage 317148 # Number of bytes of host memory used -host_seconds 80.74 # Real time elapsed on the host -sim_insts 56105324 # Number of instructions simulated -sim_ops 56105324 # Number of ops (including micro ops) simulated +host_inst_rate 1235696 # Simulator instruction rate (inst/s) +host_op_rate 1235696 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 42298287542 # Simulator tick rate (ticks/s) +host_mem_usage 370580 # Number of bytes of host memory used +host_seconds 45.40 # Real time elapsed on the host +sim_insts 56102800 # Number of instructions simulated +sim_ops 56102800 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 850752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24858304 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 850560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24857984 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25710016 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 850752 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 850752 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7404096 # Number of bytes written to this memory -system.physmem.bytes_written::total 7404096 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 13293 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388411 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25709504 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 850560 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 850560 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7403648 # Number of bytes written to this memory +system.physmem.bytes_written::total 7403648 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13290 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388406 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 401719 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115689 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115689 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 443001 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12944149 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 401711 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115682 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115682 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 442903 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12944043 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 500 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13387650 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 443001 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 443001 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3855441 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3855441 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3855441 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 443001 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12944149 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13387447 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 442903 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 442903 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3855226 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3855226 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3855226 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 442903 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12944043 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 500 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17243091 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 401719 # Number of read requests accepted -system.physmem.writeReqs 157241 # Number of write requests accepted -system.physmem.readBursts 401719 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 157241 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25703424 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6592 # Total number of bytes read from write queue -system.physmem.bytesWritten 9932992 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25710016 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10063424 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 103 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2011 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_total::total 17242673 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 401711 # Number of read requests accepted +system.physmem.writeReqs 157234 # Number of write requests accepted +system.physmem.readBursts 401711 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 157234 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25703040 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6464 # Total number of bytes read from write queue +system.physmem.bytesWritten 9922432 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25709504 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10062976 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 101 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2169 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 130 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 25160 # Per bank write bursts system.physmem.perBankRdBursts::1 25539 # Per bank write bursts system.physmem.perBankRdBursts::2 25602 # Per bank write bursts -system.physmem.perBankRdBursts::3 25522 # Per bank write bursts +system.physmem.perBankRdBursts::3 25523 # Per bank write bursts system.physmem.perBankRdBursts::4 24974 # Per bank write bursts -system.physmem.perBankRdBursts::5 24970 # Per bank write bursts +system.physmem.perBankRdBursts::5 24969 # Per bank write bursts system.physmem.perBankRdBursts::6 24210 # Per bank write bursts -system.physmem.perBankRdBursts::7 24489 # Per bank write bursts +system.physmem.perBankRdBursts::7 24487 # Per bank write bursts system.physmem.perBankRdBursts::8 25140 # Per bank write bursts system.physmem.perBankRdBursts::9 24800 # Per bank write bursts -system.physmem.perBankRdBursts::10 25361 # Per bank write bursts -system.physmem.perBankRdBursts::11 24836 # Per bank write bursts +system.physmem.perBankRdBursts::10 25360 # Per bank write bursts +system.physmem.perBankRdBursts::11 24834 # Per bank write bursts system.physmem.perBankRdBursts::12 24395 # Per bank write bursts system.physmem.perBankRdBursts::13 25368 # Per bank write bursts system.physmem.perBankRdBursts::14 25772 # Per bank write bursts -system.physmem.perBankRdBursts::15 25478 # Per bank write bursts -system.physmem.perBankWrBursts::0 10040 # Per bank write bursts -system.physmem.perBankWrBursts::1 9905 # Per bank write bursts -system.physmem.perBankWrBursts::2 10447 # Per bank write bursts -system.physmem.perBankWrBursts::3 9982 # Per bank write bursts -system.physmem.perBankWrBursts::4 9551 # Per bank write bursts -system.physmem.perBankWrBursts::5 9392 # Per bank write bursts -system.physmem.perBankWrBursts::6 8805 # Per bank write bursts -system.physmem.perBankWrBursts::7 8555 # Per bank write bursts -system.physmem.perBankWrBursts::8 9942 # Per bank write bursts -system.physmem.perBankWrBursts::9 8777 # Per bank write bursts -system.physmem.perBankWrBursts::10 9524 # Per bank write bursts -system.physmem.perBankWrBursts::11 9288 # Per bank write bursts -system.physmem.perBankWrBursts::12 9847 # Per bank write bursts -system.physmem.perBankWrBursts::13 10608 # Per bank write bursts -system.physmem.perBankWrBursts::14 10278 # Per bank write bursts -system.physmem.perBankWrBursts::15 10262 # Per bank write bursts +system.physmem.perBankRdBursts::15 25477 # Per bank write bursts +system.physmem.perBankWrBursts::0 10048 # Per bank write bursts +system.physmem.perBankWrBursts::1 9910 # Per bank write bursts +system.physmem.perBankWrBursts::2 10442 # Per bank write bursts +system.physmem.perBankWrBursts::3 9959 # Per bank write bursts +system.physmem.perBankWrBursts::4 9552 # Per bank write bursts +system.physmem.perBankWrBursts::5 9342 # Per bank write bursts +system.physmem.perBankWrBursts::6 8789 # Per bank write bursts +system.physmem.perBankWrBursts::7 8561 # Per bank write bursts +system.physmem.perBankWrBursts::8 9905 # Per bank write bursts +system.physmem.perBankWrBursts::9 8742 # Per bank write bursts +system.physmem.perBankWrBursts::10 9526 # Per bank write bursts +system.physmem.perBankWrBursts::11 9262 # Per bank write bursts +system.physmem.perBankWrBursts::12 9811 # Per bank write bursts +system.physmem.perBankWrBursts::13 10568 # Per bank write bursts +system.physmem.perBankWrBursts::14 10305 # Per bank write bursts +system.physmem.perBankWrBursts::15 10316 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1920415956000 # Total gap between requests +system.physmem.totGap 1920406851000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 401719 # Read request sizes (log2) +system.physmem.readPktSize::6 401711 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 157241 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 401602 # What read queue length does an incoming req see +system.physmem.writePktSize::6 157234 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 401596 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see @@ -149,119 +149,118 @@ system.physmem.wrQLenPdf::12 1 # Wh system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 2241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4297 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 7960 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 9080 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 9749 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 10574 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 11119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 12096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 11614 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 11639 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10464 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7710 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6526 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5950 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5885 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 274 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 211 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 7978 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 9053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 9729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 10585 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 11129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 12018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 11559 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 11623 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 10445 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9597 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7669 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6479 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5940 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5895 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 361 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 368 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 365 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 271 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 254 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 66429 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 536.458715 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 326.725513 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 417.454187 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 15065 22.68% 22.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11458 17.25% 39.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4677 7.04% 46.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3146 4.74% 51.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3014 4.54% 56.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1853 2.79% 59.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1319 1.99% 61.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1472 2.22% 63.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 24425 36.77% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 66429 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5535 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 72.556098 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2836.858046 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5532 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 66451 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 536.116417 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 326.833533 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 417.088244 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 15015 22.60% 22.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11499 17.30% 39.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4712 7.09% 46.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3144 4.73% 51.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3072 4.62% 56.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1860 2.80% 59.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1297 1.95% 61.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1463 2.20% 63.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 24389 36.70% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 66451 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5539 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 72.502618 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2835.834060 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5536 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5535 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5535 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 28.040289 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 21.079799 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 34.913440 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4499 81.28% 81.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 176 3.18% 84.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 297 5.37% 89.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 50 0.90% 90.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 97 1.75% 92.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 48 0.87% 93.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 11 0.20% 93.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 7 0.13% 93.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 21 0.38% 94.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 7 0.13% 94.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 14 0.25% 94.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 6 0.11% 94.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 14 0.25% 94.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 3 0.05% 94.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 11 0.20% 95.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 48 0.87% 95.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 16 0.29% 96.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 19 0.34% 96.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 91 1.64% 98.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 36 0.65% 98.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 6 0.11% 98.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 14 0.25% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 14 0.25% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 5 0.09% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 9 0.16% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 3 0.05% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 5 0.09% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 1 0.02% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 3 0.05% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-255 2 0.04% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5535 # Writes before turning the bus around for reads -system.physmem.totQLat 2119831750 # Total ticks spent queuing -system.physmem.totMemAccLat 9650131750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2008080000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5278.26 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5539 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5539 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 27.990251 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 21.086567 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 34.704660 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4497 81.19% 81.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 178 3.21% 84.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 301 5.43% 89.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 51 0.92% 90.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 99 1.79% 92.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 47 0.85% 93.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 17 0.31% 93.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 11 0.20% 93.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 12 0.22% 94.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 4 0.07% 94.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 17 0.31% 94.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 7 0.13% 94.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 14 0.25% 94.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 6 0.11% 94.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 9 0.16% 95.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 38 0.69% 95.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 16 0.29% 96.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 19 0.34% 96.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 88 1.59% 98.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 43 0.78% 98.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 11 0.20% 99.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 20 0.36% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 10 0.18% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 3 0.05% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 3 0.05% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 4 0.07% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 4 0.07% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-239 5 0.09% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 3 0.05% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-255 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5539 # Writes before turning the bus around for reads +system.physmem.totQLat 2115529750 # Total ticks spent queuing +system.physmem.totMemAccLat 9645717250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2008050000 # Total ticks spent in databus transfers +system.physmem.avgQLat 5267.62 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24028.26 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 24017.62 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.38 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 5.17 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.39 # Average system read bandwidth in MiByte/s @@ -271,57 +270,62 @@ system.physmem.busUtil 0.14 # Da system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.55 # Average write queue length when enqueuing -system.physmem.readRowHits 359880 # Number of row buffer hits during reads -system.physmem.writeRowHits 130510 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.61 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 84.08 # Row buffer hit rate for writes -system.physmem.avgGap 3435694.78 # Average gap between requests -system.physmem.pageHitRate 88.07 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1801057353000 # Time in different power states -system.physmem.memoryStateTime::REF 64127180000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 55239785750 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 245964600 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 256238640 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 134206875 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 139812750 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 1563634800 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1568970000 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 496866960 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 508848480 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 125432764080 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 125432764080 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 64118860245 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 64485707400 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1096009968750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1095688173000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1288002266310 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1288080514350 # Total energy per rank (pJ) -system.physmem.averagePower::0 670.686297 # Core power per rank (mW) -system.physmem.averagePower::1 670.727042 # Core power per rank (mW) +system.physmem.avgWrQLen 25.84 # Average write queue length when enqueuing +system.physmem.readRowHits 359951 # Number of row buffer hits during reads +system.physmem.writeRowHits 130246 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.63 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 83.99 # Row buffer hit rate for writes +system.physmem.avgGap 3435770.69 # Average gap between requests +system.physmem.pageHitRate 88.06 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 245601720 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 134008875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1563619200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 496387440 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 125432255520 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 64124070615 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1096000726500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1287996669870 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.686102 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1823056528000 # Time in different power states +system.physmem_0.memoryStateTime::REF 64126920000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 33233084500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 256767840 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 140101500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1568938800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 508258800 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 125432255520 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 64541926215 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1095634186500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1288082435175 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.730762 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1822448681750 # Time in different power states +system.physmem_1.memoryStateTime::REF 64126920000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 33840930750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9053154 # DTB read hits -system.cpu.dtb.read_misses 10325 # DTB read misses +system.cpu.dtb.read_hits 9052701 # DTB read hits +system.cpu.dtb.read_misses 10312 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_accesses 728854 # DTB read accesses -system.cpu.dtb.write_hits 6349573 # DTB write hits -system.cpu.dtb.write_misses 1142 # DTB write misses +system.cpu.dtb.read_accesses 728817 # DTB read accesses +system.cpu.dtb.write_hits 6349364 # DTB write hits +system.cpu.dtb.write_misses 1140 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_accesses 291931 # DTB write accesses -system.cpu.dtb.data_hits 15402727 # DTB hits -system.cpu.dtb.data_misses 11467 # DTB misses +system.cpu.dtb.write_accesses 291929 # DTB write accesses +system.cpu.dtb.data_hits 15402065 # DTB hits +system.cpu.dtb.data_misses 11452 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations -system.cpu.dtb.data_accesses 1020785 # DTB accesses -system.cpu.itb.fetch_hits 4974627 # ITB hits -system.cpu.itb.fetch_misses 5010 # ITB misses +system.cpu.dtb.data_accesses 1020746 # DTB accesses +system.cpu.itb.fetch_hits 4973977 # ITB hits +system.cpu.itb.fetch_misses 4997 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4979637 # ITB accesses +system.cpu.itb.fetch_accesses 4978974 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -334,34 +338,34 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3840855754 # number of cpu cycles simulated +system.cpu.numCycles 3840837544 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56105324 # Number of instructions committed -system.cpu.committedOps 56105324 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 51980283 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 324527 # Number of float alu accesses -system.cpu.num_func_calls 1481352 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 6461346 # number of instructions that are conditional controls -system.cpu.num_int_insts 51980283 # number of integer instructions -system.cpu.num_fp_insts 324527 # number of float instructions -system.cpu.num_int_register_reads 71211532 # number of times the integer registers were read -system.cpu.num_int_register_writes 38461399 # number of times the integer registers were written -system.cpu.num_fp_register_reads 163675 # number of times the floating registers were read -system.cpu.num_fp_register_writes 166554 # number of times the floating registers were written -system.cpu.num_mem_refs 15455353 # number of memory refs -system.cpu.num_load_insts 9090013 # Number of load instructions -system.cpu.num_store_insts 6365340 # Number of store instructions -system.cpu.num_idle_cycles 3589191785.998131 # Number of idle cycles -system.cpu.num_busy_cycles 251663968.001869 # Number of busy cycles -system.cpu.not_idle_fraction 0.065523 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.934477 # Percentage of idle cycles -system.cpu.Branches 8413247 # Number of branches fetched -system.cpu.op_class::No_OpClass 3197750 5.70% 5.70% # Class of executed instruction -system.cpu.op_class::IntAlu 36174854 64.46% 70.16% # Class of executed instruction -system.cpu.op_class::IntMult 61015 0.11% 70.27% # Class of executed instruction +system.cpu.committedInsts 56102800 # Number of instructions committed +system.cpu.committedOps 56102800 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 51978055 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 324393 # Number of float alu accesses +system.cpu.num_func_calls 1481300 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 6461124 # number of instructions that are conditional controls +system.cpu.num_int_insts 51978055 # number of integer instructions +system.cpu.num_fp_insts 324393 # number of float instructions +system.cpu.num_int_register_reads 71208426 # number of times the integer registers were read +system.cpu.num_int_register_writes 38459690 # number of times the integer registers were written +system.cpu.num_fp_register_reads 163609 # number of times the floating registers were read +system.cpu.num_fp_register_writes 166486 # number of times the floating registers were written +system.cpu.num_mem_refs 15454652 # number of memory refs +system.cpu.num_load_insts 9089529 # Number of load instructions +system.cpu.num_store_insts 6365123 # Number of store instructions +system.cpu.num_idle_cycles 3589204507.998131 # Number of idle cycles +system.cpu.num_busy_cycles 251633036.001869 # Number of busy cycles +system.cpu.not_idle_fraction 0.065515 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.934485 # Percentage of idle cycles +system.cpu.Branches 8412940 # Number of branches fetched +system.cpu.op_class::No_OpClass 3197536 5.70% 5.70% # Class of executed instruction +system.cpu.op_class::IntAlu 36173540 64.46% 70.16% # Class of executed instruction +system.cpu.op_class::IntMult 60992 0.11% 70.27% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 70.27% # Class of executed instruction -system.cpu.op_class::FloatAdd 38089 0.07% 70.34% # Class of executed instruction +system.cpu.op_class::FloatAdd 38085 0.07% 70.34% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 70.34% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 70.34% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 70.34% # Class of executed instruction @@ -387,34 +391,34 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 70.34% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 70.34% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.34% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::MemRead 9317103 16.60% 86.95% # Class of executed instruction -system.cpu.op_class::MemWrite 6371414 11.35% 98.30% # Class of executed instruction -system.cpu.op_class::IprAccess 953297 1.70% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 9316603 16.60% 86.95% # Class of executed instruction +system.cpu.op_class::MemWrite 6371197 11.35% 98.30% # Class of executed instruction +system.cpu.op_class::IprAccess 953030 1.70% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 56117158 # Class of executed instruction +system.cpu.op_class::total 56114619 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6382 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 212003 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74898 40.89% 40.89% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211965 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74895 40.89% 40.89% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1932 1.05% 42.01% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 106222 57.99% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183183 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73531 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 106217 57.99% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183175 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73528 49.31% 49.31% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1932 1.30% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73531 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149125 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1858233349500 96.76% 96.76% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 91228000 0.00% 96.77% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 737074000 0.04% 96.80% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 61365491500 3.20% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1920427143000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981749 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::31 73528 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149119 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1858230927500 96.76% 96.76% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 91348000 0.00% 96.77% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 737130000 0.04% 96.80% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 61358632500 3.20% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1920418038000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981748 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.692239 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814077 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.692243 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814079 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -450,10 +454,10 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4178 2.17% 2.17% # number of callpals executed -system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed +system.cpu.kern.callpal::swpctx 4176 2.16% 2.17% # number of callpals executed +system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175962 91.21% 93.41% # number of callpals executed +system.cpu.kern.callpal::swpipl 175954 91.22% 93.41% # number of callpals executed system.cpu.kern.callpal::rdps 6833 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed @@ -462,26 +466,26 @@ system.cpu.kern.callpal::whami 2 0.00% 96.97% # nu system.cpu.kern.callpal::rti 5157 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192910 # number of callpals executed +system.cpu.kern.callpal::total 192900 # number of callpals executed system.cpu.kern.mode_switch::kernel 5901 # number of protection mode switches system.cpu.kern.mode_switch::user 1743 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2100 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1914 +system.cpu.kern.mode_switch::idle 2098 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1913 system.cpu.kern.mode_good::user 1743 -system.cpu.kern.mode_good::idle 171 -system.cpu.kern.mode_switch_good::kernel 0.324352 # fraction of useful protection mode switches +system.cpu.kern.mode_good::idle 170 +system.cpu.kern.mode_switch_good::kernel 0.324182 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081429 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.392857 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 46106755000 2.40% 2.40% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5190620000 0.27% 2.67% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1869129766000 97.33% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4179 # number of times the context was actually changed -system.cpu.dcache.tags.replacements 1390139 # number of replacements +system.cpu.kern.mode_switch_good::idle 0.081030 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.392732 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 46109911500 2.40% 2.40% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5189208000 0.27% 2.67% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1869118916500 97.33% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4177 # number of times the context was actually changed +system.cpu.dcache.tags.replacements 1389979 # number of replacements system.cpu.dcache.tags.tagsinuse 511.978885 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 14031130 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1390651 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 10.089613 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 14030604 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1390491 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 10.090395 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 107775250 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.978885 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999959 # Average percentage of cache occupancy @@ -491,72 +495,72 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 system.cpu.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63077780 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63077780 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7803062 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7803062 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5845783 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5845783 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 183030 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183030 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 199238 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 199238 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13648845 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13648845 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13648845 # number of overall hits -system.cpu.dcache.overall_hits::total 13648845 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1069228 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1069228 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 304213 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 304213 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17228 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17228 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1373441 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1373441 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1373441 # number of overall misses -system.cpu.dcache.overall_misses::total 1373441 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 29002641750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 29002641750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10915376130 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10915376130 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228802500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 228802500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 39918017880 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 39918017880 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 39918017880 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 39918017880 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 8872290 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 8872290 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6149996 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6149996 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200258 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200258 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 199238 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 199238 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15022286 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15022286 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15022286 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15022286 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120513 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.120513 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049466 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.049466 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086029 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086029 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.091427 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.091427 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.091427 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.091427 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27124.843111 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 27124.843111 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35880.702435 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35880.702435 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13280.850940 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13280.850940 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 29064.239294 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 29064.239294 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 29064.239294 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 29064.239294 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 63074876 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63074876 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7802731 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7802731 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5845607 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5845607 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183026 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183026 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199223 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 199223 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13648338 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13648338 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13648338 # number of overall hits +system.cpu.dcache.overall_hits::total 13648338 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1069103 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1069103 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304189 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304189 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17217 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17217 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1373292 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1373292 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1373292 # number of overall misses +system.cpu.dcache.overall_misses::total 1373292 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 29000817500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 29000817500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10906930630 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10906930630 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228178000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 228178000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 39907748130 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 39907748130 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 39907748130 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 39907748130 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 8871834 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 8871834 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6149796 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6149796 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200243 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200243 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199223 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199223 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15021630 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15021630 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15021630 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15021630 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120505 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120505 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049463 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049463 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085981 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085981 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.091421 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.091421 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.091421 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.091421 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27126.308223 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 27126.308223 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35855.769374 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35855.769374 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13253.063832 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13253.063832 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 29059.914519 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 29059.914519 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 29059.914519 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 29059.914519 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -565,54 +569,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 834534 # number of writebacks -system.cpu.dcache.writebacks::total 834534 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069228 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1069228 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304213 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304213 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17228 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17228 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1373441 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1373441 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1373441 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1373441 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26738553250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 26738553250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10254282870 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10254282870 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 194333500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 194333500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36992836120 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 36992836120 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36992836120 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 36992836120 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424273000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424273000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2009400000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2009400000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3433673000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3433673000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120513 # 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average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25007.344785 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33707.576172 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33707.576172 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11280.096355 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11280.096355 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26934.419549 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26934.419549 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26934.419549 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26934.419549 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 834368 # 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number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 21717649369 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 800925500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20916723869 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 21717649369 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334183000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334183000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1893600000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1893600000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3227783000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3227783000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014315 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250318 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141560 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6607051619 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6607051619 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 802917750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20907900119 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 21710817869 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 802917750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20907900119 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 21710817869 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334182500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334182500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1893599000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1893599000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3227781500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3227781500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014316 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250348 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141588 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.384101 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.384101 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014315 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279582 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.173372 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014315 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279582 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.173372 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60251.673813 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52587.208918 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52944.379882 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.384118 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.384118 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014316 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279610 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.173402 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014316 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279610 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.173402 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60415.180587 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52584.768604 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52949.595615 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17693.153846 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17693.153846 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56616.277700 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56616.277700 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60251.673813 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53798.019730 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54011.373880 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60251.673813 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53798.019730 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54011.373880 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56548.825031 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56548.825031 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60415.180587 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53776.016520 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53995.458357 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60415.180587 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53776.016520 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53995.458357 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -885,41 +889,41 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2022188 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2022171 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2021758 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2021741 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9650 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9650 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 834534 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 834368 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304196 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304196 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1857238 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3649188 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5506426 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59430976 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142466452 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 201897428 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadExReq 304172 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304172 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1856650 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3648702 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5505352 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59412160 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142445588 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 201857748 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 41901 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3195557 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.013057 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.113520 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 3194937 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.013060 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.113530 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3153832 98.69% 98.69% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3153212 98.69% 98.69% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 41725 1.31% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3195557 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2424565000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3194937 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2424089000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1395517500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1395084250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2186897880 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2186669630 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -992,7 +996,7 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 406189794 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 406198788 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) @@ -1001,14 +1005,14 @@ system.iobus.respLayer0.utilization 0.0 # La system.iobus.respLayer1.occupancy 42010500 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.352352 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.352284 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1753525032000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.352352 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.084522 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.084522 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1753525494000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.352284 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.084518 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.084518 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1022,14 +1026,14 @@ system.iocache.demand_misses::tsunami.ide 173 # n system.iocache.demand_misses::total 173 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 173 # number of overall misses system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21133383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21133383 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13634918911 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 13634918911 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 21133383 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21133383 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 21133383 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21133383 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 23338383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 23338383 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13635239905 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 13635239905 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 23338383 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 23338383 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 23338383 # number of overall miss cycles +system.iocache.overall_miss_latency::total 23338383 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) @@ -1046,19 +1050,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122158.283237 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328141.098166 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 328141.098166 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 122158.283237 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 122158.283237 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 206323 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 134903.947977 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 134903.947977 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328148.823282 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 328148.823282 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 134903.947977 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 134903.947977 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 134903.947977 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 134903.947977 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 206255 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 23561 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.756971 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.754085 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1072,14 +1076,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 173 system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12136383 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11474214911 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11474214911 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 12136383 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 12136383 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 12136383 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 14341383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 14341383 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11474535905 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11474535905 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 14341383 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 14341383 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 14341383 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 14341383 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -1088,55 +1092,55 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276141.098166 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276141.098166 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82898.167630 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 82898.167630 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276148.823282 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276148.823282 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 82898.167630 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 82898.167630 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 82898.167630 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 82898.167630 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 292355 # Transaction distribution -system.membus.trans_dist::ReadResp 292355 # Transaction distribution +system.membus.trans_dist::ReadReq 292351 # Transaction distribution +system.membus.trans_dist::ReadResp 292351 # Transaction distribution system.membus.trans_dist::WriteReq 9650 # Transaction distribution system.membus.trans_dist::WriteResp 9650 # Transaction distribution -system.membus.trans_dist::Writeback 115689 # Transaction distribution +system.membus.trans_dist::Writeback 115682 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution system.membus.trans_dist::UpgradeReq 132 # Transaction distribution system.membus.trans_dist::UpgradeResp 132 # Transaction distribution -system.membus.trans_dist::ReadExReq 116723 # Transaction distribution -system.membus.trans_dist::ReadExResp 116723 # Transaction distribution +system.membus.trans_dist::ReadExReq 116719 # Transaction distribution +system.membus.trans_dist::ReadExResp 116719 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33160 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878118 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911278 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878095 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911255 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124804 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124804 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1036082 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1036059 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44564 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30456384 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30500948 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30455424 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30499988 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317056 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 35818004 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 35817044 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 431 # Total snoops (count) -system.membus.snoop_fanout::samples 559521 # Request fanout histogram +system.membus.snoop_fanout::samples 559506 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 559521 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 559506 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 559521 # Request fanout histogram -system.membus.reqLayer0.occupancy 30373000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 559506 # Request fanout histogram +system.membus.reqLayer0.occupancy 30371500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1824623000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1824515500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 3751921620 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3751827620 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.membus.respLayer2.occupancy 43109500 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index a51b2d079..def60114c 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.802895 # Nu sim_ticks 2802895103500 # Number of ticks simulated final_tick 2802895103500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 967895 # Simulator instruction rate (inst/s) -host_op_rate 1179365 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 18476638236 # Simulator tick rate (ticks/s) -host_mem_usage 571628 # Number of bytes of host memory used -host_seconds 151.70 # Real time elapsed on the host +host_inst_rate 834307 # Simulator instruction rate (inst/s) +host_op_rate 1016590 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15926512431 # Simulator tick rate (ticks/s) +host_mem_usage 572876 # Number of bytes of host memory used +host_seconds 175.99 # Real time elapsed on the host sim_insts 146829031 # Number of instructions simulated sim_ops 178908942 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -93,6 +93,14 @@ system.cf0.dma_write_full_pages 540 # Nu system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -114,6 +122,24 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.walker.walks 7967 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 7967 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 7967 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 7967 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 7967 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 5082 77.32% 77.32% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1491 22.68% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6573 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7967 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7967 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6573 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6573 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 14540 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses system.cpu0.dtb.read_hits 20339962 # DTB read hits @@ -135,6 +161,14 @@ system.cpu0.dtb.inst_accesses 0 # IT system.cpu0.dtb.hits 36731133 # DTB hits system.cpu0.dtb.misses 7967 # DTB misses system.cpu0.dtb.accesses 36739100 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -156,6 +190,24 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.itb.walker.walks 3358 # Table walker walks requested +system.cpu0.itb.walker.walksShort 3358 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walkWaitTime::samples 3358 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 3358 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 3358 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walksPending::samples 6702500 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 6702500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 6702500 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 2040 87.11% 87.11% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 302 12.89% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2342 # Table walker page sizes translated +system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3358 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3358 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2342 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2342 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 5700 # Table walker requests started/completed, data/inst system.cpu0.itb.inst_hits 97440315 # ITB inst hits system.cpu0.itb.inst_misses 3358 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits @@ -371,15 +423,12 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped +system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size +system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing system.cpu0.l2cache.tags.replacements 252403 # number of replacements system.cpu0.l2cache.tags.tagsinuse 16129.283805 # Cycle average of tags in use system.cpu0.l2cache.tags.total_refs 1810262 # Total number of references to valid blocks. @@ -544,6 +593,14 @@ system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::total 2656528 # Request fanout histogram +system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -565,6 +622,24 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.walker.walks 3358 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 3358 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walkWaitTime::samples 3358 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 3358 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 3358 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walksPending::samples -1804206736 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -1804206736 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -1804206736 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 1919 74.15% 74.15% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 669 25.85% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2588 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3358 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3358 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2588 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2588 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 5946 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses system.cpu1.dtb.read_hits 12173884 # DTB read hits @@ -586,6 +661,14 @@ system.cpu1.dtb.inst_accesses 0 # IT system.cpu1.dtb.hits 19761077 # DTB hits system.cpu1.dtb.misses 3358 # DTB misses system.cpu1.dtb.accesses 19764435 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -607,6 +690,24 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.itb.walker.walks 1734 # Table walker walks requested +system.cpu1.itb.walker.walksShort 1734 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walkWaitTime::samples 1734 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 1734 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 1734 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walksPending::samples -1804209236 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -1804209236 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -1804209236 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 935 85.39% 85.39% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 160 14.61% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 1095 # Table walker page sizes translated +system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1734 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1734 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1095 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1095 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 2829 # Table walker requests started/completed, data/inst system.cpu1.itb.inst_hits 53671431 # ITB inst hits system.cpu1.itb.inst_misses 1734 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits @@ -820,15 +921,12 @@ system.cpu1.icache.avg_blocked_cycles::no_targets nan system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped +system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size +system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing system.cpu1.l2cache.tags.replacements 48598 # number of replacements system.cpu1.l2cache.tags.tagsinuse 15305.342188 # Cycle average of tags in use system.cpu1.l2cache.tags.total_refs 716678 # Total number of references to valid blocks. diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index 5c160a43e..fb9bec115 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.783867 # Nu sim_ticks 2783867165000 # Number of ticks simulated final_tick 2783867165000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1064003 # Simulator instruction rate (inst/s) -host_op_rate 1295252 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 20746494205 # Simulator tick rate (ticks/s) -host_mem_usage 558936 # Number of bytes of host memory used -host_seconds 134.19 # Real time elapsed on the host +host_inst_rate 1374338 # Simulator instruction rate (inst/s) +host_op_rate 1673035 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 26797569978 # Simulator tick rate (ticks/s) +host_mem_usage 615488 # Number of bytes of host memory used +host_seconds 103.89 # Real time elapsed on the host sim_insts 142773109 # Number of instructions simulated sim_ops 173803334 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -70,6 +70,14 @@ system.cf0.dma_write_full_pages 540 # Nu system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -91,6 +99,24 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 10029 # Table walker walks requested +system.cpu.dtb.walker.walksShort 10029 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walkWaitTime::samples 10029 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 10029 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 10029 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 6354 80.79% 80.79% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1511 19.21% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7865 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 10029 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 10029 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7865 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7865 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 17894 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 31526301 # DTB read hits @@ -112,6 +138,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 54650764 # DTB hits system.cpu.dtb.misses 10029 # DTB misses system.cpu.dtb.accesses 54660793 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -133,6 +167,24 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 4762 # Table walker walks requested +system.cpu.itb.walker.walksShort 4762 # Table walker walks initiated with short descriptors +system.cpu.itb.walker.walkWaitTime::samples 4762 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 4762 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 4762 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walksPending::samples 6702500 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 6702500 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 6702500 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 2798 90.05% 90.05% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::1M 309 9.95% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 3107 # Table walker page sizes translated +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 4762 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 4762 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3107 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 3107 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 7869 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 147039592 # ITB inst hits system.cpu.itb.inst_misses 4762 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index ede2b82db..391769400 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,164 +1,160 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.867049 # Number of seconds simulated -sim_ticks 2867048515500 # Number of ticks simulated -final_tick 2867048515500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.868319 # Number of seconds simulated +sim_ticks 2868318696500 # Number of ticks simulated +final_tick 2868318696500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 753572 # Simulator instruction rate (inst/s) -host_op_rate 911512 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 16376301643 # Simulator tick rate (ticks/s) -host_mem_usage 607016 # Number of bytes of host memory used -host_seconds 175.07 # Real time elapsed on the host -sim_insts 131930165 # Number of instructions simulated -sim_ops 159581077 # Number of ops (including micro ops) simulated +host_inst_rate 534652 # Simulator instruction rate (inst/s) +host_op_rate 646675 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 11631340017 # Simulator tick rate (ticks/s) +host_mem_usage 586476 # Number of bytes of host memory used +host_seconds 246.60 # Real time elapsed on the host +sim_insts 131846562 # Number of instructions simulated +sim_ops 159471778 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 233060 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 810048 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 9243456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 53844 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 455584 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 1704320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1173796 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1283584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8628800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 156308 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 605472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 378048 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12502168 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 233060 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 53844 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 286904 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8696768 # Number of bytes written to this memory +system.physmem.bytes_read::total 12227608 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1173796 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 156308 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1330104 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8654400 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8714512 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 8 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 12095 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 13183 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 144429 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 996 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 7142 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 26630 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8672144 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 26794 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 20582 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 134825 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2597 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 9484 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 5907 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 204504 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 135887 # Number of write requests responded to by this memory +system.physmem.num_reads::total 200214 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 135225 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 140323 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 179 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 81289 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 282537 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 3224032 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 89 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 18780 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 158903 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 594451 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 139661 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 156 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 409228 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 447504 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 3008313 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 22 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 54495 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 211090 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 131801 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 335 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4360641 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 81289 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 18780 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 100069 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3033352 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6175 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4262988 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 409228 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 54495 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 463723 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3017238 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6172 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3039541 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3033352 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 179 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 81289 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 288712 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 3224032 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 89 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 18780 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 158917 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 594451 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3023424 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3017238 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 156 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 409228 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 453676 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 3008313 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 22 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 54495 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 211103 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 131801 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 335 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7400182 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 204505 # Number of read requests accepted -system.physmem.writeReqs 176547 # Number of write requests accepted -system.physmem.readBursts 204505 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 176547 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 13079232 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9088 # Total number of bytes read from write queue -system.physmem.bytesWritten 10932800 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12502232 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 11032848 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 142 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 5691 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 15171 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12666 # Per bank write bursts -system.physmem.perBankRdBursts::1 12263 # Per bank write bursts -system.physmem.perBankRdBursts::2 12897 # Per bank write bursts -system.physmem.perBankRdBursts::3 12449 # Per bank write bursts -system.physmem.perBankRdBursts::4 21010 # Per bank write bursts -system.physmem.perBankRdBursts::5 12626 # Per bank write bursts -system.physmem.perBankRdBursts::6 12991 # Per bank write bursts -system.physmem.perBankRdBursts::7 13024 # Per bank write bursts -system.physmem.perBankRdBursts::8 12039 # Per bank write bursts -system.physmem.perBankRdBursts::9 12109 # Per bank write bursts -system.physmem.perBankRdBursts::10 12276 # Per bank write bursts -system.physmem.perBankRdBursts::11 10996 # Per bank write bursts -system.physmem.perBankRdBursts::12 11725 # Per bank write bursts -system.physmem.perBankRdBursts::13 12231 # Per bank write bursts -system.physmem.perBankRdBursts::14 11672 # Per bank write bursts -system.physmem.perBankRdBursts::15 11389 # Per bank write bursts -system.physmem.perBankWrBursts::0 10702 # Per bank write bursts -system.physmem.perBankWrBursts::1 10814 # Per bank write bursts -system.physmem.perBankWrBursts::2 11122 # Per bank write bursts -system.physmem.perBankWrBursts::3 10684 # Per bank write bursts -system.physmem.perBankWrBursts::4 10817 # Per bank write bursts -system.physmem.perBankWrBursts::5 11014 # Per bank write bursts -system.physmem.perBankWrBursts::6 11094 # Per bank write bursts -system.physmem.perBankWrBursts::7 11085 # Per bank write bursts -system.physmem.perBankWrBursts::8 10650 # Per bank write bursts -system.physmem.perBankWrBursts::9 11040 # Per bank write bursts -system.physmem.perBankWrBursts::10 10845 # Per bank write bursts -system.physmem.perBankWrBursts::11 10150 # Per bank write bursts -system.physmem.perBankWrBursts::12 10760 # Per bank write bursts -system.physmem.perBankWrBursts::13 10359 # Per bank write bursts -system.physmem.perBankWrBursts::14 10115 # Per bank write bursts -system.physmem.perBankWrBursts::15 9574 # Per bank write bursts +system.physmem.bw_total::total 7286412 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 200214 # Number of read requests accepted +system.physmem.writeReqs 175885 # Number of write requests accepted +system.physmem.readBursts 200214 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 175885 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12804096 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9600 # Total number of bytes read from write queue +system.physmem.bytesWritten 10892544 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12227608 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10990480 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 150 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 5671 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 13850 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 12188 # Per bank write bursts +system.physmem.perBankRdBursts::1 12046 # Per bank write bursts +system.physmem.perBankRdBursts::2 12591 # Per bank write bursts +system.physmem.perBankRdBursts::3 12330 # Per bank write bursts +system.physmem.perBankRdBursts::4 20750 # Per bank write bursts +system.physmem.perBankRdBursts::5 12582 # Per bank write bursts +system.physmem.perBankRdBursts::6 12043 # Per bank write bursts +system.physmem.perBankRdBursts::7 12246 # Per bank write bursts +system.physmem.perBankRdBursts::8 12442 # Per bank write bursts +system.physmem.perBankRdBursts::9 12402 # Per bank write bursts +system.physmem.perBankRdBursts::10 11722 # Per bank write bursts +system.physmem.perBankRdBursts::11 11146 # Per bank write bursts +system.physmem.perBankRdBursts::12 11467 # Per bank write bursts +system.physmem.perBankRdBursts::13 11916 # Per bank write bursts +system.physmem.perBankRdBursts::14 10852 # Per bank write bursts +system.physmem.perBankRdBursts::15 11341 # Per bank write bursts +system.physmem.perBankWrBursts::0 10835 # Per bank write bursts +system.physmem.perBankWrBursts::1 11264 # Per bank write bursts +system.physmem.perBankWrBursts::2 11493 # Per bank write bursts +system.physmem.perBankWrBursts::3 10899 # Per bank write bursts +system.physmem.perBankWrBursts::4 10487 # Per bank write bursts +system.physmem.perBankWrBursts::5 11152 # Per bank write bursts +system.physmem.perBankWrBursts::6 11024 # Per bank write bursts +system.physmem.perBankWrBursts::7 10595 # Per bank write bursts +system.physmem.perBankWrBursts::8 10782 # Per bank write bursts +system.physmem.perBankWrBursts::9 10958 # Per bank write bursts +system.physmem.perBankWrBursts::10 10716 # Per bank write bursts +system.physmem.perBankWrBursts::11 10408 # Per bank write bursts +system.physmem.perBankWrBursts::12 10444 # Per bank write bursts +system.physmem.perBankWrBursts::13 9906 # Per bank write bursts +system.physmem.perBankWrBursts::14 9416 # Per bank write bursts +system.physmem.perBankWrBursts::15 9817 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2867048141000 # Total gap between requests +system.physmem.numWrRetry 1 # Number of times write queue was full causing retry +system.physmem.totGap 2868318254500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9742 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 194735 # Read request sizes (log2) +system.physmem.readPktSize::6 190444 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4436 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 172111 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 120800 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 21636 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 13302 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 11154 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 9500 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 8185 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 6994 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 6210 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 5370 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 523 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 257 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 166 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 124 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 70 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 45 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 23 # What read queue length does an incoming req see +system.physmem.writePktSize::6 171449 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 138850 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 16077 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 10399 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9072 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7297 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5697 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4782 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4036 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3549 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 129 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 88 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 52 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 20 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -188,178 +184,179 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2981 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4683 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6009 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 8149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 9072 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 10204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 10828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 11783 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 11696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 12526 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 11858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 11537 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 10823 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 10903 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8826 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8488 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 596 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 465 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2909 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4636 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 8259 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 9096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 10239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 10826 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 11796 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 11771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 12530 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 11837 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 11533 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 10810 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 10665 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8741 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8094 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 533 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 391 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 83 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 26 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 83215 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 288.553362 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 159.296581 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 336.078048 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 39267 47.19% 47.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 16171 19.43% 66.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6480 7.79% 74.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3347 4.02% 78.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3132 3.76% 82.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1913 2.30% 84.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1073 1.29% 85.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1034 1.24% 87.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10798 12.98% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 83215 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7042 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 29.019171 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 531.269210 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 7040 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::57 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 90415 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 262.086778 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 144.561031 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 323.181928 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 46335 51.25% 51.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17813 19.70% 70.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6067 6.71% 77.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3600 3.98% 81.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2534 2.80% 84.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1568 1.73% 86.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1031 1.14% 87.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 985 1.09% 88.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 10482 11.59% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 90415 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7120 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.098736 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 516.724228 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 7117 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 2 0.03% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7042 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7042 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 24.258023 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.337274 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 22.786425 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5509 78.23% 78.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 384 5.45% 83.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 77 1.09% 84.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 222 3.15% 87.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 122 1.73% 89.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 57 0.81% 90.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 43 0.61% 91.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 37 0.53% 91.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 124 1.76% 93.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 15 0.21% 93.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 18 0.26% 93.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 16 0.23% 94.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 34 0.48% 94.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 16 0.23% 94.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 7 0.10% 94.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 27 0.38% 95.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 62 0.88% 96.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 11 0.16% 96.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 6 0.09% 96.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 10 0.14% 96.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 88 1.25% 97.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 4 0.06% 97.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 12 0.17% 98.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 6 0.09% 98.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 19 0.27% 98.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 2 0.03% 98.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 11 0.16% 98.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 4 0.06% 98.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 36 0.51% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 11 0.16% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 4 0.06% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 7 0.10% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 5 0.07% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 2 0.03% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.01% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 7 0.10% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 2 0.03% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 4 0.06% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 4 0.06% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.01% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 2 0.03% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.01% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 2 0.03% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 1 0.01% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::204-207 1 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 2 0.03% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-219 1 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 1 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-235 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-251 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::252-255 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7042 # Writes before turning the bus around for reads -system.physmem.totQLat 5974898500 # Total ticks spent queuing -system.physmem.totMemAccLat 9806704750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1021815000 # Total ticks spent in databus transfers -system.physmem.avgQLat 29236.69 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 7120 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7120 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 23.903933 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.122109 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 22.073987 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5764 80.96% 80.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 237 3.33% 84.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 43 0.60% 84.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 234 3.29% 88.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 121 1.70% 89.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 62 0.87% 90.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 31 0.44% 91.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 36 0.51% 91.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 117 1.64% 93.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 18 0.25% 93.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 25 0.35% 93.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 16 0.22% 94.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 40 0.56% 94.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 10 0.14% 94.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 17 0.24% 95.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 28 0.39% 95.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 58 0.81% 96.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 14 0.20% 96.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 7 0.10% 96.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 6 0.08% 96.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 88 1.24% 97.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 4 0.06% 97.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 12 0.17% 98.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.01% 98.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 15 0.21% 98.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 6 0.08% 98.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 14 0.20% 98.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 9 0.13% 98.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 35 0.49% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 6 0.08% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.01% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 4 0.06% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 8 0.11% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 2 0.03% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 3 0.04% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.01% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 8 0.11% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 2 0.03% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.01% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.01% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 4 0.06% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.01% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.01% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 1 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 1 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 1 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 3 0.04% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 3 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7120 # Writes before turning the bus around for reads +system.physmem.totQLat 4855930250 # Total ticks spent queuing +system.physmem.totMemAccLat 8607130250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1000320000 # Total ticks spent in databus transfers +system.physmem.avgQLat 24271.88 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 47986.69 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.56 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.81 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.36 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.85 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 43021.88 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.46 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.80 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.26 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.83 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.07 # Data bus utilization in percentage -system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.06 # Data bus utilization in percentage +system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 2.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.00 # Average write queue length when enqueuing -system.physmem.readRowHits 174382 # Number of row buffer hits during reads -system.physmem.writeRowHits 117590 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.33 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 68.82 # Row buffer hit rate for writes -system.physmem.avgGap 7524033.84 # Average gap between requests -system.physmem.pageHitRate 77.81 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2731090191250 # Time in different power states -system.physmem.memoryStateTime::REF 95736940000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 40221363750 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 330432480 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 298672920 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 180295500 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 162966375 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 857422800 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 736600800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 565911360 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 541034640 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 187261454640 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 187261454640 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 82724898285 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 81530993385 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1647661560750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1648708845750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1919581975815 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1919240568510 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.533155 # Core power per rank (mW) -system.physmem.averagePower::1 669.414075 # Core power per rank (mW) +system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing +system.physmem.avgWrQLen 22.69 # Average write queue length when enqueuing +system.physmem.readRowHits 167229 # Number of row buffer hits during reads +system.physmem.writeRowHits 112615 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.59 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 66.16 # Row buffer hit rate for writes +system.physmem.avgGap 7626497.96 # Average gap between requests +system.physmem.pageHitRate 75.58 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 354707640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 193540875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 832845000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 568613520 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 187344349920 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 84727272375 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1646666587500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1920687916830 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.622475 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2739235632500 # Time in different power states +system.physmem_0.memoryStateTime::REF 95779320000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 33303656000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 328829760 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 179421000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 727646400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 534256560 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 187344349920 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 83962556955 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1647337390500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1920414451095 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.527135 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2740355751000 # Time in different power states +system.physmem_1.memoryStateTime::REF 95779320000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 32179536500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -385,6 +382,14 @@ system.cf0.dma_write_full_pages 540 # Nu system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -406,27 +411,65 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.walker.walks 7749 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 7749 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1459 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6290 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 7749 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 7749 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 7749 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 6355 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 8363.375452 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 7097.000757 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 5454.838397 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 6203 97.61% 97.61% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 142 2.23% 99.84% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 6 0.09% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::81920-98303 3 0.05% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 6355 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 987959000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 987959000 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 987959000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 4935 77.66% 77.66% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1420 22.34% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6355 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7749 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7749 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6355 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6355 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 14104 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 22739909 # DTB read hits -system.cpu0.dtb.read_misses 4142 # DTB read misses -system.cpu0.dtb.write_hits 16676295 # DTB write hits -system.cpu0.dtb.write_misses 677 # DTB write misses +system.cpu0.dtb.read_hits 19044092 # DTB read hits +system.cpu0.dtb.read_misses 6608 # DTB read misses +system.cpu0.dtb.write_hits 15688894 # DTB write hits +system.cpu0.dtb.write_misses 1141 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2392 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 3442 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1346 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 1734 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 187 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 22744051 # DTB read accesses -system.cpu0.dtb.write_accesses 16676972 # DTB write accesses +system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 19050700 # DTB read accesses +system.cpu0.dtb.write_accesses 15690035 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 39416204 # DTB hits -system.cpu0.dtb.misses 4819 # DTB misses -system.cpu0.dtb.accesses 39421023 # DTB accesses +system.cpu0.dtb.hits 34732986 # DTB hits +system.cpu0.dtb.misses 7749 # DTB misses +system.cpu0.dtb.accesses 34740735 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -448,8 +491,40 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 107931670 # ITB inst hits -system.cpu0.itb.inst_misses 2300 # ITB inst misses +system.cpu0.itb.walker.walks 3348 # Table walker walks requested +system.cpu0.itb.walker.walksShort 3348 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 298 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3050 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 3348 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 3348 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 3348 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2332 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 8781.732419 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 7396.194245 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 5559.104899 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 1469 62.99% 62.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 817 35.03% 98.03% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 4 0.17% 98.20% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 39 1.67% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.04% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::106496-114687 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2332 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 987617000 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 987617000 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 987617000 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 2034 87.22% 87.22% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 298 12.78% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2332 # Table walker page sizes translated +system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3348 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3348 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2332 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2332 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 5680 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 91510827 # ITB inst hits +system.cpu0.itb.inst_misses 3348 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -458,178 +533,179 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1397 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2150 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 107933970 # ITB inst accesses -system.cpu0.itb.hits 107931670 # DTB hits -system.cpu0.itb.misses 2300 # DTB misses -system.cpu0.itb.accesses 107933970 # DTB accesses -system.cpu0.numCycles 5733190951 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 91514175 # ITB inst accesses +system.cpu0.itb.hits 91510827 # DTB hits +system.cpu0.itb.misses 3348 # DTB misses +system.cpu0.itb.accesses 91514175 # DTB accesses +system.cpu0.numCycles 5736637393 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 104697045 # Number of instructions committed -system.cpu0.committedOps 126437300 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 112138973 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 4560 # Number of float alu accesses -system.cpu0.num_func_calls 12218983 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 14112779 # number of instructions that are conditional controls -system.cpu0.num_int_insts 112138973 # number of integer instructions -system.cpu0.num_fp_insts 4560 # number of float instructions -system.cpu0.num_int_register_reads 207168140 # number of times the integer registers were read -system.cpu0.num_int_register_writes 78157614 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3646 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 916 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 458862041 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 46623468 # number of times the CC registers were written -system.cpu0.num_mem_refs 40473955 # number of memory refs -system.cpu0.num_load_insts 22968630 # Number of load instructions -system.cpu0.num_store_insts 17505325 # Number of store instructions -system.cpu0.num_idle_cycles 5494072814.437573 # Number of idle cycles -system.cpu0.num_busy_cycles 239118136.562427 # Number of busy cycles -system.cpu0.not_idle_fraction 0.041708 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.958292 # Percentage of idle cycles -system.cpu0.Branches 26957408 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2171 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 89486890 68.80% 68.80% # Class of executed instruction -system.cpu0.op_class::IntMult 99356 0.08% 68.88% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 6997 0.01% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::MemRead 22968630 17.66% 86.54% # Class of executed instruction -system.cpu0.op_class::MemWrite 17505325 13.46% 100.00% # Class of executed instruction +system.cpu0.committedInsts 89363678 # Number of instructions committed +system.cpu0.committedOps 107297883 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 94350928 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 9820 # Number of float alu accesses +system.cpu0.num_func_calls 6606472 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 12627044 # number of instructions that are conditional controls +system.cpu0.num_int_insts 94350928 # number of integer instructions +system.cpu0.num_fp_insts 9820 # number of float instructions +system.cpu0.num_int_register_reads 169124164 # number of times the integer registers were read +system.cpu0.num_int_register_writes 64348180 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 7560 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 385798415 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 43074064 # number of times the CC registers were written +system.cpu0.num_mem_refs 35866705 # number of memory refs +system.cpu0.num_load_insts 19295047 # Number of load instructions +system.cpu0.num_store_insts 16571658 # Number of store instructions +system.cpu0.num_idle_cycles 5512519658.266078 # Number of idle cycles +system.cpu0.num_busy_cycles 224117734.733922 # Number of busy cycles +system.cpu0.not_idle_fraction 0.039068 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.960932 # Percentage of idle cycles +system.cpu0.Branches 19970568 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 73557669 67.15% 67.15% # Class of executed instruction +system.cpu0.op_class::IntMult 108302 0.10% 67.25% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 8177 0.01% 67.26% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction +system.cpu0.op_class::MemRead 19295047 17.61% 84.87% # Class of executed instruction +system.cpu0.op_class::MemWrite 16571658 15.13% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 130069369 # Class of executed instruction +system.cpu0.op_class::total 109543126 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1990 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 555287 # number of replacements -system.cpu0.dcache.tags.tagsinuse 484.900335 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 38705991 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 555652 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 69.658691 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 1015660000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 484.900335 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.947071 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.947071 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 302 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 63 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.712891 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 79342035 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 79342035 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 21654746 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 21654746 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 16040843 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 16040843 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 304713 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 304713 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 334336 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 334336 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 329300 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 329300 # 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number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 20705 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 568330 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 568330 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 660582 # number of overall misses -system.cpu0.dcache.overall_misses::total 660582 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3916535020 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 3916535020 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4029841681 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 4029841681 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 322461501 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 322461501 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 462579693 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 462579693 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1480500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1480500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 7946376701 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 7946376701 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 7946376701 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 7946376701 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 21959658 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 21959658 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 16304261 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 16304261 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 396965 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 396965 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 354406 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 354406 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 350005 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 350005 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 38263919 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 38263919 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 38660884 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 38660884 # 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Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 275 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 126 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 70103571 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 70103571 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 17785791 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 17785791 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 14958877 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 14958877 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 318525 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 318525 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 364927 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 364927 # 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number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 21710 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20007 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 20007 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 719386 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 719386 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 847118 # number of overall misses +system.cpu0.dcache.overall_misses::total 847118 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4990872752 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 4990872752 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4944330313 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 4944330313 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 327573000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 327573000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 444426745 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 444426745 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1572500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1572500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 9935203065 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 9935203065 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 9935203065 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 9935203065 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 18180696 # 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average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15088.576693 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22213.562503 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22213.562503 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13981.976494 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 13981.976494 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12029.356993 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 12029.356993 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13810.670579 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 13810.670579 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 11728.239826 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 11728.239826 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -638,82 +714,82 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 420867 # number of writebacks -system.cpu0.dcache.writebacks::total 420867 # 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number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1400500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6726360299 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 6726360299 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7766691538 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 7766691538 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5556589244 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5556589244 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4171949493 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4171949493 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 9728538737 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 9728538737 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.013557 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.013557 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.016156 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.016156 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.210152 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.210152 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016755 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016755 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.059156 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.059156 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.014664 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.014664 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.016672 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.016672 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10856.637969 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10856.637969 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 13265.336154 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 13265.336154 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12470.556549 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 12470.556549 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14526.860896 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14526.860896 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20306.221058 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20306.221058 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 504116 # number of writebacks +system.cpu0.dcache.writebacks::total 504116 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25128 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 25128 # number of ReadReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15248 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15248 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 25128 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 25128 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 25128 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 25128 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 369777 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 369777 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 324481 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 324481 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 100470 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 100470 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6462 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6462 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20007 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 20007 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 694258 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 694258 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 794728 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 794728 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3859056498 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3859056498 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4283066685 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4283066685 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1502769500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1502769500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 90797250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 90797250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 403751255 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 403751255 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1480500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1480500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8142123183 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 8142123183 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 9644892683 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 9644892683 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5991645999 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5991645999 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4628507500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4628507500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10620153499 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10620153499 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.020339 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.020339 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.021231 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021231 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225139 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225139 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016713 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016713 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052414 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052414 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.020746 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.020746 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.023436 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.023436 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10436.172336 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10436.172336 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 13199.745702 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 13199.745702 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 14957.395242 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14957.395242 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14050.951718 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14050.951718 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20180.499575 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20180.499575 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 11987.404274 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11987.404274 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 12049.938620 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12049.938620 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 11727.806065 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11727.806065 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 12136.092705 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12136.092705 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -721,58 +797,58 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 945322 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.483250 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 106985827 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 945834 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 113.112689 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 12806917500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.483250 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998991 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998991 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 1099798 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.479276 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 90410508 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1100310 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 82.168214 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 13323414750 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.479276 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998983 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998983 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 390 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 113 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::4 9 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 206 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 215 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 216809183 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 216809183 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 106985827 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 106985827 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 106985827 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 106985827 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 106985827 # number of overall hits -system.cpu0.icache.overall_hits::total 106985827 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 945843 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 945843 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 945843 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 945843 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 945843 # number of overall misses -system.cpu0.icache.overall_misses::total 945843 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 8025066767 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 8025066767 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 8025066767 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 8025066767 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 8025066767 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 8025066767 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 107931670 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 107931670 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 107931670 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 107931670 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 107931670 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 107931670 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.008763 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.008763 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.008763 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.008763 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.008763 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.008763 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8484.565374 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 8484.565374 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8484.565374 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 8484.565374 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8484.565374 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 8484.565374 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 184121973 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 184121973 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 90410508 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 90410508 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 90410508 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 90410508 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 90410508 # number of overall hits +system.cpu0.icache.overall_hits::total 90410508 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1100319 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1100319 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1100319 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1100319 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1100319 # number of overall misses +system.cpu0.icache.overall_misses::total 1100319 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10739818993 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 10739818993 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 10739818993 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 10739818993 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 10739818993 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 10739818993 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 91510827 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 91510827 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 91510827 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 91510827 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 91510827 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 91510827 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.012024 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.012024 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.012024 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.012024 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.012024 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.012024 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9760.641226 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 9760.641226 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9760.641226 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 9760.641226 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9760.641226 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 9760.641226 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -781,356 +857,353 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 945843 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 945843 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 945843 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 945843 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 945843 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 945843 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 6605629733 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 6605629733 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 6605629733 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 6605629733 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 6605629733 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 6605629733 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1100319 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1100319 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 1100319 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1100319 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 1100319 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1100319 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9082830507 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 9082830507 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9082830507 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 9082830507 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9082830507 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 9082830507 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 719096500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 719096500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 719096500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 719096500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.008763 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.008763 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.008763 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.008763 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.008763 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.008763 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 6983.854332 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6983.854332 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6983.854332 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 6983.854332 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6983.854332 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 6983.854332 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.012024 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.012024 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.012024 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.012024 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.012024 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.012024 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8254.724773 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8254.724773 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8254.724773 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 8254.724773 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8254.724773 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 8254.724773 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 8798864 # number of hwpf identified -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 212139 # number of hwpf that were already in mshr -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 8184021 # number of hwpf that were already in the cache -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 360 # number of hwpf that were already in the prefetch queue -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 34 # number of hwpf removed because MSHR allocated -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 402310 # number of hwpf issued -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 695408 # number of hwpf spanning a virtual page -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.l2cache.tags.replacements 309925 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16107.929627 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 1687462 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 325154 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 5.189732 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1853283 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1853292 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 7 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped +system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size +system.cpu0.l2cache.prefetcher.pfSpanPage 238164 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 268426 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16093.899190 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 1968322 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 284663 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 6.914569 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 6744.420736 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 3.207457 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.111326 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 773.977995 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1150.108298 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 7436.103816 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.411647 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000196 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_blocks::writebacks 7921.036071 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 2.357121 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.109776 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4473.771805 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1953.197848 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1743.426570 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.483462 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000144 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000007 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.047240 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.070197 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.453864 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.983150 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 9588 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 5627 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 66 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 1190 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 8332 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 265 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 1207 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4155 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.585205 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000854 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.343445 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 33371196 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 33371196 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 4956 # 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number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 2411 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 933239 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 492741 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 1433347 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 4956 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 2411 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 933239 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 492741 # number of overall hits -system.cpu0.l2cache.overall_hits::total 1433347 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 350 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 252 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 12604 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.data 77312 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 90518 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 29431 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 29431 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19057 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 19057 # number of SCUpgradeReq misses +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.273057 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.119214 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.106410 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.982294 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1127 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15106 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 9 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 288 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 418 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 412 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 118 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3213 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7809 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3908 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.068787 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000244 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.921997 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 39654154 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 39654154 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7774 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3610 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1053168 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.data 381762 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 1446314 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 504114 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 504114 # number of Writeback hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28406 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 28406 # number of UpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1700 # number of SCUpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::total 1700 # number of SCUpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 227802 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 227802 # number of ReadExReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 7774 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3610 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 1053168 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 609564 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 1674116 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 7774 # 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mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.181442 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.098416 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.026912 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.032690 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.042852 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.181442 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.337710 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 14777.142857 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 13642.857143 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 38461.796703 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 20786.539028 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 22948.970488 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41504.638547 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 41504.638547 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16022.760491 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16022.760491 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13487.284200 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13487.284200 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 135061.875000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 135061.875000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 25088.846516 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 25088.846516 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 14777.142857 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 13642.857143 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 38461.796703 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 22295.614310 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 23632.150845 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 14777.142857 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 13642.857143 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 38461.796703 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 22295.614310 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41504.638547 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 37234.830640 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.230973 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 15787.209302 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15241.803279 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 39810.184365 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 21210.648570 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 27355.831422 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56455.149661 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 56455.149661 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16861.304032 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16861.304032 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13443.888901 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13443.888901 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 139061.875000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 139061.875000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 34119.787657 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 34119.787657 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 15787.209302 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15241.803279 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 39810.184365 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 25069.984593 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 28852.904128 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 15787.209302 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15241.803279 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 39810.184365 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 25069.984593 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56455.149661 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 44694.051386 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1140,58 +1213,66 @@ system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 1585084 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1436635 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 26190 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 26190 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 420867 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 537670 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 82377 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43315 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 100677 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadReq 1737767 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1686227 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 27891 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 27891 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 504114 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 316054 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 89164 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42476 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 112407 # Transaction distribution system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 43 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 75 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 246727 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 235853 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1909730 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 1979159 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 7030 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 14021 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 3909940 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 60570040 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 70330266 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10652 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 21224 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 130932182 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 972661 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 2913864 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.296127 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.456548 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 81 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 298764 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 285064 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2218682 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2366147 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10130 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 22028 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 4616987 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 70456504 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 84324454 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 14928 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 31956 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 154827842 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 648932 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 2984532 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 5.180419 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.384536 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 2050990 70.39% 70.39% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 862874 29.61% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::5 2446067 81.96% 81.96% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::6 538465 18.04% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 2913864 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 1492069922 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 2984532 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 1775358935 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 116074499 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 115165999 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1430234267 # Layer occupancy (ticks) -system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 995136418 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 1664866493 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer1.occupancy 1209535062 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 4367000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 6398000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 8715750 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 14039749 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1213,27 +1294,67 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.walker.walks 3332 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 3332 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 642 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2690 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 3332 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 3332 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 3332 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 2562 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 8324.355972 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 7260.502547 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 4990.324891 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 2067 80.68% 80.68% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 375 14.64% 95.32% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-24575 62 2.42% 97.74% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-32767 50 1.95% 99.69% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-40959 4 0.16% 99.84% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::40960-49151 3 0.12% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::81920-90111 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 2562 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 1455144968 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1455144968 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 1455144968 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 1928 75.25% 75.25% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 634 24.75% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2562 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3332 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3332 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2562 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2562 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 5894 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 6438534 # DTB read hits -system.cpu1.dtb.read_misses 5066 # DTB read misses -system.cpu1.dtb.write_hits 5578600 # DTB write hits -system.cpu1.dtb.write_misses 983 # DTB write misses +system.cpu1.dtb.read_hits 10115566 # DTB read hits +system.cpu1.dtb.read_misses 2828 # DTB read misses +system.cpu1.dtb.write_hits 6544640 # DTB write hits +system.cpu1.dtb.write_misses 504 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 3048 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 2029 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 541 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 346 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 258 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 6443600 # DTB read accesses -system.cpu1.dtb.write_accesses 5579583 # DTB write accesses +system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 10118394 # DTB read accesses +system.cpu1.dtb.write_accesses 6545144 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 12017134 # DTB hits -system.cpu1.dtb.misses 6049 # DTB misses -system.cpu1.dtb.accesses 12023183 # DTB accesses +system.cpu1.dtb.hits 16660206 # DTB hits +system.cpu1.dtb.misses 3332 # DTB misses +system.cpu1.dtb.accesses 16663538 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1255,8 +1376,42 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 28023624 # ITB inst hits -system.cpu1.itb.inst_misses 2794 # ITB inst misses +system.cpu1.itb.walker.walks 1746 # Table walker walks requested +system.cpu1.itb.walker.walksShort 1746 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 168 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1578 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 1746 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 1746 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 1746 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 1107 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 8955.736224 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 7685.889357 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 5645.921496 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-4095 191 17.25% 17.25% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 643 58.08% 75.34% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 217 19.60% 94.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 1 0.09% 95.03% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-24575 3 0.27% 95.30% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 27 2.44% 97.74% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 19 1.72% 99.46% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::36864-40959 3 0.27% 99.73% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-45055 3 0.27% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 1107 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 1454651968 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1454651968 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 1454651968 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 939 84.82% 84.82% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 168 15.18% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 1107 # Table walker page sizes translated +system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1746 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1746 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1107 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1107 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 2853 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 44359905 # ITB inst hits +system.cpu1.itb.inst_misses 1746 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1265,179 +1420,178 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1901 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1148 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 28026418 # ITB inst accesses -system.cpu1.itb.hits 28023624 # DTB hits -system.cpu1.itb.misses 2794 # DTB misses -system.cpu1.itb.accesses 28026418 # DTB accesses -system.cpu1.numCycles 5734097031 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 44361651 # ITB inst accesses +system.cpu1.itb.hits 44359905 # DTB hits +system.cpu1.itb.misses 1746 # DTB misses +system.cpu1.itb.accesses 44361651 # DTB accesses +system.cpu1.numCycles 5735725430 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 27233120 # Number of instructions committed -system.cpu1.committedOps 33143777 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 29468029 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 6988 # Number of float alu accesses -system.cpu1.num_func_calls 1518648 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3438745 # number of instructions that are conditional controls -system.cpu1.num_int_insts 29468029 # number of integer instructions -system.cpu1.num_fp_insts 6988 # number of float instructions -system.cpu1.num_int_register_reads 53045981 # number of times the integer registers were read -system.cpu1.num_int_register_writes 20334319 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 5190 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1800 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 119969216 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 12226644 # number of times the CC registers were written -system.cpu1.num_mem_refs 12358568 # number of memory refs -system.cpu1.num_load_insts 6575418 # Number of load instructions -system.cpu1.num_store_insts 5783150 # Number of store instructions -system.cpu1.num_idle_cycles 5655719559.150027 # Number of idle cycles -system.cpu1.num_busy_cycles 78377471.849973 # Number of busy cycles -system.cpu1.not_idle_fraction 0.013669 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.986331 # Percentage of idle cycles -system.cpu1.Branches 5151142 # Number of branches fetched -system.cpu1.op_class::No_OpClass 168 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 21257809 63.16% 63.16% # Class of executed instruction -system.cpu1.op_class::IntMult 38403 0.11% 63.27% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 4420 0.01% 63.28% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 63.28% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 63.28% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 63.28% # Class of executed instruction -system.cpu1.op_class::MemRead 6575418 19.54% 82.82% # Class of executed instruction -system.cpu1.op_class::MemWrite 5783150 17.18% 100.00% # Class of executed instruction +system.cpu1.committedInsts 42482884 # Number of instructions committed +system.cpu1.committedOps 52173895 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 47161467 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 1857 # Number of float alu accesses +system.cpu1.num_func_calls 7121857 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 4915281 # number of instructions that are conditional controls +system.cpu1.num_int_insts 47161467 # number of integer instructions +system.cpu1.num_fp_insts 1857 # number of float instructions +system.cpu1.num_int_register_reads 90906541 # number of times the integer registers were read +system.cpu1.num_int_register_writes 34070734 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 1341 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 192636366 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 15749934 # number of times the CC registers were written +system.cpu1.num_mem_refs 16924073 # number of memory refs +system.cpu1.num_load_insts 10229886 # Number of load instructions +system.cpu1.num_store_insts 6694187 # Number of store instructions +system.cpu1.num_idle_cycles 5637554126.704413 # Number of idle cycles +system.cpu1.num_busy_cycles 98171303.295587 # Number of busy cycles +system.cpu1.not_idle_fraction 0.017116 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.982884 # Percentage of idle cycles +system.cpu1.Branches 12116511 # Number of branches fetched +system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 37117349 68.64% 68.64% # Class of executed instruction +system.cpu1.op_class::IntMult 29132 0.05% 68.70% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 3361 0.01% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::MemRead 10229886 18.92% 87.62% # Class of executed instruction +system.cpu1.op_class::MemWrite 6694187 12.38% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 33659368 # Class of executed instruction +system.cpu1.op_class::total 54073981 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2818 # number of quiesce instructions executed -system.cpu1.dcache.tags.replacements 321673 # number of replacements -system.cpu1.dcache.tags.tagsinuse 481.284483 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 11622088 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 322185 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 36.072716 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 104113347000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 481.284483 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.940009 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.940009 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 275 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 119 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 24380907 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 24380907 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 5961630 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 5961630 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 5307193 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 5307193 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 82380 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 82380 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 110885 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 110885 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 104150 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 104150 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 11268823 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 11268823 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 11351203 # number of overall hits -system.cpu1.dcache.overall_hits::total 11351203 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 210202 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 210202 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 138084 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 138084 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 48251 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 48251 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 19527 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 19527 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23870 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23870 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 348286 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 348286 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 396537 # number of overall misses -system.cpu1.dcache.overall_misses::total 396537 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2787267513 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2787267513 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2672172287 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2672172287 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 339794001 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 339794001 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 550321118 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 550321118 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1627000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1627000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 5459439800 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 5459439800 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 5459439800 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 5459439800 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 6171832 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 6171832 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 5445277 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 5445277 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 130631 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 130631 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 130412 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 130412 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 128020 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 128020 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 11617109 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 11617109 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 11747740 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 11747740 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.034058 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.034058 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.025358 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.025358 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.369369 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.369369 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.149733 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.149733 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.186455 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.186455 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029980 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.029980 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.033754 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.033754 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13259.947636 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 13259.947636 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19351.787948 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 19351.787948 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 17401.239361 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 17401.239361 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23054.927440 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23054.927440 # average StoreCondReq miss latency +system.cpu1.kern.inst.quiesce 2789 # number of quiesce instructions executed +system.cpu1.dcache.tags.replacements 191058 # number of replacements +system.cpu1.dcache.tags.tagsinuse 472.360308 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 16390617 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 191421 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 85.626013 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 104654883500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.360308 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.922579 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.922579 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 363 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 312 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 51 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.708984 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 33541448 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 33541448 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 9797337 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 9797337 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 6353174 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 6353174 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49731 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 49731 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 79655 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 79655 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71640 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 71640 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 16150511 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 16150511 # 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number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1691000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1691000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 4349365344 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 4349365344 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 4349365344 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 4349365344 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 9934703 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 9934703 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 6446321 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 6446321 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80157 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 80157 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96878 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 96878 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 95019 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 95019 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 16381024 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 16381024 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 16461181 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 16461181 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.013827 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.013827 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.014450 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.014450 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.379580 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.379580 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.177780 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.177780 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.246046 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.246046 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.014072 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.014072 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.015852 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.015852 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14540.424872 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14540.424872 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25250.467981 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 25250.467981 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18626.255588 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18626.255588 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23071.572480 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23071.572480 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15675.162941 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 15675.162941 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13767.794178 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 13767.794178 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18868.199815 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 18868.199815 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16668.130651 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 16668.130651 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1446,82 +1600,82 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 197265 # number of writebacks -system.cpu1.dcache.writebacks::total 197265 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 459 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 459 # number of ReadReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13505 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13505 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 459 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 459 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 459 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 459 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 209743 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 209743 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 138084 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 138084 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 46648 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 46648 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 6022 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 6022 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23870 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23870 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 347827 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 347827 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 394475 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 394475 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2356483739 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2356483739 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2388185713 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2388185713 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 637646247 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 637646247 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 87580250 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 87580250 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 501268882 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 501268882 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1557000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1557000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4744669452 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4744669452 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5382315699 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 5382315699 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 968585999 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 968585999 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 845308497 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 845308497 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1813894496 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1813894496 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033984 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033984 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025358 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.025358 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.357097 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.357097 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.046177 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.046177 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.186455 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.186455 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029941 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.029941 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033579 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.033579 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11235.100761 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11235.100761 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17295.166080 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17295.166080 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13669.315876 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 13669.315876 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14543.382597 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14543.382597 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 20999.953163 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20999.953163 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 118649 # number of writebacks +system.cpu1.dcache.writebacks::total 118649 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 239 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 239 # number of ReadReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12076 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12076 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 239 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 239 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 239 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 239 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 137127 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 137127 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 93147 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 93147 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29658 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 29658 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5147 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5147 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23379 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23379 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 230274 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 230274 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 259932 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 259932 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1715737747 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1715737747 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2159697659 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2159697659 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 467259500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 467259500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 82226250 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 82226250 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 491497707 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 491497707 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1621000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1621000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3875435406 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3875435406 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4342694906 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4342694906 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 525084500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 525084500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 379956000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 379956000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 905040500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 905040500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.013803 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.013803 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014450 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014450 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.369999 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.369999 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.053129 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.053129 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.246046 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.246046 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.014057 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.014057 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.015791 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.015791 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12512.034443 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12512.034443 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23185.906782 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23185.906782 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15754.922786 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15754.922786 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15975.568292 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15975.568292 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21023.042346 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21023.042346 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13640.888867 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13640.888867 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13644.250457 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13644.250457 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16829.669898 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16829.669898 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16707.042250 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16707.042250 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1529,58 +1683,58 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 680772 # number of replacements -system.cpu1.icache.tags.tagsinuse 498.691095 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 27342334 # 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Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.608741 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973845 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.973845 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 221 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 387 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 122 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::4 3 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 56728523 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 56728523 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 27342334 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 27342334 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 27342334 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 27342334 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 27342334 # number of overall hits -system.cpu1.icache.overall_hits::total 27342334 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 681285 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 681285 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 681285 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 681285 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 681285 # number of overall misses -system.cpu1.icache.overall_misses::total 681285 # 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number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 28023619 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024311 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.024311 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024311 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.024311 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024311 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.024311 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8303.398739 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8303.398739 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8303.398739 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8303.398739 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8303.398739 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8303.398739 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 89247035 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 89247035 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 43832665 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 43832665 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 43832665 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 43832665 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 43832665 # number of overall hits +system.cpu1.icache.overall_hits::total 43832665 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 527235 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 527235 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 527235 # 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number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 44359900 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 44359900 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 44359900 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 44359900 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011885 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.011885 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011885 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.011885 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011885 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.011885 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8758.828151 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 8758.828151 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8758.828151 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8758.828151 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8758.828151 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8758.828151 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1589,361 +1743,347 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 681285 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 681285 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 681285 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 681285 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 681285 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 681285 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4634848490 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 4634848490 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4634848490 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 4634848490 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4634848490 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 4634848490 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13880000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 13880000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 13880000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 13880000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024311 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024311 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024311 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.024311 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024311 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.024311 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6803.097808 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6803.097808 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6803.097808 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 6803.097808 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6803.097808 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 6803.097808 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 527235 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 527235 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 527235 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 527235 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 527235 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 527235 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3826248740 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3826248740 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3826248740 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3826248740 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3826248740 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3826248740 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13994500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 13994500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 13994500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 13994500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011885 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011885 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011885 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.011885 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011885 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.011885 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7257.197910 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7257.197910 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7257.197910 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 7257.197910 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7257.197910 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 7257.197910 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 5735095 # number of hwpf identified -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 38649 # number of hwpf that were already in mshr -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 5537320 # number of hwpf that were already in the cache -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 267 # number of hwpf that were already in the prefetch queue -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 19 # number of hwpf removed because MSHR allocated -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 158840 # number of hwpf issued -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 604377 # number of hwpf spanning a virtual page -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.l2cache.tags.replacements 130093 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15612.463834 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1076740 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 146334 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 7.358099 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.num_hwpf_issued 199846 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 199846 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped +system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size +system.cpu1.l2cache.prefetcher.pfSpanPage 59474 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 47689 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15083.724459 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 731618 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 62301 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 11.743279 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 4806.943324 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.120223 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 1.343631 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 874.835505 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 1500.703163 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 8425.517990 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.293393 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000190 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000082 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.053396 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.091596 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.514253 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.952909 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 7913 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 8324 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 47 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 90 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 2030 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 4783 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 963 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 129 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2875 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4662 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 602 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.482971 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000244 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.508057 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 21325891 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 21325891 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 5234 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2693 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 672894 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 186024 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 866845 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 197265 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 197265 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 2024 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 2024 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1217 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 1217 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 69989 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 69989 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 5234 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2693 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 672894 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 256013 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 936834 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 5234 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2693 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 672894 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 256013 # number of overall hits -system.cpu1.l2cache.overall_hits::total 936834 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 261 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 216 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 8391 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 76389 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 85257 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29955 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 29955 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22648 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 22648 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 5 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 36116 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 36116 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 261 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 216 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 8391 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 112505 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 121373 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 261 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 216 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 8391 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 112505 # number of overall misses -system.cpu1.l2cache.overall_misses::total 121373 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 5754999 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 4668500 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 255474477 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1702549656 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 1968447632 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 542491459 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 542491459 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 444517157 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 444517157 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1522000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1522000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1159011538 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 1159011538 # number of ReadExReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 5754999 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 4668500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 255474477 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 2861561194 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 3127459170 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 5754999 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 4668500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 255474477 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 2861561194 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 3127459170 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 5495 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2909 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 681285 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.data 262413 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 952102 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 197265 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 197265 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 31979 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 31979 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23865 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 23865 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 5 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 106105 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 106105 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 5495 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2909 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 681285 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 368518 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 1058207 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 5495 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2909 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 681285 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 368518 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 1058207 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.047498 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.074252 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.012316 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.291102 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.089546 # miss rate for ReadReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.936708 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.936708 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.949005 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.949005 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.tags.occ_blocks::writebacks 8757.920968 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.140482 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.100736 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3269.623984 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2111.182929 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 939.755359 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.534541 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000192 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000128 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.199562 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.128856 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.057358 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.920637 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1198 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 23 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13391 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 29 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1169 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 18 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 282 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1514 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 11595 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.073120 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001404 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.817322 # 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average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15045.980843 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14613.425926 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 25817.836919 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 18155.154600 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 18603.385918 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15045.980843 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14613.425926 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 25817.836919 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 18155.154600 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27298.605103 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23562.702529 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.186269 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 12841.121495 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 12641.304348 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 27247.926535 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 14329.890366 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16489.633445 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33922.593888 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 33922.593888 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14198.385511 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14198.385511 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13595.618508 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13595.618508 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 447000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 447000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 29385.354164 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 29385.354164 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 12841.121495 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 12641.304348 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 27247.926535 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 19396.677396 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 20293.588805 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 12841.121495 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 12641.304348 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27247.926535 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 19396.677396 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33922.593888 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 22582.097681 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1953,69 +2093,69 @@ system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 1351518 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 1008638 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 4998 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 4998 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 197265 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 224398 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 84264 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42890 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 91097 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 45 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 75 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 123576 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 111434 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1362924 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 1150758 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8243 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 16496 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2538421 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 43602948 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 39320783 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11636 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 21980 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 82957347 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 826396 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 2054321 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.357816 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.479358 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 1051189 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 750269 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 3091 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 3091 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 118649 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 33325 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 74679 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41637 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 85827 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 49 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 81 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 85544 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 68027 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1054824 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 784590 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5329 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9434 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 1854177 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 33743748 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25394480 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8020 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 13648 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 59159896 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 572639 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1437265 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 5.343414 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.474848 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 1319253 64.22% 64.22% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 735068 35.78% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::5 943688 65.66% 65.66% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::6 493577 34.34% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 2054321 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 864974439 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 1437265 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 595732734 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 89802999 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 80038500 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 1022245510 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 791497760 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 593726174 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 388635637 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 5334000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 3324000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 11001001 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 6022000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 31015 # Transaction distribution -system.iobus.trans_dist::ReadResp 31015 # Transaction distribution -system.iobus.trans_dist::WriteReq 59437 # Transaction distribution -system.iobus.trans_dist::WriteResp 23213 # Transaction distribution +system.iobus.trans_dist::ReadReq 31024 # Transaction distribution +system.iobus.trans_dist::ReadResp 31024 # Transaction distribution +system.iobus.trans_dist::WriteReq 59440 # Transaction distribution +system.iobus.trans_dist::WriteResp 23216 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56642 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56656 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 844 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -2031,16 +2171,16 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107950 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72954 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72954 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180904 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71586 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107970 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 180928 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71600 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 446 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2056,11 +2196,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162833 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2484089 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 40126000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 162850 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2484122 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 40136000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -2070,7 +2210,7 @@ system.iobus.reqLayer3.occupancy 12000 # La system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 503000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) @@ -2100,52 +2240,52 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 347096127 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 347109131 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 84737000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 84754000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36842563 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36846525 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36459 # number of replacements -system.iocache.tags.tagsinuse 14.453181 # Cycle average of tags in use +system.iocache.tags.replacements 36445 # number of replacements +system.iocache.tags.tagsinuse 14.387294 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36475 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36461 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 277163175000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.453181 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.903324 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.903324 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 287959539000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.387294 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.899206 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.899206 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328293 # Number of tag accesses -system.iocache.tags.data_accesses 328293 # Number of data accesses -system.iocache.ReadReq_misses::realview.ide 253 # number of ReadReq misses -system.iocache.ReadReq_misses::total 253 # number of ReadReq misses +system.iocache.tags.tag_accesses 328311 # Number of tag accesses +system.iocache.tags.data_accesses 328311 # Number of data accesses +system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses +system.iocache.ReadReq_misses::total 255 # number of ReadReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses -system.iocache.demand_misses::realview.ide 253 # number of demand (read+write) misses -system.iocache.demand_misses::total 253 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 253 # number of overall misses -system.iocache.overall_misses::total 253 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 31619377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 31619377 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9617084187 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 9617084187 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 31619377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 31619377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 31619377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 31619377 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 253 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 253 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::realview.ide 255 # number of demand (read+write) misses +system.iocache.demand_misses::total 255 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 255 # number of overall misses +system.iocache.overall_misses::total 255 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 31782377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 31782377 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9599974229 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 9599974229 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ide 31782377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 31782377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 31782377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 31782377 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 253 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 253 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 253 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 253 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 255 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 255 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 255 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 255 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses @@ -2154,40 +2294,40 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 124977.774704 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 124977.774704 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265489.294032 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 265489.294032 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 124977.774704 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 124977.774704 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 124977.774704 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 124977.774704 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 56586 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 124636.772549 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 124636.772549 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265016.956410 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 265016.956410 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 124636.772549 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 124636.772549 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 124636.772549 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 124636.772549 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 55555 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7227 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7160 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.829805 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.759078 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 36206 # number of writebacks -system.iocache.writebacks::total 36206 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 253 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 253 # number of ReadReq MSHR misses +system.iocache.writebacks::writebacks 36190 # number of writebacks +system.iocache.writebacks::total 36190 # number of writebacks +system.iocache.ReadReq_mshr_misses::realview.ide 255 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 253 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 253 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 253 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 253 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 18462377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 18462377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7733310313 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7733310313 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 18462377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 18462377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 18462377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 18462377 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::realview.ide 255 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 255 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 255 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 255 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 18521377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 18521377 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7716276279 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7716276279 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 18521377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 18521377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 18521377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 18521377 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -2196,517 +2336,491 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72973.822134 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 72973.822134 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213485.819153 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213485.819153 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 72973.822134 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 72973.822134 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 72973.822134 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 72973.822134 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72632.850980 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 72632.850980 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213015.577490 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213015.577490 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 72632.850980 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 72632.850980 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 72632.850980 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 72632.850980 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 132552 # number of replacements -system.l2c.tags.tagsinuse 64217.240538 # Cycle average of tags in use -system.l2c.tags.total_refs 486427 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 197317 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.465206 # Average number of references to valid blocks. +system.l2c.tags.replacements 130735 # number of replacements +system.l2c.tags.tagsinuse 63966.604731 # Cycle average of tags in use +system.l2c.tags.total_refs 343053 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 195063 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 1.758678 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 12673.098262 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.830088 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.037001 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 1135.719993 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 1432.608438 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 38719.774998 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.654088 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.007784 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 545.091140 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 913.810052 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 8789.608693 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.193376 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000074 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.017330 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.021860 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.590817 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000040 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.008317 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.013944 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.134119 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.979877 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 45108 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 19652 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 175 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 5031 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 39902 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 175 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 1352 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 18116 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.688293 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.299866 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 6110572 # Number of tag accesses -system.l2c.tags.data_accesses 6110572 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 83 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 80 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 7661 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 21794 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 138574 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 103 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 107 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 6377 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 17292 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 75612 # number of ReadReq hits -system.l2c.ReadReq_hits::total 267683 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 239712 # number of Writeback hits -system.l2c.Writeback_hits::total 239712 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 8881 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 1415 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 10296 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 213 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 148 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 361 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 3683 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 2891 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 6574 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 83 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 80 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 7661 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 25477 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 138574 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 103 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 107 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 6377 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 20183 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 75612 # number of demand (read+write) hits -system.l2c.demand_hits::total 274257 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 83 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 80 # number of overall hits -system.l2c.overall_hits::cpu0.inst 7661 # number of overall hits -system.l2c.overall_hits::cpu0.data 25477 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 138574 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 103 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 107 # number of overall hits -system.l2c.overall_hits::cpu1.inst 6377 # number of overall hits -system.l2c.overall_hits::cpu1.data 20183 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 75612 # number of overall hits -system.l2c.overall_hits::total 274257 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 8 # 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number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 41 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 14102 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 9461 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 11692 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 317584 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 227719 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 227719 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 11251 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 3668 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 14919 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 922 # 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number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 41 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 14102 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 19520 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 11692 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 342892 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 89 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 65 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 47151 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 69709 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 180488 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 35 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 41 # 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average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99256.705231 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 86246.639722 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62460.730674 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61824.462414 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 103009.293889 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 79396.679517 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -2721,58 +2835,58 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 228161 # Transaction distribution -system.membus.trans_dist::ReadResp 228160 # Transaction distribution -system.membus.trans_dist::WriteReq 31188 # Transaction distribution -system.membus.trans_dist::WriteResp 31188 # Transaction distribution -system.membus.trans_dist::Writeback 135887 # Transaction distribution +system.membus.trans_dist::ReadReq 215303 # Transaction distribution +system.membus.trans_dist::ReadResp 215303 # Transaction distribution +system.membus.trans_dist::WriteReq 30982 # Transaction distribution +system.membus.trans_dist::WriteResp 30982 # Transaction distribution +system.membus.trans_dist::Writeback 135225 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 85485 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 41282 # Transaction distribution -system.membus.trans_dist::UpgradeResp 15173 # Transaction distribution +system.membus.trans_dist::UpgradeReq 76008 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40410 # Transaction distribution +system.membus.trans_dist::UpgradeResp 13867 # Transaction distribution system.membus.trans_dist::SCUpgradeFailReq 5 # Transaction distribution -system.membus.trans_dist::ReadExReq 28446 # Transaction distribution -system.membus.trans_dist::ReadExResp 11501 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107950 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 40350 # Transaction distribution +system.membus.trans_dist::ReadExResp 19836 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107970 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14612 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 676793 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 799389 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108922 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108922 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 908311 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162833 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13762 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 659440 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 781206 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108908 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108908 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 890114 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162850 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 29224 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18898536 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 19090661 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4636480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 4636480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 23727141 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 129157 # Total snoops (count) -system.membus.snoop_fanout::samples 511174 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27524 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18582632 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18773074 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 23408530 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 123675 # Total snoops (count) +system.membus.snoop_fanout::samples 499419 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 511174 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 499419 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 511174 # Request fanout histogram -system.membus.reqLayer0.occupancy 88144997 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 499419 # Request fanout histogram +system.membus.reqLayer0.occupancy 88165000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 18500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 12118496 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11453500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1838586997 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1828859499 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 1967573382 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1931425684 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38564437 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 38544475 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2805,44 +2919,44 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 630354 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 630338 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 31188 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 31188 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 239712 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 95586 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 41643 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 137229 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 75 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 75 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 39856 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 39856 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1145062 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 504022 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1649084 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 33792786 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 11864019 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 45656805 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 304478 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 1039135 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.035103 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.184041 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 482729 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 482714 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30982 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30982 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 227719 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 79027 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 40738 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 119765 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 81 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 81 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 51496 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 51496 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1065854 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 282098 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1347952 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 31837086 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4944756 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 36781842 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 286323 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 873908 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.041744 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.200003 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 1002658 96.49% 96.49% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 36477 3.51% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 837428 95.83% 95.83% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 36480 4.17% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 1039135 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1515175521 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 873908 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 1446151615 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 1071000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 1080000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1922628953 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1735034184 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1047459467 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 618323353 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 5265a0ac0..b3648bdab 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.902845 # Number of seconds simulated -sim_ticks 2902845442000 # Number of ticks simulated -final_tick 2902845442000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.902862 # Number of seconds simulated +sim_ticks 2902861767000 # Number of ticks simulated +final_tick 2902861767000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 666753 # Simulator instruction rate (inst/s) -host_op_rate 803907 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 17201244826 # Simulator tick rate (ticks/s) -host_mem_usage 558784 # Number of bytes of host memory used -host_seconds 168.76 # Real time elapsed on the host -sim_insts 112519801 # Number of instructions simulated -sim_ops 135665611 # Number of ops (including micro ops) simulated +host_inst_rate 747193 # Simulator instruction rate (inst/s) +host_op_rate 900893 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 19275657141 # Simulator tick rate (ticks/s) +host_mem_usage 615228 # Number of bytes of host memory used +host_seconds 150.60 # Real time elapsed on the host +sim_insts 112525269 # Number of instructions simulated +sim_ops 135672104 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1190500 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1191332 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 8985828 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10177864 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1190500 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1190500 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7575744 # Number of bytes written to this memory +system.physmem.bytes_read::total 10178696 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1191332 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1191332 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7576000 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 7593268 # Number of bytes written to this memory +system.physmem.bytes_written::total 7593524 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 27055 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 27068 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 140923 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 168002 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 118371 # Number of write requests responded to by this memory +system.physmem.num_reads::total 168015 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 118375 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122752 # Number of write requests responded to by this memory +system.physmem.num_writes::total 122756 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 154 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 44 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 410115 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3095524 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 410399 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3095507 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 331 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3506168 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 410115 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 410115 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2609765 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3506435 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 410399 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 410399 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2609838 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6037 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2615802 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2609765 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2615875 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2609838 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 44 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 410115 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3101561 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 410399 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3101543 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 331 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6121970 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 168002 # Number of read requests accepted -system.physmem.writeReqs 158976 # Number of write requests accepted -system.physmem.readBursts 168002 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 158976 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10744064 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8064 # Total number of bytes read from write queue -system.physmem.bytesWritten 9803776 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10177864 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 9911604 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 126 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 5765 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4503 # Number of requests that are neither read nor write +system.physmem.bw_total::total 6122310 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 168015 # Number of read requests accepted +system.physmem.writeReqs 158980 # Number of write requests accepted +system.physmem.readBursts 168015 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 158980 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10745280 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7680 # Total number of bytes read from write queue +system.physmem.bytesWritten 9814400 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10178696 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 9911860 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 120 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 5603 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4500 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 9689 # Per bank write bursts -system.physmem.perBankRdBursts::1 9233 # Per bank write bursts -system.physmem.perBankRdBursts::2 10196 # Per bank write bursts -system.physmem.perBankRdBursts::3 10261 # Per bank write bursts +system.physmem.perBankRdBursts::1 9230 # Per bank write bursts +system.physmem.perBankRdBursts::2 10198 # Per bank write bursts +system.physmem.perBankRdBursts::3 10267 # Per bank write bursts system.physmem.perBankRdBursts::4 18984 # Per bank write bursts -system.physmem.perBankRdBursts::5 10217 # Per bank write bursts -system.physmem.perBankRdBursts::6 10550 # Per bank write bursts -system.physmem.perBankRdBursts::7 10349 # Per bank write bursts -system.physmem.perBankRdBursts::8 9691 # Per bank write bursts +system.physmem.perBankRdBursts::5 10226 # Per bank write bursts +system.physmem.perBankRdBursts::6 10551 # Per bank write bursts +system.physmem.perBankRdBursts::7 10350 # Per bank write bursts +system.physmem.perBankRdBursts::8 9702 # Per bank write bursts system.physmem.perBankRdBursts::9 9930 # Per bank write bursts -system.physmem.perBankRdBursts::10 9906 # Per bank write bursts -system.physmem.perBankRdBursts::11 8846 # Per bank write bursts -system.physmem.perBankRdBursts::12 9937 # Per bank write bursts -system.physmem.perBankRdBursts::13 10409 # Per bank write bursts -system.physmem.perBankRdBursts::14 9928 # Per bank write bursts +system.physmem.perBankRdBursts::10 9908 # Per bank write bursts +system.physmem.perBankRdBursts::11 8848 # Per bank write bursts +system.physmem.perBankRdBursts::12 9929 # Per bank write bursts +system.physmem.perBankRdBursts::13 10408 # Per bank write bursts +system.physmem.perBankRdBursts::14 9925 # Per bank write bursts system.physmem.perBankRdBursts::15 9750 # Per bank write bursts -system.physmem.perBankWrBursts::0 9383 # Per bank write bursts -system.physmem.perBankWrBursts::1 8873 # Per bank write bursts -system.physmem.perBankWrBursts::2 10202 # Per bank write bursts -system.physmem.perBankWrBursts::3 10003 # Per bank write bursts -system.physmem.perBankWrBursts::4 9293 # Per bank write bursts -system.physmem.perBankWrBursts::5 9372 # Per bank write bursts -system.physmem.perBankWrBursts::6 9902 # Per bank write bursts -system.physmem.perBankWrBursts::7 9747 # Per bank write bursts -system.physmem.perBankWrBursts::8 9662 # Per bank write bursts -system.physmem.perBankWrBursts::9 9936 # Per bank write bursts -system.physmem.perBankWrBursts::10 9764 # Per bank write bursts -system.physmem.perBankWrBursts::11 9057 # Per bank write bursts -system.physmem.perBankWrBursts::12 9756 # Per bank write bursts -system.physmem.perBankWrBursts::13 9847 # Per bank write bursts -system.physmem.perBankWrBursts::14 9332 # Per bank write bursts -system.physmem.perBankWrBursts::15 9055 # Per bank write bursts +system.physmem.perBankWrBursts::0 9389 # Per bank write bursts +system.physmem.perBankWrBursts::1 8975 # Per bank write bursts +system.physmem.perBankWrBursts::2 10251 # Per bank write bursts +system.physmem.perBankWrBursts::3 9953 # Per bank write bursts +system.physmem.perBankWrBursts::4 9418 # Per bank write bursts +system.physmem.perBankWrBursts::5 9499 # Per bank write bursts +system.physmem.perBankWrBursts::6 9770 # Per bank write bursts +system.physmem.perBankWrBursts::7 9764 # Per bank write bursts +system.physmem.perBankWrBursts::8 9682 # Per bank write bursts +system.physmem.perBankWrBursts::9 9836 # Per bank write bursts +system.physmem.perBankWrBursts::10 9791 # Per bank write bursts +system.physmem.perBankWrBursts::11 9091 # Per bank write bursts +system.physmem.perBankWrBursts::12 9681 # Per bank write bursts +system.physmem.perBankWrBursts::13 9852 # Per bank write bursts +system.physmem.perBankWrBursts::14 9372 # Per bank write bursts +system.physmem.perBankWrBursts::15 9026 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2902845065500 # Total gap between requests +system.physmem.totGap 2902861390500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9558 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 158430 # Read request sizes (log2) +system.physmem.readPktSize::6 158443 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 154595 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 167074 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 546 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 244 # What read queue length does an incoming req see +system.physmem.writePktSize::6 154599 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 167093 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 544 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 246 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -159,114 +159,135 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4010 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 7794 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 8553 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 8920 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 9728 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 10123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 10886 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 10725 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 11224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10377 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9848 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6857 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6734 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6646 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 405 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 375 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4056 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 7902 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 8734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 8985 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 9766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 10233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 10902 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 10695 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 11219 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 10360 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9893 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8867 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8350 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6866 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6660 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 386 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 329 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 285 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 60629 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 338.910027 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 195.312314 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 353.501529 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 21458 35.39% 35.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14532 23.97% 59.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5550 9.15% 68.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3471 5.72% 74.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2318 3.82% 78.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1576 2.60% 80.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1018 1.68% 82.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1077 1.78% 84.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9629 15.88% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 60629 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6199 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 27.078561 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 543.579220 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6197 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 60962 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 337.252977 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 194.461800 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 352.629111 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 21587 35.41% 35.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14795 24.27% 59.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5550 9.10% 68.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3419 5.61% 74.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2349 3.85% 78.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1576 2.59% 80.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1011 1.66% 82.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1092 1.79% 84.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9583 15.72% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 60962 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6214 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 27.016254 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 542.923852 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6212 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6199 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6199 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 24.711082 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.355367 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 23.633562 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 5127 82.71% 82.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 245 3.95% 86.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 162 2.61% 89.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 57 0.92% 90.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 142 2.29% 92.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 31 0.50% 92.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 44 0.71% 93.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 53 0.85% 94.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 77 1.24% 95.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 20 0.32% 96.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 101 1.63% 97.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 12 0.19% 97.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 30 0.48% 98.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 13 0.21% 98.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 38 0.61% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 11 0.18% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 15 0.24% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 2 0.03% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 3 0.05% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 2 0.03% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 3 0.05% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 2 0.03% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 1 0.02% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 2 0.03% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 2 0.03% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 3 0.05% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-279 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6199 # Writes before turning the bus around for reads -system.physmem.totQLat 1496514000 # Total ticks spent queuing -system.physmem.totMemAccLat 4644189000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 839380000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8914.40 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6214 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6214 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 24.678146 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.366342 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 23.738225 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5089 81.90% 81.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 32 0.51% 82.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 24 0.39% 82.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 212 3.41% 86.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 128 2.06% 88.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 65 1.05% 89.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 41 0.66% 89.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 30 0.48% 90.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 138 2.22% 92.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 16 0.26% 92.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 13 0.21% 93.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 16 0.26% 93.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 29 0.47% 93.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 17 0.27% 94.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 11 0.18% 94.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 29 0.47% 94.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 66 1.06% 95.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 8 0.13% 95.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 3 0.05% 96.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 17 0.27% 96.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 91 1.46% 97.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.02% 97.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 15 0.24% 98.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.03% 98.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 8 0.13% 98.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 6 0.10% 98.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 11 0.18% 98.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 98.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 39 0.63% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 7 0.11% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 2 0.03% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 4 0.06% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 9 0.14% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 3 0.05% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.02% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 5 0.08% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 2 0.03% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 3 0.05% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 5 0.08% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.02% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 3 0.05% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 1 0.02% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 1 0.02% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::220-223 4 0.06% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 2 0.03% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-235 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::252-255 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6214 # Writes before turning the bus around for reads +system.physmem.totQLat 1487834250 # Total ticks spent queuing +system.physmem.totMemAccLat 4635865500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 839475000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8861.69 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27664.40 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 27611.69 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.70 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.38 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.51 # Average system read bandwidth in MiByte/s @@ -276,36 +297,41 @@ system.physmem.busUtil 0.06 # Da system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 27.52 # Average write queue length when enqueuing -system.physmem.readRowHits 138272 # Number of row buffer hits during reads -system.physmem.writeRowHits 122158 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.37 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.73 # Row buffer hit rate for writes -system.physmem.avgGap 8877799.32 # Average gap between requests -system.physmem.pageHitRate 81.11 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2755332461750 # Time in different power states -system.physmem.memoryStateTime::REF 96932160000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 50580729750 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 234216360 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 224138880 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 127796625 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 122298000 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 697936200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 611488800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 497502000 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 495130320 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 189599304960 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 189599304960 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 86744243025 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 85632450615 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1665611854500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1666587111000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1943512853670 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1943271922575 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.521448 # Core power per rank (mW) -system.physmem.averagePower::1 669.438449 # Core power per rank (mW) +system.physmem.avgWrQLen 25.07 # Average write queue length when enqueuing +system.physmem.readRowHits 138089 # Number of row buffer hits during reads +system.physmem.writeRowHits 122193 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.25 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 79.67 # Row buffer hit rate for writes +system.physmem.avgGap 8877387.70 # Average gap between requests +system.physmem.pageHitRate 81.02 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 235320120 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 128398875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 698061000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 499083120 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 189600322080 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 86740865775 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1665624160500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1943526211470 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.522458 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2770750790000 # Time in different power states +system.physmem_0.memoryStateTime::REF 96932680000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 35170942500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 225552600 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 123069375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 611512200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 494624880 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 189600322080 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 85548905145 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1666669740000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1943273726280 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.435479 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2772511956000 # Time in different power states +system.physmem_1.memoryStateTime::REF 96932680000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 33417040500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -325,6 +351,14 @@ system.cf0.dma_write_full_pages 540 # Nu system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -346,11 +380,41 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 9552 # Table walker walks requested +system.cpu.dtb.walker.walksShort 9552 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1261 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8291 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 9552 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 9552 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 9552 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 7388 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 9945.756632 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 7345.780525 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 7322.338006 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-16383 5745 77.76% 77.76% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::16384-32767 1639 22.18% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-81919 2 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::147456-163839 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 7388 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 809108000 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 809108000 100.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 809108000 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 6174 83.57% 83.57% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1214 16.43% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7388 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9552 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9552 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7388 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7388 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 16940 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 24536392 # DTB read hits -system.cpu.dtb.read_misses 8144 # DTB read misses -system.cpu.dtb.write_hits 19617454 # DTB write hits +system.cpu.dtb.read_hits 24537663 # DTB read hits +system.cpu.dtb.read_misses 8142 # DTB read misses +system.cpu.dtb.write_hits 19618927 # DTB write hits system.cpu.dtb.write_misses 1410 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -358,15 +422,23 @@ system.cpu.dtb.flush_tlb_mva_asid 0 # Nu system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_entries 4273 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 1630 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 1664 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 24544536 # DTB read accesses -system.cpu.dtb.write_accesses 19618864 # DTB write accesses +system.cpu.dtb.read_accesses 24545805 # DTB read accesses +system.cpu.dtb.write_accesses 19620337 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 44153846 # DTB hits -system.cpu.dtb.misses 9554 # DTB misses -system.cpu.dtb.accesses 44163400 # DTB accesses +system.cpu.dtb.hits 44156590 # DTB hits +system.cpu.dtb.misses 9552 # DTB misses +system.cpu.dtb.accesses 44166142 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -388,7 +460,37 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 115618887 # ITB inst hits +system.cpu.itb.walker.walks 4762 # Table walker walks requested +system.cpu.itb.walker.walksShort 4762 # Table walker walks initiated with short descriptors +system.cpu.itb.walker.walksShortTerminationLevel::Level1 309 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksShortTerminationLevel::Level2 4453 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 4762 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 4762 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 4762 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 3107 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 9893.949147 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 7210.941913 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 7351.443657 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-8191 1400 45.06% 45.06% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::8192-16383 1004 32.31% 77.37% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-24575 701 22.56% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::73728-81919 1 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::81920-90111 1 0.03% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 3107 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 808810000 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 808810000 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 808810000 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 2798 90.05% 90.05% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::1M 309 9.95% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 3107 # Table walker page sizes translated +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 4762 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 4762 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3107 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 3107 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 7869 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 115624412 # ITB inst hits system.cpu.itb.inst_misses 4762 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -405,38 +507,38 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 115623649 # ITB inst accesses -system.cpu.itb.hits 115618887 # DTB hits +system.cpu.itb.inst_accesses 115629174 # ITB inst accesses +system.cpu.itb.hits 115624412 # DTB hits system.cpu.itb.misses 4762 # DTB misses -system.cpu.itb.accesses 115623649 # DTB accesses -system.cpu.numCycles 5805690884 # number of cpu cycles simulated +system.cpu.itb.accesses 115629174 # DTB accesses +system.cpu.numCycles 5805723534 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 112519801 # Number of instructions committed -system.cpu.committedOps 135665611 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 119963928 # Number of integer alu accesses +system.cpu.committedInsts 112525269 # Number of instructions committed +system.cpu.committedOps 135672104 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 119969678 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 11290 # Number of float alu accesses -system.cpu.num_func_calls 9899743 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 15237612 # number of instructions that are conditional controls -system.cpu.num_int_insts 119963928 # number of integer instructions +system.cpu.num_func_calls 9899985 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 15238216 # number of instructions that are conditional controls +system.cpu.num_int_insts 119969678 # number of integer instructions system.cpu.num_fp_insts 11290 # number of float instructions -system.cpu.num_int_register_reads 218192496 # number of times the integer registers were read -system.cpu.num_int_register_writes 82697523 # number of times the integer registers were written +system.cpu.num_int_register_reads 218203287 # number of times the integer registers were read +system.cpu.num_int_register_writes 82701548 # number of times the integer registers were written system.cpu.num_fp_register_reads 8578 # number of times the floating registers were read system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written -system.cpu.num_cc_register_reads 490031044 # number of times the CC registers were read -system.cpu.num_cc_register_writes 51919223 # number of times the CC registers were written -system.cpu.num_mem_refs 45435185 # number of memory refs -system.cpu.num_load_insts 24859277 # Number of load instructions -system.cpu.num_store_insts 20575908 # Number of store instructions -system.cpu.num_idle_cycles 5386811452.570145 # Number of idle cycles -system.cpu.num_busy_cycles 418879431.429856 # Number of busy cycles -system.cpu.not_idle_fraction 0.072150 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.927850 # Percentage of idle cycles -system.cpu.Branches 25931479 # Number of branches fetched +system.cpu.num_cc_register_reads 490054820 # number of times the CC registers were read +system.cpu.num_cc_register_writes 51921339 # number of times the CC registers were written +system.cpu.num_mem_refs 45438019 # number of memory refs +system.cpu.num_load_insts 24860597 # Number of load instructions +system.cpu.num_store_insts 20577422 # Number of store instructions +system.cpu.num_idle_cycles 5386825418.146145 # Number of idle cycles +system.cpu.num_busy_cycles 418898115.853856 # Number of busy cycles +system.cpu.not_idle_fraction 0.072153 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.927847 # Percentage of idle cycles +system.cpu.Branches 25932360 # Number of branches fetched system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 93227451 67.17% 67.17% # Class of executed instruction -system.cpu.op_class::IntMult 114534 0.08% 67.26% # Class of executed instruction +system.cpu.op_class::IntAlu 93231199 67.17% 67.17% # Class of executed instruction +system.cpu.op_class::IntMult 114517 0.08% 67.26% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 67.26% # Class of executed instruction @@ -460,24 +562,24 @@ system.cpu.op_class::SimdFloatAlu 0 0.00% 67.26% # Cl system.cpu.op_class::SimdFloatCmp 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatCvt 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatDiv 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 8511 0.01% 67.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 8515 0.01% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::MemRead 24859277 17.91% 85.17% # Class of executed instruction -system.cpu.op_class::MemWrite 20575908 14.83% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 24860597 17.91% 85.17% # Class of executed instruction +system.cpu.op_class::MemWrite 20577422 14.83% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 138788018 # Class of executed instruction +system.cpu.op_class::total 138794587 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 3037 # number of quiesce instructions executed -system.cpu.dcache.tags.replacements 823273 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.850546 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 43258722 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 823785 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 52.512151 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 823321 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.850573 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 43261398 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 823833 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 52.512339 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 876905250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.850546 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.850573 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999708 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999708 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -486,168 +588,168 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 368 system.cpu.dcache.tags.age_task_id_blocks_1024::2 82 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 177222055 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 177222055 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23125535 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23125535 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18834160 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18834160 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 392158 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 392158 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 443620 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 443620 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460509 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460509 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41959695 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41959695 # 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number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 443636 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 443636 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460570 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460570 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 41962335 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41962335 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42354457 # number of overall hits +system.cpu.dcache.overall_hits::total 42354457 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 402703 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 402703 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 299019 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 299019 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 119172 # 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number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5915644250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 11659723253 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 11659723253 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 280150250 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 280150250 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 701722 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 701722 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 820894 # number of overall misses +system.cpu.dcache.overall_misses::total 820894 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5916458250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5916458250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 11650381750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 11650381750 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 280295250 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 280295250 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 150000 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 150000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 17575367503 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17575367503 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 17575367503 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17575367503 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23528141 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23528141 # 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number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 43172729 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017112 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.017112 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015632 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.015632 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.233063 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.233063 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048675 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048675 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_latency::cpu.data 17566840000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17566840000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 17566840000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17566840000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23529387 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23529387 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19134670 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19134670 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 511294 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 511294 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466379 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 466379 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 460572 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 460572 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 42664057 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42664057 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 43175351 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 43175351 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017115 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.017115 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015627 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.015627 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.233079 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.233079 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048765 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048765 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.016448 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.016448 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.019014 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.019014 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14693.383233 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14693.383233 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38982.952922 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38982.952922 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12342.508150 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12342.508150 # average LoadLockedReq miss latency +system.cpu.dcache.overall_miss_rate::cpu.data 0.019013 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.019013 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14691.865345 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14691.865345 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38962.011611 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38962.011611 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12324.462472 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12324.462472 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 75000 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 75000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 25046.697045 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 25046.697045 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 21410.502321 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 21410.502321 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 58 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 25033.902315 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 25033.902315 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 21399.644778 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 21399.644778 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 78 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 33 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 34 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 1.757576 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.294118 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 686473 # number of writebacks -system.cpu.dcache.writebacks::total 686473 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 636 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 636 # number of ReadReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14226 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 14226 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 636 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 636 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 636 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 636 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 401970 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 401970 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299098 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 299098 # 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number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 299019 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 117021 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 117021 # number of SoftPFReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8472 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 8472 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8489 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 8489 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 701068 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 701068 # 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number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 100012000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 146000 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 146000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16100671997 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16100671997 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17515042747 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 17515042747 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5791399500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5791399500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4429678500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4429678500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10221078000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 10221078000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017085 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017085 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015632 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015632 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228856 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228856 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018168 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018168 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16093036000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16093036000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17504178000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 17504178000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5791398250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5791398250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4429682000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4429682000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10221080250 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 10221080250 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017088 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017088 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015627 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015627 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228872 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228872 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018202 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018202 # 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average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21395.768805 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 21395.768805 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -655,13 +757,13 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 1700967 # number of replacements -system.cpu.icache.tags.tagsinuse 510.782035 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 113917402 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1701479 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 66.951988 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 1701491 # number of replacements +system.cpu.icache.tags.tagsinuse 510.782044 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 113922403 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1702003 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 66.934314 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 25181626250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.782035 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 510.782044 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7345006540 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7345006540 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 408750 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 125000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1087188750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8131188288 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9218969038 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 467000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1090271000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8120295290 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9211100040 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 408750 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 125000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1087188750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8131188288 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9218969038 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1090271000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8120295290 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9211100040 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 474215000 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5385925500 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5860140500 # number of ReadReq MSHR uncacheable cycles @@ -966,48 +1068,48 @@ system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4098165500 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 474215000 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9484091000 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9958306000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001003 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001001 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000546 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010603 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.023113 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013503 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991600 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991600 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010607 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.023103 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013504 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991584 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991584 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.439466 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.439466 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001003 # mshr miss rate for demand accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.439589 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.439589 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001001 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000546 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010603 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172890 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.063283 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001003 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010607 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172883 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.063274 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001001 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000546 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010603 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172890 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.063283 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 66714.285714 # average ReadReq mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010607 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172883 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.063274 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 58392.857143 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60265.451774 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63809.880240 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61695.998677 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10058.458564 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10058.458564 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60392.787902 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63605.607515 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61687.002083 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10067.420664 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10067.420664 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 60000 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 60000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56459.475107 # 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average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60392.787902 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57011.333680 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57391.819309 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 58392.857143 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60265.451774 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57088.613350 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57446.217834 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60392.787902 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57011.333680 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57391.819309 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1017,54 +1119,54 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2296418 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2296403 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2297061 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2297046 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27618 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27618 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 686473 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 686487 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2738 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2733 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2740 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 296360 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 296360 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3420989 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2457362 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::UpgradeResp 2735 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 296286 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 296286 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3422037 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2457460 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12875 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 24821 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5916047 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108929528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96856201 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 24836 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5917208 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108963064 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96860105 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14640 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27904 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 205828273 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 53126 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3278039 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.011122 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.104872 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27972 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 205865781 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 53107 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3278617 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.011120 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.104863 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 3241581 98.89% 98.89% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 3242159 98.89% 98.89% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::6 36458 1.11% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3278039 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2354969500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3278617 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2355272500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 328500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2566643750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2567431500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1312602003 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1312657000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer2.occupancy 9215000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 17845000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 17843250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 30195 # Transaction distribution system.iobus.trans_dist::ReadResp 30195 # Transaction distribution @@ -1161,23 +1263,23 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 347056142 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 347060139 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36804505 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36804507 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36424 # number of replacements -system.iocache.tags.tagsinuse 1.134557 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.134613 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 298397320000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.134557 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.070910 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.070910 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 298400039000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.134613 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.070913 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.070913 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1193,8 +1295,8 @@ system.iocache.overall_misses::realview.ide 234 # system.iocache.overall_misses::total 234 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ide 28034377 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 28034377 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9588161260 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 9588161260 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9587408255 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 9587408255 # number of WriteInvalidateReq miss cycles system.iocache.demand_miss_latency::realview.ide 28034377 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::total 28034377 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ide 28034377 # number of overall miss cycles @@ -1217,17 +1319,17 @@ system.iocache.overall_miss_rate::realview.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ide 119805.029915 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 119805.029915 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 264690.847504 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 264690.847504 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 264670.060043 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 264670.060043 # average WriteInvalidateReq miss latency system.iocache.demand_avg_miss_latency::realview.ide 119805.029915 # average overall miss latency system.iocache.demand_avg_miss_latency::total 119805.029915 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ide 119805.029915 # average overall miss latency system.iocache.overall_avg_miss_latency::total 119805.029915 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 55275 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 55358 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7147 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7146 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.734014 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.746711 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1243,8 +1345,8 @@ system.iocache.overall_mshr_misses::realview.ide 234 system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ide 15865377 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 15865377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7704503270 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7704503270 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7703746269 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7703746269 # number of WriteInvalidateReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ide 15865377 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 15865377 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ide 15865377 # number of overall MSHR miss cycles @@ -1259,64 +1361,64 @@ system.iocache.overall_mshr_miss_rate::realview.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67800.756410 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 67800.756410 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 212690.571720 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212690.571720 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 212669.673945 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212669.673945 # average WriteInvalidateReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ide 67800.756410 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 67800.756410 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ide 67800.756410 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 67800.756410 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 70650 # Transaction distribution -system.membus.trans_dist::ReadResp 70650 # Transaction distribution +system.membus.trans_dist::ReadReq 70661 # Transaction distribution +system.membus.trans_dist::ReadResp 70661 # Transaction distribution system.membus.trans_dist::WriteReq 27618 # Transaction distribution system.membus.trans_dist::WriteResp 27618 # Transaction distribution -system.membus.trans_dist::Writeback 118371 # Transaction distribution +system.membus.trans_dist::Writeback 118375 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4503 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4500 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4505 # Transaction distribution -system.membus.trans_dist::ReadExReq 128452 # Transaction distribution -system.membus.trans_dist::ReadExResp 128452 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4502 # Transaction distribution +system.membus.trans_dist::ReadExReq 128454 # Transaction distribution +system.membus.trans_dist::ReadExResp 128454 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2122 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 436202 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 543884 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 436226 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 543908 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108887 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 108887 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 652771 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 652795 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4244 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15454012 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15617473 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15455100 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15618561 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20252929 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20254017 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 498 # Total snoops (count) -system.membus.snoop_fanout::samples 318026 # Request fanout histogram +system.membus.snoop_fanout::samples 318040 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 318026 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 318040 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 318026 # Request fanout histogram +system.membus.snoop_fanout::total 318040 # Request fanout histogram system.membus.reqLayer0.occupancy 86773500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1756500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1758500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1589715500 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1589750000 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 1594842247 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1594947750 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38335495 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 38337493 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt index b2b55eb3a..f0c87683a 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.783867 # Nu sim_ticks 2783867165000 # Number of ticks simulated final_tick 2783867165000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1108011 # Simulator instruction rate (inst/s) -host_op_rate 1348825 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 21604583679 # Simulator tick rate (ticks/s) -host_mem_usage 560868 # Number of bytes of host memory used -host_seconds 128.86 # Real time elapsed on the host +host_inst_rate 1311458 # Simulator instruction rate (inst/s) +host_op_rate 1596489 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 25571502260 # Simulator tick rate (ticks/s) +host_mem_usage 616488 # Number of bytes of host memory used +host_seconds 108.87 # Real time elapsed on the host sim_insts 142773109 # Number of instructions simulated sim_ops 173803334 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -87,6 +87,14 @@ system.cf0.dma_write_full_pages 540 # Nu system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -108,6 +116,24 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.walker.walks 5682 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 5682 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 5682 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 5682 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 5682 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 3049 65.42% 65.42% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1612 34.58% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 4661 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 5682 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 5682 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4661 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4661 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 10343 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses system.cpu0.dtb.read_hits 15994592 # DTB read hits @@ -129,6 +155,14 @@ system.cpu0.dtb.inst_accesses 0 # IT system.cpu0.dtb.hits 27280368 # DTB hits system.cpu0.dtb.misses 5682 # DTB misses system.cpu0.dtb.accesses 27286050 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -150,6 +184,24 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.itb.walker.walks 2611 # Table walker walks requested +system.cpu0.itb.walker.walksShort 2611 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walkWaitTime::samples 2611 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 2611 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 2611 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walksPending::samples 6702500 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 6702500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 6702500 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 1374 72.85% 72.85% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 512 27.15% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 1886 # Table walker page sizes translated +system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2611 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2611 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 1886 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 1886 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 4497 # Table walker requests started/completed, data/inst system.cpu0.itb.inst_hits 74779253 # ITB inst hits system.cpu0.itb.inst_misses 2611 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits @@ -408,6 +460,14 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -429,6 +489,24 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.walker.walks 6203 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 6203 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walkWaitTime::samples 6203 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 6203 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 6203 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walksPending::samples 1000002000 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1000002000 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 1000002000 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 3703 73.18% 73.18% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 1357 26.82% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 5060 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 6203 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 6203 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5060 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5060 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 11263 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses system.cpu1.dtb.read_hits 15530019 # DTB read hits @@ -450,6 +528,14 @@ system.cpu1.dtb.inst_accesses 0 # IT system.cpu1.dtb.hits 27368468 # DTB hits system.cpu1.dtb.misses 6203 # DTB misses system.cpu1.dtb.accesses 27374671 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -471,6 +557,24 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.itb.walker.walks 3040 # Table walker walks requested +system.cpu1.itb.walker.walksShort 3040 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walkWaitTime::samples 3040 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 3040 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 3040 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 1720 81.52% 81.52% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 390 18.48% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 2110 # Table walker page sizes translated +system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 3040 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 3040 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2110 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2110 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 5150 # Table walker requests started/completed, data/inst system.cpu1.itb.inst_hits 72259450 # ITB inst hits system.cpu1.itb.inst_misses 3040 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt index 818a22f67..83b8a4ab7 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 47.177080 # Nu sim_ticks 47177080006500 # Number of ticks simulated final_tick 47177080006500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1024538 # Simulator instruction rate (inst/s) -host_op_rate 1205255 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 49483118923 # Simulator tick rate (ticks/s) -host_mem_usage 669884 # Number of bytes of host memory used -host_seconds 953.40 # Real time elapsed on the host +host_inst_rate 1049876 # Simulator instruction rate (inst/s) +host_op_rate 1235062 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 50706899360 # Simulator tick rate (ticks/s) +host_mem_usage 670076 # Number of bytes of host memory used +host_seconds 930.39 # Real time elapsed on the host sim_insts 976792036 # Number of instructions simulated sim_ops 1149086878 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -105,6 +105,14 @@ system.cf0.dma_write_full_pages 1667 # Nu system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -126,6 +134,24 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.walker.walks 123914 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 123914 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 123914 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 123914 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 123914 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 95376 89.74% 89.74% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 10905 10.26% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 106281 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 123914 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 123914 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 106281 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 106281 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 230195 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses system.cpu0.dtb.read_hits 91355479 # DTB read hits @@ -147,6 +173,14 @@ system.cpu0.dtb.inst_accesses 0 # IT system.cpu0.dtb.hits 175957422 # DTB hits system.cpu0.dtb.misses 123914 # DTB misses system.cpu0.dtb.accesses 176081336 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -168,6 +202,24 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.itb.walker.walks 60226 # Table walker walks requested +system.cpu0.itb.walker.walksLong 60226 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walkWaitTime::samples 60226 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 60226 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 60226 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 54190 98.81% 98.81% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 654 1.19% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 54844 # Table walker page sizes translated +system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 60226 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 60226 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 54844 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 54844 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 115070 # Table walker requests started/completed, data/inst system.cpu0.itb.inst_hits 491372488 # ITB inst hits system.cpu0.itb.inst_misses 60226 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits @@ -392,15 +444,12 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped +system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size +system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing system.cpu0.l2cache.tags.replacements 2648971 # number of replacements system.cpu0.l2cache.tags.tagsinuse 16219.904236 # Cycle average of tags in use system.cpu0.l2cache.tags.total_refs 11415809 # Total number of references to valid blocks. @@ -576,6 +625,14 @@ system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::total 20196192 # Request fanout histogram +system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -597,6 +654,24 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.walker.walks 144852 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 144852 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walkWaitTime::samples 144852 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 144852 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 144852 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walksPending::samples -274403872 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -274403872 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -274403872 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 112422 89.02% 89.02% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 13865 10.98% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 126287 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 144852 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 144852 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 126287 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 126287 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 271139 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses system.cpu1.dtb.read_hits 91720002 # DTB read hits @@ -618,6 +693,14 @@ system.cpu1.dtb.inst_accesses 0 # IT system.cpu1.dtb.hits 174219015 # DTB hits system.cpu1.dtb.misses 144852 # DTB misses system.cpu1.dtb.accesses 174363867 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -639,6 +722,24 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.itb.walker.walks 61939 # Table walker walks requested +system.cpu1.itb.walker.walksLong 61939 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walkWaitTime::samples 61939 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 61939 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 61939 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walksPending::samples -274404872 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -274404872 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -274404872 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 54929 99.06% 99.06% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 521 0.94% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 55450 # Table walker page sizes translated +system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 61939 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 61939 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55450 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55450 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 117389 # Table walker requests started/completed, data/inst system.cpu1.itb.inst_hits 485906850 # ITB inst hits system.cpu1.itb.inst_misses 61939 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits @@ -861,15 +962,12 @@ system.cpu1.icache.avg_blocked_cycles::no_targets nan system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped +system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size +system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing system.cpu1.l2cache.tags.replacements 2333825 # number of replacements system.cpu1.l2cache.tags.tagsinuse 13484.024344 # Cycle average of tags in use system.cpu1.l2cache.tags.total_refs 11006559 # Total number of references to valid blocks. diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt index 09df20817..70b8700c6 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 51.111151 # Nu sim_ticks 51111150553500 # Number of ticks simulated final_tick 51111150553500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1176583 # Simulator instruction rate (inst/s) -host_op_rate 1382679 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 61065327647 # Simulator tick rate (ticks/s) -host_mem_usage 656288 # Number of bytes of host memory used -host_seconds 836.99 # Real time elapsed on the host +host_inst_rate 1336104 # Simulator instruction rate (inst/s) +host_op_rate 1570142 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 69344550867 # Simulator tick rate (ticks/s) +host_mem_usage 712616 # Number of bytes of host memory used +host_seconds 737.06 # Real time elapsed on the host sim_insts 984789519 # Number of instructions simulated sim_ops 1157289961 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -74,6 +74,14 @@ system.cf0.dma_write_full_pages 1666 # Nu system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -95,6 +103,24 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 265618 # Table walker walks requested +system.cpu.dtb.walker.walksLong 265618 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walkWaitTime::samples 265618 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 265618 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 265618 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 204344 89.54% 89.54% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 23878 10.46% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 228222 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 265618 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 265618 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 228222 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 228222 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 493840 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 184057973 # DTB read hits @@ -116,6 +142,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 352334273 # DTB hits system.cpu.dtb.misses 265618 # DTB misses system.cpu.dtb.accesses 352599891 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -137,6 +171,24 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 126829 # Table walker walks requested +system.cpu.itb.walker.walksLong 126829 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walkWaitTime::samples 126829 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 126829 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 126829 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 113566 99.02% 99.02% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1125 0.98% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 114691 # Table walker page sizes translated +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 126829 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 126829 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 114691 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 114691 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 241520 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 985266544 # ITB inst hits system.cpu.itb.inst_misses 126829 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt index 2d0abc648..cd0cb8f17 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt @@ -1,172 +1,172 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.398431 # Number of seconds simulated -sim_ticks 47398431268500 # Number of ticks simulated -final_tick 47398431268500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.410782 # Number of seconds simulated +sim_ticks 47410781652000 # Number of ticks simulated +final_tick 47410781652000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 671569 # Simulator instruction rate (inst/s) -host_op_rate 790318 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 37657329129 # Simulator tick rate (ticks/s) -host_mem_usage 861000 # Number of bytes of host memory used -host_seconds 1258.68 # Real time elapsed on the host -sim_insts 845288376 # Number of instructions simulated -sim_ops 994755388 # Number of ops (including micro ops) simulated +host_inst_rate 787433 # Simulator instruction rate (inst/s) +host_op_rate 926573 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 41969003911 # Simulator tick rate (ticks/s) +host_mem_usage 699232 # Number of bytes of host memory used +host_seconds 1129.66 # Real time elapsed on the host +sim_insts 889532971 # Number of instructions simulated +sim_ops 1046714541 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 36416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 41984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 768052 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 7936536 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 44723840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 83456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 97984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 589368 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 8667104 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 21031552 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 441920 # Number of bytes read from this memory -system.physmem.bytes_read::total 84418212 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 768052 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 589368 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1357420 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65101248 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 154432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 156800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3551860 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 14084888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 14587840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 66560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 59904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2809592 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 8562400 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 11943680 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 428992 # Number of bytes read from this memory +system.physmem.bytes_read::total 56406948 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3551860 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2809592 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 6361452 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 74353408 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20812 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 65122064 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 569 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 656 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 52408 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 124030 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 698810 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1304 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1531 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 9297 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 135438 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 328618 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6905 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1359566 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1017207 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 74374224 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2413 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2450 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 95905 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 220098 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 227935 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1040 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 936 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 43988 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 133802 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 186620 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6703 # Number of read requests responded to by this memory +system.physmem.num_reads::total 921890 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1161772 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2602 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1019810 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 768 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 886 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 16204 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 167443 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 943572 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 1761 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 2067 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 12434 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 182856 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 443718 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9324 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1781034 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 16204 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 12434 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 28639 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1373490 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1164375 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3257 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 3307 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 74917 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 297082 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 307690 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 1404 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 1264 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 59261 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 180600 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 251919 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9048 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1189749 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 74917 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 59261 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 134177 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1568281 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 439 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1373929 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1373490 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 768 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 886 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 16204 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 167882 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 943572 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 1761 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 2067 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 12434 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 182856 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 443718 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9324 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3154963 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1359566 # Number of read requests accepted -system.physmem.writeReqs 1139623 # Number of write requests accepted -system.physmem.readBursts 1359566 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1139623 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 86962304 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 49920 # Total number of bytes read from write queue -system.physmem.bytesWritten 72439488 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 84418212 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 72790096 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 780 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 7732 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 85004 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 81504 # Per bank write bursts -system.physmem.perBankRdBursts::1 94599 # Per bank write bursts -system.physmem.perBankRdBursts::2 79086 # Per bank write bursts -system.physmem.perBankRdBursts::3 89082 # Per bank write bursts -system.physmem.perBankRdBursts::4 90127 # Per bank write bursts -system.physmem.perBankRdBursts::5 94039 # Per bank write bursts -system.physmem.perBankRdBursts::6 78740 # Per bank write bursts -system.physmem.perBankRdBursts::7 79772 # Per bank write bursts -system.physmem.perBankRdBursts::8 80197 # Per bank write bursts -system.physmem.perBankRdBursts::9 124149 # Per bank write bursts -system.physmem.perBankRdBursts::10 71869 # Per bank write bursts -system.physmem.perBankRdBursts::11 83577 # Per bank write bursts -system.physmem.perBankRdBursts::12 73174 # Per bank write bursts -system.physmem.perBankRdBursts::13 83519 # Per bank write bursts -system.physmem.perBankRdBursts::14 78794 # Per bank write bursts -system.physmem.perBankRdBursts::15 76558 # Per bank write bursts -system.physmem.perBankWrBursts::0 70549 # Per bank write bursts -system.physmem.perBankWrBursts::1 76959 # Per bank write bursts -system.physmem.perBankWrBursts::2 69527 # Per bank write bursts -system.physmem.perBankWrBursts::3 76268 # Per bank write bursts -system.physmem.perBankWrBursts::4 71760 # Per bank write bursts -system.physmem.perBankWrBursts::5 76111 # Per bank write bursts -system.physmem.perBankWrBursts::6 67646 # Per bank write bursts -system.physmem.perBankWrBursts::7 68141 # Per bank write bursts -system.physmem.perBankWrBursts::8 69345 # Per bank write bursts -system.physmem.perBankWrBursts::9 72887 # Per bank write bursts -system.physmem.perBankWrBursts::10 65485 # Per bank write bursts -system.physmem.perBankWrBursts::11 73987 # Per bank write bursts -system.physmem.perBankWrBursts::12 65828 # Per bank write bursts -system.physmem.perBankWrBursts::13 73935 # Per bank write bursts -system.physmem.perBankWrBursts::14 66021 # Per bank write bursts -system.physmem.perBankWrBursts::15 67418 # Per bank write bursts +system.physmem.bw_write::total 1568720 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1568281 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3257 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 3307 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 74917 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 297521 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 307690 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 1404 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 1264 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 59261 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 180600 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 251919 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9048 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2758469 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 921890 # Number of read requests accepted +system.physmem.writeReqs 1829645 # Number of write requests accepted +system.physmem.readBursts 921890 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1829645 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 58978368 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 22592 # Total number of bytes read from write queue +system.physmem.bytesWritten 116660480 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 56406948 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 116951504 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 353 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 6803 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 114603 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 54393 # Per bank write bursts +system.physmem.perBankRdBursts::1 56084 # Per bank write bursts +system.physmem.perBankRdBursts::2 54659 # Per bank write bursts +system.physmem.perBankRdBursts::3 58883 # Per bank write bursts +system.physmem.perBankRdBursts::4 54974 # Per bank write bursts +system.physmem.perBankRdBursts::5 58047 # Per bank write bursts +system.physmem.perBankRdBursts::6 51881 # Per bank write bursts +system.physmem.perBankRdBursts::7 58759 # Per bank write bursts +system.physmem.perBankRdBursts::8 52533 # Per bank write bursts +system.physmem.perBankRdBursts::9 95950 # Per bank write bursts +system.physmem.perBankRdBursts::10 53815 # Per bank write bursts +system.physmem.perBankRdBursts::11 56993 # Per bank write bursts +system.physmem.perBankRdBursts::12 52328 # Per bank write bursts +system.physmem.perBankRdBursts::13 55917 # Per bank write bursts +system.physmem.perBankRdBursts::14 52932 # Per bank write bursts +system.physmem.perBankRdBursts::15 53389 # Per bank write bursts +system.physmem.perBankWrBursts::0 113787 # Per bank write bursts +system.physmem.perBankWrBursts::1 117144 # Per bank write bursts +system.physmem.perBankWrBursts::2 115098 # Per bank write bursts +system.physmem.perBankWrBursts::3 118536 # Per bank write bursts +system.physmem.perBankWrBursts::4 116769 # Per bank write bursts +system.physmem.perBankWrBursts::5 120895 # Per bank write bursts +system.physmem.perBankWrBursts::6 109520 # Per bank write bursts +system.physmem.perBankWrBursts::7 112924 # Per bank write bursts +system.physmem.perBankWrBursts::8 111914 # Per bank write bursts +system.physmem.perBankWrBursts::9 117541 # Per bank write bursts +system.physmem.perBankWrBursts::10 111832 # Per bank write bursts +system.physmem.perBankWrBursts::11 116807 # Per bank write bursts +system.physmem.perBankWrBursts::12 108182 # Per bank write bursts +system.physmem.perBankWrBursts::13 109739 # Per bank write bursts +system.physmem.perBankWrBursts::14 110202 # Per bank write bursts +system.physmem.perBankWrBursts::15 111930 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 5 # Number of times write queue was full causing retry -system.physmem.totGap 47398428076000 # Total gap between requests +system.physmem.numWrRetry 2 # Number of times write queue was full causing retry +system.physmem.totGap 47410778671000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43195 # Read request sizes (log2) system.physmem.readPktSize::3 37 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1316329 # Read request sizes (log2) +system.physmem.readPktSize::6 878653 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2601 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1137020 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 566894 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 282234 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 134057 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 101972 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 67644 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 58693 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 53670 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 46721 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 35916 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 3762 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1955 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1465 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1125 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 882 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 709 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 471 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 229 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 184 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 107 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 75 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1827042 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 652905 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 75815 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 40303 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 33479 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 29162 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 25818 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 22543 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 19321 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 15689 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2492 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1008 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 754 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 600 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 460 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 351 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 292 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 214 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 179 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 82 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 63 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see @@ -188,158 +188,182 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 16911 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 22466 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 30737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 39170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 44059 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 50283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 58139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 68202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 72051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 76579 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 76851 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 78478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 78341 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 80363 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 74556 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 75992 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 78312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 75395 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 11828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 7611 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 4129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1848 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1099 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 916 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 777 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 712 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 642 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 648 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 562 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 544 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 505 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 463 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 418 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 372 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 356 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 192 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 5 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 648906 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 245.646870 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 142.183985 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 295.195613 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 325424 50.15% 50.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 135792 20.93% 71.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 50411 7.77% 78.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 26706 4.12% 82.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 22287 3.43% 86.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 16108 2.48% 88.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 10950 1.69% 90.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 13619 2.10% 92.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 47609 7.34% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 648906 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 58676 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.156827 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 139.787244 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 58673 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 54841 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 74169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 96317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 106970 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 112981 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 116642 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 107891 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 106380 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 105711 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 108843 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 109894 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 108607 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 105867 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 106408 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 98436 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 96529 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 94372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 91211 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 4176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 3101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1802 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1394 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 899 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 725 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 589 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 554 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 484 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 413 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 392 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 373 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 345 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 302 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 273 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 268 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 219 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 6 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1000117 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 175.617981 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 106.594305 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 248.236984 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 645970 64.59% 64.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 191036 19.10% 83.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 45051 4.50% 88.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 21747 2.17% 90.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 15328 1.53% 91.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 10644 1.06% 92.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8285 0.83% 93.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 7295 0.73% 94.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 54761 5.48% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1000117 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 87721 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 10.505238 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 108.849756 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 87718 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::24576-25599 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 58676 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 58676 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.290119 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.850822 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 13.308232 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 54948 93.65% 93.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 970 1.65% 95.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 598 1.02% 96.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 219 0.37% 96.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 626 1.07% 97.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 147 0.25% 98.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 195 0.33% 98.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 132 0.22% 98.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 184 0.31% 98.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 81 0.14% 99.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 205 0.35% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 24 0.04% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 63 0.11% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 38 0.06% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 129 0.22% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 15 0.03% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 27 0.05% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 11 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 19 0.03% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 8 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 11 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 2 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 5 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 6 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 3 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 4 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-255 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-279 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 58676 # Writes before turning the bus around for reads -system.physmem.totQLat 69966976258 # Total ticks spent queuing -system.physmem.totMemAccLat 95444213758 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 6793930000 # Total ticks spent in databus transfers -system.physmem.avgQLat 51492.27 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 87721 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 87721 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.779745 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.605058 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 11.125024 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 56948 64.92% 64.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 16031 18.27% 83.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 6972 7.95% 91.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 3738 4.26% 95.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 1084 1.24% 96.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 357 0.41% 97.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 239 0.27% 97.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 271 0.31% 97.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 649 0.74% 98.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 108 0.12% 98.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 85 0.10% 98.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 76 0.09% 98.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 135 0.15% 98.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 76 0.09% 98.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 51 0.06% 98.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 73 0.08% 99.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 134 0.15% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 41 0.05% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 31 0.04% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 49 0.06% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 179 0.20% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 16 0.02% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 31 0.04% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 14 0.02% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 43 0.05% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 12 0.01% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 20 0.02% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 30 0.03% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 97 0.11% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 18 0.02% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 14 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 10 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 13 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 11 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 6 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 6 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 14 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 3 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 12 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::204-207 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::212-215 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::220-223 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 4 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 87721 # Writes before turning the bus around for reads +system.physmem.totQLat 32913462781 # Total ticks spent queuing +system.physmem.totMemAccLat 50192281531 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4607685000 # Total ticks spent in databus transfers +system.physmem.avgQLat 35715.83 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 70242.27 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.83 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.53 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.78 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.54 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 54465.83 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.24 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.46 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.19 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.47 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.73 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.44 # Average write queue length when enqueuing -system.physmem.readRowHits 1114788 # Number of row buffer hits during reads -system.physmem.writeRowHits 726958 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.04 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 64.23 # Row buffer hit rate for writes -system.physmem.avgGap 18965523.65 # Average gap between requests -system.physmem.pageHitRate 73.95 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 45538400789750 # Time in different power states -system.physmem.memoryStateTime::REF 1582737780000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 277292625250 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 2564850960 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 2340878400 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 1399472250 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 1277265000 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 5358202200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 5240320800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 3738707280 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 3595790880 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 3095835097680 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 3095835097680 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 1171174509540 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 1161726671475 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 27411712647750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 27420000225000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 31691783487660 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 31690016249235 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.625157 # Core power per rank (mW) -system.physmem.averagePower::1 668.587872 # Core power per rank (mW) +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.25 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.28 # Average write queue length when enqueuing +system.physmem.readRowHits 687654 # Number of row buffer hits during reads +system.physmem.writeRowHits 1056585 # Number of row buffer hits during writes +system.physmem.readRowHitRate 74.62 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 57.96 # Row buffer hit rate for writes +system.physmem.avgGap 17230665.31 # Average gap between requests +system.physmem.pageHitRate 63.56 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3832851960 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2091337875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3491865000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 5991881040 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3096641673840 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1200455054145 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27393437346750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31705942010610 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.749637 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45570820980751 # Time in different power states +system.physmem_0.memoryStateTime::REF 1583150140000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 256810103749 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 3728032560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2034144750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3696084600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 5819992560 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3096641673840 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1191404828700 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27401376141000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31704700898010 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.723459 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45584059811251 # Time in different power states +system.physmem_1.memoryStateTime::REF 1583150140000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 243570222499 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory @@ -373,6 +397,14 @@ system.cf0.dma_write_full_pages 1670 # Nu system.cf0.dma_write_bytes 6842880 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1673 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -394,27 +426,74 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.walker.walks 107972 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 107972 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9276 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 83163 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 107963 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 107963 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 107963 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 92448 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 17595.764614 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 15306.328665 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 15454.252367 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 91009 98.44% 98.44% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 1235 1.34% 99.78% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 66 0.07% 99.85% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 55 0.06% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 65 0.07% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 12 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 92448 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples -2398441544 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.163884 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.370170 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 -2005375084 83.61% 83.61% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 -393066460 16.39% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total -2398441544 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 83163 89.97% 89.97% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 9276 10.03% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 92439 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 107972 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 107972 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 92439 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 92439 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 200411 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 74706058 # DTB read hits -system.cpu0.dtb.read_misses 64792 # DTB read misses -system.cpu0.dtb.write_hits 67192400 # DTB write hits -system.cpu0.dtb.write_misses 21129 # DTB write misses +system.cpu0.dtb.read_hits 83792624 # DTB read hits +system.cpu0.dtb.read_misses 78614 # DTB read misses +system.cpu0.dtb.write_hits 76883618 # DTB write hits +system.cpu0.dtb.write_misses 29358 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 37660 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1002 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 33482 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 41330 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 38297 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 3817 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 4651 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 8375 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 74770850 # DTB read accesses -system.cpu0.dtb.write_accesses 67213529 # DTB write accesses +system.cpu0.dtb.perms_faults 10679 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 83871238 # DTB read accesses +system.cpu0.dtb.write_accesses 76912976 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 141898458 # DTB hits -system.cpu0.dtb.misses 85921 # DTB misses -system.cpu0.dtb.accesses 141984379 # DTB accesses +system.cpu0.dtb.hits 160676242 # DTB hits +system.cpu0.dtb.misses 107972 # DTB misses +system.cpu0.dtb.accesses 160784214 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -436,201 +515,236 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 397874920 # ITB inst hits -system.cpu0.itb.inst_misses 49120 # ITB inst misses +system.cpu0.itb.walker.walks 64255 # Table walker walks requested +system.cpu0.itb.walker.walksLong 64255 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 637 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 58227 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 64255 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 64255 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 64255 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 58864 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 20635.902164 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 17664.674655 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 19771.927470 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 57276 97.30% 97.30% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 1371 2.33% 99.63% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 47 0.08% 99.71% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 91 0.15% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 53 0.09% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 19 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 5 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 58864 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples -673300296 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 -673300296 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total -673300296 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 58227 98.92% 98.92% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 637 1.08% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 58864 # Table walker page sizes translated +system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 64255 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 64255 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 58864 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 58864 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 123119 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 448595101 # ITB inst hits +system.cpu0.itb.inst_misses 64255 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 37660 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1002 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 23760 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 41330 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 26739 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 397924040 # ITB inst accesses -system.cpu0.itb.hits 397874920 # DTB hits -system.cpu0.itb.misses 49120 # DTB misses -system.cpu0.itb.accesses 397924040 # DTB accesses -system.cpu0.numCycles 94796862537 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 448659356 # ITB inst accesses +system.cpu0.itb.hits 448595101 # DTB hits +system.cpu0.itb.misses 64255 # DTB misses +system.cpu0.itb.accesses 448659356 # DTB accesses +system.cpu0.numCycles 94821563304 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 397643174 # Number of instructions committed -system.cpu0.committedOps 466635553 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 429030148 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 322477 # Number of float alu accesses -system.cpu0.num_func_calls 23930039 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 59901605 # number of instructions that are conditional controls -system.cpu0.num_int_insts 429030148 # number of integer instructions -system.cpu0.num_fp_insts 322477 # number of float instructions -system.cpu0.num_int_register_reads 621630892 # number of times the integer registers were read -system.cpu0.num_int_register_writes 340702516 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 547437 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 211832 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 102593685 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 102325899 # number of times the CC registers were written -system.cpu0.num_mem_refs 141893093 # number of memory refs -system.cpu0.num_load_insts 74704433 # Number of load instructions -system.cpu0.num_store_insts 67188660 # Number of store instructions -system.cpu0.num_idle_cycles 93886429062.298019 # Number of idle cycles -system.cpu0.num_busy_cycles 910433474.701981 # Number of busy cycles -system.cpu0.not_idle_fraction 0.009604 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.990396 # Percentage of idle cycles -system.cpu0.Branches 88352328 # Number of branches fetched -system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 323823287 69.35% 69.35% # Class of executed instruction -system.cpu0.op_class::IntMult 1114929 0.24% 69.59% # Class of executed instruction -system.cpu0.op_class::IntDiv 56737 0.01% 69.61% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 22377 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::MemRead 74704433 16.00% 85.61% # Class of executed instruction -system.cpu0.op_class::MemWrite 67188660 14.39% 100.00% # Class of executed instruction +system.cpu0.committedInsts 448345930 # Number of instructions committed +system.cpu0.committedOps 527651436 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 484594714 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 558267 # Number of float alu accesses +system.cpu0.num_func_calls 26890258 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 68074268 # number of instructions that are conditional controls +system.cpu0.num_int_insts 484594714 # number of integer instructions +system.cpu0.num_fp_insts 558267 # number of float instructions +system.cpu0.num_int_register_reads 706750752 # number of times the integer registers were read +system.cpu0.num_int_register_writes 384547382 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 893879 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 490056 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 117567828 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 117277075 # number of times the CC registers were written +system.cpu0.num_mem_refs 160668093 # number of memory refs +system.cpu0.num_load_insts 83788812 # Number of load instructions +system.cpu0.num_store_insts 76879281 # Number of store instructions +system.cpu0.num_idle_cycles 93729284290.716034 # Number of idle cycles +system.cpu0.num_busy_cycles 1092279013.283977 # Number of busy cycles +system.cpu0.not_idle_fraction 0.011519 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.988481 # Percentage of idle cycles +system.cpu0.Branches 100174256 # Number of branches fetched +system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 365953478 69.32% 69.32% # Class of executed instruction +system.cpu0.op_class::IntMult 1186010 0.22% 69.54% # Class of executed instruction +system.cpu0.op_class::IntDiv 57830 0.01% 69.55% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 21 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 78277 0.01% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::MemRead 83788812 15.87% 85.44% # Class of executed instruction +system.cpu0.op_class::MemWrite 76879281 14.56% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 466910423 # Class of executed instruction +system.cpu0.op_class::total 527943731 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 5105 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 4859280 # number of replacements -system.cpu0.dcache.tags.tagsinuse 480.680410 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 136835586 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 4859789 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 28.156693 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 3644536500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 480.680410 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.938829 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.938829 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 406 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 9 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 288671468 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 288671468 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 69599952 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 69599952 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 63413457 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 63413457 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 173858 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 173858 # number of SoftPFReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 133135 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::total 133135 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1596886 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1596886 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1561841 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1561841 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 133013409 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 133013409 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 133187267 # number of overall hits -system.cpu0.dcache.overall_hits::total 133187267 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 2622769 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 2622769 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1185607 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1185607 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 553155 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 553155 # number of SoftPFReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 697992 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::total 697992 # number of WriteInvalidateReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 145021 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 145021 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 178721 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 178721 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3808376 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3808376 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 4361531 # number of overall misses -system.cpu0.dcache.overall_misses::total 4361531 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 36725560788 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 36725560788 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 18496940456 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 18496940456 # number of WriteReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 11951080104 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 11951080104 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2007745317 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 2007745317 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3807661334 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 3807661334 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 927000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 927000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 55222501244 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 55222501244 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 55222501244 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 55222501244 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 72222721 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 72222721 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 64599064 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 64599064 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 727013 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 727013 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 831127 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::total 831127 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1741907 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 1741907 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1740562 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 1740562 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 136821785 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 136821785 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 137548798 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 137548798 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036315 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.036315 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018353 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.018353 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.760860 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.760860 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.839814 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.839814 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.083254 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.083254 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.102680 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.102680 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027835 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.027835 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.031709 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.031709 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14002.590693 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14002.590693 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15601.240931 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 15601.240931 # average WriteReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 17122.087508 # average WriteInvalidateReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 17122.087508 # average WriteInvalidateReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13844.514360 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13844.514360 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21305.058354 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21305.058354 # average StoreCondReq miss latency +system.cpu0.kern.inst.quiesce 5474 # number of quiesce instructions executed +system.cpu0.dcache.tags.replacements 5753925 # number of replacements +system.cpu0.dcache.tags.tagsinuse 509.684776 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 154679022 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 5754435 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 26.879967 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 3644714000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 509.684776 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.995478 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.995478 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 390 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 55 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 327127592 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 327127592 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 77833401 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 77833401 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 72535559 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 72535559 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 180949 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 180949 # number of SoftPFReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 117408 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::total 117408 # number of WriteInvalidateReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1813577 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1813577 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1784599 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1784599 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 150368960 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 150368960 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 150549909 # number of overall hits +system.cpu0.dcache.overall_hits::total 150549909 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 3079415 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 3079415 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1439122 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1439122 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 698265 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 698265 # number of SoftPFReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 782756 # number of WriteInvalidateReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::total 782756 # number of WriteInvalidateReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 172905 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 172905 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 200615 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 200615 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 4518537 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 4518537 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 5216802 # number of overall misses +system.cpu0.dcache.overall_misses::total 5216802 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 45365631768 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 45365631768 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 25986134990 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 25986134990 # number of WriteReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 26026367891 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 26026367891 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2610218258 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 2610218258 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4265500897 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4265500897 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2243000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2243000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 71351766758 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 71351766758 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 71351766758 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 71351766758 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 80912816 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 80912816 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 73974681 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 73974681 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 879214 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 879214 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 900164 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::total 900164 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1986482 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 1986482 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1985214 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 1985214 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 154887497 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 154887497 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 155766711 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 155766711 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.038058 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.038058 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.019454 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.019454 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.794192 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.794192 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.869570 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.869570 # 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average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 18056.936792 # average WriteReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 33249.656203 # average WriteInvalidateReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 33249.656203 # average WriteInvalidateReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15096.256661 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15096.256661 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21262.123455 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21262.123455 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14500.275510 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 14500.275510 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12661.265332 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 12661.265332 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15790.900187 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 15790.900187 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13677.300146 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 13677.300146 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -639,92 +753,92 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # 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number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4770852392 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4770852392 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036027 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036027 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018022 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018022 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.758494 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.758494 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.839814 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.839814 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.062487 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.062487 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.102680 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.102680 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027526 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.027526 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031389 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.031389 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11745.684807 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11745.684807 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 13440.434019 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 13440.434019 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 20898.682731 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 20898.682731 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 15103.489576 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 15103.489576 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11345.358228 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11345.358228 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19250.724123 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19250.724123 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 3895213 # number of writebacks +system.cpu0.dcache.writebacks::total 3895213 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 35120 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 35120 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21470 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 21470 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 46933 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 46933 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 56590 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 56590 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 56590 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 56590 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3044295 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 3044295 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1417652 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1417652 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 692633 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 692633 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 782756 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 782756 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 125972 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 125972 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 200615 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 200615 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 4461947 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 4461947 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 5154580 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 5154580 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 37795344499 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 37795344499 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 22579422262 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 22579422262 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14234213672 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14234213672 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 24458156109 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 24458156109 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1564829744 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1564829744 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3853276103 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3853276103 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2137000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2137000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 60374766761 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 60374766761 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 74608980433 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 74608980433 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2287793998 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2287793998 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2244465248 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2244465248 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4532259246 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4532259246 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.037624 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037624 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019164 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019164 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.787787 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.787787 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.869570 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.869570 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.063415 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.063415 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.101055 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.101055 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028808 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.028808 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.033092 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.033092 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12415.138644 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12415.138644 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15927.337782 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15927.337782 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 20550.874232 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 20550.874232 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 31246.207131 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 31246.207131 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12422.044137 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12422.044137 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19207.318012 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19207.318012 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 12269.565120 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 12269.565120 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13371.668756 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13371.668756 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13531.036286 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13531.036286 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14474.308369 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14474.308369 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -732,59 +846,58 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 4269396 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.932974 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 393605012 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 4269908 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 92.181146 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 18918806750 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.932974 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999869 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999869 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 5166576 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.910022 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 443428013 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 5167088 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 85.817778 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 30209622750 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.910022 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999824 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999824 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 269 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 222 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 324 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 127 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 800019748 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 800019748 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 393605012 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 393605012 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 393605012 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 393605012 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 393605012 # number of overall hits -system.cpu0.icache.overall_hits::total 393605012 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 4269908 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 4269908 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 4269908 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 4269908 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 4269908 # number of overall misses -system.cpu0.icache.overall_misses::total 4269908 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 37643365597 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 37643365597 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 37643365597 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 37643365597 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 37643365597 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 37643365597 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 397874920 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 397874920 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 397874920 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 397874920 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 397874920 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 397874920 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010732 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.010732 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.010732 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.010732 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.010732 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.010732 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8815.966432 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 8815.966432 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8815.966432 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 8815.966432 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8815.966432 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 8815.966432 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 902357290 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 902357290 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 443428013 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 443428013 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 443428013 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 443428013 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 443428013 # number of overall hits +system.cpu0.icache.overall_hits::total 443428013 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 5167088 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 5167088 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 5167088 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 5167088 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 5167088 # number of overall misses +system.cpu0.icache.overall_misses::total 5167088 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 53694723563 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 53694723563 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 53694723563 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 53694723563 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 53694723563 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 53694723563 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 448595101 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 448595101 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 448595101 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 448595101 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 448595101 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 448595101 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011518 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.011518 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011518 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.011518 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011518 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.011518 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10391.679717 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10391.679717 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10391.679717 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10391.679717 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10391.679717 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10391.679717 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -793,384 +906,383 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 4269908 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 4269908 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 4269908 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 4269908 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 4269908 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 4269908 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 31235618425 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 31235618425 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 31235618425 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 31235618425 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 31235618425 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 31235618425 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 5167088 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 5167088 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 5167088 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 5167088 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 5167088 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 5167088 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 45925261947 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 45925261947 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 45925261947 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 45925261947 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 45925261947 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 45925261947 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3405609750 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 3405609750 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 3405609750 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 3405609750 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.010732 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010732 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.010732 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.010732 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.010732 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.010732 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 7315.290733 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7315.290733 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7315.290733 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 7315.290733 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7315.290733 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 7315.290733 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011518 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011518 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011518 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.011518 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011518 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.011518 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8888.035572 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8888.035572 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8888.035572 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 8888.035572 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8888.035572 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 8888.035572 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 45505774 # number of hwpf identified -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 2657797 # number of hwpf that were already in mshr -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 39900232 # number of hwpf that were already in the cache -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 8744 # number of hwpf that were already in the prefetch queue -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 580 # number of hwpf removed because MSHR allocated -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 2938421 # number of hwpf issued -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 3808538 # number of hwpf spanning a virtual page -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.l2cache.tags.replacements 3291824 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16191.272385 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 9909292 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 3307923 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 2.995624 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 16044231500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 5217.724609 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 49.949148 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 58.574202 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 727.292976 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 2667.900561 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 7469.830889 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.318465 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003049 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003575 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.044390 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.162836 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.455922 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.988237 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8632 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 100 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 7367 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 22 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 210 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 1111 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 7012 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 277 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::0 6 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 10 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 7 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 77 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1042 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 1532 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4604 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 127 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.526855 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.006104 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.449646 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 215960486 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 215960486 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 166834 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 106498 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 4104943 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.data 2390641 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 6768916 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 3276433 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 3276433 # number of Writeback hits -system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data 610572 # number of WriteInvalidateReq hits -system.cpu0.l2cache.WriteInvalidateReq_hits::total 610572 # number of WriteInvalidateReq hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 75583 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 75583 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 31346 # 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number of overall hits -system.cpu0.l2cache.overall_hits::total 7583453 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 9451 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 7593 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 164965 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.data 871580 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 1053589 # number of ReadReq misses -system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data 86357 # number of WriteInvalidateReq misses -system.cpu0.l2cache.WriteInvalidateReq_misses::total 86357 # number of WriteInvalidateReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 106896 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 106896 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 147374 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 147374 # 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number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 2994303005 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 2994303005 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 855000 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 855000 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 6538293027 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 6538293027 # number of ReadExReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 247144715 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 215825476 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 4449371565 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 32240016803 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 37152358559 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 247144715 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 215825476 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 4449371565 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 32240016803 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 37152358559 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 176285 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 114091 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 4269908 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.data 3262221 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 7822505 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 3276433 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 3276433 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data 696929 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.l2cache.WriteInvalidateReq_accesses::total 696929 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 182479 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 182479 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 178720 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 178720 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 1 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 987504 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 987504 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 176285 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 114091 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 4269908 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 4249725 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 8810009 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 176285 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 114091 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 4269908 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 4249725 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 8810009 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.053612 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.066552 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.038634 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.267174 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.134687 # miss rate for ReadReq accesses -system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data 0.123911 # miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.123911 # miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.585799 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.585799 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.824608 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.824608 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.prefetcher.num_hwpf_issued 7865373 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 7866135 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 648 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped +system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size +system.cpu0.l2cache.prefetcher.pfSpanPage 985913 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 2427001 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16243.780061 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 11146490 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 2442996 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 4.562631 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 4729494500 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 7283.700781 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 78.630524 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 92.657228 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 3931.432813 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3992.358247 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 865.000469 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.444562 # 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Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 826 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 313 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 23 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 41 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 947 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4330 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6826 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2259 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.089478 # 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average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 29683.053592 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 29683.053592 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 19129.700667 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 21397.343606 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 21780.932052 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 23590.654453 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 23328.795643 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 19129.700667 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 21397.343606 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 21780.932052 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 23590.654453 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 43752.426923 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 37852.554233 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.231978 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 31456.355779 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 34671.120177 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 22958.552072 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 26026.451805 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 25072.510487 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49425.192319 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 49425.192319 # average HardPFReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 34326.997887 # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 34326.997887 # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16986.530742 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16986.530742 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13741.236699 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13741.236699 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 214125 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 214125 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 36924.550389 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 36924.550389 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 31456.355779 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 34671.120177 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 22958.552072 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28227.276368 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 26740.395420 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 31456.355779 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 34671.120177 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 22958.552072 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28227.276368 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49425.192319 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 33232.542850 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1180,59 +1292,67 @@ system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 11465749 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 8074092 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 15773 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 15773 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 3276433 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 4228803 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 811507 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 696929 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 407420 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 328722 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 423022 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 30 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 53 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1108208 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 995011 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 8626066 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 14109371 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 260774 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 426575 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 23422786 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 273446612 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 532438419 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 912728 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1410280 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 808208039 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 8581549 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 21569506 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.385644 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.486747 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 11541292 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 9690709 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 15329 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 15329 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 3895213 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 1069383 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1166255 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 781481 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 444610 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 368177 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 498972 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 55 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 100 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1328849 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1215209 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 10420426 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 16690518 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 351532 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 549297 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 28011773 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 330866132 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 630631769 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1276280 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1881728 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 964655909 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 4194903 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 19756578 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 5.197801 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.398341 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 13251364 61.44% 61.44% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 8318142 38.56% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::5 15848715 80.22% 80.22% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::6 3907863 19.78% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 21569506 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 10644176370 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 19756578 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 12645685295 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 173370992 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 194485993 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 6459583336 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 7813325558 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 6973558574 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 8298663367 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 146771777 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 192341003 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 250366041 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 314436506 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1254,27 +1374,82 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.walker.walks 99527 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 99527 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9603 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 74573 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 99518 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 0.271308 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 67.169326 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-2047 99516 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::6144-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::18432-20479 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 99518 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 84185 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 16581.674289 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 15037.130908 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 10932.627488 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-32767 81471 96.78% 96.78% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-65535 2185 2.60% 99.37% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-98303 285 0.34% 99.71% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-131071 159 0.19% 99.90% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-163839 19 0.02% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::163840-196607 14 0.02% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-229375 18 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::229376-262143 4 0.00% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-294911 15 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::294912-327679 5 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-360447 5 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::360448-393215 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 84185 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -1589468256 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.778279 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.415405 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -352419148 22.17% 22.17% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 -1237049108 77.83% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -1589468256 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 74574 88.59% 88.59% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 9603 11.41% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 84177 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 99527 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 99527 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 84177 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 84177 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 183704 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 84980512 # DTB read hits -system.cpu1.dtb.read_misses 74547 # DTB read misses -system.cpu1.dtb.write_hits 77969612 # DTB write hits -system.cpu1.dtb.write_misses 26781 # DTB write misses +system.cpu1.dtb.read_hits 83767099 # DTB read hits +system.cpu1.dtb.read_misses 74857 # DTB read misses +system.cpu1.dtb.write_hits 75685520 # DTB write hits +system.cpu1.dtb.write_misses 24670 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 37660 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1002 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 37319 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 41330 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 36584 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 4156 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 4104 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 10210 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 85055059 # DTB read accesses -system.cpu1.dtb.write_accesses 77996393 # DTB write accesses +system.cpu1.dtb.perms_faults 9015 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 83841956 # DTB read accesses +system.cpu1.dtb.write_accesses 75710190 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 162950124 # DTB hits -system.cpu1.dtb.misses 101328 # DTB misses -system.cpu1.dtb.accesses 163051452 # DTB accesses +system.cpu1.dtb.hits 159452619 # DTB hits +system.cpu1.dtb.misses 99527 # DTB misses +system.cpu1.dtb.accesses 159552146 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1296,201 +1471,239 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 447940407 # ITB inst hits -system.cpu1.itb.inst_misses 68561 # ITB inst misses +system.cpu1.itb.walker.walks 55326 # Table walker walks requested +system.cpu1.itb.walker.walksLong 55326 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 571 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 49211 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 55326 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 55326 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 55326 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 49782 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 18533.691816 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 16693.913266 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 13345.941074 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-32767 47101 94.61% 94.61% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-65535 2168 4.35% 98.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-98303 178 0.36% 99.33% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::98304-131071 248 0.50% 99.83% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-163839 12 0.02% 99.85% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::163840-196607 16 0.03% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-229375 24 0.05% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::229376-262143 6 0.01% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-294911 18 0.04% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::294912-327679 3 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::360448-393215 3 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 49782 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -1199136648 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -1199136648 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -1199136648 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 49211 98.85% 98.85% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 571 1.15% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 49782 # Table walker page sizes translated +system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 55326 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 55326 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 49782 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 49782 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 105108 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 441493680 # ITB inst hits +system.cpu1.itb.inst_misses 55326 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 37660 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1002 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 26339 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 41330 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 25739 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 448008968 # ITB inst accesses -system.cpu1.itb.hits 447940407 # DTB hits -system.cpu1.itb.misses 68561 # DTB misses -system.cpu1.itb.accesses 448008968 # DTB accesses -system.cpu1.numCycles 94796862537 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 441549006 # ITB inst accesses +system.cpu1.itb.hits 441493680 # DTB hits +system.cpu1.itb.misses 55326 # DTB misses +system.cpu1.itb.accesses 441549006 # DTB accesses +system.cpu1.numCycles 94821563303 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 447645202 # Number of instructions committed -system.cpu1.committedOps 528119835 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 486291398 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 624474 # Number of float alu accesses -system.cpu1.num_func_calls 27450761 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 67545606 # number of instructions that are conditional controls -system.cpu1.num_int_insts 486291398 # number of integer instructions -system.cpu1.num_fp_insts 624474 # number of float instructions -system.cpu1.num_int_register_reads 698728829 # number of times the integer registers were read -system.cpu1.num_int_register_writes 384530758 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 985803 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 576512 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 114161169 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 113813296 # number of times the CC registers were written -system.cpu1.num_mem_refs 162934099 # number of memory refs -system.cpu1.num_load_insts 84972579 # Number of load instructions -system.cpu1.num_store_insts 77961520 # Number of store instructions -system.cpu1.num_idle_cycles 93770083152.566025 # Number of idle cycles -system.cpu1.num_busy_cycles 1026779384.433978 # Number of busy cycles -system.cpu1.not_idle_fraction 0.010831 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.989169 # Percentage of idle cycles -system.cpu1.Branches 100081816 # Number of branches fetched -system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 364276895 68.94% 68.94% # Class of executed instruction -system.cpu1.op_class::IntMult 1051011 0.20% 69.14% # Class of executed instruction -system.cpu1.op_class::IntDiv 60606 0.01% 69.15% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 92495 0.02% 69.17% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.17% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.17% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.17% # Class of executed instruction -system.cpu1.op_class::MemRead 84972579 16.08% 85.25% # Class of executed instruction -system.cpu1.op_class::MemWrite 77961520 14.75% 100.00% # Class of executed instruction +system.cpu1.committedInsts 441187041 # Number of instructions committed +system.cpu1.committedOps 519063105 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 477531543 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 364386 # Number of float alu accesses +system.cpu1.num_func_calls 26570520 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 66815511 # number of instructions that are conditional controls +system.cpu1.num_int_insts 477531543 # number of integer instructions +system.cpu1.num_fp_insts 364386 # number of float instructions +system.cpu1.num_int_register_reads 690361032 # number of times the integer registers were read +system.cpu1.num_int_register_writes 378560518 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 602629 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 273816 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 113424708 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 113111436 # number of times the CC registers were written +system.cpu1.num_mem_refs 159443034 # number of memory refs +system.cpu1.num_load_insts 83763663 # Number of load instructions +system.cpu1.num_store_insts 75679371 # Number of store instructions +system.cpu1.num_idle_cycles 93795188251.508850 # Number of idle cycles +system.cpu1.num_busy_cycles 1026375051.491154 # Number of busy cycles +system.cpu1.not_idle_fraction 0.010824 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.989176 # Percentage of idle cycles +system.cpu1.Branches 98214896 # Number of branches fetched +system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 358777055 69.08% 69.08% # Class of executed instruction +system.cpu1.op_class::IntMult 1052972 0.20% 69.28% # Class of executed instruction +system.cpu1.op_class::IntDiv 61499 0.01% 69.29% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 35293 0.01% 69.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.30% # Class of executed instruction +system.cpu1.op_class::MemRead 83763663 16.13% 85.43% # Class of executed instruction +system.cpu1.op_class::MemWrite 75679371 14.57% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 528415149 # Class of executed instruction +system.cpu1.op_class::total 519369853 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 13701 # number of quiesce instructions executed -system.cpu1.dcache.tags.replacements 5194711 # number of replacements -system.cpu1.dcache.tags.tagsinuse 457.134068 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 157559099 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5195223 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 30.327687 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8367548601000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 457.134068 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.892840 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.892840 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 415 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 331059949 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 331059949 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 79405575 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 79405575 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 74066119 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 74066119 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 191889 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 191889 # number of SoftPFReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 197632 # number of WriteInvalidateReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::total 197632 # number of WriteInvalidateReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1669680 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1669680 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1654141 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1654141 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 153471694 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 153471694 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 153663583 # number of overall hits -system.cpu1.dcache.overall_hits::total 153663583 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 2946837 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 2946837 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1283113 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1283113 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 571898 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 571898 # number of SoftPFReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 550709 # number of WriteInvalidateReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::total 550709 # number of WriteInvalidateReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 171203 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 171203 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 185528 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 185528 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 4229950 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 4229950 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 4801848 # number of overall misses -system.cpu1.dcache.overall_misses::total 4801848 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 41215882509 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 41215882509 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 19312866378 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 19312866378 # number of WriteReq miss cycles -system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 6595698094 # number of WriteInvalidateReq miss cycles -system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 6595698094 # number of WriteInvalidateReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2383654561 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 2383654561 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3901847697 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 3901847697 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1095500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1095500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 60528748887 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 60528748887 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 60528748887 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 60528748887 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 82352412 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 82352412 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 75349232 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 75349232 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 763787 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 763787 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 748341 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::total 748341 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1840883 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1840883 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1839669 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1839669 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 157701644 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 157701644 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 158465431 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 158465431 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035783 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.035783 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.017029 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.017029 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.748766 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.748766 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.735906 # miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.735906 # miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.093000 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.093000 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100849 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100849 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026822 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.026822 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.030302 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.030302 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13986.481950 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 13986.481950 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 15051.570967 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 15051.570967 # average WriteReq miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 11976.739247 # average WriteInvalidateReq miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 11976.739247 # average WriteInvalidateReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13922.971916 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13922.971916 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21031.044893 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21031.044893 # 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Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 442 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 323862009 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 323862009 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 78232018 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 78232018 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 71864508 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 71864508 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 191698 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 191698 # number of SoftPFReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 211446 # number of WriteInvalidateReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::total 211446 # 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number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 39400522531 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 39400522531 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 20561069776 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 20561069776 # number of WriteReq miss cycles +system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 12119187041 # number of WriteInvalidateReq miss cycles +system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 12119187041 # number of WriteInvalidateReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2308132257 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 2308132257 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4261474455 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 4261474455 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1966000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1966000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 59961592307 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 59961592307 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 59961592307 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 59961592307 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 81102062 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 81102062 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 73100357 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 73100357 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 766582 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 766582 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 680241 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::total 680241 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1874166 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1874166 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1872599 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1872599 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 154202419 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 154202419 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 154969001 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 154969001 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035388 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.035388 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.016906 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.016906 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.749932 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.749932 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.689160 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.689160 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.086146 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.086146 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106476 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106476 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026627 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.026627 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.030205 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.030205 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13728.194596 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13728.194596 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16637.202260 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 16637.202260 # average WriteReq miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 25851.783916 # average WriteInvalidateReq miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 25851.783916 # average WriteInvalidateReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14296.089593 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14296.089593 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21372.987346 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21372.987346 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14309.566044 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 14309.566044 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 12605.302976 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 12605.302976 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14603.788337 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 14603.788337 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 12810.179230 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 12810.179230 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1499,92 +1712,92 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 3397427 # number of writebacks -system.cpu1.dcache.writebacks::total 3397427 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 14736 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 14736 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 407 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 407 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 48814 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 48814 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 15143 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 15143 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 15143 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 15143 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2932101 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 2932101 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1282706 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1282706 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 571898 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 571898 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 550709 # number of WriteInvalidateReq MSHR misses -system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 550709 # number of WriteInvalidateReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 122389 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 122389 # 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number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 11612454284 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 5490664906 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 5490664906 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1373965707 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1373965707 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3521472303 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3521472303 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1037500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1037500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 51359578044 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 51359578044 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 62972032328 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 62972032328 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3972621225 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3972621225 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3807943973 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 3807943973 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 7780565198 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 7780565198 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035604 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035604 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017023 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017023 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.748766 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.748766 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.735906 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.735906 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.066484 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.066484 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100849 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100849 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026726 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026726 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030207 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.030207 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11822.914496 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11822.914496 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 13014.360756 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 13014.360756 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20305.114346 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20305.114346 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 9970.174640 # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 9970.174640 # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11226.218917 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11226.218917 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 18980.813155 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 18980.813155 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 3230902 # number of writebacks +system.cpu1.dcache.writebacks::total 3230902 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 11797 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 11797 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 280 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 280 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 42800 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 42800 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 12077 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 12077 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 12077 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 12077 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2858247 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 2858247 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1235569 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1235569 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 574884 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 574884 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 468795 # number of WriteInvalidateReq MSHR misses +system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 468795 # number of WriteInvalidateReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 118652 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 118652 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 199386 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 199386 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4093816 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4093816 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 4668700 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 4668700 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 33045194740 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 33045194740 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 18021373474 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 18021373474 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 10397149259 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 10397149259 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 11178014959 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 11178014959 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1426804491 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1426804491 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3852246545 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3852246545 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1872000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1872000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 51066568214 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 51066568214 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 61463717473 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 61463717473 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 4074474250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 4074474250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3958410750 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 3958410750 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 8032885000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 8032885000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035243 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035243 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.016902 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.016902 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.749932 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.749932 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.689160 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.689160 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.063309 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.063309 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106476 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106476 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026548 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026548 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030127 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.030127 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11561.350275 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11561.350275 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 14585.485290 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14585.485290 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18085.647294 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 18085.647294 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 23844.142875 # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 23844.142875 # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12025.119602 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12025.119602 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19320.546804 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19320.546804 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12185.511233 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12185.511233 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13155.611705 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13155.611705 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12474.075096 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12474.075096 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13165.060396 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13165.060396 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1592,59 +1805,59 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 5786522 # number of replacements -system.cpu1.icache.tags.tagsinuse 496.339295 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 442153368 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 5787034 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 76.404142 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8367526246000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.339295 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969413 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.969413 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 4937125 # number of replacements +system.cpu1.icache.tags.tagsinuse 496.391317 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 436556038 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 4937637 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 88.413960 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8378975635000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.391317 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969514 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.969514 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 339 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 108 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 239 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 901667853 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 901667853 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 442153368 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 442153368 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 442153368 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 442153368 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 442153368 # number of overall hits -system.cpu1.icache.overall_hits::total 442153368 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 5787039 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 5787039 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 5787039 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 5787039 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 5787039 # 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number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 447940407 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 447940407 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.012919 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.012919 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.012919 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.012919 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.012919 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.012919 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8649.015752 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8649.015752 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8649.015752 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8649.015752 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8649.015752 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8649.015752 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 887925002 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 887925002 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 436556038 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 436556038 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 436556038 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 436556038 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 436556038 # number of overall hits +system.cpu1.icache.overall_hits::total 436556038 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 4937642 # 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number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 441493680 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 441493680 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 441493680 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 441493680 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 441493680 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011184 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.011184 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011184 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.011184 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011184 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.011184 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10295.576387 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 10295.576387 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10295.576387 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 10295.576387 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10295.576387 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 10295.576387 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1653,384 +1866,377 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # 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Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 6824.630764 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.216571 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003566 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004009 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.046289 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.151194 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.416542 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.838171 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 8592 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 40 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 7474 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 93 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 541 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 2721 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 4842 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 395 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 15 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 20 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 810 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 3409 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2963 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 229 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.524414 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002441 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.456177 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 249010603 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 249010603 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 204488 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 158918 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 5602514 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 2695724 # 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number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 10812394931 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 25372226222 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 29755594933 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 66314319843 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8087000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 3880010250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3888097250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 3784845500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 3784845500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8087000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 7664855750 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 7672942750 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.041303 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.052181 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.099533 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.240390 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.153988 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.087836 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.087836 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.591620 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.591620 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.808666 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.808666 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.611609 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.611609 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.682408 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.682408 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.840661 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.840661 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.176371 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.176371 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.051364 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.057789 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.026944 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.237888 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.119344 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.051364 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.057789 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.026944 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.237888 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.193226 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.193226 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.041303 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.052181 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.099533 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.229620 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.158158 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.041303 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.052181 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.099533 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.229620 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.370592 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 23590.774025 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 26697.193393 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 21030.079325 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 22855.890509 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 22639.849443 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 25466.057437 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 25466.057437 # average HardPFReq mshr miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 15325.803477 # average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 15325.803477 # average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16571.950039 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16571.950039 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13824.139322 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13824.139322 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 201375 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 201375 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 27369.696466 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 27369.696466 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 23590.774025 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 26697.193393 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 21030.079325 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 23632.313965 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 23342.822566 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 23590.774025 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 26697.193393 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 21030.079325 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 23632.313965 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 25466.057437 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 24782.300723 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.222784 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 22828.151261 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 24354.897355 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22000.738481 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 22345.362493 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 22234.428550 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 46551.597527 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 46551.597527 # average HardPFReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 27079.147948 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 27079.147948 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16917.663474 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16917.663474 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13665.224287 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13665.224287 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 249333.166667 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 249333.166667 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 30989.120825 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 30989.120825 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 22828.151261 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 24354.897355 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22000.738481 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 24006.292202 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 23371.034447 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 22828.151261 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 24354.897355 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22000.738481 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 24006.292202 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 46551.597527 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 30095.390338 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -2040,65 +2246,66 @@ system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 13482596 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 10019474 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 22090 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 22090 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 3397427 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 3948207 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 669175 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 549365 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 394300 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 332875 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 429984 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 28 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 53 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1203009 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1101184 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 11574298 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 14922836 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 373561 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 511408 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 27382103 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 370370936 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 560535931 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1349320 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1724480 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 933980667 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 8332859 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 23404111 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.344949 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.475352 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 11132088 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 9059631 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 23142 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 23142 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 3230902 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 957658 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1110389 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 467130 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 407372 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 365584 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 452132 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 59 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 100 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1208854 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1057926 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 9875504 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 14402767 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 299311 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 504421 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 25082003 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 316009528 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 537745480 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1072416 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1728704 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 856556128 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 4579678 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 18388489 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 5.234421 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.423637 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 15330876 65.51% 65.51% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 8073235 34.49% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::5 14077834 76.56% 76.56% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::6 4310655 23.44% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 23404111 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 11646725084 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 18388489 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 10772824519 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 158989494 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 181931492 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 8682146940 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 7414134377 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7623277083 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7417250282 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 205120292 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 165377004 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 296049290 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 288475000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40487 # Transaction distribution -system.iobus.trans_dist::ReadResp 40487 # Transaction distribution -system.iobus.trans_dist::WriteReq 137083 # Transaction distribution -system.iobus.trans_dist::WriteResp 30163 # Transaction distribution +system.iobus.trans_dist::ReadReq 40416 # Transaction distribution +system.iobus.trans_dist::ReadResp 40416 # Transaction distribution +system.iobus.trans_dist::WriteReq 136984 # Transaction distribution +system.iobus.trans_dist::WriteResp 30064 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 106920 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48390 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48038 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -2108,18 +2315,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29756 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29704 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 123480 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231580 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231580 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 123076 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231644 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231644 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 355140 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48410 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 354800 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48058 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2129,18 +2336,18 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17674 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17645 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 156518 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7351088 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7351088 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 156137 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7351344 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7351344 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7509692 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36789000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7509567 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36527000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -2160,7 +2367,7 @@ system.iobus.reqLayer16.occupancy 12000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 22103000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 22064000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) @@ -2168,71 +2375,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 1044839337 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 1044902599 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 93320000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 93015000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 179372271 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 179432954 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115786 # number of replacements -system.iocache.tags.tagsinuse 11.223287 # Cycle average of tags in use +system.iocache.tags.replacements 115804 # number of replacements +system.iocache.tags.tagsinuse 11.285754 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115802 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115820 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9123835798000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 7.412555 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 3.810732 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.463285 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.238171 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.701455 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9175904776000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.836841 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.448912 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.239803 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.465557 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.705360 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1042467 # Number of tag accesses -system.iocache.tags.data_accesses 1042467 # Number of data accesses +system.iocache.tags.tag_accesses 1042755 # Number of tag accesses +system.iocache.tags.data_accesses 1042755 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8870 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8907 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8902 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8939 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 106920 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 106920 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8870 # number of demand (read+write) misses -system.iocache.demand_misses::total 8910 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8902 # number of demand (read+write) misses +system.iocache.demand_misses::total 8942 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8870 # number of overall misses -system.iocache.overall_misses::total 8910 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5627000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1958941092 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1964568092 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 8902 # number of overall misses +system.iocache.overall_misses::total 8942 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5707000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1942659591 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1948366591 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 357000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 357000 # number of WriteReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28897474974 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 28897474974 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5984000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1958941092 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1964925092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5984000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1958941092 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1964925092 # number of overall miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28987663054 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 28987663054 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 6064000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1942659591 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1948723591 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 6064000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1942659591 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1948723591 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8870 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8907 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8902 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8939 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 106920 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 106920 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8870 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8910 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8902 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8942 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8870 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8910 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8902 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8942 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2246,55 +2453,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 152081.081081 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 220850.179481 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 220564.510161 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 154243.243243 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 218227.318692 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 217962.478018 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 119000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 119000 # average WriteReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270271.932043 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 270271.932043 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 149600 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 220850.179481 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 220530.313356 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 149600 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 220850.179481 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 220530.313356 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 225288 # number of cycles access was blocked +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 271115.441957 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 271115.441957 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 151600 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 218227.318692 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 217929.276560 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 151600 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 218227.318692 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 217929.276560 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 228501 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27401 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27689 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.221890 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.252411 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106886 # number of writebacks -system.iocache.writebacks::total 106886 # number of writebacks +system.iocache.writebacks::writebacks 106887 # number of writebacks +system.iocache.writebacks::total 106887 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8870 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8907 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8902 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8939 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106920 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 106920 # 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number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1483600613 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3984000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1479616613 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1483600613 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -2308,567 +2515,560 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # 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average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 166211.706695 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 165913.734399 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 99600 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 166211.706695 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 165913.734399 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1310456 # number of replacements -system.l2c.tags.tagsinuse 64677.337118 # Cycle average of tags in use -system.l2c.tags.total_refs 7257968 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1373726 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 5.283418 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 5621833500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 9998.305247 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 56.991260 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 77.146603 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 791.679733 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4513.780403 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 23818.675732 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 150.211809 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 222.184258 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 784.998757 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 7219.989726 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 17043.373589 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.152562 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000870 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.001177 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.012080 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.068875 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.363444 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002292 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.003390 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.011978 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.110168 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.260061 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.986898 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 38915 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 205 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 24150 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::0 26 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 26 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 487 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 8729 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 29647 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 17 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 188 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 161 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 550 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5282 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 18136 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.593796 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.003128 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.368500 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 74054042 # Number of tag accesses -system.l2c.tags.data_accesses 74054042 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 5514 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4407 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 131001 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 549137 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 1653135 # 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number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 7299 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 8593 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 15892 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 45918 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 59655 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 105573 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 5514 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4407 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 131001 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 595055 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 1653135 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 7096 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 6374 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 146834 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 667608 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 1853450 # number of demand (read+write) hits -system.l2c.demand_hits::total 5070474 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 5514 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4407 # number of overall hits -system.l2c.overall_hits::cpu0.inst 131001 # number of overall hits -system.l2c.overall_hits::cpu0.data 595055 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 1653135 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 7096 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 6374 # number of overall hits -system.l2c.overall_hits::cpu1.inst 146834 # number of overall hits -system.l2c.overall_hits::cpu1.data 667608 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 1853450 # number of overall hits -system.l2c.overall_hits::total 5070474 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 569 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 656 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 9314 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 87213 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 698997 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 1304 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 1531 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 9213 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 99987 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 328949 # number of ReadReq misses -system.l2c.ReadReq_misses::total 1237733 # number of ReadReq misses -system.l2c.WriteInvalidateReq_misses::cpu0.data 9435 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::cpu1.data 3626 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::total 13061 # number of WriteInvalidateReq misses -system.l2c.UpgradeReq_misses::cpu0.data 30881 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 31286 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 62167 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 9976 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 9599 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 19575 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 38485 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 37338 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 75823 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 569 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 656 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 9314 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 125698 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 698997 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 1304 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 1531 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 9213 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 137325 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 328949 # number of demand (read+write) misses -system.l2c.demand_misses::total 1313556 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 569 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 656 # number of overall misses -system.l2c.overall_misses::cpu0.inst 9314 # number of overall misses -system.l2c.overall_misses::cpu0.data 125698 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 698997 # 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Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1415378 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.902022 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 9445810500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 19768.926665 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 228.224478 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 327.605712 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4403.400979 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 13076.363837 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 14280.609802 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 81.212634 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 119.963342 # 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mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.186815 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.208139 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.089341 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.206143 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.411296 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.250858 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.310833 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.349003 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.102691 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.265836 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.443410 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.186815 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.208139 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.089341 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.206143 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.411296 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.250858 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 68440.219644 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 69325.509796 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 64762.763882 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 70801.479758 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 115369.864860 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 68654.805769 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 70250.533120 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 64112.168470 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 70176.265391 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 117769.320522 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 95099.746219 # average ReadReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 22466.608046 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 20243.971628 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 21892.569988 # average WriteInvalidateReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10081.122986 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10172.643319 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10127.734904 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10094.514924 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10170.084593 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10131.367291 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 66785.676932 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 63285.951301 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 65436.965728 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 68440.219644 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 69325.509796 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 64762.763882 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 69412.984539 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 115369.864860 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 68654.805769 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 70250.533120 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 64112.168470 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 67729.415418 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 117769.320522 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 90866.823975 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 68440.219644 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 69325.509796 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 64762.763882 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 69412.984539 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 115369.864860 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 68654.805769 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 70250.533120 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 64112.168470 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 67729.415418 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 117769.320522 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 90866.823975 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -2883,58 +3083,58 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 1327465 # Transaction distribution -system.membus.trans_dist::ReadResp 1327465 # Transaction distribution -system.membus.trans_dist::WriteReq 37863 # Transaction distribution -system.membus.trans_dist::WriteResp 37863 # Transaction distribution -system.membus.trans_dist::Writeback 1017207 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 119813 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 119813 # Transaction distribution -system.membus.trans_dist::UpgradeReq 367379 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 281461 # Transaction distribution -system.membus.trans_dist::UpgradeResp 85028 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution -system.membus.trans_dist::ReadExReq 87184 # Transaction distribution -system.membus.trans_dist::ReadExResp 72708 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123480 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 841910 # Transaction distribution +system.membus.trans_dist::ReadResp 841910 # Transaction distribution +system.membus.trans_dist::WriteReq 38471 # Transaction distribution +system.membus.trans_dist::WriteResp 38471 # Transaction distribution +system.membus.trans_dist::Writeback 1161772 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 665270 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 665270 # Transaction distribution +system.membus.trans_dist::UpgradeReq 386597 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 321242 # Transaction distribution +system.membus.trans_dist::UpgradeResp 114625 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution +system.membus.trans_dist::ReadExReq 138806 # Transaction distribution +system.membus.trans_dist::ReadExResp 121371 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123076 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 22714 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4395675 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4541961 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 336541 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 336541 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4878502 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156518 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25442 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4847759 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4996369 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 336372 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 336372 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5332741 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156137 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 45428 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 143082804 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 143284954 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14125504 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14125504 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 157410458 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 581037 # Total snoops (count) -system.membus.snoop_fanout::samples 3119395 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50884 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 159245812 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 159453037 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14112640 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14112640 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 173565677 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 613627 # Total snoops (count) +system.membus.snoop_fanout::samples 3433927 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3119395 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3433927 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3119395 # Request fanout histogram -system.membus.reqLayer0.occupancy 101251489 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3433927 # Request fanout histogram +system.membus.reqLayer0.occupancy 100976496 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 55500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 19693498 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 22065500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 11963097483 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 18062213474 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 12443113804 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 9212060141 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 187409729 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 187637046 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -2978,45 +3178,45 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 7096727 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 7089473 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 37863 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 37863 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 2477309 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 127465 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 20542 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 430421 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 297353 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 727774 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 53 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 53 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 228196 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 228196 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8832957 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8435767 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 17268724 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 294458407 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 274483891 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 568942298 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1532220 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 10576474 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.010952 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.104077 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 4185645 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4178412 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38471 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38471 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 2302237 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 921111 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 814190 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 436280 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 333774 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 770054 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 100 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 100 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 280654 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 280654 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 7279651 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5709072 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 12988723 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 243910125 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 179631296 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 423541421 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1593139 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 8378399 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.013829 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.116780 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 10460641 98.90% 98.90% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 115833 1.10% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 8262536 98.62% 98.62% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 115863 1.38% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 10576474 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 15316484616 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 8378399 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 16938572035 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 7440499 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 7678500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 16737915607 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 11018810399 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 16438547163 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 9692180196 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt index e087cdc41..11eb5dd0c 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt @@ -1,138 +1,138 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.821204 # Number of seconds simulated -sim_ticks 51821203872000 # Number of ticks simulated -final_tick 51821203872000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.821157 # Number of seconds simulated +sim_ticks 51821157171000 # Number of ticks simulated +final_tick 51821157171000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 797175 # Simulator instruction rate (inst/s) -host_op_rate 936716 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 46008450754 # Simulator tick rate (ticks/s) -host_mem_usage 656028 # Number of bytes of host memory used -host_seconds 1126.34 # Real time elapsed on the host -sim_insts 897890420 # Number of instructions simulated -sim_ops 1055061464 # Number of ops (including micro ops) simulated +host_inst_rate 734878 # Simulator instruction rate (inst/s) +host_op_rate 863519 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 42416153440 # Simulator tick rate (ticks/s) +host_mem_usage 712380 # Number of bytes of host memory used +host_seconds 1221.73 # Real time elapsed on the host +sim_insts 897823750 # Number of instructions simulated +sim_ops 1054987960 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 274944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 280896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 5219828 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 52654408 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 402752 # Number of bytes read from this memory -system.physmem.bytes_read::total 58832828 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5219828 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5219828 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 79485888 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 267456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 270528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 5250612 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 52674824 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 383808 # Number of bytes read from this memory +system.physmem.bytes_read::total 58847228 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5250612 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5250612 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 79637568 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 79506468 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 4296 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 4389 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 121967 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 822738 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6293 # Number of read requests responded to by this memory -system.physmem.num_reads::total 959683 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1241967 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 79658148 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 4179 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 4227 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 122448 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 823057 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 5997 # Number of read requests responded to by this memory +system.physmem.num_reads::total 959908 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1244337 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1244540 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 5306 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 5420 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 100728 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1016078 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 7772 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1135304 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 100728 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 100728 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1533849 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1246910 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 5161 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 5220 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 101322 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1016473 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 7406 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1135583 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 101322 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 101322 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1536777 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 397 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1534246 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1533849 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 5306 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 5420 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 100728 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1016476 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 7772 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2669550 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 959683 # Number of read requests accepted -system.physmem.writeReqs 1860672 # Number of write requests accepted -system.physmem.readBursts 959683 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1860672 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 61376064 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 43648 # Total number of bytes read from write queue -system.physmem.bytesWritten 118595648 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 58832828 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 118938916 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 682 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 7593 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 36288 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 56975 # Per bank write bursts -system.physmem.perBankRdBursts::1 58359 # Per bank write bursts -system.physmem.perBankRdBursts::2 58716 # Per bank write bursts -system.physmem.perBankRdBursts::3 57264 # Per bank write bursts -system.physmem.perBankRdBursts::4 61545 # Per bank write bursts -system.physmem.perBankRdBursts::5 66145 # Per bank write bursts -system.physmem.perBankRdBursts::6 57228 # Per bank write bursts -system.physmem.perBankRdBursts::7 52937 # Per bank write bursts -system.physmem.perBankRdBursts::8 52189 # Per bank write bursts -system.physmem.perBankRdBursts::9 99547 # Per bank write bursts -system.physmem.perBankRdBursts::10 57680 # Per bank write bursts -system.physmem.perBankRdBursts::11 61393 # Per bank write bursts -system.physmem.perBankRdBursts::12 54506 # Per bank write bursts -system.physmem.perBankRdBursts::13 60286 # Per bank write bursts -system.physmem.perBankRdBursts::14 51564 # Per bank write bursts -system.physmem.perBankRdBursts::15 52667 # Per bank write bursts -system.physmem.perBankWrBursts::0 114739 # Per bank write bursts -system.physmem.perBankWrBursts::1 115397 # Per bank write bursts -system.physmem.perBankWrBursts::2 117633 # Per bank write bursts -system.physmem.perBankWrBursts::3 119136 # Per bank write bursts -system.physmem.perBankWrBursts::4 120318 # Per bank write bursts -system.physmem.perBankWrBursts::5 121968 # Per bank write bursts -system.physmem.perBankWrBursts::6 116613 # Per bank write bursts -system.physmem.perBankWrBursts::7 113695 # Per bank write bursts -system.physmem.perBankWrBursts::8 109286 # Per bank write bursts -system.physmem.perBankWrBursts::9 116370 # Per bank write bursts -system.physmem.perBankWrBursts::10 115629 # Per bank write bursts -system.physmem.perBankWrBursts::11 118249 # Per bank write bursts -system.physmem.perBankWrBursts::12 111968 # Per bank write bursts -system.physmem.perBankWrBursts::13 117797 # Per bank write bursts -system.physmem.perBankWrBursts::14 110347 # Per bank write bursts -system.physmem.perBankWrBursts::15 113912 # Per bank write bursts +system.physmem.bw_write::total 1537174 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1536777 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 5161 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 5220 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 101322 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1016870 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 7406 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2672757 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 959908 # Number of read requests accepted +system.physmem.writeReqs 1865455 # Number of write requests accepted +system.physmem.readBursts 959908 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1865455 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 61382336 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 51776 # Total number of bytes read from write queue +system.physmem.bytesWritten 118954432 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 58847228 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 119245028 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 809 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 6774 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 36275 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 56974 # Per bank write bursts +system.physmem.perBankRdBursts::1 60608 # Per bank write bursts +system.physmem.perBankRdBursts::2 56247 # Per bank write bursts +system.physmem.perBankRdBursts::3 58787 # Per bank write bursts +system.physmem.perBankRdBursts::4 55621 # Per bank write bursts +system.physmem.perBankRdBursts::5 61105 # Per bank write bursts +system.physmem.perBankRdBursts::6 53454 # Per bank write bursts +system.physmem.perBankRdBursts::7 55202 # Per bank write bursts +system.physmem.perBankRdBursts::8 54549 # Per bank write bursts +system.physmem.perBankRdBursts::9 101006 # Per bank write bursts +system.physmem.perBankRdBursts::10 57136 # Per bank write bursts +system.physmem.perBankRdBursts::11 59250 # Per bank write bursts +system.physmem.perBankRdBursts::12 54470 # Per bank write bursts +system.physmem.perBankRdBursts::13 61564 # Per bank write bursts +system.physmem.perBankRdBursts::14 57688 # Per bank write bursts +system.physmem.perBankRdBursts::15 55438 # Per bank write bursts +system.physmem.perBankWrBursts::0 113578 # Per bank write bursts +system.physmem.perBankWrBursts::1 118177 # Per bank write bursts +system.physmem.perBankWrBursts::2 119014 # Per bank write bursts +system.physmem.perBankWrBursts::3 122732 # Per bank write bursts +system.physmem.perBankWrBursts::4 115108 # Per bank write bursts +system.physmem.perBankWrBursts::5 118421 # Per bank write bursts +system.physmem.perBankWrBursts::6 110433 # Per bank write bursts +system.physmem.perBankWrBursts::7 110649 # Per bank write bursts +system.physmem.perBankWrBursts::8 111009 # Per bank write bursts +system.physmem.perBankWrBursts::9 115530 # Per bank write bursts +system.physmem.perBankWrBursts::10 116272 # Per bank write bursts +system.physmem.perBankWrBursts::11 116171 # Per bank write bursts +system.physmem.perBankWrBursts::12 116950 # Per bank write bursts +system.physmem.perBankWrBursts::13 121923 # Per bank write bursts +system.physmem.perBankWrBursts::14 117171 # Per bank write bursts +system.physmem.perBankWrBursts::15 115525 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 1 # Number of times write queue was full causing retry -system.physmem.totGap 51821201316000 # Total gap between requests +system.physmem.totGap 51821154615000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43101 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 916567 # Read request sizes (log2) +system.physmem.readPktSize::6 916792 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1599 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 925 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 811 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 637 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 502 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 379 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 307 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 269 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 242 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 1 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 617611 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 291.399266 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 166.446996 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 330.841680 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 256797 41.58% 41.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 151085 24.46% 66.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 51876 8.40% 74.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 29038 4.70% 79.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 19766 3.20% 82.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 13229 2.14% 84.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 10059 1.63% 86.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 9064 1.47% 87.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 76697 12.42% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 617611 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 92036 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 10.419705 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 106.178395 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 92034 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 618930 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 291.368084 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 166.608476 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 330.498173 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 256436 41.43% 41.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 152224 24.59% 66.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 51996 8.40% 74.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 28892 4.67% 79.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 20098 3.25% 82.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 13547 2.19% 84.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 10018 1.62% 86.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 9306 1.50% 87.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 76413 12.35% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 618930 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 92468 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 10.372118 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 105.903641 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 92466 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 92036 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 92036 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.134045 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.130429 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 10.695121 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 84651 91.98% 91.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 3801 4.13% 96.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 1276 1.39% 97.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 446 0.48% 97.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 607 0.66% 98.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 136 0.15% 98.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 198 0.22% 99.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 105 0.11% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 166 0.18% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 53 0.06% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 197 0.21% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 35 0.04% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 54 0.06% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 56 0.06% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 137 0.15% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 24 0.03% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 33 0.04% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 9 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 16 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 5 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 6 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 4 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 8 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-255 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-279 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 92036 # Writes before turning the bus around for reads -system.physmem.totQLat 12714966775 # Total ticks spent queuing -system.physmem.totMemAccLat 30696235525 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4795005000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13258.55 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 92468 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 92468 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.100608 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.118632 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 10.444453 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 55053 59.54% 59.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 30512 33.00% 92.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 2134 2.31% 94.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 1149 1.24% 96.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 862 0.93% 97.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 455 0.49% 97.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 271 0.29% 97.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 154 0.17% 97.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 523 0.57% 98.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 85 0.09% 98.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 63 0.07% 98.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 90 0.10% 98.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 138 0.15% 98.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 53 0.06% 99.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 45 0.05% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 77 0.08% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 126 0.14% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 47 0.05% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 24 0.03% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 42 0.05% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 157 0.17% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 6 0.01% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 21 0.02% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 16 0.02% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 59 0.06% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 9 0.01% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 28 0.03% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 35 0.04% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 128 0.14% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 15 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 2 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 6 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 16 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 15 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 3 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 7 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 10 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 3 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 3 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 5 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 4 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::212-215 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-219 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-251 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 92468 # Writes before turning the bus around for reads +system.physmem.totQLat 12424177254 # Total ticks spent queuing +system.physmem.totMemAccLat 30407283504 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4795495000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12954.01 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32008.55 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 31704.01 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.18 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.29 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 2.30 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.14 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.30 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s @@ -280,36 +300,41 @@ system.physmem.busUtil 0.03 # Da system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.23 # Average write queue length when enqueuing -system.physmem.readRowHits 722338 # Number of row buffer hits during reads -system.physmem.writeRowHits 1472108 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.32 # Row buffer hit rate for reads +system.physmem.avgWrQLen 24.29 # Average write queue length when enqueuing +system.physmem.readRowHits 722238 # Number of row buffer hits during reads +system.physmem.writeRowHits 1476593 # Number of row buffer hits during writes +system.physmem.readRowHitRate 75.30 # Row buffer hit rate for reads system.physmem.writeRowHitRate 79.44 # Row buffer hit rate for writes -system.physmem.avgGap 18373999.48 # Average gap between requests -system.physmem.pageHitRate 78.04 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 49686658091000 # Time in different power states -system.physmem.memoryStateTime::REF 1730423760000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 404121645500 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 2414648880 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 2254490280 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 1317516750 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 1230128625 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 3659518200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 3820650600 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 6087953520 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 5919855840 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 3384708874560 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 3384708874560 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 1312804436175 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 1305168623550 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 29941137312000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 29947835393250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 34652130260085 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 34650938016705 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.686370 # Core power per rank (mW) -system.physmem.averagePower::1 668.663363 # Core power per rank (mW) +system.physmem.avgGap 18341414.75 # Average gap between requests +system.physmem.pageHitRate 78.03 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2336584320 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1274922000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3572345400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 6014165760 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3384705823200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1308692927565 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29944715868000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34651312636245 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.671195 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49815023694250 # Time in different power states +system.physmem_0.memoryStateTime::REF 1730422200000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 275710901250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 2342526480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1278164250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3908587800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 6029970480 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3384705823200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1310912306640 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29942769044250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34651946423100 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.683425 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49811721549250 # Time in different power states +system.physmem_1.memoryStateTime::REF 1730422200000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 279009798250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory @@ -333,6 +358,14 @@ system.cf0.dma_write_full_pages 1666 # Nu system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -354,27 +387,81 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 215397 # Table walker walks requested +system.cpu.dtb.walker.walksLong 215397 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 16603 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 166513 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 14 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 215383 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 0.157858 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 54.935133 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-2047 215381 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::10240-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::22528-24575 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 215383 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 183130 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 21825.061432 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 17519.574906 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 14463.524428 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-32767 181175 98.93% 98.93% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::32768-65535 4 0.00% 98.93% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-98303 1496 0.82% 99.75% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::98304-131071 183 0.10% 99.85% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-163839 74 0.04% 99.89% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::163840-196607 58 0.03% 99.92% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-229375 49 0.03% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::229376-262143 36 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-294911 18 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::294912-327679 14 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-360447 8 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::360448-393215 11 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-491519 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 183130 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 800972760 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 2.488036 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 -1191876296 -148.80% -148.80% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::1 1992849056 248.80% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 800972760 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 166514 90.93% 90.93% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 16603 9.07% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 183117 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 215397 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 215397 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 183117 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 183117 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 398514 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 168646043 # DTB read hits -system.cpu.dtb.read_misses 158497 # DTB read misses -system.cpu.dtb.write_hits 153371607 # DTB write hits -system.cpu.dtb.write_misses 56347 # DTB write misses +system.cpu.dtb.read_hits 168647599 # DTB read hits +system.cpu.dtb.read_misses 158984 # DTB read misses +system.cpu.dtb.write_hits 153347297 # DTB write hits +system.cpu.dtb.write_misses 56413 # DTB write misses system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 43049 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_mva_asid 43021 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 74830 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 74349 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 7977 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 8039 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 19966 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 168804540 # DTB read accesses -system.cpu.dtb.write_accesses 153427954 # DTB write accesses +system.cpu.dtb.perms_faults 19949 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 168806583 # DTB read accesses +system.cpu.dtb.write_accesses 153403710 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 322017650 # DTB hits -system.cpu.dtb.misses 214844 # DTB misses -system.cpu.dtb.accesses 322232494 # DTB accesses +system.cpu.dtb.hits 321994896 # DTB hits +system.cpu.dtb.misses 215397 # DTB misses +system.cpu.dtb.accesses 322210293 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -396,56 +483,91 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 898442559 # ITB inst hits -system.cpu.itb.inst_misses 123457 # ITB inst misses +system.cpu.itb.walker.walks 123370 # Table walker walks requested +system.cpu.itb.walker.walksLong 123370 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1120 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 111048 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 123370 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 123370 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 123370 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 112168 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 24898.509379 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 20785.013360 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 17155.421945 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 109848 97.93% 97.93% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 2031 1.81% 99.74% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 132 0.12% 99.86% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 101 0.09% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 23 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 19 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 7 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::458752-524287 5 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 112168 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples -1257598296 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 -1257598296 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total -1257598296 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 111048 99.00% 99.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1120 1.00% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 112168 # Table walker page sizes translated +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 123370 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 123370 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 112168 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 112168 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 235538 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 898375907 # ITB inst hits +system.cpu.itb.inst_misses 123370 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 43049 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_mva_asid 43021 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 53017 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 52826 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 898566016 # ITB inst accesses -system.cpu.itb.hits 898442559 # DTB hits -system.cpu.itb.misses 123457 # DTB misses -system.cpu.itb.accesses 898566016 # DTB accesses -system.cpu.numCycles 103642407744 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 898499277 # ITB inst accesses +system.cpu.itb.hits 898375907 # DTB hits +system.cpu.itb.misses 123370 # DTB misses +system.cpu.itb.accesses 898499277 # DTB accesses +system.cpu.numCycles 103642314342 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 897890420 # Number of instructions committed -system.cpu.committedOps 1055061464 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 968615704 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 900077 # Number of float alu accesses -system.cpu.num_func_calls 53165114 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 137212632 # number of instructions that are conditional controls -system.cpu.num_int_insts 968615704 # number of integer instructions -system.cpu.num_fp_insts 900077 # number of float instructions -system.cpu.num_int_register_reads 1413530400 # number of times the integer registers were read -system.cpu.num_int_register_writes 768471074 # number of times the integer registers were written -system.cpu.num_fp_register_reads 1450010 # number of times the floating registers were read -system.cpu.num_fp_register_writes 764580 # number of times the floating registers were written -system.cpu.num_cc_register_reads 236283447 # number of times the CC registers were read -system.cpu.num_cc_register_writes 235682818 # number of times the CC registers were written -system.cpu.num_mem_refs 322001322 # number of memory refs -system.cpu.num_load_insts 168639088 # Number of load instructions -system.cpu.num_store_insts 153362234 # Number of store instructions -system.cpu.num_idle_cycles 100472196154.122070 # Number of idle cycles -system.cpu.num_busy_cycles 3170211589.877939 # Number of busy cycles -system.cpu.not_idle_fraction 0.030588 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.969412 # Percentage of idle cycles -system.cpu.Branches 200577010 # Number of branches fetched +system.cpu.committedInsts 897823750 # Number of instructions committed +system.cpu.committedOps 1054987960 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 968534129 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 900653 # Number of float alu accesses +system.cpu.num_func_calls 53156799 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 137185420 # number of instructions that are conditional controls +system.cpu.num_int_insts 968534129 # number of integer instructions +system.cpu.num_fp_insts 900653 # number of float instructions +system.cpu.num_int_register_reads 1413400107 # number of times the integer registers were read +system.cpu.num_int_register_writes 768429309 # number of times the integer registers were written +system.cpu.num_fp_register_reads 1451290 # number of times the floating registers were read +system.cpu.num_fp_register_writes 764324 # number of times the floating registers were written +system.cpu.num_cc_register_reads 236274909 # number of times the CC registers were read +system.cpu.num_cc_register_writes 235673566 # number of times the CC registers were written +system.cpu.num_mem_refs 321978685 # number of memory refs +system.cpu.num_load_insts 168640749 # Number of load instructions +system.cpu.num_store_insts 153337936 # Number of store instructions +system.cpu.num_idle_cycles 100474351324.032059 # Number of idle cycles +system.cpu.num_busy_cycles 3167963017.967939 # Number of busy cycles +system.cpu.not_idle_fraction 0.030566 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.969434 # Percentage of idle cycles +system.cpu.Branches 200551202 # Number of branches fetched system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 731218910 69.27% 69.27% # Class of executed instruction -system.cpu.op_class::IntMult 2226806 0.21% 69.48% # Class of executed instruction -system.cpu.op_class::IntDiv 99223 0.01% 69.49% # Class of executed instruction +system.cpu.op_class::IntAlu 731167173 69.27% 69.27% # Class of executed instruction +system.cpu.op_class::IntMult 2227672 0.21% 69.48% # Class of executed instruction +system.cpu.op_class::IntDiv 99245 0.01% 69.49% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 69.49% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 69.49% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 69.49% # Class of executed instruction @@ -472,122 +594,122 @@ system.cpu.op_class::SimdFloatMisc 110423 0.01% 69.50% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 69.50% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.50% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.50% # Class of executed instruction -system.cpu.op_class::MemRead 168639088 15.97% 85.47% # Class of executed instruction -system.cpu.op_class::MemWrite 153362234 14.53% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 168640749 15.98% 85.47% # Class of executed instruction +system.cpu.op_class::MemWrite 153337936 14.53% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1055656727 # Class of executed instruction +system.cpu.op_class::total 1055583241 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 16365 # number of quiesce instructions executed -system.cpu.dcache.tags.replacements 10282368 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.969706 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 311548704 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 10282880 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 30.297806 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 10281150 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.969700 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 311526777 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 10281662 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 30.299263 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 3093156250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.969706 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.969700 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999941 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999941 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 410 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 401 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 64 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1298012717 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1298012717 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 157556193 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 157556193 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 145511723 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 145511723 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 396994 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 396994 # number of SoftPFReq hits -system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 336687 # number of WriteInvalidateReq hits -system.cpu.dcache.WriteInvalidateReq_hits::total 336687 # number of WriteInvalidateReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3698345 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3698345 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 4003149 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 4003149 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 303067916 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 303067916 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 303464910 # number of overall hits -system.cpu.dcache.overall_hits::total 303464910 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 5344087 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 5344087 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2236666 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2236666 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1310162 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1310162 # number of SoftPFReq misses -system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1231947 # number of WriteInvalidateReq misses -system.cpu.dcache.WriteInvalidateReq_misses::total 1231947 # number of WriteInvalidateReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 306495 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 306495 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 4 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 7580753 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7580753 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 8890915 # number of overall misses -system.cpu.dcache.overall_misses::total 8890915 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 83712196260 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 83712196260 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 64378240535 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 64378240535 # number of WriteReq miss cycles -system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data 27514486506 # number of WriteInvalidateReq miss cycles -system.cpu.dcache.WriteInvalidateReq_miss_latency::total 27514486506 # number of WriteInvalidateReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4474608500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 4474608500 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 251501 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 251501 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 148090436795 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 148090436795 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 148090436795 # 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miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.024405 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.024405 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.028466 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.028466 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15647.890284 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15647.890284 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28672.667077 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 28672.667077 # average WriteReq miss latency +system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 22370.821070 # average WriteInvalidateReq miss latency +system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 22370.821070 # average WriteInvalidateReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14559.235651 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14559.235651 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 75000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 75000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19493.969413 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19493.969413 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16621.748543 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16621.748543 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -596,88 +718,88 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 7918344 # number of writebacks -system.cpu.dcache.writebacks::total 7918344 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7198 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 7198 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 21104 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 21104 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 70788 # 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number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 243499 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 131595257705 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 131595257705 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 151068392205 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 151068392205 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5727938750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5727938750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5573388000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5573388000 # 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average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26688.386385 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26688.386385 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14883.018206 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14883.018206 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 20334.147893 # average WriteInvalidateReq mshr miss latency -system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 20334.147893 # average WriteInvalidateReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12313.246955 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12313.246955 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 60874.750000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 60874.750000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17424.178946 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17424.178946 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17048.946040 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17048.946040 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 7913457 # number of writebacks +system.cpu.dcache.writebacks::total 7913457 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7211 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 7211 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 21165 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 21165 # 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number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 72364530247 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 58930269477 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 58930269477 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 19541293498 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 19541293498 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 25112944493 # number of WriteInvalidateReq MSHR miss cycles +system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 25112944493 # number of WriteInvalidateReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 2872283000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 2872283000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 146000 # 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Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 254 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 193 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 912299374 # Number of tag accesses -system.cpu.icache.tags.data_accesses 912299374 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 884585744 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 884585744 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 884585744 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 884585744 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 884585744 # number of overall hits -system.cpu.icache.overall_hits::total 884585744 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 13856815 # 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mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.042136 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.017717 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.415226 # mshr miss rate for WriteInvalidateReq accesses +system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.415226 # mshr miss rate for WriteInvalidateReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.780981 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.780981 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.246582 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.246582 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.011216 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.017188 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005692 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.091032 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.038711 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.011216 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.017188 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005692 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.091032 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.038711 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 65814.594972 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 66260.822511 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62136.636697 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63764.581031 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63475.943573 # average ReadReq mshr miss latency -system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 21568.658213 # average WriteInvalidateReq mshr miss latency -system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 21568.658213 # average WriteInvalidateReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10005.590282 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10005.590282 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 47500.250000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 47500.250000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61617.263057 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61617.263057 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 65814.594972 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 66260.822511 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62136.636697 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62370.072593 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62384.840746 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 65814.594972 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 66260.822511 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62136.636697 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62370.072593 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62384.840746 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.246111 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.246111 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.010861 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.016551 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005754 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.091088 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.038840 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.010861 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.016551 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005754 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.091088 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.038840 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 65693.527160 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 66687.544358 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61986.826021 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63479.273949 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63225.991053 # average ReadReq mshr miss latency +system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 21565.936570 # average WriteInvalidateReq mshr miss latency +system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 21565.936570 # average WriteInvalidateReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.708273 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.708273 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 60000 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 60000 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61281.495461 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61281.495461 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 65693.527160 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 66687.544358 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61986.826021 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62054.166126 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62086.457372 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 65693.527160 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 66687.544358 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61986.826021 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62054.166126 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62086.457372 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1067,58 +1189,58 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 21819690 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 21811671 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 21752331 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 21744344 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33872 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 33872 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 7918344 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1338611 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1231947 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 45612 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 4 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 45616 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2169953 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2169953 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 27799880 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 28711563 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 624328 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1010117 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 58145888 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 887008660 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1165125804 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2042816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3064096 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2057241376 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 474114 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 33215302 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.003479 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.058876 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::Writeback 7913457 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1339455 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1232790 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 45725 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 45727 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2171658 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2171658 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 27670608 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 28704497 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 624113 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1013195 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 58012413 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 882871956 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1164737260 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2043192 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3078296 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2052730704 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 473368 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 33145716 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.003486 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.058938 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 33099762 99.65% 99.65% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 115540 0.35% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 33030174 99.65% 99.65% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 115542 0.35% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 33215302 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 25772593750 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 33145716 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 25733748000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1282500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1332000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 20852498735 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 20755677476 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14430330552 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14427270036 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 369475750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 369197500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 627605250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 628893000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40402 # Transaction distribution -system.iobus.trans_dist::ReadResp 40402 # Transaction distribution +system.iobus.trans_dist::ReadReq 40403 # Transaction distribution +system.iobus.trans_dist::ReadResp 40403 # Transaction distribution system.iobus.trans_dist::WriteReq 136733 # Transaction distribution system.iobus.trans_dist::WriteResp 30069 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution @@ -1138,11 +1260,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231000 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231000 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231002 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231002 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354270 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 354272 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1159,11 +1281,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334432 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334432 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334440 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334440 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492838 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 7492846 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) @@ -1192,71 +1314,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 1042392405 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 1042395169 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 179042528 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 179037771 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115480 # number of replacements -system.iocache.tags.tagsinuse 10.457351 # Cycle average of tags in use +system.iocache.tags.replacements 115482 # number of replacements +system.iocache.tags.tagsinuse 10.457347 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115496 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115498 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13153949219000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.511147 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.946204 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.219447 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.434138 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13153920852000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.510781 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.946566 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.219424 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.434160 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.653584 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039857 # Number of tag accesses -system.iocache.tags.data_accesses 1039857 # Number of data accesses +system.iocache.tags.tag_accesses 1039866 # Number of tag accesses +system.iocache.tags.data_accesses 1039866 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8836 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8873 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8837 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8874 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8836 # number of demand (read+write) misses -system.iocache.demand_misses::total 8876 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8837 # number of demand (read+write) misses +system.iocache.demand_misses::total 8877 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8836 # number of overall misses -system.iocache.overall_misses::total 8876 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5485000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1916450860 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1921935860 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 8837 # number of overall misses +system.iocache.overall_misses::total 8877 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5479000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1901914612 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1907393612 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 339000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 339000 # number of WriteReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28823836017 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 28823836017 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5824000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1916450860 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1922274860 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5824000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1916450860 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1922274860 # number of overall miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28843036786 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 28843036786 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5818000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1901914612 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1907732612 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5818000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1901914612 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1907732612 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8836 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8873 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8837 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8874 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8836 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8876 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8837 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8877 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8836 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8876 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8837 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8877 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1270,55 +1392,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 148243.243243 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 216891.224536 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 216604.965626 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 148081.081081 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 215221.750820 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 214941.808880 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 113000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 113000 # average WriteReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270230.218415 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 270230.218415 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 145600 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 216891.224536 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 216569.948175 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 145600 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 216891.224536 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 216569.948175 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 223291 # number of cycles access was blocked +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270410.230125 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 270410.230125 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 145450 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 215221.750820 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 214907.357441 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 145450 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 215221.750820 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 214907.357441 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 223600 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27458 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27526 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.132093 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.123229 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106629 # number of writebacks -system.iocache.writebacks::total 106629 # number of writebacks +system.iocache.writebacks::writebacks 106630 # number of writebacks +system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8836 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8873 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8837 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8874 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106664 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 106664 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8836 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8876 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8837 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8877 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8836 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8876 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3561000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1456881862 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1460442862 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8837 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8877 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3555000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1442304112 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1445859112 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 183000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 183000 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23277254071 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23277254071 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3744000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1456881862 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1460625862 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3744000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1456881862 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1460625862 # number of overall MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23296466828 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23296466828 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3738000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1442304112 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1446042112 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3738000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1442304112 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1446042112 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1332,71 +1454,71 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 96243.243243 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 164880.246944 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 164594.033810 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 96081.081081 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 163211.962431 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 162932.061303 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 61000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218229.712658 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218229.712658 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 93600 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 164880.246944 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 164559.020054 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 93600 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 164880.246944 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 164559.020054 # average overall mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218409.836758 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218409.836758 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 93450 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 163211.962431 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 162897.613158 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 93450 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 163211.962431 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 162897.613158 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 462201 # Transaction distribution -system.membus.trans_dist::ReadResp 462201 # Transaction distribution +system.membus.trans_dist::ReadReq 463332 # Transaction distribution +system.membus.trans_dist::ReadResp 463332 # Transaction distribution system.membus.trans_dist::WriteReq 33872 # Transaction distribution system.membus.trans_dist::WriteResp 33872 # Transaction distribution -system.membus.trans_dist::Writeback 1241967 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 616132 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 616132 # Transaction distribution -system.membus.trans_dist::UpgradeReq 36293 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 4 # Transaction distribution -system.membus.trans_dist::UpgradeResp 36297 # Transaction distribution -system.membus.trans_dist::ReadExReq 534513 # Transaction distribution -system.membus.trans_dist::ReadExResp 534513 # Transaction distribution +system.membus.trans_dist::Writeback 1244337 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 618545 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 618545 # Transaction distribution +system.membus.trans_dist::UpgradeReq 36281 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 36283 # Transaction distribution +system.membus.trans_dist::ReadExReq 533903 # Transaction distribution +system.membus.trans_dist::ReadExResp 533903 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 123190 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6942 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4139437 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4269627 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335126 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 335126 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4604753 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4147646 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4277836 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 334832 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 334832 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4612668 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 156320 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13884 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 163718240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 163888576 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14053504 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14053504 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 177942080 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3244 # Total snoops (count) -system.membus.snoop_fanout::samples 2814199 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 164057632 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 164227968 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14034624 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14034624 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 178262592 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3539 # Total snoops (count) +system.membus.snoop_fanout::samples 2819489 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2814199 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2819489 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2814199 # Request fanout histogram -system.membus.reqLayer0.occupancy 106092500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2819489 # Request fanout histogram +system.membus.reqLayer0.occupancy 106085000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 31000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5680000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5679999 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 17856822743 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 17900056737 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 9254301682 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 9260714451 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 186599472 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 186597229 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt index 72bc2e01a..5213927ce 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 51.111151 # Nu sim_ticks 51111150553500 # Number of ticks simulated final_tick 51111150553500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1088550 # Simulator instruction rate (inst/s) -host_op_rate 1279225 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56496360239 # Simulator tick rate (ticks/s) -host_mem_usage 672572 # Number of bytes of host memory used -host_seconds 904.68 # Real time elapsed on the host +host_inst_rate 1151312 # Simulator instruction rate (inst/s) +host_op_rate 1352981 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59753764865 # Simulator tick rate (ticks/s) +host_mem_usage 728116 # Number of bytes of host memory used +host_seconds 855.36 # Real time elapsed on the host sim_insts 984789519 # Number of instructions simulated sim_ops 1157289961 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -92,6 +92,14 @@ system.cf0.dma_write_full_pages 1666 # Nu system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -113,6 +121,24 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.walker.walks 144982 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 144982 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 144982 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 144982 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 144982 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 108340 85.69% 85.69% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 18088 14.31% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 126428 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 144982 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 144982 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 126428 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 126428 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 271410 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses system.cpu0.dtb.read_hits 91965302 # DTB read hits @@ -134,6 +160,14 @@ system.cpu0.dtb.inst_accesses 0 # IT system.cpu0.dtb.hits 176331252 # DTB hits system.cpu0.dtb.misses 144982 # DTB misses system.cpu0.dtb.accesses 176476234 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -155,6 +189,24 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.itb.walker.walks 70785 # Table walker walks requested +system.cpu0.itb.walker.walksLong 70785 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walkWaitTime::samples 70785 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 70785 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 70785 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 62159 96.07% 96.07% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 2545 3.93% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 64704 # Table walker page sizes translated +system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 70785 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 70785 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 64704 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 64704 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 135489 # Table walker requests started/completed, data/inst system.cpu0.itb.inst_hits 493804573 # ITB inst hits system.cpu0.itb.inst_misses 70785 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits @@ -424,6 +476,14 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -445,6 +505,24 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.walker.walks 143312 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 143312 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walkWaitTime::samples 143312 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 143312 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 143312 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walksPending::samples 1000001000 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1000001000 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 1000001000 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 106567 85.62% 85.62% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 17903 14.38% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 124470 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 143312 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 143312 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 124470 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 124470 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 267782 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses system.cpu1.dtb.read_hits 92072581 # DTB read hits @@ -466,6 +544,14 @@ system.cpu1.dtb.inst_accesses 0 # IT system.cpu1.dtb.hits 175979862 # DTB hits system.cpu1.dtb.misses 143312 # DTB misses system.cpu1.dtb.accesses 176123174 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -487,6 +573,24 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.itb.walker.walks 69790 # Table walker walks requested +system.cpu1.itb.walker.walksLong 69790 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walkWaitTime::samples 69790 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 69790 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 69790 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 61179 95.99% 95.99% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 2554 4.01% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 63733 # Table walker page sizes translated +system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 69790 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 69790 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 63733 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 63733 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 133523 # Table walker requests started/completed, data/inst system.cpu1.itb.inst_hits 491448225 # ITB inst hits system.cpu1.itb.inst_misses 69790 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index e0cd774db..806ccbd13 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.196466 # Number of seconds simulated -sim_ticks 5196466347000 # Number of ticks simulated -final_tick 5196466347000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.192453 # Number of seconds simulated +sim_ticks 5192452884000 # Number of ticks simulated +final_tick 5192452884000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 596082 # Simulator instruction rate (inst/s) -host_op_rate 1149061 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 24120553188 # Simulator tick rate (ticks/s) -host_mem_usage 596696 # Number of bytes of host memory used -host_seconds 215.44 # Real time elapsed on the host -sim_insts 128418244 # Number of instructions simulated -sim_ops 247550593 # Number of ops (including micro ops) simulated +host_inst_rate 836744 # Simulator instruction rate (inst/s) +host_op_rate 1613002 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 33830425760 # Simulator tick rate (ticks/s) +host_mem_usage 654168 # Number of bytes of host memory used +host_seconds 153.48 # Real time elapsed on the host +sim_insts 128427413 # Number of instructions simulated +sim_ops 247571076 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 828416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9035072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 827456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9039104 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::total 9892224 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 828416 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 828416 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8113920 # Number of bytes written to this memory -system.physmem.bytes_written::total 8113920 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 9895360 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 827456 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 827456 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8137984 # Number of bytes written to this memory +system.physmem.bytes_written::total 8137984 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 2 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12944 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141173 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12929 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141236 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 154566 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 126780 # Number of write requests responded to by this memory -system.physmem.num_writes::total 126780 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 12 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 154615 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 127156 # Number of write requests responded to by this memory +system.physmem.num_writes::total 127156 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 25 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 159419 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1738695 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::pc.south_bridge.ide 5456 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1903644 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 159419 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 159419 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1561430 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1561430 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1561430 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 12 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 159357 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1740816 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::pc.south_bridge.ide 5460 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1905720 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 159357 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 159357 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1567272 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1567272 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1567272 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 25 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 159419 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1738695 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 5456 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3465075 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 154566 # Number of read requests accepted -system.physmem.writeReqs 173500 # Number of write requests accepted -system.physmem.readBursts 154566 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 173500 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9886080 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6144 # Total number of bytes read from write queue -system.physmem.bytesWritten 10951744 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9892224 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 11104000 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 96 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2352 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 1595 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9833 # Per bank write bursts -system.physmem.perBankRdBursts::1 9504 # Per bank write bursts -system.physmem.perBankRdBursts::2 9844 # Per bank write bursts -system.physmem.perBankRdBursts::3 9497 # Per bank write bursts -system.physmem.perBankRdBursts::4 9570 # Per bank write bursts -system.physmem.perBankRdBursts::5 9679 # Per bank write bursts -system.physmem.perBankRdBursts::6 9540 # Per bank write bursts -system.physmem.perBankRdBursts::7 9680 # Per bank write bursts -system.physmem.perBankRdBursts::8 9214 # Per bank write bursts -system.physmem.perBankRdBursts::9 9453 # Per bank write bursts -system.physmem.perBankRdBursts::10 9241 # Per bank write bursts -system.physmem.perBankRdBursts::11 9575 # Per bank write bursts -system.physmem.perBankRdBursts::12 9600 # Per bank write bursts -system.physmem.perBankRdBursts::13 10182 # Per bank write bursts -system.physmem.perBankRdBursts::14 10246 # Per bank write bursts -system.physmem.perBankRdBursts::15 9812 # Per bank write bursts -system.physmem.perBankWrBursts::0 10679 # Per bank write bursts -system.physmem.perBankWrBursts::1 10594 # Per bank write bursts -system.physmem.perBankWrBursts::2 10884 # Per bank write bursts -system.physmem.perBankWrBursts::3 10241 # Per bank write bursts -system.physmem.perBankWrBursts::4 10237 # Per bank write bursts -system.physmem.perBankWrBursts::5 10759 # Per bank write bursts -system.physmem.perBankWrBursts::6 10579 # Per bank write bursts -system.physmem.perBankWrBursts::7 10814 # Per bank write bursts -system.physmem.perBankWrBursts::8 10762 # Per bank write bursts -system.physmem.perBankWrBursts::9 11220 # Per bank write bursts -system.physmem.perBankWrBursts::10 10499 # Per bank write bursts -system.physmem.perBankWrBursts::11 10145 # Per bank write bursts -system.physmem.perBankWrBursts::12 11054 # Per bank write bursts -system.physmem.perBankWrBursts::13 11426 # Per bank write bursts -system.physmem.perBankWrBursts::14 10852 # Per bank write bursts -system.physmem.perBankWrBursts::15 10376 # Per bank write bursts +system.physmem.bw_total::cpu.inst 159357 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1740816 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 5460 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3472991 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 154615 # Number of read requests accepted +system.physmem.writeReqs 173876 # Number of write requests accepted +system.physmem.readBursts 154615 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 173876 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9886592 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8768 # Total number of bytes read from write queue +system.physmem.bytesWritten 10962560 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9895360 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 11128064 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 137 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2557 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 1589 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10281 # Per bank write bursts +system.physmem.perBankRdBursts::1 9591 # Per bank write bursts +system.physmem.perBankRdBursts::2 10028 # Per bank write bursts +system.physmem.perBankRdBursts::3 9674 # Per bank write bursts +system.physmem.perBankRdBursts::4 9945 # Per bank write bursts +system.physmem.perBankRdBursts::5 9558 # Per bank write bursts +system.physmem.perBankRdBursts::6 9523 # Per bank write bursts +system.physmem.perBankRdBursts::7 9498 # Per bank write bursts +system.physmem.perBankRdBursts::8 9124 # Per bank write bursts +system.physmem.perBankRdBursts::9 8990 # Per bank write bursts +system.physmem.perBankRdBursts::10 9390 # Per bank write bursts +system.physmem.perBankRdBursts::11 9205 # Per bank write bursts +system.physmem.perBankRdBursts::12 9557 # Per bank write bursts +system.physmem.perBankRdBursts::13 10069 # Per bank write bursts +system.physmem.perBankRdBursts::14 10020 # Per bank write bursts +system.physmem.perBankRdBursts::15 10025 # Per bank write bursts +system.physmem.perBankWrBursts::0 10769 # Per bank write bursts +system.physmem.perBankWrBursts::1 10634 # Per bank write bursts +system.physmem.perBankWrBursts::2 10541 # Per bank write bursts +system.physmem.perBankWrBursts::3 10043 # Per bank write bursts +system.physmem.perBankWrBursts::4 11026 # Per bank write bursts +system.physmem.perBankWrBursts::5 9713 # Per bank write bursts +system.physmem.perBankWrBursts::6 10229 # Per bank write bursts +system.physmem.perBankWrBursts::7 10822 # Per bank write bursts +system.physmem.perBankWrBursts::8 11151 # Per bank write bursts +system.physmem.perBankWrBursts::9 11218 # Per bank write bursts +system.physmem.perBankWrBursts::10 10861 # Per bank write bursts +system.physmem.perBankWrBursts::11 10308 # Per bank write bursts +system.physmem.perBankWrBursts::12 10862 # Per bank write bursts +system.physmem.perBankWrBursts::13 11716 # Per bank write bursts +system.physmem.perBankWrBursts::14 11104 # Per bank write bursts +system.physmem.perBankWrBursts::15 10293 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 5196466283500 # Total gap between requests +system.physmem.totGap 5192452820500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 154566 # Read request sizes (log2) +system.physmem.readPktSize::6 154615 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 173500 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 151257 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2780 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 62 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 55 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 35 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 38 # What read queue length does an incoming req see +system.physmem.writePktSize::6 173876 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 151192 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2858 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 61 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 51 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 34 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 39 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 35 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 32 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see @@ -156,377 +156,360 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2693 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 8647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 9871 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 10255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 11236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 11623 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 12575 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 12144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 12750 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 11495 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9581 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8954 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7428 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7073 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7063 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6898 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 506 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 442 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 395 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 348 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 267 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2714 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5087 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 8567 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 9777 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 10086 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 11162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 11557 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 58532 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 356.006287 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 207.370190 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 358.892439 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 19432 33.20% 33.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 13728 23.45% 56.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5812 9.93% 66.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3460 5.91% 72.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2276 3.89% 76.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1654 2.83% 79.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1160 1.98% 81.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1010 1.73% 82.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10000 17.08% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 58532 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6314 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.461831 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 602.615488 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6313 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 60024 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 347.345862 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 200.231116 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 357.371422 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 21054 35.08% 35.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 13721 22.86% 57.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5818 9.69% 67.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3428 5.71% 73.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2258 3.76% 77.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1594 2.66% 79.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1149 1.91% 81.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 996 1.66% 83.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 10006 16.67% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 60024 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6317 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.452430 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 602.471336 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6316 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::47104-49151 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6314 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6314 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 27.101837 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 21.618222 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 26.504313 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4900 77.61% 77.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 45 0.71% 78.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 20 0.32% 78.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 269 4.26% 82.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 162 2.57% 85.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 59 0.93% 86.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 31 0.49% 86.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 30 0.48% 87.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 184 2.91% 90.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 10 0.16% 90.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 13 0.21% 90.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 9 0.14% 90.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 33 0.52% 91.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 21 0.33% 91.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 17 0.27% 91.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 41 0.65% 92.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 96 1.52% 94.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 7 0.11% 94.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 8 0.13% 94.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 18 0.29% 94.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 170 2.69% 97.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 5 0.08% 97.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 12 0.19% 97.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 4 0.06% 97.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 20 0.32% 97.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 4 0.06% 98.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 7 0.11% 98.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 6 0.10% 98.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 38 0.60% 98.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 9 0.14% 98.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 3 0.05% 99.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 7 0.11% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 12 0.19% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 3 0.05% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 2 0.03% 99.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 3 0.05% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 7 0.11% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 3 0.05% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.02% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 2 0.03% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 3 0.05% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 4 0.06% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 2 0.03% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.02% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 4 0.06% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 3 0.05% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::204-207 1 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-219 1 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::220-223 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 2 0.03% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-251 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6314 # Writes before turning the bus around for reads -system.physmem.totQLat 1460181000 # Total ticks spent queuing -system.physmem.totMemAccLat 4356493500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 772350000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9452.85 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6317 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6317 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 27.115719 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 21.572083 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 27.245873 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4954 78.42% 78.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 303 4.80% 83.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 227 3.59% 86.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 68 1.08% 87.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 174 2.75% 90.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 37 0.59% 91.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 45 0.71% 91.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 56 0.89% 92.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 90 1.42% 94.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 19 0.30% 94.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 157 2.49% 97.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 22 0.35% 97.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 27 0.43% 97.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 21 0.33% 98.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 36 0.57% 98.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 11 0.17% 98.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 22 0.35% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 8 0.13% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 14 0.22% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 6 0.09% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 5 0.08% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 1 0.02% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 1 0.02% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 4 0.06% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 3 0.05% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-239 1 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-255 3 0.05% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6317 # Writes before turning the bus around for reads +system.physmem.totQLat 1525176500 # Total ticks spent queuing +system.physmem.totMemAccLat 4421639000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 772390000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9873.10 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28202.85 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 28623.10 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.90 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.11 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.90 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.91 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.14 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.87 # Average write queue length when enqueuing -system.physmem.readRowHits 127064 # Number of row buffer hits during reads -system.physmem.writeRowHits 139994 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.26 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 81.80 # Row buffer hit rate for writes -system.physmem.avgGap 15839697.75 # Average gap between requests -system.physmem.pageHitRate 82.02 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 4974958806500 # Time in different power states -system.physmem.memoryStateTime::REF 173521400000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 47986025500 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 218272320 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 224229600 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 119097000 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 122347500 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 601746600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 603111600 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 549419760 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 559444320 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 339407858400 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 339407858400 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 134224004700 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 134453555955 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 3000139025250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 2999937664500 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 3475259424030 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 3475308211875 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.773676 # Core power per rank (mW) -system.physmem.averagePower::1 668.783065 # Core power per rank (mW) +system.physmem.avgWrQLen 25.96 # Average write queue length when enqueuing +system.physmem.readRowHits 125716 # Number of row buffer hits during reads +system.physmem.writeRowHits 140027 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.38 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 81.73 # Row buffer hit rate for writes +system.physmem.avgGap 15806986.56 # Average gap between requests +system.physmem.pageHitRate 81.57 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 224879760 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 122702250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 609164400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 542874960 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 339145441440 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 134202799845 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2997747003000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 3472594865655 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.777986 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 4986908920500 # Time in different power states +system.physmem_0.memoryStateTime::REF 173387240000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 32151782000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 228901680 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 124896750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 595756200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 567084240 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 339145441440 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 134282501235 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2997677089500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 3472621671045 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.783148 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 4986802992250 # Time in different power states +system.physmem_1.memoryStateTime::REF 173387240000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 32262536750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.numCycles 10392932694 # number of cpu cycles simulated +system.cpu.numCycles 10384905768 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 128418244 # Number of instructions committed -system.cpu.committedOps 247550593 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 232131886 # Number of integer alu accesses +system.cpu.committedInsts 128427413 # Number of instructions committed +system.cpu.committedOps 247571076 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 232151918 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 2300917 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 23183149 # number of instructions that are conditional controls -system.cpu.num_int_insts 232131886 # number of integer instructions +system.cpu.num_func_calls 2302537 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 23180236 # number of instructions that are conditional controls +system.cpu.num_int_insts 232151918 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 434791523 # number of times the integer registers were read -system.cpu.num_int_register_writes 197987761 # number of times the integer registers were written +system.cpu.num_int_register_reads 434861886 # number of times the integer registers were read +system.cpu.num_int_register_writes 198003963 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 132892118 # number of times the CC registers were read -system.cpu.num_cc_register_writes 95599960 # number of times the CC registers were written -system.cpu.num_mem_refs 22255642 # number of memory refs -system.cpu.num_load_insts 13887148 # Number of load instructions -system.cpu.num_store_insts 8368494 # Number of store instructions -system.cpu.num_idle_cycles 9795963958.998116 # Number of idle cycles -system.cpu.num_busy_cycles 596968735.001885 # Number of busy cycles -system.cpu.not_idle_fraction 0.057440 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.942560 # Percentage of idle cycles -system.cpu.Branches 26322824 # Number of branches fetched -system.cpu.op_class::No_OpClass 174818 0.07% 0.07% # Class of executed instruction -system.cpu.op_class::IntAlu 224858584 90.83% 90.90% # Class of executed instruction -system.cpu.op_class::IntMult 140018 0.06% 90.96% # Class of executed instruction -system.cpu.op_class::IntDiv 123105 0.05% 91.01% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::MemRead 13887148 5.61% 96.62% # Class of executed instruction -system.cpu.op_class::MemWrite 8368494 3.38% 100.00% # Class of executed instruction +system.cpu.num_cc_register_reads 132886732 # number of times the CC registers were read +system.cpu.num_cc_register_writes 95589498 # number of times the CC registers were written +system.cpu.num_mem_refs 22270580 # number of memory refs +system.cpu.num_load_insts 13896035 # Number of load instructions +system.cpu.num_store_insts 8374545 # Number of store instructions +system.cpu.num_idle_cycles 9787798534.998116 # Number of idle cycles +system.cpu.num_busy_cycles 597107233.001885 # Number of busy cycles +system.cpu.not_idle_fraction 0.057498 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.942502 # Percentage of idle cycles +system.cpu.Branches 26321851 # Number of branches fetched +system.cpu.op_class::No_OpClass 175044 0.07% 0.07% # Class of executed instruction +system.cpu.op_class::IntAlu 224863247 90.83% 90.90% # Class of executed instruction +system.cpu.op_class::IntMult 140296 0.06% 90.95% # Class of executed instruction +system.cpu.op_class::IntDiv 123429 0.05% 91.00% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::MemRead 13896035 5.61% 96.62% # Class of executed instruction +system.cpu.op_class::MemWrite 8374545 3.38% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 247552167 # Class of executed instruction +system.cpu.op_class::total 247572596 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.dcache.tags.replacements 1622836 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.996904 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 20034858 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1623348 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.341690 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 1622236 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.996968 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 20050453 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1622748 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.355864 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 51171250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.996904 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.996968 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 323 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 77 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 320 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 88294796 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 88294796 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 11940626 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11940626 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8032822 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8032822 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 59222 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 59222 # number of SoftPFReq hits -system.cpu.dcache.demand_hits::cpu.data 19973448 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 19973448 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20032670 # number of overall hits -system.cpu.dcache.overall_hits::total 20032670 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 907502 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 907502 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 325247 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 325247 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 402429 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 402429 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 1232749 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1232749 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1635178 # number of overall misses -system.cpu.dcache.overall_misses::total 1635178 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 12738871000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 12738871000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 11339051069 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 11339051069 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 24077922069 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 24077922069 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 24077922069 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 24077922069 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 12848128 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 12848128 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8358069 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8358069 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 461651 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 461651 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21206197 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21206197 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21667848 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21667848 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070633 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.070633 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038914 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.038914 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.871717 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.871717 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.058132 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.058132 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.075466 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.075466 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14037.292480 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14037.292480 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34862.892107 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34862.892107 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19531.893410 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19531.893410 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14724.954757 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14724.954757 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 6197 # number of cycles access was blocked +system.cpu.dcache.tags.tag_accesses 88354150 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 88354150 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 11949885 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11949885 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8039029 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8039029 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 59358 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 59358 # number of SoftPFReq hits +system.cpu.dcache.demand_hits::cpu.data 19988914 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 19988914 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20048272 # number of overall hits +system.cpu.dcache.overall_hits::total 20048272 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 907019 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 907019 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 325091 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 325091 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 402457 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 402457 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 1232110 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1232110 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1634567 # number of overall misses +system.cpu.dcache.overall_misses::total 1634567 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12730749000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12730749000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 11380492066 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 11380492066 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 24111241066 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 24111241066 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 24111241066 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 24111241066 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 12856904 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 12856904 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8364120 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8364120 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 461815 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 461815 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21221024 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21221024 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21682839 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21682839 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070547 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.070547 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038867 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.038867 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.871468 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.871468 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.058061 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.058061 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.075385 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.075385 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14035.812921 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14035.812921 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35007.096678 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35007.096678 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19569.065316 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19569.065316 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14750.842924 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14750.842924 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 6388 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 83 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 73 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 74.662651 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 87.506849 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1539435 # number of writebacks -system.cpu.dcache.writebacks::total 1539435 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 291 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 291 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9259 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 9259 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 9550 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 9550 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 9550 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 9550 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 907211 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 907211 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315988 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 315988 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402393 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 402393 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1223199 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1223199 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1625592 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1625592 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10916933250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10916933250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10204146879 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10204146879 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5337559000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5337559000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21121080129 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 21121080129 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26458639129 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26458639129 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 1539114 # number of writebacks +system.cpu.dcache.writebacks::total 1539114 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 287 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 287 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9270 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 9270 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 9557 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 9557 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 9557 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 9557 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 906732 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 906732 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315821 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 315821 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402422 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 402422 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1222553 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1222553 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1624975 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1624975 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10909979000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10909979000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10244477888 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10244477888 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5364351750 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5364351750 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21154456888 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 21154456888 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26518808638 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26518808638 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94240373000 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94240373000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2561805000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2561805000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96802178000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 96802178000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070610 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070610 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037806 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037806 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.871639 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.871639 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057681 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.057681 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.075023 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.075023 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12033.510672 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12033.510672 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32292.830357 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32292.830357 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13264.542375 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13264.542375 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17267.084202 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17267.084202 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16276.309879 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16276.309879 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2561567000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2561567000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96801940000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 96801940000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070525 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070525 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037759 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037759 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.871392 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.871392 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057610 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.057610 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074943 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.074943 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12032.198047 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12032.198047 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32437.608291 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32437.608291 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13330.165225 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13330.165225 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17303.509041 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 17303.509041 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16319.517924 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16319.517924 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -534,58 +517,58 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 7764 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 5.069200 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 13087 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 7779 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.682350 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 5159703878000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.069200 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.316825 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.316825 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.replacements 7361 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 5.061574 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 13446 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 7376 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.822939 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 5159721667000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.061574 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.316348 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.316348 # Average percentage of cache occupancy system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id -system.cpu.dtb_walker_cache.tags.tag_accesses 53125 # Number of tag accesses -system.cpu.dtb_walker_cache.tags.data_accesses 53125 # Number of data accesses -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13088 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 13088 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13088 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 13088 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13088 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 13088 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8983 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 8983 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8983 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 8983 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8983 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 8983 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 95259000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 95259000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 95259000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 95259000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 95259000 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 95259000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22071 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 22071 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22071 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 22071 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22071 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 22071 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.407005 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.407005 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.407005 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.407005 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.407005 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.407005 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10604.363798 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10604.363798 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10604.363798 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10604.363798 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10604.363798 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10604.363798 # average overall miss latency +system.cpu.dtb_walker_cache.tags.tag_accesses 52616 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 52616 # Number of data accesses +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13447 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 13447 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13447 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 13447 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13447 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 13447 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8574 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 8574 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8574 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 8574 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8574 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 8574 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 90024000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 90024000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 90024000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 90024000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 90024000 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 90024000 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22021 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 22021 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22021 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 22021 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22021 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 22021 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.389356 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.389356 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.389356 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.389356 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.389356 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.389356 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10499.650105 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10499.650105 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10499.650105 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10499.650105 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10499.650105 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10499.650105 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -594,86 +577,86 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 3015 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 3015 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8983 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8983 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8983 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 8983 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8983 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 8983 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 77292500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 77292500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 77292500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 77292500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 77292500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 77292500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.407005 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.407005 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.407005 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.407005 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.407005 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.407005 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8604.308138 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8604.308138 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8604.308138 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8604.308138 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8604.308138 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8604.308138 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 2787 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 2787 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8574 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8574 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8574 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 8574 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8574 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 8574 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 72875500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 72875500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 72875500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 72875500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 72875500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 72875500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.389356 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.389356 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.389356 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.389356 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.389356 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.389356 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8499.591789 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8499.591789 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8499.591789 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8499.591789 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8499.591789 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8499.591789 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 791291 # number of replacements -system.cpu.icache.tags.tagsinuse 510.349956 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 144673577 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 791803 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 182.714106 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 793260 # number of replacements +system.cpu.icache.tags.tagsinuse 510.348682 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 144679610 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 793772 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 182.268473 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 161114367250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.349956 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996777 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996777 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 510.348682 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996775 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996775 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 150 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 292 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 151 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 298 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 146257197 # Number of tag accesses -system.cpu.icache.tags.data_accesses 146257197 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 144673577 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 144673577 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 144673577 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 144673577 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 144673577 # number of overall hits -system.cpu.icache.overall_hits::total 144673577 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 791810 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 791810 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 791810 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 791810 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 791810 # number of overall misses -system.cpu.icache.overall_misses::total 791810 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11120002617 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11120002617 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11120002617 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11120002617 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11120002617 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11120002617 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 145465387 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 145465387 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 145465387 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 145465387 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 145465387 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 145465387 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005443 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.005443 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.005443 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.005443 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.005443 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.005443 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14043.776432 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14043.776432 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14043.776432 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14043.776432 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14043.776432 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14043.776432 # average overall miss latency +system.cpu.icache.tags.tag_accesses 146267168 # Number of tag accesses +system.cpu.icache.tags.data_accesses 146267168 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 144679610 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 144679610 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 144679610 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 144679610 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 144679610 # number of overall hits +system.cpu.icache.overall_hits::total 144679610 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 793779 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 793779 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 793779 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 793779 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 793779 # number of overall misses +system.cpu.icache.overall_misses::total 793779 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11142507120 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11142507120 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11142507120 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11142507120 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11142507120 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11142507120 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 145473389 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 145473389 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 145473389 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 145473389 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 145473389 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 145473389 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005457 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.005457 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.005457 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.005457 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.005457 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.005457 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14037.291387 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14037.291387 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14037.291387 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14037.291387 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14037.291387 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14037.291387 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -682,88 +665,88 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 791810 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 791810 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 791810 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 791810 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 791810 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 791810 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9531495383 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9531495383 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9531495383 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9531495383 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9531495383 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9531495383 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005443 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005443 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005443 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.005443 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005443 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.005443 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12037.604202 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12037.604202 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12037.604202 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12037.604202 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12037.604202 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12037.604202 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 793779 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 793779 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 793779 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 793779 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 793779 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 793779 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9550046380 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9550046380 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9550046380 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9550046380 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9550046380 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9550046380 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005457 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005457 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005457 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.005457 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005457 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.005457 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12031.114932 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12031.114932 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12031.114932 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12031.114932 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12031.114932 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12031.114932 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.tags.replacements 3671 # number of replacements -system.cpu.itb_walker_cache.tags.tagsinuse 3.091001 # Cycle average of tags in use -system.cpu.itb_walker_cache.tags.total_refs 7743 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.tags.sampled_refs 3683 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.tags.avg_refs 2.102362 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.tags.warmup_cycle 5161228729000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.091001 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.193188 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_percent::total 0.193188 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 12 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.replacements 3392 # number of replacements +system.cpu.itb_walker_cache.tags.tagsinuse 3.080377 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.total_refs 8023 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.tags.sampled_refs 3405 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.tags.avg_refs 2.356241 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.tags.warmup_cycle 5161936228000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.080377 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.192524 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_percent::total 0.192524 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 13 # Occupied blocks per task id system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.750000 # Percentage of cache occupancy per task id -system.cpu.itb_walker_cache.tags.tag_accesses 29095 # Number of tag accesses -system.cpu.itb_walker_cache.tags.data_accesses 29095 # Number of data accesses -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7743 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 7743 # number of ReadReq hits +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id +system.cpu.itb_walker_cache.tags.tag_accesses 28882 # Number of tag accesses +system.cpu.itb_walker_cache.tags.data_accesses 28882 # Number of data accesses +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 8043 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 8043 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7745 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 7745 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7745 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 7745 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4535 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 4535 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4535 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 4535 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4535 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 4535 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 45208750 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 45208750 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 45208750 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 45208750 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 45208750 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 45208750 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12278 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 12278 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 8045 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 8045 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 8045 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 8045 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4264 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 4264 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4264 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 4264 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4264 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 4264 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 41583500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 41583500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 41583500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 41583500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 41583500 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 41583500 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12307 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 12307 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12280 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 12280 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12280 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 12280 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.369360 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.369360 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.369300 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.369300 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.369300 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.369300 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 9968.853363 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 9968.853363 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 9968.853363 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9968.853363 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9968.853363 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9968.853363 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12309 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 12309 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12309 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 12309 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.346469 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.346469 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.346413 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.346413 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.346413 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.346413 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 9752.227955 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 9752.227955 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 9752.227955 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9752.227955 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9752.227955 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9752.227955 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -772,177 +755,177 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 782 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 782 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4535 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4535 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4535 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 4535 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4535 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 4535 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 36137250 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 36137250 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 36137250 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 36137250 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 36137250 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 36137250 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.369360 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.369360 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.369300 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.369300 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.369300 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.369300 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 7968.522602 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 7968.522602 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 7968.522602 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7968.522602 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7968.522602 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7968.522602 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 713 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 713 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4264 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4264 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4264 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 4264 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4264 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 4264 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 33053500 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 33053500 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 33053500 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 33053500 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 33053500 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 33053500 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.346469 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.346469 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.346413 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.346413 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.346413 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.346413 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 7751.758912 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 7751.758912 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 7751.758912 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7751.758912 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7751.758912 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7751.758912 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 87090 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64747.295038 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3489215 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 151848 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 22.978340 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 87367 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64711.001958 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3492751 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 152091 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 22.964876 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 50370.250728 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.007923 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.141558 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3248.489299 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 11128.405530 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.768589 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 50199.140845 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.014318 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.141821 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3238.410068 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 11273.294906 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.765978 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049568 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.169806 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.987965 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 64758 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 86 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2868 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4655 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 57121 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.988129 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 32220029 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 32220029 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6582 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2969 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 778852 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1280153 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2068556 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1543232 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1543232 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 331 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 331 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 200337 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 200337 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 6582 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 2969 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 778852 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1480490 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2268893 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 6582 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 2969 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 778852 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1480490 # number of overall hits -system.cpu.l2cache.overall_hits::total 2268893 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 1 # number of ReadReq misses +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049414 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.172017 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.987412 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 64724 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2777 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4943 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56808 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987610 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 32220272 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 785787500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8281029527 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9067229777 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86680074500 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86680074500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2395003500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2395003500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 89075078000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 89075078000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000152 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001681 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016349 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021886 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019712 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.800962 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.800962 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.361567 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.361567 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000152 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001681 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016349 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087578 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.063968 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000152 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001681 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016349 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087578 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.063968 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 57550 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60940.073387 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62274.585442 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61859.042937 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10662.023273 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10662.023273 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56679.443318 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56679.443318 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 57550 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60940.073387 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57807.307235 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58068.963264 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 57550 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60940.073387 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57807.307235 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58068.963264 # average overall mshr miss latency +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2394785000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2394785000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 89074859500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 89074859500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000324 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001859 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016289 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021852 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019672 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.809495 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.809495 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.362122 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.362122 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000324 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001859 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016289 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087648 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.063969 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000324 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001859 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016289 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087648 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.063969 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 55625 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 60300 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60772.428461 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63250.760756 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62478.375515 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10692.715789 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10692.715789 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56990.951072 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56990.951072 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 55625 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 60300 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60772.428461 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58249.834888 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58460.163229 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 55625 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 60300 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60772.428461 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58249.834888 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58460.163229 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1042,59 +1025,59 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2697337 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2696818 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 13890 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 13890 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1543232 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2698168 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2697644 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 13888 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 13888 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1542614 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2201 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2201 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 313800 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 313800 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1583607 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5980523 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 8291 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18581 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7591002 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50675008 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204057491 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 240384 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 614272 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 255587155 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 53212 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4021729 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.011827 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.108106 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeReq 2194 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2194 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 313640 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 313640 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1587545 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5978947 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 7667 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 17540 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7591699 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50801024 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 203997643 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 217792 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 573824 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 255590283 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 53203 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4021775 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.011825 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.108096 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 3974165 98.82% 98.82% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 47564 1.18% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 3974219 98.82% 98.82% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 47556 1.18% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4021729 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3834985000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 4021775 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3834392000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 487500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 468000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1190158617 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1193119870 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3054984845 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3054097839 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 6803250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 6397000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 13474750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 12861250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 230264 # Transaction distribution -system.iobus.trans_dist::ReadResp 230264 # Transaction distribution +system.iobus.trans_dist::ReadReq 230256 # Transaction distribution +system.iobus.trans_dist::ReadResp 230256 # Transaction distribution system.iobus.trans_dist::WriteReq 57694 # Transaction distribution system.iobus.trans_dist::WriteResp 10974 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.iobus.trans_dist::MessageReq 1655 # Transaction distribution -system.iobus.trans_dist::MessageResp 1655 # Transaction distribution +system.iobus.trans_dist::MessageReq 1654 # Transaction distribution +system.iobus.trans_dist::MessageResp 1654 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes) @@ -1114,11 +1097,11 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 480788 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3310 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3310 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 579226 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95112 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95112 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3308 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3308 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 579208 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) @@ -1138,12 +1121,12 @@ system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 246674 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027296 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027296 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6620 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6620 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 3280590 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 3947664 # Layer occupancy (ticks) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027232 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027232 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 3280522 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 3944816 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1179,54 +1162,54 @@ system.iobus.reqLayer17.occupancy 9000 # La system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 448397612 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 448430581 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 469814000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 52228501 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 52212002 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1655000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1654000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47510 # number of replacements -system.iocache.tags.tagsinuse 0.132770 # Cycle average of tags in use +system.iocache.tags.replacements 47501 # number of replacements +system.iocache.tags.tagsinuse 0.119711 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47526 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47517 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 5045851378000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.132770 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.008298 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.008298 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 5045856556000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.119711 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007482 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.007482 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428076 # Number of tag accesses -system.iocache.tags.data_accesses 428076 # Number of data accesses -system.iocache.ReadReq_misses::pc.south_bridge.ide 844 # number of ReadReq misses -system.iocache.ReadReq_misses::total 844 # number of ReadReq misses +system.iocache.tags.tag_accesses 428004 # Number of tag accesses +system.iocache.tags.data_accesses 428004 # Number of data accesses +system.iocache.ReadReq_misses::pc.south_bridge.ide 836 # number of ReadReq misses +system.iocache.ReadReq_misses::total 836 # number of ReadReq misses system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses -system.iocache.demand_misses::pc.south_bridge.ide 844 # number of demand (read+write) misses -system.iocache.demand_misses::total 844 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 844 # number of overall misses -system.iocache.overall_misses::total 844 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 143496186 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 143496186 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 12353940925 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 12353940925 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 143496186 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 143496186 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 143496186 # number of overall miss cycles -system.iocache.overall_miss_latency::total 143496186 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 844 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 844 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 836 # number of demand (read+write) misses +system.iocache.demand_misses::total 836 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 836 # number of overall misses +system.iocache.overall_misses::total 836 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 143698686 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 143698686 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 12361223893 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 12361223893 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 143698686 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 143698686 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 143698686 # number of overall miss cycles +system.iocache.overall_miss_latency::total 143698686 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 836 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 836 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 844 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 844 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 844 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 844 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 836 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 836 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 836 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 836 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses @@ -1235,40 +1218,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 170019.177725 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 170019.177725 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 264425.105415 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 264425.105415 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 170019.177725 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 170019.177725 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 170019.177725 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 170019.177725 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 70456 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 171888.380383 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 171888.380383 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 264580.990860 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 264580.990860 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 171888.380383 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 171888.380383 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 171888.380383 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 171888.380383 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 70511 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 9155 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 9153 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.695904 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.703594 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 46668 # number of writebacks -system.iocache.writebacks::total 46668 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 844 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 844 # number of ReadReq MSHR misses +system.iocache.writebacks::writebacks 46667 # number of writebacks +system.iocache.writebacks::total 46667 # number of writebacks +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 836 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 836 # number of ReadReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 844 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 844 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 844 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 844 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 99583186 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 99583186 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 9924498927 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 9924498927 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 99583186 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 99583186 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 99583186 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 99583186 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 836 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 836 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 836 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 836 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 100200686 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 100200686 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 9931779897 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 9931779897 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 100200686 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 100200686 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 100200686 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 100200686 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -1277,71 +1260,71 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 117989.556872 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 117989.556872 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 212425.062650 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212425.062650 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 117989.556872 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 117989.556872 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 117989.556872 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 117989.556872 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 119857.279904 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 119857.279904 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 212580.905330 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212580.905330 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 119857.279904 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 119857.279904 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 119857.279904 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 119857.279904 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 624001 # Transaction distribution -system.membus.trans_dist::ReadResp 624001 # Transaction distribution -system.membus.trans_dist::WriteReq 13890 # Transaction distribution -system.membus.trans_dist::WriteResp 13890 # Transaction distribution -system.membus.trans_dist::Writeback 126780 # Transaction distribution +system.membus.trans_dist::ReadReq 623924 # Transaction distribution +system.membus.trans_dist::ReadResp 623924 # Transaction distribution +system.membus.trans_dist::WriteReq 13888 # Transaction distribution +system.membus.trans_dist::WriteResp 13888 # Transaction distribution +system.membus.trans_dist::Writeback 127156 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2150 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1612 # Transaction distribution -system.membus.trans_dist::ReadExReq 113178 # Transaction distribution -system.membus.trans_dist::ReadExResp 113178 # Transaction distribution -system.membus.trans_dist::MessageReq 1655 # Transaction distribution -system.membus.trans_dist::MessageResp 1655 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3310 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3310 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeReq 2158 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1607 # Transaction distribution +system.membus.trans_dist::ReadExReq 113297 # Transaction distribution +system.membus.trans_dist::ReadExResp 113297 # Transaction distribution +system.membus.trans_dist::MessageReq 1654 # Transaction distribution +system.membus.trans_dist::MessageResp 1654 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3308 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3308 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 480788 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710114 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 392754 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1583656 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141395 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 141395 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1728361 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6620 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::total 6620 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710110 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 393232 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1584130 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141386 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 141386 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1728824 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6616 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::total 6616 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 246674 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420225 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 14991040 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16657939 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6005184 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 6005184 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22669743 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 1607 # Total snoops (count) -system.membus.snoop_fanout::samples 331268 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420217 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15018304 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16685195 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6005120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 6005120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22696931 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 1614 # Total snoops (count) +system.membus.snoop_fanout::samples 331694 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 331268 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 331694 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 331268 # Request fanout histogram -system.membus.reqLayer0.occupancy 257196000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 331694 # Request fanout histogram +system.membus.reqLayer0.occupancy 257197500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 358100000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 358100500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3310000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3308000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1728081500 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 1731913000 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1655000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1654000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 2618580655 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 2619410411 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer4.occupancy 54329499 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 54258998 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). |